Chip security module and security encryption method

Abstract

The embodiment of the invention discloses a chip security module and a security encryption method, and the method comprises the steps: monitoring an executed encryption operation instruction, judging whether the execution process of the encryption operation instruction is matched with a corresponding security sequence or not, and if the execution process of the encryption operation instruction is matched with the corresponding security sequence, executing the encryption operation instruction; the current encryption operation instruction is controlled to output an execution result, if the execution process of the encryption operation instruction is not matched with a corresponding security sequence, a corresponding processing action is carried out according to actual application requirements, and the security sequence is used for representing the preset execution process of the corresponding encryption operation instruction. According to the embodiment of the invention, the security of the chip can be improved, and different application requirements can be met by configuring different security sequences due to the fact that monitoring is carried out on the software level, and meanwhile, the design cost of the chip is reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and more specifically, to a chip security module and a security encryption method. Background Art

[0002] With the development of computer technology, most system-level chips have encryption units such as identity authentication. In the prior art, a combination of software and hardware is usually used to implement a security module, and encryption is implemented by combining software with a chip digital system module to improve the flexibility of the application. However, there are some loopholes in the prior art, resulting in poor security of the security module. For example, if the software is exposed to a third party through operations such as disassembly, it may lead to the leakage of private keys. In addition, the prior art usually uses chip curing or ROM (Read-Only Memory) state machine curing to ensure the security of the security module, resulting in a relatively single function. When there are different requirements, it is necessary to rewire the chip or use a dual-core design in the chip, which is costly. Summary of the invention

[0003] In view of this, the embodiments of the present invention provide a chip security module and a security encryption method to improve chip security and reduce chip design costs so as to meet different application requirements.

[0004] In a first aspect, an embodiment of the present invention provides a chip security module, the chip security module comprising a chip encryption unit, the chip encryption unit being configured to execute an encryption operation instruction, monitor the execution process of the encryption operation instruction, and determine whether the execution process of the encryption operation instruction matches a corresponding security sequence;

[0005] If the execution process of the encryption operation instruction matches the corresponding security sequence, the chip security module controls the current encryption operation instruction to output the execution result; and

[0006] If the execution process of the encryption operation instruction does not match the corresponding security sequence, perform corresponding processing actions according to actual application requirements;

[0007] The security sequence is used to characterize the preset execution process of the corresponding encryption operation instruction.

[0008] Optionally, the chip encryption unit receives and executes multiple sub-instructions extracted from the corresponding encryption operation instruction, monitors the execution order of each sub-instruction, and determines whether the execution order matches the corresponding security sequence.

[0009] Optionally, the security sequence is determined according to a sub-instruction extracted from a corresponding encryption operation instruction and is preset in the chip security module.

[0010] Optionally, the chip encryption unit receives and executes multiple tag commands extracted from corresponding encryption operation instructions, monitors the execution order of each tag command, and determines whether the execution order matches the corresponding security sequence.

[0011] Optionally, the security sequence is determined according to a marking command extracted from a corresponding encryption operation instruction and is preset in the chip security module;

[0012] The marking command includes at least one of a basic instruction for implementing the encryption operation instruction, an input parameter address, and an output parameter address.

[0013] Optionally, the security sequence is determined based on at least part of the plurality of marking commands.

[0014] Optionally, the chip security module further includes:

[0015] The chip storage unit is configured to store at least one set of the security sequence, key and / or private key.

[0016] Optionally, the processing action includes a combination of one or more of the following: controlling the current encryption operation instruction not to output the execution result, self-destructing the key and / or private key stored in the chip security module, self-destructing the chip storage unit in the chip security module, controlling the chip to freeze, and controlling the chip to restart.

[0017] Optionally, the chip security module also includes a software code unit and a register unit, the software code unit is configured to extract multiple marking commands from the encryption operation instructions, and pass the multiple marking commands to the chip encryption unit through the register unit, and the chip encryption unit is configured to perform corresponding encryption operations according to the multiple marking commands.

[0018] Optionally, the security sequence includes a sequence header, sequence data and a terminator, the sequence header is used to identify the encryption operation instruction corresponding to the security sequence, and the sequence data is formed by a marking command extracted from the corresponding encryption operation instruction.

[0019] Optionally, the chip security module is further configured to query the sequence header of each security sequence according to the encryption operation instruction currently being executed, so as to obtain the security sequence corresponding to the encryption operation instruction currently being executed.

[0020] Optionally, the chip encryption unit includes a microprocessor and a buffer;

[0021] The microprocessor is configured to obtain and sequentially execute the plurality of tag commands from the register unit, and selectively write output parameters of each of the tag commands into the buffer.

[0022] Optionally, the chip encryption unit also includes a hardware monitor, which is configured to monitor the operating status of the register unit or the microprocessor, and obtain a tag command sequence formed by multiple tag commands corresponding to the encryption operation instructions executed by the microprocessor to determine whether the tag command sequence matches the corresponding security sequence.

[0023] In a second aspect, an embodiment of the present invention provides a security encryption method, which is applied to a chip security module. The method includes:

[0024] Executing an encryption operation instruction, monitoring the execution process of the encryption operation instruction, and determining whether the execution process of the encryption operation instruction matches the corresponding security sequence;

[0025] If the execution process of the encryption operation instruction matches the corresponding security sequence, controlling the current encryption operation instruction to output an execution result; and

[0026] If the execution process of the encryption operation instruction does not match the corresponding security sequence, perform corresponding processing actions according to actual application requirements;

[0027] The security sequence is used to characterize the preset execution process of the corresponding encryption operation instruction.

[0028] Optionally, the executing the encryption operation instruction, monitoring the execution process of the encryption operation instruction, and determining whether the execution process of the encryption operation instruction matches the corresponding security sequence includes:

[0029] Receive and execute multiple sub-instructions extracted from the corresponding encryption operation instruction, monitor the execution order of each sub-instruction, and determine whether the execution order matches the corresponding security sequence.

[0030] Optionally, the security sequence is determined according to a sub-instruction extracted from a corresponding encryption operation instruction and is preset in the chip security module.

[0031] Optionally, the executing the encryption operation instruction, monitoring the execution process of the encryption operation instruction, and determining whether the execution process of the encryption operation instruction matches the corresponding security sequence includes:

[0032] Receive and execute multiple tag commands extracted from corresponding encryption operation instructions, monitor the execution order of each tag command, and determine whether the execution order matches the corresponding security sequence.

[0033] Optionally, the security sequence is determined according to a marking command extracted from a corresponding encryption operation instruction and is preset in the chip security module;

[0034] The marking command includes at least one of a basic instruction for implementing the encryption operation instruction, an input parameter address, and an output parameter address.

[0035] Optionally, the security sequence is determined based on at least part of the plurality of marking commands.

[0036] Optionally, the instruction to execute the encryption operation further includes:

[0037] receiving an encryption request;

[0038] In response to receiving the encryption request, a corresponding encryption operation instruction is executed according to the encryption request.

[0039] Optionally, the security sequence includes a sequence header, sequence data and a terminator, the sequence header is used to identify the encryption operation instruction corresponding to the security sequence, and the sequence data is formed by a marking command extracted from the corresponding encryption operation instruction.

[0040] Optionally, the method further comprises:

[0041] Acquire a marking command sequence formed by a plurality of marking commands corresponding to the encryption operation instruction;

[0042] Querying a sequence header of at least one security sequence according to the encryption operation instruction to obtain a security sequence corresponding to the encryption operation instruction;

[0043] Determine whether the marking command sequence matches the corresponding security sequence.

[0044] Optionally, the processing action includes a combination of one or more of the following: controlling the current encryption operation instruction not to output the execution result, self-destructing the key and / or private key stored in the chip security module, self-destructing the chip storage unit in the chip security module, controlling the chip to freeze, and controlling the chip to restart.

[0045] The embodiment of the present invention monitors the execution process of the encryption operation instruction and determines whether it matches the corresponding security sequence. When it matches, it controls the encryption operation output execution result, and when it does not match, it performs corresponding processing actions according to actual application requirements, thereby improving the security of the chip. Moreover, since the embodiment of the present invention monitors at the software level, different application requirements can be met by configuring different security sequences, while reducing the chip design cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0047] Figure 1is a schematic diagram of a chip security module according to an embodiment of the present invention;

[0048] Figure 2 is a schematic diagram of another chip security module according to an embodiment of the present invention;

[0049] Figure 3 is a schematic diagram of a process of generating a set of security sequences according to an embodiment of the present invention;

[0050] Figure 4 is a schematic diagram of a chip encryption unit according to an embodiment of the present invention;

[0051] Figure 5 is a schematic diagram of a monitoring process of a hardware monitor according to an embodiment of the present invention;

[0052] Figure 6 It is a flow chart of a secure encryption method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0053] The present application is described below based on embodiments, but the present application is not limited to these embodiments. In the detailed description of the present application below, some specific details are described in detail. It is possible for those skilled in the art to fully understand the present application without the description of these details. In order to avoid confusing the essence of the present application, known methods, processes, flows, components and circuits are not described in detail.

[0054] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0055] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0056] In the description of this application, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, the meaning of "plurality" is two or more.

[0057] With the continuous development of chip technology, encryption units such as identity authentication are generally equipped in the design of security chips and SOC chips, and most of them use a combination of software and hardware to build security modules. While this method improves the flexibility of application, it also brings obvious security risks due to the lack of security measures in the software part. Based on this, the embodiment of the present invention provides a chip security module and a security encryption method, which, on the basis of retaining the flexible advantages brought by the combination of software and hardware in the prior art, focuses on strengthening the ability to respond to software exposure risks, so as to improve the security of the chip and reduce the cost of chip design.

[0058] The embodiment of the present invention is mainly described by taking data encryption operation as an example. It should be understood that the present embodiment can also be applied to other fields such as data decryption, digital signature, signature verification, etc., and the present embodiment is not limited to this.

[0059] Figure 1 FIG. 1 is a schematic diagram of a chip security module according to an embodiment of the present invention. In an optional implementation, Figure 1 As shown, the chip security module of the embodiment of the present invention includes a chip encryption unit 10, which executes encryption operation instructions, monitors the execution process of the encryption operation instructions, and determines whether the execution process matches the corresponding security sequence. If the execution process matches the corresponding security sequence, the chip security module controls the current encryption operation instruction to output the execution result. If the execution process does not match the corresponding security sequence, the chip security module or other modules outside the chip security module perform corresponding processing actions according to actual application requirements. Among them, the security sequence is used to characterize the preset execution process of the corresponding encryption operation instruction, which can be read by the chip encryption unit 10 from other storage units of the chip security module, or can be built into the chip encryption unit 10, and this embodiment does not limit this.

[0060] In one embodiment, the chip encryption unit 10 receives multiple sub-instructions extracted from the corresponding encryption operation instruction, executes each sub-instruction, monitors the execution order of each sub-instruction, and determines whether the execution order matches the corresponding security sequence. In the present invention, any scheme of obtaining multiple sub-instructions according to the encryption operation instruction to complete the execution of the encryption operation instruction is within the protection scope of the present invention. For example, when the encryption operation instruction is f=x+yz, the chip encryption unit receives multiple sub-instructions split from the encryption operation instruction. When the encryption operation instruction is digital signature verification, the chip encryption unit receives multiple sub-instructions that need to be executed when executing the encryption operation instruction.

[0061] The security sequence is determined based on at least part of the multiple sub-instructions. In one embodiment, the security sequence is determined based on all the sub-instructions, and the number of the multiple sub-instructions is the same as the number of sequences in the security sequence. At this time, the execution order of each sub-sequence corresponds to the sequence in the corresponding security sequence one-to-one. In another embodiment, the security sequence is determined based on part of the multiple sub-instructions, and the number of sequences in the security sequence is less than the number of the multiple sub-instructions. At this time, N of the multiple sub-instructions correspond to the sequences in the corresponding security sequence one-to-one, and N is greater than or equal to 2. In one embodiment, the number of the multiple sub-instructions is 5, the number of sequences in the security sequence is three, and three of the multiple sub-instructions (for example, the first sub-instruction, the second sub-instruction and the third sub-instruction) correspond to the sequences in the security sequence one-to-one. In one embodiment, each sub-instruction received and executed by the chip encryption unit 10 is configured as a tag command, and optionally, each sub-instruction is configured as a tag command, and the security sequence is determined based on at least part of the multiple tag commands. Among them, the marking command includes at least one of the basic instructions, input parameter addresses and output parameter addresses for implementing the encryption operation instructions. The following description will be given by taking the basic instructions, input parameter addresses and output parameter addresses as an example, but the present invention is not limited to this. Each sub-command is set as a marking command, and the marking command is transmitted during the communication process. At this time, if a third party obtains the marking command during the communication process, it cannot obtain the specific sub-command, which prevents the intermediate variables and context results from being obtained by the non-encrypted unit and the private key from being deduced, thereby improving the security of the chip security module. The following description will be given in the form of a sub-command as a marking command, but the present invention is not limited to this.

[0062] The security sequence is determined according to the sub-instructions extracted from the corresponding encryption operation instruction. Optionally, the sub-instructions are configured in the form of tag commands. In an optional implementation, the security sequence is determined according to the tag commands extracted from the corresponding encryption operation instruction. The encryption operation instruction (such as an encryption algorithm or digital signature verification) can be decomposed into at least two basic instructions. In this embodiment, each basic instruction and the input parameter address and output parameter address corresponding to the basic instruction can be combined to generate at least two tag commands, and then the obtained at least two tag commands can be combined to generate a security sequence. In an optional implementation, this embodiment can generate corresponding tag commands according to all basic instructions obtained by decomposing the encryption operation instruction, and combine all tag commands to generate a security sequence. In another optional implementation, this embodiment can generate corresponding tag commands from some basic instructions (such as the main basic instructions in the encryption operation instruction) obtained by decomposing the encryption operation instruction, and combine the obtained tag commands to generate a security sequence. Therefore, the security sequence of this embodiment can represent the preset execution process of the corresponding encryption operation instruction, and then determine whether the current encryption operation is correct by comparing the instruction process of the current encryption operation instruction and the preset execution process represented by the security sequence, thereby ensuring the security of the chip. In one embodiment, the security sequence is set in the chip encryption unit or the chip storage unit in the chip security module. In another embodiment, the security sequence is set in other modules other than the chip encryption unit and the chip storage unit in the chip security module. The security sequence is readable only by the chip security module and cannot be rewritten once the protection is locked. Optionally, the security sequence can be written during the product debugging stage. By writing different security sequences to meet different application requirements, there is no need to modify the chip metal (metal layer) to achieve changes in requirements, thereby taking less time and lowering costs. Optionally, the security sequence cannot be rewritten after the product is mass-produced, thereby ensuring the security of the chip.

[0063] Furthermore, when the execution process of the encryption operation instruction does not match the corresponding security sequence, the corresponding processing action according to the actual application requirements may include a combination of one or more of the following: the chip security module controls the current encryption operation instruction not to output the execution result, the chip security module or other modules outside the chip security module controls the key and / or private key stored in the self-destruct chip security module, the chip storage unit in the self-destruct chip security module, controls the chip to freeze and controls the chip to restart, etc., to ensure the security of the chip and data.

[0064] Furthermore, if the execution process matches the corresponding security sequence, the chip security module controls the current encryption operation instruction to output the execution result. The execution result here includes the operation result and / or operation status of the current encryption operation instruction, and the operation status is used to characterize whether the current encryption operation instruction is successfully executed or whether the encryption operation corresponding to the current encryption operation instruction is successful. If the encryption operation fails to execute, encryption retry can be performed, or feedback can be given to the main control module to operate based on the main control module instruction, and this embodiment does not limit this.

[0065] Therefore, this embodiment can ensure chip security by pre-configuring the security sequence corresponding to the encryption operation instruction required by the application requirements, monitoring the execution process when executing the encryption operation instruction, and performing corresponding processing actions when the execution process is inconsistent with the pre-configured security sequence to avoid being deciphered, thereby ensuring data security. At the same time, this embodiment implements chip security monitoring through software configuration, so that it can meet different application requirements by pre-configuring different security sequences, while reducing the hardware cost required to ensure chip security.

[0066] Figure 2 FIG. 1 is a schematic diagram of another chip security module according to an embodiment of the present invention. In another optional implementation, Figure 2 As shown, the chip security module includes a chip encryption unit 13 and a chip storage unit 14. Among them, the chip storage unit 14 is configured to store at least one set of security sequences. Optionally, the chip storage unit 14 is also configured to store keys and / or private keys. Further, the chip storage unit 14 is a protected and independent storage unit, such as a Flash area storage unit, etc., to further avoid the leakage of security sequences, keys and / or private keys, and ensure data security. Optionally, the chip storage unit 14 can also store other parameters required for encryption. The specific parameters can be determined based on the encryption algorithm used in the actual application requirements, and this embodiment does not limit this.

[0067] Further optionally, the chip security module of this embodiment also includes a software code unit 11 and a register unit 12. The software code unit 11 and the chip encryption unit 13 are respectively connected to the register unit 12, and can perform read and write operations. Optionally, the software code unit 11 can also be connected to the chip encryption unit 13, so that when the software code unit 11 receives an encryption request, the software code unit 11 calls and starts the chip encryption unit 13. The chip encryption unit 13 is also connected to the chip storage unit 14, and can read the security sequence, parameters required for encryption, keys and / or private keys, etc. from the chip storage unit 14 to implement encryption operations.

[0068] Optionally, the chip security module of this embodiment controls the software code unit 11 to interact with the main control module, and enables the chip encryption unit 13 to strictly control the output to ensure that the security sequence, parameters required for encryption, keys and / or private keys and other data cannot be obtained through external connections, so as to further ensure the security of the chip and data. Optionally, the main control module can be the central processing unit of the chip, or other processing units or devices, and this embodiment does not limit this.

[0069] It should be understood that the above connection method is merely exemplary and is not limited to this embodiment. For example, the chip encryption unit 13 can self-start the execution of corresponding encryption operation instructions by monitoring the status of the register unit 12. In this case, it does not need to communicate and interact with the software code unit 11.

[0070] When the data needs to be encrypted, the main control module sends an encryption request to the software code unit 11, and the encryption request includes input parameters and encryption operation instructions. In this embodiment, the input parameters can specifically be the data to be encrypted. In another optional implementation, if the software code unit 11 is pre-configured with encryption operation instructions required for various types of data to be encrypted, the encryption request can include the data to be encrypted. The software code unit 11 can obtain the corresponding encryption operation instructions based on the type of data to be encrypted.

[0071] Further, the software code unit 11 is configured to extract at least two tag commands from the encryption operation instruction, and pass the at least two tag commands to the chip encryption unit 13 through the register unit 12. The chip encryption unit 13 is configured to perform corresponding encryption operations according to the at least two tag commands.

[0072] Further, the software code unit 11 is configured to obtain the corresponding encryption operation instruction according to the encryption request, and extract at least two marking commands from the encryption operation instruction. Further, the software code unit 11 can decompose the obtained encryption operation instruction, obtain the corresponding at least two basic instructions and the input and output parameters corresponding to each basic instruction, so as to generate at least two marking commands including basic instructions, input parameter addresses and output parameter addresses. Optionally, the marking command includes two parts, ID and Data, the ID part is used to store the basic instructions of a step after the encryption operation instruction is decomposed, and the Data part is used to store the relevant input parameter address and / or output parameter address. The input parameter address and the output parameter address are used to indicate the address for storing the input parameters and the output parameters, and the output parameters include intermediate output parameters and output results. Among them, the intermediate output parameter is used to characterize the output result of the non-last marking command, and the output result is used to characterize the output result of the last marking command, that is, the output result of the encryption operation instruction.

[0073] In an optional implementation, the register unit 12 may be used only to pass the marking command to the chip encryption unit 13, or may implement both the passing of the marking command and the parameter cache and output result cache of the encryption operation instruction. The parameter cache of the encryption operation instruction includes the parameters contained in the encryption operation instruction itself (that is, it does not include the intermediate output result of the decomposed basic instruction), for example, the input parameter. Furthermore, if the register unit 12 is only used to pass the marking command to the chip encryption unit 13, the chip security module of this embodiment may also include a parameter register ( Figure 2 (not shown) to cache the parameters and output results of the encryption operation instructions to facilitate data transmission.

[0074] Furthermore, the software code unit 11 writes the acquired tag command of the encryption operation instruction into the register unit 12. The chip encryption unit 13 reads the tag command of the encryption operation instruction from the register unit 12 after being called and started by the software code unit 11 or self-started by monitoring the state change of the register unit 12.

[0075] In an optional implementation, the chip encryption unit 13 executes the encryption operation instruction and monitors the execution process. After startup, the chip encryption unit 13 reads the corresponding tag command from the register unit 12, and obtains the security sequence, encryption parameters, keys and / or private keys corresponding to the encryption operation instruction from the chip storage unit 14, and executes each tag command (i.e., the sub-instruction of the encryption operation instruction) in sequence based on the obtained encryption parameters, keys and / or private keys, and monitors the execution process of the encryption operation instruction at the same time, obtains the executed tag command sequence, and determines whether the tag command sequence matches the corresponding security sequence, thereby determining whether the execution process of the encryption operation instruction matches the corresponding security sequence. If the execution process of the encryption operation instruction matches the corresponding security sequence, the chip security module controls the current encryption operation to output the execution result, and returns the output execution result to the main control module through the register unit 12 or the parameter register. Further, after the chip encryption unit 13 executes the encryption operation instruction, the execution result is written into the register unit 12 or the parameter register, and the software code unit 11 reads the execution result of the encrypted output from the register unit 12 or the parameter register and returns it to the main control module. In other optional implementations, the main control module can also directly read the execution result of the encryption request from the register unit 12 or the parameter register, and this embodiment does not limit this. Among them, the execution result includes the operation result and / or operation status of the execution of this encryption operation instruction, and the operation status is used to characterize whether the encryption operation instruction is successfully executed or whether the encryption operation corresponding to the encryption operation instruction is successful. If the execution process of the encryption operation instruction does not match the corresponding security sequence, the corresponding processing action is performed according to the actual application requirements. Further, the execution process of the encryption operation instruction of this embodiment matches the corresponding security sequence to characterize that the marking commands in the security sequence are all located in the marking command sequence currently executed, and the corresponding marking commands are in the same order in the two sequences.

[0076] Optionally, the security sequence is predetermined based on the tag command extracted from the corresponding encryption operation instruction and burned into the chip storage unit 14. The security sequence includes three parts: Group Header, Data and End.

[0077] Figure 3 FIG. 1 is a schematic diagram of the generation process of the security sequence according to an embodiment of the present invention. Figure 3As shown, taking the encryption operation instruction f=x+yz as an example, this embodiment can decompose and convert the encryption operation instruction into multiple tags (i.e., tag commands). Specifically, in this embodiment, the encryption operation instruction f=x+yz is split and converted into 3 tag commands: Tag0 (a, x, y, d), Tag1 (e, d, z, h), Tag2 (r, h, f), and then Tag0-Tag2 are arranged and merged in sequence as the data part of the security sequence. Among them, Tag0 represents d=x+y, a represents the addition instruction, x and y are the two input parameter addresses of the addition operation, and d is the address of the intermediate output parameter for storing x+y. Tag1 represents h=dz, e represents the subtraction instruction, d and z are the two input parameter addresses of the subtraction operation, and h is the address of the intermediate output parameter for storing dz. Tag2 represents the data stored in address h is taken out and stored in the register address f, r represents the result fetch instruction, and f is the register address. Furthermore, a security sequence is generated based on Tag0(a,x,y,d), Tag1(e,d,z,h), and Tag2(r,h,f). Figure 3 As shown, the security sequence includes a sequence header (Tag[0xA_]), sequence data (Tag0Tag1Tag2) and an end mark (0xFFFF), wherein the sequence header is used to identify the encryption operation instruction corresponding to the security sequence, and the sequence data is formed by a tag command extracted from the corresponding encryption operation instruction.

[0078] Optionally, after generating the security sequence based on the above method, this embodiment will burn the security sequence and the parameters, keys and / or private keys required for encryption into the chip storage unit 14 to achieve subsequent encryption operations and security monitoring. It should be understood that this embodiment does not limit the format of the marking command and the storage format of the security sequence, which can achieve subsequent monitoring and comparison.

[0079] Optionally, the chip storage unit 14 may be a Flash Memory (a type of electronic non-volatile computer memory), or may be a region directly fixed in the chip, which is not limited in this embodiment. After writing the security sequence, parameters required for encryption, keys and / or private keys, the chip storage unit 14 enters a protection lock state, prohibiting any rewrite operation, and only the chip encryption unit 13 is readable to ensure chip and data security.

[0080] In practical applications, a chip may need to undertake multiple different tasks, and multiple encryption operation instructions may be involved in the process. Therefore, in the above embodiment, a sequence header corresponding to the encryption operation instruction is set to identify the corresponding security sequence to be used when executing different encryption operation instructions. In an optional implementation, if the chip function is relatively simple, the chip security module only executes one encryption operation instruction, and only one set of security sequences is stored in the chip storage unit 14. At this time, the header sequence and the terminator part in the security sequence can be removed, and only the data part is retained to save storage space and improve loading efficiency.

[0081] Further optionally, the chip security module of this embodiment is also configured to query the sequence header of each security sequence according to the currently executed encryption operation instruction to obtain the security sequence corresponding to the currently executed encryption operation instruction. In an optional implementation, this embodiment can monitor the execution process of the encryption operation instruction through the chip encryption unit 13, that is, when the chip encryption unit 13 executes the marking command corresponding to the encryption operation instruction, it obtains the executed marking command sequence, and queries the sequence header of each security sequence in the chip storage unit 14 based on the encryption operation instruction corresponding to the executed marking command, so as to obtain the security sequence corresponding to the currently executed encryption operation instruction, and then compares the executed marking command sequence and the security sequence. In other optional implementations, this embodiment can configure other security monitoring modules to obtain the executed marking command sequence from the chip encryption unit 13, and query the sequence header of each security sequence in the chip storage unit 14 based on the currently executed encryption operation instruction, so as to obtain the security sequence corresponding to the currently executed encryption operation instruction, and then compare the executed marking command sequence and the security sequence.

[0082] Figure 4 Schematic diagram of the chip encryption unit 13 of the embodiment of the present invention. In an optional implementation, the present embodiment takes the encryption process of the chip encryption unit 13 monitoring the encryption operation instruction as an example. Figure 4 As shown, the chip encryption unit 13 of the embodiment of the present invention includes a microprocessor 131 , a hardware monitor 132 and a buffer 133 .

[0083] The microprocessor 131 is configured to obtain and sequentially execute at least two marking commands from the register unit 12, and selectively write the output parameters of each marking command into the buffer 133, for example, write the output parameters of each marking command except the last marking command into the buffer 133, which can be determined according to the actual application situation, and this embodiment does not limit this. Specifically, the microprocessor 131 reads the marking command from the register unit 12, obtains the input parameters according to the input parameter address in the marking command, and reads the security sequence, the parameters required for encryption, the key and / or the private key from the chip storage unit 14, calculates the input parameters according to the parameters required for encryption, the key and / or the private key and the basic instructions in the marking command, obtains the output parameters, and stores them according to the location indicated by the output parameter address. In different marking commands, the output parameter can be an intermediate output parameter or an output result, the intermediate output parameter is used to characterize the output result of the non-last marking command, and the output result is used to characterize the output result of the last marking command, and the intermediate output parameter address is located in the buffer 133.

[0084] Optionally, the cache 133 may be a buffer or other storage area that can meet the requirements, and this embodiment does not limit this. The cache 133 has access restrictions and can only be accessed from within the chip encryption unit 13. In this way, it is possible to prevent the intermediate variables or context results from being obtained externally, resulting in reverse calculation of the key and / or private key, further improving data security.

[0085] During the execution of the microprocessor 131 , the hardware monitor 132 continuously monitors the operating status of the register unit 12 and / or the microprocessor 131 to ensure that the software code unit 11 is not invaded. Figure 5 1 is a schematic diagram of the monitoring process of the hardware monitor 132 according to an embodiment of the present invention.

[0086] like Figure 5 As shown, the specific steps of the monitoring process are as follows:

[0087] Step S510, obtain the marking command corresponding to the encryption operation instruction being executed. The source of the marking command is obtained by monitoring the operating state of the register unit 12 and / or the microprocessor 131. Optionally, it can be obtained only by monitoring the register unit 12, or only by monitoring the operating state of the microprocessor 131, or it can also monitor the operating state of the register unit 12 and the microprocessor 131 at the same time to ensure the reliability of the monitoring data, which is not limited in this embodiment.

[0088] Step S520, converting the marking command into a marking command sequence. The process of determining the marking command sequence is similar to the process of determining the data portion of the security sequence described above, and will not be described in detail here.

[0089] Step S530: query the sequence header of each security sequence according to the encryption operation instruction currently being executed to obtain the security sequence corresponding to the encryption operation instruction currently being executed.

[0090] Step S540, determine whether the tag command sequence matches the security sequence. Since the data portion of the security sequence is formed by the tag command extracted from the corresponding encryption operation instruction, the data portion in the aforementioned security sequence is the tag command sequence under ideal circumstances. The chip encryption unit 13 of this embodiment can asynchronously execute encryption operation instructions and monitor, that is, determine the tag command sequence in real time during the encryption operation instruction process, and compare the tag commands in the tag command sequence with the security sequence in turn, and stop executing the encryption operation instruction in time when there is no match, or perform other processing actions. In another optional implementation, the chip encryption unit 13 of this embodiment can obtain the complete tag command sequence corresponding to the executed encryption operation instruction after the execution of the encryption operation instruction is completed, and determine whether it matches the corresponding security sequence. This embodiment does not limit the specific comparison method, and it can be configured based on the specific application.

[0091] Optionally, step S530 and step S540 may be executed by a hardware monitor, or may be executed by other units, such as an additional digital hardware unit, which is not limited in this embodiment.

[0092] In an optional implementation, the security sequence may also be generated based on the key parts of all the marked commands extracted from the encryption operation instruction (e.g., the main basic instructions in the encryption operation instruction). In this case, the security sequence may only include a part of the marked command sequence, and the hardware monitor 132 may set different matching rules for the security sequence, such as whether the security sequence can match at least a part of the marked command sequence, to meet different requirements.

[0093] Specifically, if the marking command sequence does not match the security sequence, it means that the software code unit may have been exposed to an intruder, and the intruder attempts to reversely calculate the key and / or private key through the output result of the encryption operation. It is necessary to make corresponding processing actions according to the actual application requirements to protect the output result and ensure data security. Optionally, in response to the hardware monitor 132 monitoring that the marking command sequence does not match the security sequence, the processing actions made include controlling the current encryption operation not to output the execution result, self-destructing the key and / or private key, self-destructing the chip storage unit 14, controlling the chip to crash, and / or controlling the chip to restart. In actual applications, one of the above strategies or a combination of multiple strategies can be selected according to the chip confidentiality level and importance, and other feasible strategies can also be adopted according to actual conditions. This embodiment does not limit this.

[0094] If the hardware monitor 132 detects that the marked command sequence matches the security sequence, the execution result is output so that the software code unit 11 reads the execution result for feedback. The execution result includes the operation result and / or the operation status, and the operation status is used to characterize whether the operation is successful or whether the operation is executed smoothly. Optionally, the chip encryption unit 13 can write the output result into the register unit 12 in the form of a marked command, or directly write the output result into the parameter register to realize the feedback of the encryption result.

[0095] Furthermore, if the encryption operation fails, the software code unit 11 may control the retry of the encryption operation, or feedback to the main control module so as to perform operations based on the instructions of the main control module, which is not limited in this embodiment.

[0096] The embodiment of the present invention monitors the execution process of the executed encryption operation instruction and determines whether it matches the corresponding security sequence. In response to the execution process of the encryption operation instruction matching the corresponding security sequence, the embodiment of the present invention controls the current encryption operation instruction to output the execution result. In response to the execution process of the encryption operation instruction not matching the corresponding security sequence, the embodiment of the present invention performs corresponding processing actions according to actual application requirements, wherein the security sequence is used to characterize the preset execution process of the corresponding encryption operation instruction. Therefore, the embodiment of the present invention can improve the chip security, and because the embodiment of the present invention performs monitoring at the software level, it can meet different application requirements by configuring different security sequences, while reducing the chip design cost.

[0097] Figure 6 is a flowchart of a security encryption method according to an embodiment of the present invention. Further, an embodiment of the present invention also provides a security encryption method, which is applied to a chip security module, such as Figure 6 As shown, the secure encryption method includes the following steps:

[0098] S610, executing the encryption operation instruction and monitoring the execution process of the encryption operation instruction.

[0099] S620, determining whether the execution process matches the corresponding security sequence. The security sequence is used to represent the preset execution process of the corresponding encryption operation instruction.

[0100] If the execution process does not match the corresponding safety sequence, step S630 is executed to perform corresponding processing actions according to actual application requirements.

[0101] If the execution process matches the corresponding security sequence, step S631 is executed to control the current encryption operation instruction to output the execution result.

[0102] In one embodiment, step S610 includes: receiving multiple sub-instructions extracted from the corresponding encryption operation instruction, executing each sub-instruction, and monitoring the execution order of each sub-instruction.

[0103] Further, in one embodiment, the number of the plurality of sub-instructions is the same as the number of sequences in the security sequence. At this time, the execution order of each sub-sequence corresponds to the sequence in the corresponding security sequence one by one. In another embodiment, the security sequence is determined based on at least part of the plurality of tag commands, and the number of sequences in the security sequence is less than the number of the plurality of sub-instructions. In an optional implementation, each sub-instruction is configured as a tag command, and optionally, each sub-instruction is configured as a tag command. Wherein, the tag command includes at least one of a basic instruction for implementing the encryption operation instruction, an input parameter address, and an output parameter address.

[0104] The security sequence is determined based on the sub-instructions extracted from the corresponding encryption operation instructions. Optionally, the sub-instructions are configured in the form of marking commands. In an optional implementation, the security sequence is determined based on the marking commands extracted from the corresponding encryption operation instructions, and the marking commands include at least one of the basic instructions, input parameter addresses, and output parameter addresses for implementing the encryption operation instructions. Among them, the input parameter address and the output parameter address represent the storage location of the input and output parameters, and the actual parameter values ​​are not stored in the marking command. The output parameter address includes an intermediate output parameter address and an output result address. The intermediate output parameter address and the output result address are located in different storage units. The intermediate output parameter address is used to represent the output result of the non-last marking command, and the outside world does not have read and write permissions. The output result is used to represent the output result of the last marking command, that is, the output result of the encryption operation instruction.

[0105] The encryption operation instruction (i.e., the encryption algorithm) can be decomposed into at least two basic instructions. This embodiment can combine each basic instruction and the input and output corresponding to the basic instruction to generate a tag command, and then the at least two tag commands obtained can be combined to generate a security sequence. In an optional implementation, this embodiment can generate corresponding tag commands from all basic instructions obtained by decomposing the encryption operation instruction, and combine all tag commands to generate a security sequence. In another optional implementation, this embodiment can generate corresponding tag commands from some basic instructions (such as the main basic instructions in the encryption operation instruction) obtained by decomposing the encryption operation instruction, and combine the obtained tag commands to generate a security sequence. Therefore, the security sequence of this embodiment can represent the preset execution process of the corresponding encryption operation instruction, and then determine whether the current encryption operation is correct by comparing the execution process of the current encryption operation instruction with the preset execution process represented by the security sequence, thereby ensuring chip security.

[0106] In an optional implementation, executing the encryption operation instruction includes: receiving an encryption request, and in response to receiving the encryption operation request, executing the corresponding encryption operation instruction according to the encryption request.

[0107] In an optional implementation, the security sequence includes a sequence header, sequence data and an end character. The sequence header is used to identify the encryption operation instruction corresponding to the security sequence. The sequence data is formed by a marking command extracted from the corresponding encryption operation instruction and is used to characterize a predetermined marking command execution process (that is, the preset execution process of the corresponding encryption operation instruction).

[0108] Furthermore, determining whether the execution process matches the corresponding security sequence also includes: obtaining a marked command sequence corresponding to the encryption operation instruction, querying the sequence header of each security sequence according to the currently executed encryption operation instruction to obtain the security sequence corresponding to the currently executed encryption operation instruction, obtaining at least two marked commands corresponding to the currently executed encryption operation instruction, generating a marked command sequence, and determining whether the marked command sequence matches the corresponding security sequence.

[0109] In an optional implementation, at least one of the security sequence, parameters required for encryption, keys and / or private keys is stored separately in a chip storage unit. The processing action performed when the execution process does not match the corresponding security sequence includes a combination of one or more of the following: controlling the current encryption operation instruction not to output the execution result, the keys and / or private keys stored in the self-destruct chip security module, the chip storage unit in the self-destruct chip security module, controlling the chip to freeze, and controlling the chip to restart.

[0110] In an optional implementation, if the execution process matches the corresponding security sequence, the current encryption operation instruction is controlled to output the execution result. The execution result here includes the operation result and / or operation status of the current encryption operation instruction, and the operation status is used to characterize whether the current encryption operation instruction is successfully executed or whether the encryption operation corresponding to the current encryption operation instruction is successful. If the encryption operation fails to execute, encryption retry can be performed, or feedback can be given to the main control module to operate based on the main control module instruction, and this embodiment does not limit this.

[0111] The embodiment of the present invention monitors the executed encryption operation instructions and determines whether they match the corresponding security sequence. In response to the execution process of the encryption operation instruction matching the corresponding security sequence, the embodiment of the present invention controls the current encryption operation instruction to output the execution result. In response to the execution process of the encryption operation instruction not matching the corresponding security sequence, the embodiment of the present invention performs corresponding processing actions according to actual application requirements, wherein the security sequence is used to characterize the preset execution process of the corresponding encryption operation instruction. Therefore, the embodiment of the present invention can improve the chip security, and because the embodiment of the present invention performs monitoring at the software level, it can meet different application requirements by configuring different security sequences, while reducing the chip design cost.

[0112] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip security module, characterized in that: The chip security module includes a chip encryption unit, which is configured to execute encryption operation instructions, monitor the execution process of the encryption operation instructions, and determine whether the execution process of the encryption operation instructions matches the corresponding security sequence; If the execution process of the encryption operation instruction matches the corresponding security sequence, the chip security module controls the current encryption operation instruction to output the execution result; and If the execution process of the encryption operation instruction does not match the corresponding security sequence, perform corresponding processing actions according to actual application requirements; The security sequence is used to characterize the preset execution process of the corresponding encryption operation instruction.

2. The chip security module according to claim 1, characterized in that: The chip encryption unit receives and executes a plurality of sub-instructions extracted from the corresponding encryption operation instruction, monitors the execution order of each sub-instruction, and determines whether the execution order matches the corresponding security sequence.

3. The chip security module according to claim 2, characterized in that: The security sequence is determined according to sub-instructions extracted from the corresponding encryption operation instructions and is preset in the chip security module.

4. The chip security module according to claim 1, characterized in that: The chip encryption unit receives and executes a plurality of tag commands extracted from corresponding encryption operation instructions, monitors the execution order of each tag command, and determines whether the execution order matches the corresponding security sequence.

5. The chip security module according to claim 4, characterized in that: The security sequence is determined according to a tag command extracted from a corresponding encryption operation instruction and is preset in the chip security module; The marking command includes at least one of a basic instruction for implementing the encryption operation instruction, an input parameter address, and an output parameter address.

6. The chip security module according to claim 4, characterized in that: The security sequence is determined based on at least a portion of the plurality of marking commands.

7. The chip security module according to claim 1, characterized in that: The chip security module also includes: The chip storage unit is configured to store at least one set of the security sequence, key and / or private key.

8. The chip security module according to claim 1, characterized in that: The processing action includes a combination of one or more of the following: controlling the current encryption operation instruction not to output the execution result, self-destructing the key and / or private key stored in the chip security module, self-destructing the chip storage unit in the chip security module, controlling the chip to freeze, and controlling the chip to restart.

9. The chip security module according to claim 1, characterized in that: The chip security module also includes a software code unit and a register unit. The software code unit is configured to extract multiple tag commands from the encryption operation instructions and pass the multiple tag commands to the chip encryption unit through the register unit. The chip encryption unit is configured to perform corresponding encryption operations according to the multiple tag commands.

10. The chip security module according to claim 1, characterized in that: The security sequence includes a sequence header, sequence data and a terminator, wherein the sequence header is used to identify the encryption operation instruction corresponding to the security sequence, and the sequence data is formed by a marking command extracted from the corresponding encryption operation instruction.

11. The chip security module according to claim 10, characterized in that: The chip security module is further configured to query the sequence header of each of the security sequences according to the currently executed encryption operation instruction to obtain the security sequence corresponding to the currently executed encryption operation instruction.

12. The chip security module according to claim 9, characterized in that: The chip encryption unit includes a microprocessor and a buffer; The microprocessor is configured to obtain and sequentially execute the plurality of tag commands from the register unit, and selectively write output parameters of each of the tag commands into the buffer.

13. The chip security module according to claim 12, characterized in that: The chip encryption unit also includes a hardware monitor, which is configured to monitor the operating status of the register unit or the microprocessor, and obtain a tag command sequence formed by multiple tag commands corresponding to the encryption operation instructions executed by the microprocessor to determine whether the tag command sequence matches the corresponding security sequence.

14. A security encryption method, applied to a chip security module, characterized in that: The method comprises: Executing an encryption operation instruction, monitoring the execution process of the encryption operation instruction, and determining whether the execution process of the encryption operation instruction matches the corresponding security sequence; If the execution process of the encryption operation instruction matches the corresponding security sequence, controlling the current encryption operation instruction to output an execution result; and If the execution process of the encryption operation instruction does not match the corresponding security sequence, perform corresponding processing actions according to actual application requirements; The security sequence is used to characterize the preset execution process of the corresponding encryption operation instruction.

15. The method according to claim 14, characterized in that The executing the encryption operation instruction, monitoring the execution process of the encryption operation instruction, and determining whether the execution process of the encryption operation instruction matches the corresponding security sequence includes: Receive and execute multiple sub-instructions extracted from the corresponding encryption operation instruction, monitor the execution order of each sub-instruction, and determine whether the execution order matches the corresponding security sequence.

16. The method according to claim 15, characterized in that The security sequence is determined according to sub-instructions extracted from the corresponding encryption operation instructions and is preset in the chip security module.

17. The method according to claim 14, characterized in that The executing the encryption operation instruction, monitoring the execution process of the encryption operation instruction, and determining whether the execution process of the encryption operation instruction matches the corresponding security sequence includes: Receive and execute multiple tag commands extracted from corresponding encryption operation instructions, monitor the execution order of each tag command, and determine whether the execution order matches the corresponding security sequence.

18. The method according to claim 17, characterized in that The security sequence is determined according to a tag command extracted from a corresponding encryption operation instruction and is preset in the chip security module; The marking command includes at least one of a basic instruction for implementing the encryption operation instruction, an input parameter address, and an output parameter address.

19. The method according to claim 17, characterized in that The security sequence is determined based on at least a portion of the plurality of marking commands.

20. The method according to claim 14, characterized in that The execution of the encryption operation instruction also includes: receiving an encryption request; In response to receiving the encryption request, a corresponding encryption operation instruction is executed according to the encryption request.

21. The method according to claim 14, characterized in that The security sequence includes a sequence header, sequence data and a terminator, wherein the sequence header is used to identify the encryption operation instruction corresponding to the security sequence, and the sequence data is formed by a marking command extracted from the corresponding encryption operation instruction.

22. The method according to claim 21, characterized in that The method further comprises: Acquire a marking command sequence formed by a plurality of marking commands corresponding to the encryption operation instruction; Querying a sequence header of at least one security sequence according to the encryption operation instruction to obtain a security sequence corresponding to the encryption operation instruction; Determine whether the marking command sequence matches the corresponding security sequence.

23. The method according to claim 14, characterized in that The processing action includes a combination of one or more of the following: controlling the current encryption operation instruction not to output the execution result, self-destructing the key and / or private key stored in the chip security module, self-destructing the chip storage unit in the chip security module, controlling the chip to freeze, and controlling the chip to restart.

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