Semiconductor device simulation method based on graph attention neural network

Abstract

The invention provides a semiconductor device simulation method based on a graph attention neural network, and relates to the technical field of semiconductor device simulation. The semiconductor device simulation method comprises the following steps: generating a heterogeneous attribute graph according to a netlist file of a semiconductor device; according to attention information between each node and a neighborhood node in the heterogeneous attribute graph, obtaining an embedded representation of the node in a graph attention layer, and stacking the graph attention layer to obtain a final embedded representation of the node; and obtaining a simulation model of the semiconductor device according to the final embedding representation of the nodes, the graph pooling layer and the full connection layer. The physical information of the semiconductor device is unified through the heterogeneous attribute graph, the importance of different areas is adaptively learned by using the graph attention layer, so that the features of the device are efficiently extracted, key features are highlighted, the simulation precision of the semiconductor device can be greatly improved, the simulation speed is high, the calculation difficulty is small, and the method is suitable for large-scale popularization and application. And the efficiency requirement of device design and development is effectively met.

Description

Technical Field

[0001] The present application relates to the field of semiconductor device simulation technology. Specifically, the present application relates to a semiconductor device simulation method based on a graph attention neural network. Background Art

[0002] DTCO (Decign Technology Co Optimization) is an emerging design and process collaborative optimization paradigm. By building a bridge between devices, processes and designs, it achieves global optimization of parameter space at a higher level. It is expected to break through the performance upgrade bottleneck of Moore's Law and continue the development of the semiconductor industry.

[0003] Semiconductor device simulation is one of the key links in the DTCO process, and its goal is to establish a high-fidelity mapping relationship between device structure, process parameters and performance indicators. Accurate and efficient device simulation can accelerate the convergence of the DTCO process, shorten the design iteration cycle, and reduce the cost of trial and error. However, traditional TCAD simulation methods require fine meshing of the device's geometric structure and solving the semiconductor transport equations. The calculations are difficult and time-consuming, and it is difficult to meet the efficiency requirements of device design and development in the industry. Summary of the invention

[0004] The embodiment of the present application provides a semiconductor device simulation method based on a graph attention neural network, which can solve the problems of high computational difficulty and time consumption of semiconductor device simulation and difficulty in meeting design and development needs.

[0005] In order to achieve this purpose, the embodiments of the present application provide the following solutions.

[0006] According to one aspect of an embodiment of the present application, a semiconductor device simulation method based on a graph attention neural network is provided, wherein the graph attention neural network includes a graph attention layer, a graph pooling layer, and a fully connected layer, and the method includes:

[0007] generating a heterogeneous property graph according to a netlist file of a semiconductor device, wherein the netlist file includes a device structure and simulation information;

[0008] Obtaining an embedded representation of the node in a graph attention layer according to attention information between each node and its neighboring nodes in the heterogeneous attribute graph, and stacking the graph attention layers to obtain a final embedded representation of the node, wherein the attention information includes an attention coefficient and an attention weight;

[0009] A simulation model of the semiconductor device is obtained according to the final embedding representation of the node, the graph pooling layer, and the fully connected layer.

[0010] In a possible implementation, generating a heterogeneous property graph according to a netlist file of a semiconductor device includes:

[0011] Acquire component region information and interaction information of the semiconductor device according to the netlist file, wherein the component region information includes the component region of the semiconductor device and attribute information of the component region, and the interaction information includes interaction between component regions and information of the interaction;

[0012] The heterogeneous property graph is generated based on the composition region information and the interaction information.

[0013] In a possible implementation, obtaining an embedded representation of the node in the graph attention layer according to the attention information between each node and its neighboring nodes in the heterogeneous attribute graph includes:

[0014] For each graph attention layer, calculate the attention coefficient of each node to its neighboring nodes, and obtain the attention weight according to the attention coefficient;

[0015] The information of the neighborhood nodes is aggregated according to the attention weights to obtain an embedded representation of the node in the graph attention layer.

[0016] In a possible implementation, obtaining an attention weight according to the attention coefficient includes:

[0017] The attention coefficient is normalized, and the attention weight of each node to its neighboring nodes is obtained according to the normalized result.

[0018] In a possible implementation, the calculation formula of the attention coefficient is:

[0019] in, is the attention coefficient of the c-th graph attention layer, which measures the node v j For node v i The importance of is the attention function of the c-th graph attention layer, is node v i The embedding representation at the c-1th graph attention layer, is node v j The embedding representation at the c-1th graph attention layer, For edge e ij The properties of e ij Represents the connection node v i and node v j edge.

[0020] In one possible implementation, node v iThe embedding representation at the cth graph attention layer is:

[0021]

[0022] in, is the message passing function of the c-th graph attention layer, is the node v in the cth graph attention layer i To its neighboring node v j is the attention weight, and σ is the activation function.

[0023] In a possible implementation, stacking the graph attention layer includes:

[0024] Obtain the embedding representations of all nodes at different graph attention layers, and obtain the node embedding matrix of each graph attention layer according to the embedding representation and the mapping function of the graph attention layer.

[0025] In a possible implementation, obtaining the simulation model of the semiconductor device according to the final embedded representation of the node, the graph pooling layer, and the fully connected layer includes:

[0026] Using the graph pooling layer and the embedded representation of all nodes, a graph representation vector is generated to represent the device features;

[0027] Parameters of the simulation model are obtained according to the graph representation vector and the fully connected layer, and the simulation model is obtained based on the parameters.

[0028] In a possible implementation, the step of generating a graph representation vector for representing device features by using a graph pooling layer and an embedded representation of all nodes includes:

[0029] The graph pooling layer is used to aggregate the embedded representations of all nodes into a fixed-length vector.

[0030] In a possible implementation, the fully connected layer includes a first hidden layer, a second hidden layer, and an output layer, and acquiring the parameters of the simulation model according to the graph representation vector and the fully connected layer includes:

[0031] Obtaining a first hidden feature corresponding to the graph representation vector using the graph representation vector and the first hidden layer;

[0032] Obtaining a second hidden feature corresponding to the first hidden feature according to the first hidden feature and the second hidden layer;

[0033] The parameter is obtained according to the second hidden feature and the output layer.

[0034] The beneficial effects of the technical solution provided by the embodiment of the present application are:

[0035] The layout file generation method provided by the present application includes generating a heterogeneous attribute graph according to a netlist file of a semiconductor device, wherein the netlist file includes a device structure and simulation information; obtaining an embedded representation of the node in the graph attention layer according to the attention information between each node and its neighboring nodes in the heterogeneous attribute graph, stacking the graph attention layer to obtain the final embedded representation of the node, and the attention information includes an attention coefficient and an attention weight; obtaining a simulation model of the semiconductor device according to the final embedded representation of the node, the graph pooling layer, and the fully connected layer. The implementation of the present application unifies the physical information of semiconductor devices through heterogeneous attribute graphs, and uses the graph attention layer to adaptively learn the importance of different regions, thereby efficiently extracting the features of the device and highlighting the key features, greatly improving the accuracy of semiconductor device simulation, and the simulation speed is fast, the calculation difficulty is small, and the efficiency requirements of device design and development are effectively met. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in describing the embodiments of the present application.

[0037] Figure 1 A flowchart of a semiconductor device simulation method based on a graph attention neural network provided in an embodiment of the present application;

[0038] Figure 2 A flowchart of a semiconductor device simulation method provided in an embodiment of the present application;

[0039] Figure 3 A schematic diagram of a netlist file provided for an embodiment of the present application;

[0040] Figure 4 A schematic diagram of a graph attention network provided for an embodiment of the present application. DETAILED DESCRIPTION

[0041] The embodiments of the present application are described below in conjunction with the drawings in the present application. It should be understood that the implementation methods described below in conjunction with the drawings are exemplary descriptions for explaining the technical solutions of the embodiments of the present application and do not constitute a limitation on the technical solutions of the embodiments of the present application.

[0042] It will be understood by those skilled in the art that, unless specifically stated, the singular forms "one", "said", and "the" used herein may also include plural forms. It should be further understood that the terms "including" and "comprising" used in the embodiments of the present application refer to that the corresponding features can be implemented as the presented features, information, data, steps, operations, elements and / or components, but do not exclude the implementation of other features, information, data, steps, operations, elements, components and / or combinations thereof supported by the present technical field. It should be understood that when we say that an element is "connected" or "coupled" to another element, the one element may be directly connected or coupled to the other element, or it may refer to that the one element and the other element establish a connection relationship through an intermediate element. In addition, the "connection" or "coupling" used herein may include wireless connection or wireless coupling. The term "and / or" used herein indicates at least one of the items defined by the term, for example, "A and / or B" indicates that it is implemented as "A", or is implemented as "A", or is implemented as "A and B".

[0043] In order to make the objectives, technical solutions and advantages of the present invention more clear, the embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0044] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present invention and the technical effects produced by the technical solutions of the present invention. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0045] The semiconductor device simulation method based on graph attention neural network provided in this application is intended to solve at least one technical problem existing in the prior art.

[0046] An embodiment of the present application provides a semiconductor device simulation method based on a graph attention neural network, wherein the graph attention neural network includes an attention layer, a graph pooling layer and a fully connected layer, the graph pooling layer is respectively connected to the graph attention layer and the fully connected layer, and the graph attention neural network is used to obtain a simulation model of the semiconductor device.

[0047] Alternatively, if Figure 1-Figure 4 As shown, the semiconductor device simulation method based on the graph attention neural network includes:

[0048] S101: Generate a heterogeneous property graph according to a netlist file of a semiconductor device.

[0049] Optionally, the netlist file includes device structure and simulation information.

[0050] In one embodiment, the semiconductor device may be a 14 nm FinFET, such as Figure 3 As shown, the netlist file includes the structure, position, material, node netlist text of the semiconductor device and the simulation information text of the semiconductor device, the front schematic diagram, the side profile schematic diagram, the adjacency matrix, the node characteristics, the output to be predicted and other information that can describe the structure of the semiconductor device and be used for semiconductor device simulation.

[0051] Optionally, a heterogeneous property graph is generated based on a netlist file of a semiconductor device, including: obtaining component region information and interaction information of the semiconductor device based on the netlist file, the component region information including component regions of the semiconductor device and property information of the component regions, the interaction information including interactions between component intervals and information on the interactions; and generating a heterogeneous property graph based on the component region information and the interaction information.

[0052] In one embodiment, the heterogeneous attribute graph is defined as:

[0053]

[0054] Where v is a node set, representing the component area of ​​the device, V = {v 1 , v 2 , ..., v |V|}, |V| is the number of nodes; E is the edge set, which represents the interaction between regions, e ij Represents the connection node v i With node v j The side of H v is a set of node attributes. For any node v i ∈V, its properties is a d-dimensional real-valued vector containing the material, doping, geometry and other characteristics of the device area:

[0055]

[0056] in, Represents node v i The k-th attribute value of , such as the material type, can be represented by one-hot encoding, the doping concentration can be represented by a real value, and the geometric size can be represented by parameters such as length, width, and height. is the edge attribute set, For any edge Its properties is a p-dimensional real-valued vector containing information such as the type and strength of the interaction between regions:

[0057]

[0058] in, Represents edge e ij The kth property value of , such as the interaction type can be represented by a discrete variable (such as 0 for Ohmic contact and 1 for Schottky contact), and the interaction strength can be represented by physical quantities such as coupling coefficient and interface charge density.

[0059] The heterogeneous attribute graph G comprehensively encodes the structure and physical information of semiconductor devices and is the input of the subsequent graph attention neural network. The node and edge attribute dimensions d and p of the graph can be determined according to the modeling object and application scenario. The attribute encoding process uses domain knowledge to map the key physical parameters of the device into node and edge features of the graph, providing rich prior information for feature extraction of the graph neural network.

[0060] S102: Obtain an embedded representation of the node in the graph attention layer according to the attention information between each node and its neighboring nodes in the heterogeneous attribute graph, and stack the graph attention layers to obtain the final embedded representation of the node.

[0061] Optionally, the attention information includes an attention coefficient and an attention weight. The embedded representation of the node in the graph attention layer is obtained according to the attention information between each node and its neighboring nodes in the heterogeneous attribute graph, including: for each layer of the graph attention layer, the attention coefficient of each node to its neighboring nodes is calculated, and the attention weight is obtained according to the attention coefficient; the information of the neighboring nodes is aggregated according to the attention weight to obtain the embedded representation of the node in the graph attention layer.

[0062] Optionally, the attention coefficient is calculated as:

[0063] in, is the attention coefficient of the c-th graph attention layer, which measures the node v j For node v i The importance of is the attention function of the c-th graph attention layer, is node v i The embedding representation at the c-1th graph attention layer is, is node v j The embedding representation at the c-1th graph attention layer is, For edge e ij The properties of e ij Represents the connection node v i and node v j edge.

[0064] In one embodiment, It can be a function such as a multi-layer perceptron or a bilinear mapping. According to the node v j , node v iThe embedding representation of the previous layer is weighted and aggregated through the attention mechanism, so as to update the embedding representation of the node in the next layer.

[0065] Optionally, obtaining the attention weight according to the attention coefficient includes: normalizing the attention coefficient, and determining the attention weight of each node to its neighboring nodes according to the normalization result.

[0066] In one embodiment, the attention coefficient can be processed by softmax normalization, and the attention weight of each node to its neighboring nodes can be obtained according to the normalization result. Specifically, the calculation formula of the attention weight can be:

[0067]

[0068] in, Represents node v i The sum of the attention weights of all neighbors of is 1. For node v j For node v i The contribution of aggregated information.

[0069] Optionally, the attention weight is used to aggregate the neighborhood node information of each node to obtain the embedded representation of each node at different attention layers. Specifically, node v i The embedding representation at the cth graph attention layer is:

[0070]

[0071] in, is the message passing function of the c-th graph attention layer, which transforms node v j The previous layer embedding and edge ij Properties Mapped as inter-layer messages, is the node v in the cth graph attention layer i To its neighboring node v j The attention weight of the control node v j Passed to node v i is the message strength, and σ is the activation function.

[0072] The graph attention layer introduces an attention mechanism to adaptively assign weights to different neighbors and focus on important nodes and connections. Prior knowledge for modeling semiconductor devices can be introduced into the attention function and message passing function.

[0073] Optionally, the embedding representations of all nodes in different graph attention layers are obtained, and the node embedding matrix of each graph attention layer is obtained according to the embedding representation and the mapping function of the graph attention layer. The node embedding matrix is ​​used to stack multiple graph attention layers.

[0074] In one embodiment, c layers of graph attention layers are stacked to obtain the final embedding representation of the node in For node v i D L dimensional embedding vector. The stacking process of the graph attention layer is expressed as:

[0075] H c =GAT c (H c-1 , E), 1, 2, ..., c

[0076] Among them, H c is the node embedding matrix of the cth layer, H 0 is the initial node attribute matrix, GAT c Represents the mapping function of the c-th graph attention layer.

[0077] The stacking of multiple layers of graph attention can model high-order, long-range interactions within the device. The first layer of graph attention aggregates the 1-hop neighbor information of the node, the second layer of graph attention aggregates the 2-hop neighbor information of the node, and so on. After multiple layers are stacked, the embedding vector of each node is The structure and attribute information of its c-hop subgraph are encoded, thereby capturing the multi-scale characteristics of semiconductor devices.

[0078] S103: Obtain a simulation model of the semiconductor device according to the final embedding representation of the node, the graph pooling layer, and the fully connected layer.

[0079] Optionally, a simulation model of a semiconductor device is obtained based on the final embedding representation of the node, a graph pooling layer, and a fully connected layer, including: using the graph pooling layer and the embedded representation of all nodes to generate a graph representation vector for representing device characteristics; obtaining parameters of the simulation model based on the graph representation vector and the fully connected layer, and obtaining the simulation model based on the parameters.

[0080] In one embodiment, after the graph attention layer is stacked, a graph pooling layer f is used pool Aggregate the embedding representations of all nodes to generate a graph representation vector

[0081]

[0082] The graph pooling layer aggregates the embedding information of different nodes into a fixed-length vector representation, abstracting the characteristics of the entire device structure. L , which can balance the information aggregation degree and computational complexity of the graph representation vector. The multi-layer graph attention network can model the complex structure and attribute interaction inside the device, and the graph pooling layer further aggregates the information of different regions to obtain a comprehensive feature representation of the device.

[0083] Optionally, the fully connected layer includes a first hidden layer, a second hidden layer, and an output layer, and obtaining parameters of the simulation model according to the graph representation vector and the fully connected layer includes: obtaining a first hidden feature corresponding to the graph representation vector using the graph representation vector and the first hidden layer; obtaining a second hidden feature corresponding to the first hidden feature according to the first hidden feature and the second hidden layer; and obtaining parameters according to the second hidden feature and the output layer. The simulation model of the semiconductor device is established using the parameters.

[0084] In one embodiment, a multi-layer fully connected network f is used fc Let the graph represent the vector h G Mapped to the parameters of the simulation model θ∈R m , the dimension of θ is m:

[0085] θ=f fc (h G )=W (out) ·σ(W (2) ·σ(W (1) ·h G +b (1) )+b (2) )

[0086] in, are the weight matrices of the first, second hidden layers and output layer, respectively, d h is the hidden layer dimension; is the bias vector of the hidden layer; σ is the activation function. The fully connected layer represents the graph vector h G Mapped to the parameter θ of the simulation model. Specifically, the execution steps include:

[0087] (1) Use the first hidden layer to represent the graph vector h G Mapping to d h The first hidden feature of dimension:

[0088]

[0089] (2) Use the second hidden layer to transform the first hidden feature h (1) Further mapped to d h The second hidden feature of dimension:

[0090]

[0091] (3) The second hidden feature h is transformed into (2) Mapping to m-dimensional parameters:

[0092] θ=W (out) ·h (2) ∈R m

[0093] Where m is the number of parameters of the simulation model, which depends on the selected device model. h As well as the activation function σ, a simulation alternative mapping network with different expression capabilities and nonlinearity levels is constructed. The multi-layer fully connected network can fit complex nonlinear functions and transform the structure and physical characteristics of the device into the simulation output of the simulation model.

[0094] Optionally, after obtaining the parameters of the simulation model, it is also possible to verify whether the accuracy of the parameters meets expectations (such as the error with the actual product of the semiconductor device is less than a preset error). If so, the simulation model is constructed using the parameters; if not, the parameters of the simulation model are obtained again based on the heterogeneous attribute graph.

[0095] The semiconductor device simulation method of the present application is further explained below by taking FinFET device as an example.

[0096] In one embodiment, the semiconductor device is a FinFET device, and a netlist file (such as Figure 3 ). Obtain the heterogeneous attribute graph corresponding to the netlist file. In the heterogeneous attribute graph, the key areas of the device, such as the source, drain, gate, fin, and insulating layer, are represented by the nodes of the graph, and the connection relationship between the nodes reflects the physical interaction inside the device, such as pn junction, ohmic contact, Schottky contact, etc. The physical information of FinFET, such as material, doping, and geometric parameters, is encoded into the attribute vectors of nodes and edges. The heterogeneous attribute graph comprehensively characterizes the structure and physical characteristics of the device.

[0097] Use graph attention neural network to learn high-dimensional feature representation of devices. Figure 4 As shown in Figure 1, by introducing the attention mechanism into the graph convolutional network of the graph attention neural network, the importance of different nodes and edges can be adaptively adjusted. For nodes in heterogeneous attribute graphs, the graph attention layer first calculates the attention coefficient between them and the neighboring nodes, and then normalizes them using the softmax function (such as softmaxA, softmaxB) to obtain the attention weight. The attention weight is used to aggregate the hidden features of the neighboring nodes and the attributes of the edges to obtain the embedded representation of the nodes in different graph attention layers (such as A corresponding to node A). ′ , such as node B corresponding to B ′). Multiple layers of graph attention layers are stacked to capture the high-order interactions within the semiconductor device layer by layer. After multiple layers of graph attention layers, a high-dimensional embedding representation of each component region of the device can be learned. The graph pooling layer is used to aggregate the embedded features of all nodes to generate a graph-level representation vector of the entire device structure. It is then mapped into compact simulation surrogate model parameters through a multi-layer perceptron. The entire network is trained in an end-to-end manner to minimize the prediction error of the simulation results.

[0098] Use the trained graph attention neural network to quickly predict the electrical characteristic parameters of new device structures. This application implements device physical simulation based on the graph attention network, which comprehensively utilizes the powerful ability of graph data structure to characterize devices and the advantages of the attention mechanism to adaptively model complex interactions. Through an end-to-end data-driven approach, there is no need for manual feature extraction, which significantly improves the accuracy and efficiency of modeling. This method has good interpretability, and the attention weights intuitively reveal the key areas inside the device, which is qualitatively consistent with the physical mechanism and provides inspiration for optimized design. Moreover, this method can be extended to semiconductor devices of different types and scales, providing new solutions for device modeling and circuit performance evaluation in DTCO.

[0099] The terms "first", "second", "third", "fourth", "1", "2", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than that shown or described in the drawings.

[0100] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0101] The above is only an optional implementation method for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the solution of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A semiconductor device simulation method based on graph attention neural network, characterized in that: The graph attention neural network includes a graph attention layer, a graph pooling layer and a fully connected layer, and the method includes: generating a heterogeneous property graph according to a netlist file of a semiconductor device, wherein the netlist file includes a device structure and simulation information; Obtaining an embedded representation of the node in a graph attention layer according to attention information between each node and its neighboring nodes in the heterogeneous attribute graph, and stacking the graph attention layers to obtain a final embedded representation of the node, wherein the attention information includes an attention coefficient and an attention weight; A simulation model of the semiconductor device is obtained according to the final embedding representation of the node, the graph pooling layer, and the fully connected layer.

2. The semiconductor device simulation method based on graph attention neural network according to claim 1 is characterized in that: The generating of a heterogeneous property graph according to a netlist file of a semiconductor device comprises: Acquire component region information and interaction information of the semiconductor device according to the netlist file, wherein the component region information includes the component region of the semiconductor device and attribute information of the component region, and the interaction information includes interaction between component regions and information of the interaction; The heterogeneous property graph is generated based on the composition region information and the interaction information.

3. The semiconductor device simulation method based on graph attention neural network according to claim 1, characterized in that: Obtaining an embedded representation of the node in the graph attention layer according to the attention information between each node and its neighboring nodes in the heterogeneous attribute graph, including: For each graph attention layer, calculate the attention coefficient of each node to its neighboring nodes, and obtain the attention weight according to the attention coefficient; The information of the neighborhood nodes is aggregated according to the attention weights to obtain an embedded representation of the node in the graph attention layer.

4. The semiconductor device simulation method based on graph attention neural network according to claim 3 is characterized in that: The obtaining of the attention weight according to the attention coefficient comprises: The attention coefficient is normalized, and the attention weight of each node to its neighboring nodes is obtained according to the normalized result.

5. The semiconductor device simulation method based on graph attention neural network according to claim 3 is characterized in that: The calculation formula of the attention coefficient is: in, is the attention coefficient of the c-th graph attention layer, which measures the node v j For node v i The importance of is the attention function of the c-th graph attention layer, is node v i The embedding representation at the c-1th graph attention layer is, is node v j The embedding representation at the c-1th graph attention layer is, For edge e ij The properties of e ij Represents the connection node v i and node v j edge.

6. The semiconductor device simulation method based on graph attention neural network according to claim 5, characterized in that: Node v i The embedding representation at the cth graph attention layer is: in, is the message passing function of the c-th graph attention layer, is the node v in the cth graph attention layer i To its neighboring node v j is the attention weight, and σ is the activation function.

7. The semiconductor device simulation method based on graph attention neural network according to claim 3 is characterized in that: The stacking of the graph attention layer comprises: Obtain the embedding representations of all nodes at different graph attention layers, and obtain the node embedding matrix of each graph attention layer according to the embedding representation and the mapping function of the graph attention layer.

8. The semiconductor device simulation method based on graph attention neural network according to claim 3 is characterized in that: The step of obtaining the simulation model of the semiconductor device according to the final embedding representation of the node, the graph pooling layer, and the fully connected layer includes: Using the graph pooling layer and the embedded representation of all nodes, a graph representation vector is generated to represent the device features; Parameters of the simulation model are obtained according to the graph representation vector and the fully connected layer, and the simulation model is obtained based on the parameters.

9. The semiconductor device simulation method based on graph attention neural network according to claim 8, characterized in that: The method of using the graph pooling layer and the embedded representation of all nodes to generate a graph representation vector for representing device features includes: The graph pooling layer is used to aggregate the embedded representations of all nodes into a fixed-length vector.

10. The semiconductor device simulation method based on graph attention neural network according to claim 8, characterized in that: The fully connected layer includes a first hidden layer, a second hidden layer and an output layer, and the acquiring the parameters of the simulation model according to the graph representation vector and the fully connected layer includes: Obtaining a first hidden feature corresponding to the graph representation vector using the graph representation vector and the first hidden layer; Obtaining a second hidden feature corresponding to the first hidden feature according to the first hidden feature and the second hidden layer; The parameter is obtained according to the second hidden feature and the output layer.

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