Voltage-insensitive fpga clock network and control method

Abstract

The application relates to the technical field of clock network, in particular to a voltage-insensitive FPGA clock network and a control method, the FPGA clock network comprises a plurality of clock buffers with adjustable time delay; the clock buffer receives local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjusts the transmission time delay according to the local feedback information or the global feedback information; the clock buffer comprises a local feedback module and a global feedback module; the local feedback module adaptively adjusts circuit parameters of the current clock buffer based on the local feedback information, so as to balance local power supply voltage fluctuation; and the global feedback module adaptively adjusts the circuit parameters of the current clock buffer based on the global feedback information, so as to balance global power supply voltage fluctuation. The application can dynamically adjust the transmission time delay of the clock network, and effectively reduces the influence of power supply voltage fluctuation on the clock network.

Description

Technical Field

[0001] The present invention relates to the technical field of clock networks, and in particular to a voltage-insensitive FPGA clock network and a control method thereof. Background Art

[0002] In modern electronic systems, Field-Programmable Gate Array (FPGA) is widely used in various high-speed computing and digital signal processing fields due to its flexibility and reconfigurability. One of the core performance of FPGA is its clock network, such as Figure 1 As shown, it is responsible for providing a synchronous clock signal for the entire chip to ensure that data is transmitted correctly and efficiently between different parts.

[0003] In traditional FPGA clock network design, such as Figure 2 As shown in Figure 1, a clock buffer is usually composed of a cascade of inverters. This design is simple and low-cost. However, this design is very sensitive to power supply fluctuations. Figure 3 As shown in the figure (vdd represents the FPGA chip's supply voltage, clock buffer delay represents the clock buffer's delay time, and clock output represents the clock signal's output waveform), variations in supply voltage cause fluctuations in the clock buffer's transmission delay. These fluctuations accumulate on the FPGA's clock network, causing clock jitter. Clock jitter can severely impact FPGA performance, especially in high-speed data transmission and processing applications, where it can lead to data errors and system instability.

[0004] As FPGAs grow in size, the complexity of clock networks increases, and the impact of voltage fluctuations on clock networks becomes more significant. This not only limits FPGA performance improvements but also places higher demands on designers to ensure clock network stability and accuracy under varying power supply conditions. Summary of the Invention

[0005] In view of this, the present invention provides a voltage-insensitive FPGA clock network and control method to solve the problem that traditional clock buffers are affected by the chip power supply voltage, resulting in transmission delay fluctuations and clock jitter accumulated in the clock network.

[0006] In a first aspect, the present application provides a voltage-insensitive FPGA clock network, comprising a plurality of delay-adjustable clock buffers distributed at grid nodes of the FPGA clock network; the clock buffer is configured to receive local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjust a transmission delay according to the local feedback information or the global feedback information.

[0007] The clock buffer comprises a one-to-one local feedback module and a global feedback module.

[0008] The local feedback module is configured to obtain local feedback information of a current clock buffer, and adaptively adjust circuit parameters of the current clock buffer according to the local feedback information, so as to balance local power supply voltage fluctuation.

[0009] The global feedback module is configured to receive global feedback information of a backward clock buffer between the current clock buffer and the backward clock buffer through a clock tree, and adaptively adjust circuit parameters of the current clock buffer according to the global feedback information, so as to balance global power supply voltage fluctuation.

[0010] In an optional embodiment, the clock buffer is further provided with a one-to-one local delay module.

[0011] The local delay module is connected to a path between an input end and an output end of the clock buffer; the local delay module is configured to fine-tune a local clock signal delay of the clock buffer.

[0012] In an optional embodiment, in the current clock buffer, an input end of a current local feedback module corresponding to the current clock buffer is connected to an output end of a current local delay module corresponding to the current clock buffer; an output end of the current local feedback module is connected to a local feedback end of the current clock buffer.

[0013] An input end of a current global feedback module corresponding to the current clock buffer is connected to an output end of a backward local delay module corresponding to the backward clock buffer; an output end of the current global feedback module is connected to a global feedback end of the current clock buffer.

[0014] In an optional embodiment, the local feedback module comprises:

[0015] A delay monitoring unit is configured to monitor local delay information of the current clock buffer in real time, and transmit a monitoring result to a comparison unit;

[0016] The comparison unit is configured to compare the local delay information with pre-stored expected delay information, and generate a local adjustment signal according to a comparison result, and transmit the local adjustment signal to the local feedback end of the current clock buffer to adjust a circuit parameter of the current clock buffer.

[0017] In an optional embodiment, the global feedback module comprises:

[0018] A backward node information acquisition unit is configured to acquire global feedback information of a backward clock buffer of the clock tree, wherein the global feedback information comprises a clock signal state, delay information and supply voltage information of the backward clock buffer;

[0019] An information processing unit is configured to analyze and process the acquired global feedback information, generate a global adjustment signal, and transmit the global adjustment signal to the global feedback end of the current clock buffer to uniformly and coordinately adjust the circuit parameter of the current clock buffer and balance global supply voltage fluctuation of the FPGA clock network.

[0020] In an optional embodiment, each clock buffer is internally provided with a delay unit, and the delay unit is configured to adjust transmission delay of a clock signal of the clock buffer.

[0021] In a second aspect, the application provides a control method of a voltage-insensitive FPGA clock network, which is applied to a clock buffer of a voltage-insensitive FPGA clock network as described above, and the method comprises:

[0022] Based on the local feedback module, local feedback information of a current clock buffer is acquired, and a circuit parameter of the current clock buffer is adaptively adjusted according to the local feedback information to balance local supply voltage fluctuation.

[0023] Based on the global feedback module, global feedback information of a backward clock buffer is received through a clock tree between the current clock buffer and the backward clock buffer, and a circuit parameter of the current clock buffer is adaptively adjusted according to the global feedback information to balance global supply voltage fluctuation.

[0024] In an optional embodiment, the adaptively adjusting the circuit parameter of the current clock buffer according to the local feedback information comprises:

[0025] If the local delay information of the current clock buffer exceeds the expected delay information, the output delay of the current clock buffer is reduced.

[0026] If the local latency information of the current clock buffer is lower than the expected latency information, then the output latency of the current clock buffer is raised.

[0027] In a third aspect, the present application provides a computer device, comprising: a memory and a processor, which are connected with each other in communication, and the memory stores computer instructions; the processor executes the computer instructions to perform the method for controlling a voltage-insensitive FPGA clock network according to the first aspect or any of the possible implementation manners thereof.

[0028] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions for making a computer perform the method for controlling a voltage-insensitive FPGA clock network according to the first aspect or any of the possible implementation manners thereof.

[0029] In a fifth aspect, the present application provides a computer program product, which comprises computer instructions for making a computer perform the method for controlling a voltage-insensitive FPGA clock network according to the first aspect or any of the possible implementation manners thereof.

[0030] The technical scheme provided by the present application can have the following beneficial effects:

[0031] The application provides a voltage-insensitive FPGA clock network, which comprises a plurality of delay-adjustable clock buffers distributed at grid nodes of the FPGA clock network; the clock buffer is used for receiving local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjusting a transmission delay according to the local feedback information or the global feedback information; the clock buffer comprises a one-to-one local feedback module and a global feedback module; the local feedback module is used for acquiring the local feedback information of the current clock buffer, and adaptively adjusting circuit parameters of the current clock buffer according to the local feedback information, so as to balance local power supply voltage fluctuation; and the global feedback module is used for receiving the global feedback information of the backward clock buffer through a clock tree between the current clock buffer and the backward clock buffer, and adaptively adjusting the circuit parameters of the current clock buffer according to the global feedback information, so as to balance global power supply voltage fluctuation. By introducing the delay-adjustable clock buffer and the two-stage adaptive feedback mechanism, the application can dynamically adjust the transmission delay of the clock network, effectively reduces the influence of power supply voltage fluctuation on the clock network, and thus significantly improves the stability and accuracy of the clock. Moreover, by accurately controlling the delay of the clock buffer, the application can effectively reduce clock jitter caused by voltage fluctuation, improve the clock performance and voltage fluctuation resistance of the FPGA, and thus enhances the reliability of the whole system. In addition, the design method of the application has strong expansibility, and can adapt to FPGA chips of different scales and complexities. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the present application in the embodiments or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings described below are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without any creative effort.

[0033] Figure 1 FIG. 1 is a schematic diagram of a grid structure of an FPGA clock network according to an embodiment of the present application;

[0034] Figure 2 FIG. 2 is a schematic diagram of a clock buffer composed of inverters in cascade according to an embodiment of the present application;

[0035] Figure 3 FIG. 3 is a schematic diagram of the influence of power supply voltage fluctuation on the delay of a clock buffer according to an embodiment of the present application;

[0036] Figure 4 FIG. 4 is a schematic diagram of a voltage-insensitive FPGA clock network according to an embodiment of the present application;

[0037] Figure 5 is a structural diagram of a clock buffer according to an embodiment of the present application;

[0038] Figure 6 is a flowchart of a control method of a voltage-insensitive FPGA clock network according to an embodiment of the present application;

[0039] Figure 7 is a hardware structural diagram of a computer device according to an embodiment of the present application. DETAILED DESCRIPTION

[0040] To make the objects, technical solutions and advantages of embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0041] In the present embodiment, a voltage-insensitive FPGA clock network is provided, please refer to Figure 4 a structural diagram of a voltage-insensitive FPGA clock network is shown, the FPGA clock network comprises a plurality of clock buffers with adjustable time delay (each block in Figure 4 represents a clock buffer, i.e. Figure 4 three clock buffers clockbuffer connected in series are given, and this connection mode constitutes a transmission path of a clock signal in the network, and the clock buffers are distributed at grid nodes of the FPGA clock network; the clock buffer is configured to receive local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjust a transmission time delay according to the local feedback information or the global feedback information.

[0042] Please refer to Figure 5 a structural diagram of a clock buffer is shown, the clock buffer comprises a one-to-one local feedback module and a global feedback module (the clock buffer further comprises a local feedback end and a global feedback end, the local feedback module is connected to the local feedback end of the clock buffer, i.e. Figure 5 vadj_local in Figure 5 the global feedback module is connected to the global feedback end of the clock buffer, i.e.

[0043] The local feedback module is used to obtain local feedback information of the current clock buffer and adaptively adjust circuit parameters of the current clock buffer according to the local feedback information to balance local power supply voltage fluctuations;

[0044] The global feedback module is used to receive global feedback information of the backward clock buffer through the clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the global feedback information to balance the global power supply voltage fluctuation.

[0045] Furthermore, first, this embodiment proposes a clock buffer design with adjustable delay. Different from the traditional inverter cascade structure, the circuit parameters of the clock buffer with adjustable delay can be adjusted in real time. This embodiment fine-tunes the delay of the clock buffer through feedback circuit signals; at the grid nodes, the circuit parameters of the clock buffer are adaptively adjusted through local feedback, thereby balancing the impact of local power supply voltage fluctuations; between grid nodes, the circuit parameters of the clock buffer are adaptively adjusted through clock tree backward node feedback information, thereby balancing the impact of global power supply voltage fluctuations; through a two-level adaptive feedback mechanism, this embodiment can reduce the impact of the overall clock network on power supply voltage fluctuations and improve the overall performance of the clock network.

[0046] In an optional embodiment, as Figure 4 As shown, the clock buffer is also provided with a one-to-one corresponding local delay module (the local delay module is Figure 4 local delay unit in the IO_CONTENT_DELTA_STORAGE_ENGINE);

[0047] The local delay module is connected to the path between the input end and the output end of the clock buffer; the local delay module is used to fine-tune the local clock signal delay of the clock buffer.

[0048] Furthermore, each clock buffer is equipped with a local delay module (local delay unit), which is connected to the path between the clock buffer's input and output. Its main function is to fine-tune the clock signal delay of the clock buffer. During clock signal transmission, factors such as slight differences in the local circuit environment may require more precise delay adjustment of the clock signal. This local delay unit can play such a role. For example, in certain areas with complex local wiring, the clock signal may need to be delayed slightly to ensure synchronization with other parts. The local delay unit can then make fine adjustments based on the actual situation.

[0049] In an alternative embodiment, in the current clock buffer, the input end (i.e. IN in Figure 5 ) of the current local feedback module corresponding to the current clock buffer is connected to the output end (i.e. OUT in Figure 5 ) of the current local delay module corresponding to the current clock buffer; the output end of the current local feedback module is connected to the local feedback end of the current clock buffer;

[0050] The input end of the current global feedback module corresponding to the current clock buffer is connected to the output end of the backward local delay module corresponding to the backward clock buffer; the output end of the current global feedback module is connected to the global feedback end of the current clock buffer.

[0051] In an alternative embodiment, the local feedback module comprises:

[0052] A delay monitoring unit for monitoring the local delay information of the current clock buffer in real time and transmitting the monitoring result to the comparison unit;

[0053] The comparison unit is configured to compare the local delay information with the pre-stored expected delay information and generate a local adjustment signal according to the comparison result, which is transmitted to the local feedback end of the current clock buffer to adjust the circuit parameters of the current clock buffer.

[0054] Further, the clock buffer of the embodiment is equipped with a local feedback module connected to the local feedback end (vadj_local). The module first acquires the local feedback information of the current clock buffer, which can include the transmission state of the clock signal in the local range of the current buffer, etc. Then, the local delay information of the current clock buffer is monitored in real time by a delay monitoring unit and transmitted to a comparison unit. The comparison unit compares the local delay information with the pre-stored expected delay information. If there is a deviation between the local delay and the expected delay, the comparison unit generates a local adjustment signal according to the comparison result and transmits it to the local feedback end of the current clock buffer, thereby adjusting the circuit parameters of the current clock buffer to balance the influence of local power supply voltage fluctuation on the transmission of the clock signal. For example, if the local power supply voltage fluctuation causes the clock signal to transmit too fast, so that the local delay is less than the expected delay, the comparison unit can generate a signal to increase the delay of the clock buffer, and vice versa.

[0055] In an alternative embodiment, the global feedback module comprises:

[0056] A backward node information acquisition unit for acquiring the global feedback information of the backward clock buffer of the clock tree, which includes the clock signal state, delay information and power supply voltage information of the backward clock buffer;

[0057] The information processing unit is configured to analyze the collected global feedback information, generate a global adjustment signal, and transmit the global adjustment signal to the global feedback end of the current clock buffer, so as to uniformly coordinate and adjust the circuit parameters of the current clock buffer and balance the global power supply voltage fluctuation of the FPGA clock network.

[0058] Further, the global feedback module is connected to the global feedback end (vadj_backward) of the clock buffer. It receives the global feedback information of the backward clock buffer between the current clock buffer and the backward clock buffer through the clock tree, which includes the clock signal state, time delay information, and power supply voltage information of the backward clock buffer. The information processing unit will analyze the collected global feedback information in depth, generate a global adjustment signal according to the information, and transmit the global adjustment signal to the global feedback end of the current clock buffer, so as to uniformly coordinate and adjust the circuit parameters of the current clock buffer, and balance the global power supply voltage fluctuation of the entire FPGA clock network. For example, when the power supply voltage fluctuation in a certain region of the network affects the clock signal of the backward clock buffer, the global feedback module can transmit this influence to the current clock buffer and make corresponding adjustments to ensure the clock stability of the entire network.

[0059] In an optional embodiment, as shown in Figure 4 Each clock buffer is internally provided with a delay unit (the delay unit in the local delay module Figure 4 The delay unit is configured to adjust the transmission delay of the clock signal of the clock buffer.

[0060] Further, each clock buffer is internally provided with a delay unit (the delay unit in the local delay module Figure 4 The delay unit is mainly configured to adjust the transmission delay of the clock signal of the clock buffer. Unlike the fine adjustment of the local delay module, the internal delay unit can adjust the transmission delay of the clock signal on a more macro level to adapt to different working conditions and voltage fluctuation conditions, so as to ensure that the clock signal can maintain a relatively stable transmission time after passing through the clock buffer.

[0061] Further, the embodiment uses a clock buffer with adjustable delay on the FPGA clock network, can accept local or backward clock network node feedback information, and dynamically adjusts the transmission delay. At the clock network node, the embodiment adjusts the circuit parameters of the clock buffer through local feedback to balance the influence of local power supply voltage fluctuation; if the local delay exceeds the expected delay, the clock buffer output delay is reduced; otherwise, the clock buffer output delay is increased; and between the grid nodes, the embodiment adjusts the circuit parameters of the clock buffer through backward feedback information of the clock tree node to balance the influence of global power supply voltage fluctuation.

[0062] The two-stage adaptive feedback mechanism of the embodiment can reduce the influence of power supply voltage fluctuation on the overall clock network and improve the overall performance of the clock network. This delay adjustment method is adaptive and does not require specific configuration or design by the FPGA user. The embodiment has strong scalability, and as the size of the FPGA increases, it can significantly reduce the influence of local / overall voltage fluctuation on the clock network and improve the performance of the clock network.

[0063] In summary, the embodiment provides a voltage-insensitive FPGA clock network, which comprises a plurality of delay-adjustable clock buffers distributed at grid nodes of the FPGA clock network; the clock buffer is configured to receive local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjust a transmission delay according to the local feedback information or the global feedback information; the clock buffer comprises a one-to-one local feedback module and a global feedback module; the local feedback module is configured to obtain the local feedback information of the current clock buffer, and adaptively adjust circuit parameters of the current clock buffer according to the local feedback information, so as to balance local power supply voltage fluctuation; and the global feedback module is configured to receive the global feedback information of the backward clock buffer through a clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust the circuit parameters of the current clock buffer according to the global feedback information, so as to balance global power supply voltage fluctuation. By introducing the delay-adjustable clock buffer and the two-stage adaptive feedback mechanism, the embodiment can dynamically adjust the transmission delay of the clock network, effectively reduce the influence of power supply voltage fluctuation on the clock network, and thus significantly improve the stability and accuracy of the clock. Moreover, by precisely controlling the delay of the clock buffer, the embodiment can effectively reduce clock jitter caused by voltage fluctuation, improve the clock performance and voltage fluctuation resistance of the FPGA, and thus enhance the reliability of the entire system. In addition, the design method of the embodiment has strong expansibility and can adapt to FPGA chips of different scales and complexities.

[0064] According to the embodiment of the present application, a control method for a voltage-insensitive FPGA clock network is provided. It should be noted that the steps shown in the flowchart can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0065] In the embodiment, a control method for a voltage-insensitive FPGA clock network is provided, which is applied to Figure 4 As shown in a clock buffer of a voltage-insensitive FPGA clock network, Figure 6 The flowchart shown includes the following steps:

[0066] In step S601, based on the local feedback module, the local feedback information of the current clock buffer is obtained, and the circuit parameters of the current clock buffer are adaptively adjusted according to the local feedback information, so as to balance the local power supply voltage fluctuation.

[0067] Further, the embodiment utilizes a local feedback module to obtain local feedback information of the current clock buffer. The local feedback information contains relevant information of the clock signal in the local region where the current clock buffer is located, which can include the transmission time of the clock signal, signal quality, etc. These information reflect the state of the clock signal in the local region. The local feedback module continuously monitors the working state of the current clock buffer to obtain the local feedback information. Then, the circuit parameters of the current clock buffer are adaptively adjusted according to the obtained local feedback information. The circuit parameters can involve the bias voltage and current size of various transistors in the clock buffer, and the change of these parameters will affect the transmission characteristics of the clock signal.

[0068] In an alternative embodiment, the step S601 comprises:

[0069] If the local delay information of the current clock buffer exceeds the expected delay information, the output delay of the current clock buffer is reduced.

[0070] If the local delay information of the current clock buffer is lower than the expected delay information, the output delay of the current clock buffer is increased.

[0071] Further, if the local delay information of the current clock buffer exceeds the expected delay information, the output delay of the current clock buffer is reduced. This means that when the monitored local clock signal transmission delay is longer than expected, it may be due to the local supply voltage being too high, causing the signal transmission speed to be too fast. In order to make the local clock signal return to the normal state, the output delay needs to be reduced. If the local delay information of the current clock buffer is lower than the expected delay information, the output delay of the current clock buffer is increased. Conversely, when the local clock signal transmission delay is shorter than expected, it may be due to the local supply voltage being too low, causing the signal transmission to slow down, at which time the output delay needs to be increased.

[0072] Step S602, based on the global feedback module, receiving the global feedback information of the backward clock buffer through the clock tree between the current clock buffer and the backward clock buffer, and adaptively adjusting the circuit parameters of the current clock buffer according to the global feedback information to balance the global supply voltage fluctuation.

[0073] Further, the global feedback module receives global feedback information of the backward clock buffer through a clock tree between the current clock buffer and the backward clock buffer. The clock tree is a network structure connecting various clock buffers, through which clock signals and feedback information can be transmitted between different clock buffers. The global feedback information of the backward clock buffer contains more extensive clock network information, which can involve the overall state of multiple clock buffers and the region where they are located, including clock signal state, time delay information, and power supply voltage information, etc. Based on the received global feedback information, the circuit parameters of the current clock buffer are adaptively adjusted in this embodiment. Through steps S601 and S602 described above, the circuit parameters of the clock buffer can be dynamically adjusted at both local and global levels to cope with power supply voltage fluctuations of different ranges, so as to realize a voltage-insensitive FPGA clock network and improve the performance and reliability of the entire FPGA clock network.

[0074] In summary, by introducing the clock buffer with adjustable time delay and the two-stage adaptive feedback mechanism, the embodiment can dynamically adjust the transmission time delay of the clock network, effectively reduce the influence of power supply voltage fluctuation on the clock network, and significantly improve the stability and accuracy of the clock. Moreover, by precisely controlling the time delay of the clock buffer, the embodiment can effectively reduce the clock jitter caused by voltage fluctuation, improve the clock performance and voltage fluctuation resistance of the FPGA, and thus enhance the reliability of the entire system. In addition, the design method of the embodiment has strong scalability and can adapt to FPGA chips of different scales and complexities.

[0075] The embodiment of the present application also provides a computer device, please refer to Figure 7 , Figure 7 is a structural schematic diagram of a computer device provided by an optional embodiment of the present application, as Figure 7 shown, the computer device comprises one or more processors 10, a memory 20, and an interface for connecting various components, including a high-speed interface and a low-speed interface. Various components are communicatively connected to each other by different buses, and can be installed on a common motherboard or in other ways as needed. The processor can process instructions executed within the computer device, including instructions stored in the memory or on the memory to display graphical information on a GUI on an external input / output device, such as a display device coupled to the interface. In some optional embodiments, multiple processors and / or multiple buses can be used with multiple memories and multiple memories, if necessary. Similarly, multiple computer devices can be connected, each providing part of the necessary operations (for example, as a server array, a set of blade servers, or a multi-processor system). Figure 7 In the above embodiment, the processor 10 is taken as an example.

[0076] The processor 10 can be a central processing unit, a network processing unit, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic device, a general array logic, or any combination thereof.

[0077] The memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods illustrated by the above embodiments.

[0078] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system, application programs required by at least one function, and the like. The data storage area can store data created according to the use of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory such as at least one disk storage device, a flash memory device, or other non-transitory solid state memory device. In some alternative embodiments, the memory 20 can optionally include a memory disposed remotely from the processor 10, which can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0079] The memory 20 can include a volatile memory such as a random access memory, and can also include a non-volatile memory such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned types of memories.

[0080] The computer device further includes a communication interface 30 for communication of the computer device with other devices or communication networks.

[0081] The embodiments of the present application also provide a computer readable storage medium. The above-mentioned methods according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or stored in a remote storage medium or a non-transitory machine readable storage medium originally through network downloading and then stored in a local storage medium, so that the methods described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can further include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer code, when the software or computer code is accessed and executed by the computer, the processor, or the hardware, the methods illustrated by the above embodiments are implemented.

[0082] Part of the present application can be applied as a computer program product, for example, computer program instructions, when executed by a computer, through the operation of the computer, can invoke or provide the method and / or technical solutions according to the present application. Those skilled in the art should understand that the form of computer program instructions in computer readable medium includes but is not limited to source file, executable file, installation package file and the like, and accordingly, the way of computer program instructions executed by computer includes but is not limited to: the computer directly executes the instructions, or the computer compiles the instructions and then executes the corresponding compiled program, or the computer reads and executes the instructions, or the computer reads and installs the instructions and then executes the corresponding installed program. Here, the computer readable medium can be any available computer readable storage medium or communication medium accessible to the computer.

[0083] Although the embodiments of the present application are described in conjunction with the drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined.

Claims

1. A voltage insensitive FPGA clock network, characterized in that, The FPGA clock network comprises a plurality of delay-adjustable clock buffers distributed at the grid nodes of the FPGA clock network; the clock buffer is configured to receive local feedback information of a current clock buffer or global feedback information of a backward clock buffer corresponding to a backward node, and dynamically adjust a transmission delay according to the local feedback information or the global feedback information; The clock buffer comprises a one-to-one local feedback module and a global feedback module; The local feedback module is configured to acquire local feedback information of a current clock buffer, and adaptively adjust circuit parameters of the current clock buffer according to the local feedback information, so as to balance local power supply voltage fluctuation; The global feedback module is configured to receive global feedback information of a backward clock buffer through a clock tree between the current clock buffer and the backward clock buffer, and adaptively adjust circuit parameters of the current clock buffer according to the global feedback information, so as to balance global power supply voltage fluctuation; the clock buffer is further provided with a one-to-one local delay module; The local delay module is connected on a path between an input end and an output end of the clock buffer; the local delay module is configured to fine-tune local clock signal delay of the clock buffer; in the current clock buffer, an input end of a current local feedback module corresponding to the current clock buffer is connected to an output end of a current local delay module corresponding to the current clock buffer; and an output end of the current local feedback module is connected to a local feedback end of the current clock buffer; An input end of a current global feedback module corresponding to the current clock buffer is connected to an output end of a backward local delay module corresponding to the backward clock buffer; and an output end of the current global feedback module is connected to a global feedback end of the current clock buffer.

2. The FPGA clock network of claim 1, wherein, The local feedback module comprises: A delay monitoring unit is configured to monitor local delay information of the current clock buffer in real time, and transmit a monitoring result to a comparison unit; The comparison unit is configured to compare the local delay information with pre-stored expected delay information, and generate a local adjustment signal according to a comparison result, and transmit the local adjustment signal to the local feedback end of the current clock buffer, so as to adjust circuit parameters of the current clock buffer.

3. The FPGA clock network of claim 1, wherein, The global feedback module comprises: A backward node information acquisition unit is configured to acquire global feedback information of a backward clock buffer of the clock tree, wherein the global feedback information comprises clock signal state, delay information and power supply voltage information of the backward clock buffer; An information processing unit is configured to analyze and process the acquired global feedback information, generate a global adjustment signal, and transmit the global adjustment signal to the global feedback end of the current clock buffer, so as to uniformly and coordinately adjust circuit parameters of the current clock buffer, and balance global power supply voltage fluctuation of the FPGA clock network.

4. The FPGA clock network of claim 1, wherein, Each clock buffer is internally provided with a delay unit, and the delay unit is configured to adjust transmission delay of a clock signal of the clock buffer.

5. A method of controlling a voltage-insensitive FPGA clock network, characterized by, The control method is applied to a clock buffer of the voltage-insensitive FPGA clock network in any one of claims 1 to 4, and the method comprises: Based on the local feedback module, local feedback information of the current clock buffer is obtained, and circuit parameters of the current clock buffer are adaptively adjusted according to the local feedback information to balance local power supply voltage fluctuation; Based on the global feedback module, global feedback information of the backward clock buffer is received through the clock tree between the current clock buffer and the backward clock buffer, and circuit parameters of the current clock buffer are adaptively adjusted according to the global feedback information to balance global power supply voltage fluctuation.

6. The control method according to claim 5, characterized by The adaptive adjustment of the circuit parameters of the current clock buffer according to the local feedback information comprises: If the local time delay information of the current clock buffer exceeds the expected time delay information, the output time delay of the current clock buffer is reduced; If the local time delay information of the current clock buffer is lower than the expected time delay information, the output time delay of the current clock buffer is increased.

7. A computer device, comprising: It comprises: A memory and a processor, which are connected in communication with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the control method of the voltage-insensitive FPGA clock network in claim 5 or 6.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the control method of the voltage-insensitive FPGA clock network in claim 5 or 6.

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