Gate driver and display device including the same

Abstract

A gate driver and a display device including the same are provided. The gate driver includes a plurality of stages. Each of the plurality of stages includes: a common circuit controlling a voltage of a first control node, a voltage of a second control node, and a voltage of an inverting control node; and individual circuits outputting a plurality of scan signals in response to a voltage of the first control node and a voltage of the inverting control node. The individual circuit includes: a plurality of scan buffer transistors outputting a plurality of scan clock signals as a plurality of scan signals in response to a voltage of a first control node; and a scan hold transistor holding the plurality of scan signals at a first low voltage in response to a voltage of the inverting control node.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly, to a gate driver having a reduced area and a display device including the gate driver. Background Art

[0002] The display device may include a display panel and a panel driver. The display panel may include a plurality of pixels. The panel driver may include a data driver and a gate driver. The gate driver may generate a gate signal applied to a gate electrode of a transistor included in the pixel.

[0003] The gate driver may include a plurality of stages, wherein each of the stages may output a plurality of gate signals. One stage may output a plurality of gate signals, so that the area of ​​the gate driver may be reduced. Summary of the invention

[0004] Embodiments provide a gate driver having a reduced area.

[0005] Embodiments provide a display device with a reduced dead space.

[0006] In an embodiment, in a gate driver including a plurality of stages, each of the plurality of stages may include: a common circuit controlling a voltage of a first control node, a voltage of a second control node, and a voltage of an inverting control node; and a separate circuit outputting a plurality of scan signals in response to the voltage of the first control node and the voltage of the inverting control node. The separate circuit may include: a plurality of scan buffer transistors outputting a plurality of scan clock signals as a plurality of scan signals in response to the voltage of the first control node; and a scan holding transistor holding the plurality of scan signals at a first low voltage in response to the voltage of the inverting control node.

[0007] In an embodiment, the plurality of scan buffer transistors may include: a first scan buffer transistor including a gate electrode connected to a first control node, a first electrode receiving a first scan clock signal, and a second electrode connected to a first scan output node outputting the first scan signal; a second scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a second scan clock signal, and a second electrode connected to a second scan output node outputting the second scan signal; a third scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a third scan clock signal, and a second electrode connected to a third scan output node outputting the third scan signal; and a fourth scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a fourth scan clock signal, and a second electrode connected to a fourth scan output node outputting the fourth scan signal. The scan holding transistor may include a gate electrode connected to an inverting control node, a first electrode receiving a first low voltage, and a second electrode connected to the first scan output node to the fourth scan output node.

[0008] In an embodiment, in a first time period in which a voltage having a turn-on voltage level is applied to a first control node, first to fourth pulses corresponding to first to fourth scan clock signals, respectively, may be sequentially output from a first to fourth scan output node, respectively.

[0009] In an embodiment, in the second period in which a voltage having a turn-on voltage level is applied to the inversion control node, the first low voltage may be output from the first output node to the fourth output node.

[0010] In an embodiment, the separate circuit may further include: a plurality of sensing buffer transistors that output a plurality of sensing clock signals as a plurality of sensing signals in response to a voltage of a first control node; and a sensing holding transistor that holds the plurality of sensing signals at a first low voltage in response to a voltage of an inverting control node.

[0011] In an embodiment, the plurality of sensing buffer transistors may include: a first sensing buffer transistor including a gate electrode connected to a first control node, a first electrode receiving a first sensing clock signal, and a second electrode connected to a first sensing output node outputting the first sensing signal; a second sensing buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a second sensing clock signal, and a second electrode connected to a second sensing output node outputting the second sensing signal; a third sensing buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a third sensing clock signal, and a second electrode connected to a third sensing output node outputting the third sensing signal; and a fourth sensing buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a fourth sensing clock signal, and a second electrode connected to a fourth sensing output node outputting the fourth sensing signal. The sensing holding transistor may include a gate electrode connected to an inverting control node, a first electrode receiving a first low voltage, and a second electrode connected to the first sensing output node to the fourth sensing output node.

[0012] In an embodiment, the common circuit may include a carry buffer transistor outputting a carry clock signal as a carry signal in response to a voltage of the second control node; and a carry hold transistor holding the carry signal at a second low voltage in response to a voltage of the inverting control node.

[0013] In an embodiment, the common circuit may further include: a fourth transistor, including a gate electrode receiving the advanced input signal, a first electrode receiving the advanced input signal, and a second electrode connected to the first control node; and a thirteenth transistor, including a gate electrode receiving the advanced input signal, a first electrode receiving a high voltage, and a second electrode connected to the second control node.

[0014] In an embodiment, the fourth transistor may include sub-transistors connected in series, wherein the intermediate node is provided between the sub-transistors connected in series. The common circuit may further include a tenth transistor including a gate electrode connected to a carry output node from which a carry signal is output, a first electrode receiving a high voltage, and a second electrode connected to the intermediate node of the fourth transistor.

[0015] In an embodiment, the common circuit may further include: an eighth transistor, including a gate electrode receiving a carry-after signal, a first electrode receiving a high voltage, and a second electrode connected to an inverting control node; and a ninth transistor, including a gate electrode receiving a carry-after signal, a first electrode receiving a second low voltage, and a second electrode connected to the first control node.

[0016] In an embodiment, the common circuit may further include a seventh transistor including a gate electrode connected to the first control node, a first electrode receiving the second low voltage, and a second electrode connected to the inverting control node.

[0017] In an embodiment, the seventh transistor may include sub-transistors connected in series, wherein the intermediate node is set between the sub-transistors connected in series. The common circuit may further include a twelfth transistor including a gate electrode connected to the inverting control node, a first electrode receiving a high voltage, and a second electrode connected to the intermediate node of the seventh transistor.

[0018] In an embodiment, the common circuit may further include: an eleventh transistor, comprising a gate electrode connected to the inverting control node, a first electrode receiving the second low voltage, and a second electrode connected to the first control node; and a fourteenth transistor, comprising a gate electrode connected to the inverting control node, a first electrode receiving the second low voltage, and a second electrode connected to the second control node.

[0019] In an embodiment, a display device may include: a display panel including a plurality of pixels; a data driver providing a plurality of data signals to the display panel; and a gate driver including a plurality of stages providing a plurality of scan signals to the display panel. Each of the plurality of stages may include: a common circuit controlling a voltage of a first control node, a voltage of a second control node, and a voltage of an inverting control node; and a separate circuit outputting a plurality of scan signals in response to a voltage of the first control node and a voltage of the inverting control node. The separate circuit may include: a plurality of scan buffer transistors outputting a plurality of scan clock signals as a plurality of scan signals in response to a voltage of the first control node; and a scan holding transistor maintaining the plurality of scan signals at a first low voltage in response to a voltage of the inverting control node.

[0020] In an embodiment, the plurality of scan buffer transistors may include: a first scan buffer transistor including a gate electrode connected to a first control node, a first electrode receiving a first scan clock signal, and a second electrode connected to a first scan output node outputting the first scan signal; a second scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a second scan clock signal, and a second electrode connected to a second scan output node outputting the second scan signal; a third scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a third scan clock signal, and a second electrode connected to a third scan output node outputting the third scan signal; and a fourth scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a fourth scan clock signal, and a second electrode connected to a fourth scan output node outputting the fourth scan signal. The scan holding transistor may include a gate electrode connected to an inverting control node, a first electrode receiving a first low voltage, and a second electrode connected to the first scan output node to the fourth scan output node.

[0021] In an embodiment, each of the plurality of pixels may include: a first pixel transistor including a gate electrode connected to a first pixel node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second pixel node; a second pixel transistor including a gate electrode receiving a scan signal among a plurality of scan signals, a first electrode receiving a data signal among a plurality of data signals, and a second electrode connected to the first pixel node; a third pixel transistor including a gate electrode, a first electrode receiving an initialization voltage, and a second electrode connected to the second pixel node; a storage capacitor including a first electrode connected to the first pixel node and a second electrode connected to the second pixel node; and a light emitting element including a first electrode connected to the second pixel node and a second electrode receiving a second power supply voltage.

[0022] In an embodiment, the gate electrode of the third pixel transistor may receive the above-mentioned scan signal among a plurality of scan signals.

[0023] In an embodiment, the separate circuit may further include: a plurality of sensing buffer transistors that output a plurality of sensing clock signals as a plurality of sensing signals in response to a voltage of a first control node; and a sensing holding transistor that holds the plurality of sensing signals at a first low voltage in response to a voltage of an inverting control node.

[0024] In an embodiment, a gate electrode of the third pixel transistor may receive a sensing signal among the plurality of sensing signals.

[0025] In an embodiment, the common circuit may include a carry buffer transistor outputting a carry clock signal as a carry signal in response to a voltage of the second control node; and a carry hold transistor holding the carry signal at a second low voltage in response to a voltage of the inverting control node.

[0026] In an embodiment, in the gate driver, the individual circuits of the stages may include one scan holding transistor which holds the plurality of scan signals at the first low voltage, so that the area of ​​the gate driver may be reduced.

[0027] According to the embodiment, a display device may include a gate driver having a reduced area, so that a dead space of the display device may be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a schematic block diagram showing a display device according to an embodiment.

[0030] Figure 2 is a diagram showing the embodiment including Figure 1 A schematic block diagram of an example of a gate driver in a display device.

[0031] Figure 3 is a diagram showing the embodiment including Figure 2 A circuit diagram of an example of a stage in a gate driver.

[0032] Figure 4 It is used to describe the Figure 3 A timing diagram of the operation of the stage.

[0033] Figure 5 is a diagram showing the embodiment including Figure 1 A circuit diagram of an example of a pixel in a display device.

[0034] Figure 6 is a diagram showing the embodiment including Figure 1 A schematic block diagram of an example of a gate driver in a display device.

[0035] Figure 7 is a diagram showing the embodiment including Figure 6 A circuit diagram of an example of a stage in a gate driver.

[0036] Figure 8 is a diagram showing the embodiment including Figure 1 A circuit diagram of an example of a pixel in a display device.

[0037] Fig. 9is a block diagram illustrating an electronic device according to an embodiment.

[0038] Fig.10 According to an embodiment of the invention Fig. 9 A perspective view of an example of an electronic device implemented as a computer monitor. DETAILED DESCRIPTION

[0039] Hereinafter, a gate driver and a display device according to an embodiment will be described in more detail with reference to the accompanying drawings. In the accompanying drawings, the same or similar reference numerals will be used for the same elements. However, the present invention can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art.

[0040] It will be understood that when an element (or region, layer, portion, etc.) is referred to as being related to another element such as being "on", "connected to" or "coupled to" another element, the element can be directly on, directly connected to or coupled to the other element, or intervening elements can be disposed between the element and the other element.

[0041] The same reference numerals or symbols always refer to the same elements. In the accompanying drawings, the thickness, proportion and size of the elements are exaggerated for the effective description of the technical content. As used in this article, the term "and / or" includes any and all combinations of one or more of the related listed items. The term "and / or" includes all combinations of one or more that the related configuration can define.

[0042] It will be understood that although the terms "first", "second", etc. can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part discussed below can be referred to as the second element, component, region, layer or part, without departing from the scope of the present invention. Similarly, the second element, component, region, layer or part can be referred to as the first element, component, region, layer or part. As used in this article, the singular form "one" and "the (described)" are intended to also include plural forms, unless the context clearly indicates otherwise.

[0043] In addition, terms such as "under", "lower", "over" or "upper" etc. may be used to describe the relationship of elements shown in the drawings. These terms have relative concepts and are described based on the directions indicated in the drawings.

[0044] It will be further understood that when used in this specification, the terms "comprising", "including", "containing" and / or "having" specify the presence of the described features, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence and / or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. As used herein, "directly disposed on..." may mean that there are no additional layers, films, regions or plates, etc. between a part (e.g., a layer, film, region or plate, etc.) and another part. For example, "directly disposed on..." may mean that two layers or two components are disposed without using an additional component such as a bonding component between them.

[0045] As used herein, "about" or "approximately" includes the stated value and means within an acceptable range of deviation for that particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, or ±5% of the stated value.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which the present invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined as such in this article, these terms will not be interpreted in an idealized or overly formal sense.

[0047] Figure 1 is a schematic block diagram showing a display device 100 according to an embodiment.

[0048] In the examples and with reference to Figure 1 , the display device 100 may include a display panel 110 , a data driver 120 , a gate driver 130 , a power management circuit 140 , and a controller 150 .

[0049] In an embodiment, the display panel 110 may include a plurality of pixels PX. The pixels PX may receive a plurality of data signals DS[1], DS[2], ..., a plurality of gate signals GS[1], GS[2], ..., an initialization voltage VINT, a first power voltage ELVDD, and a second power voltage ELVSS.

[0050] In an embodiment, the data driver 120 may provide data signals DS[1], DS[2], ... to the display panel 110. The data driver 120 may generate the data signals DS[1], DS[2], ... based on the second image data IMG2 and the data control signal DCS. The second image data IMG2 may include gray values ​​corresponding to the pixels PX.

[0051] In an embodiment, the gate driver 130 may provide gate signals GS[1], GS[2], ... to the display panel 110. The gate driver 130 may generate the gate signals GS[1], GS[2], ... based on the gate control signal GCS.

[0052] In an embodiment, the power management circuit 140 may provide the initialization voltage VINT, the first power voltage ELVDD and the second power voltage ELVSS to the display panel 110. The power management circuit 140 may generate the initialization voltage VINT, the first power voltage ELVDD and the second power voltage ELVSS based on the power control signal PCS.

[0053] In an embodiment, the controller 150 may control the operation (or driving) of the data driver 120, the operation (or driving) of the gate driver 130, and the operation (or driving) of the power management circuit 140. The controller 150 may generate the second image data IMG2, the data control signal DCS, the gate control signal GCS, and the power control signal PCS based on the first image data IMG1 and the control signal CS. The first image data IMG1 may include a grayscale value corresponding to the pixel PX.

[0054] Figure 2 is a diagram showing the embodiment including Figure 1 1 is a schematic block diagram of an example of a gate driver 130 in a display device 100 .

[0055] In the examples and with reference to Figure 1 and Figure 2 , the gate driver 130 may include a plurality of stages ST[1], ST[2], . . . , ST[n / 4-1], ST[n / 4] (n is a multiple of 8 (ie, greater than 16)).

[0056] In an embodiment, the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may receive the first to eighth clock signals CK1 to CK8, the first input signal S1, the second input signal S2, the fourth input signal S4 and the sixth input signal S6, the boost clock signal BCK, the carry clock signal CR_CK, the first low voltage VSS1, the second low voltage VSS2 and the gate start signal STVP. In an embodiment, the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may output the first to nth scan signals SC[1] to SC[n]. In this case, the gate signals GS[1], GS[2], ... may include the first to nth scan signals SC[1] to SC[n].

[0057] In an embodiment, each of the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may output a plurality of scan signals. In an embodiment, each of the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may output four scan signals. For example, the first stage ST[1] may output the first to fourth scan signals SC[1] to SC[4], the second stage ST[2] may output the fifth to eighth scan signals SC[5] to SC[8], the n / 4-1 stage ST[n / 4-1] may output the n-7th to n-4th scan signals SC[n-7] to SC[n-4], and the n / 4th stage ST[n / 4] may output the n-3rd to nth scan signals SC[n-3] to SC[n].

[0058] In an embodiment, the odd-numbered stages ST[1], ..., ST[n / 4-1] may receive the first to fourth clock signals CK1 to CK4, and the even-numbered stages ST[2], ..., ST[n / 4] may receive the fifth to eighth clock signals CK5 to CK8.

[0059] In an embodiment, the first stage ST[1] may receive a gate start signal STVP, and the second to n / 4th stages ST[2], ..., ST[n / 4-1], ST[n / 4] may receive first carry signals CR[1], ..., CR[n / 4-2], CR[n / 4-1], respectively. The first to n / 4-1th stages ST[1], ST[2], ..., ST[n / 4-1] may receive last carry signals CR[2], CR[3], ..., CR[n / 4], respectively, and the n / 4th stage ST[n / 4] may receive a gate end signal END. The first to n / 4th stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may output carry signals CR[1], CR[2], ..., CR[n / 4-1], CR[n / 4], respectively.

[0060] Figure 3 is a diagram showing the embodiment including Figure 2 1 is a circuit diagram of an example of a stage ST[k] (k is a natural number greater than or equal to 1 and less than or equal to n / 4) in the gate driver 130.

[0061] In the examples and with reference to Figure 2 and Figure 3 , the stage ST[k] may include a common circuit CCM and a separate circuit CID. The common circuit CCM may control the voltage of the first control node Q1, the voltage of the second control node Q2, and the voltage of the inverting control node QB, and may output a carry signal CR[k] in response to the voltage of the second control node Q2 and the voltage of the inverting control node QB. The separate circuit CID may output a plurality of scan signals SC1, SC2, SC3, and SC4 in response to the voltage of the first control node Q1 and the voltage of the inverting control node QB.

[0062] In an embodiment, when Figure 3 The level ST[k] is Figure 2 When the first stage ST[1] is used, the scan signals SC1, SC2, SC3, and SC4 may be first to fourth scan signals SC[1] to SC[4], respectively. Figure 3 The level ST[k] is Figure 2 When the second stage ST[2] is used, the scan signals SC1, SC2, SC3, and SC4 may be the fifth to eighth scan signals SC[5] to SC[8], respectively. Figure 3 The level ST[k] is Figure 2 When the n / 4-1th stage ST[n / 4-1] is used, the scan signals SC1, SC2, SC3, and SC4 may be the n-7th to n-4th scan signals SC[n-7] to SC[n-4], respectively. Figure 3 The level ST[k] is Figure 2 When the n / 4th stage ST[n / 4] is formed, the scan signals SC1, SC2, SC3 and SC4 may be n-3th to nth scan signals SC[n-3] to SC[n], respectively.

[0063] In an embodiment, when Figure 3 The level ST[k] is Figure 2 When one of the odd-numbered stages ST[1], ..., ST[n / 4-1] is selected, the scan clock signals SC_CK1, SC_CK2, SC_CK3, and SC_CK4 may be the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4, respectively. Figure 3 The level ST[k] is Figure 2When one of the even stages ST[2], ..., ST[n / 4] is selected, the scan clock signals SC_CK1, SC_CK2, SC_CK3 and SC_CK4 may be the fifth clock signal CK5, the sixth clock signal CK6, the seventh clock signal CK7 and the eighth clock signal CK8 respectively.

[0064] In an embodiment, the common circuit CCM may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

[0065] In an embodiment, the first transistor T1 may include a gate electrode receiving the first input signal S1, a first electrode receiving the carry signal CR[k], and a second electrode connected to the first node N1. In an embodiment, the first transistor T1 may include sub-transistors connected in series, wherein an intermediate node is between the sub-transistors connected in series. The intermediate node of the first transistor T1 may be connected to the second node N2.

[0066] In an embodiment, the second transistor T2 may include a gate electrode receiving the second input signal S2, a first electrode connected to the second node N2, and a second electrode connected to the first control node Q1. In an embodiment, the second transistor T2 may include sub-transistors connected in series, wherein the intermediate node is between the sub-transistors connected in series.

[0067] In an embodiment, the third transistor T3 may include a gate electrode connected to the first node N1, a first electrode receiving the sixth input signal S6, and a second electrode connected to the second node N2. The sixth input signal S6 may be a high voltage VH having a turn-on voltage level of the transistor.

[0068] In an embodiment, the fourth transistor T4 may include a gate electrode receiving the advanced signal CR[k-1], a first electrode receiving the advanced signal CR[k-1], and a second electrode connected to the first control node Q1. In an embodiment, the fourth transistor T4 may include sub-transistors connected in series, wherein the intermediate node is between the sub-transistors connected in series.

[0069] In an embodiment, the fifth transistor T5 may include a gate electrode receiving the fourth input signal S4, a first electrode receiving the high voltage VH, and a second electrode connected to the inverting control node QB. In an embodiment, the fifth transistor T5 may include sub-transistors connected in series, wherein the intermediate node is between the sub-transistors connected in series.

[0070] In an embodiment, the sixth transistor T6 may include a gate electrode receiving the fourth input signal S4, a first electrode receiving the second low voltage VSS2, and a second electrode connected to the first control node Q1. The second low voltage VSS2 may have a cut-off voltage level of the transistor. In an embodiment, the sixth transistor T6 may include sub-transistors connected in series, wherein the intermediate node is between the sub-transistors connected in series.

[0071] In an embodiment, the seventh transistor T7 may include a gate electrode connected to the first control node Q1, a first electrode receiving the second low voltage VSS2, and a second electrode connected to the inverting control node QB. In an embodiment, the seventh transistor T7 may include sub-transistors connected in series, wherein the intermediate node is between the sub-transistors connected in series.

[0072] In an embodiment, the eighth transistor T8 may include a gate electrode receiving the carry signal CR[k+1], a first electrode receiving the high voltage VH, and a second electrode connected to the inverting control node QB. In an embodiment, the eighth transistor T8 may include sub-transistors connected in series, wherein the intermediate node is between the sub-transistors connected in series.

[0073] In an embodiment, the ninth transistor T9 may include a gate electrode receiving the carry signal CR[k+1], a first electrode receiving the second low voltage VSS2, and a second electrode connected to the first control node Q1. In an embodiment, the ninth transistor T9 may include sub-transistors connected in series, wherein the intermediate node is between the sub-transistors connected in series.

[0074] In an embodiment, the tenth transistor T10 may include a gate electrode connected to a carry output node NCR from which a carry signal CR[k] is output, a first electrode receiving a high voltage VH, and a second electrode connected to an intermediate node of the fourth transistor T4.

[0075] In an embodiment, the eleventh transistor T11 may include a gate electrode connected to the inverting control node QB, a first electrode receiving the second low voltage VSS2, and a second electrode connected to the first control node Q1. In an embodiment, the eleventh transistor T11 may include sub-transistors connected in series, wherein the intermediate node is interposed between the sub-transistors connected in series.

[0076] In an embodiment, the twelfth transistor T12 may include a gate electrode connected to the inversion control node QB, a first electrode receiving the high voltage VH, and a second electrode connected to the middle node of the seventh transistor T7.

[0077] In an embodiment, the thirteenth transistor T13 may include a gate electrode receiving the advanced signal CR[k-1], a first electrode receiving the high voltage VH, and a second electrode connected to the second control node Q2.

[0078] In an embodiment, the fourteenth transistor T14 may include a gate electrode connected to the inverting control node QB, a first electrode receiving the second low voltage VSS2, and a second electrode connected to the second control node Q2. In an embodiment, the fourteenth transistor T14 may include sub-transistors connected in series, wherein the intermediate node is interposed between the sub-transistors connected in series.

[0079] In an embodiment, the fifteenth transistor T15 may include a gate electrode connected to the first control node Q1 , a first electrode receiving the boosting clock signal BCK, and a second electrode connected to the carry output node NCR.

[0080] In an embodiment, the sixteenth transistor T16 may output the carry clock signal CR_CK as the carry signal CR[k] in response to the voltage of the second control node Q2. The sixteenth transistor T16 may include a gate electrode connected to the second control node Q2, a first electrode receiving the carry clock signal CR_CK, and a second electrode connected to the carry output node NCR. The sixteenth transistor T16 may be referred to as a carry buffer transistor.

[0081] In an embodiment, the seventeenth transistor T17 may maintain the carry signal CR[k] at the second low voltage VSS2 in response to the voltage of the inverting control node QB. The seventeenth transistor T17 may include a gate electrode connected to the inverting control node QB, a first electrode receiving the second low voltage VSS2, and a second electrode connected to the carry output node NCR.

[0082] In an embodiment, the eighteenth transistor T18 may maintain the carry signal CR[k] at the second low voltage VSS2 in response to the voltage of the inverting control node QB. The eighteenth transistor T18 may include a gate electrode connected to the inverting control node QB, a first electrode receiving the second low voltage VSS2, and a second electrode connected to the carry output node NCR. The seventeenth transistor T17 and the eighteenth transistor T18 may be referred to as carry-hold transistors.

[0083] In an embodiment, the first capacitor C1 may include a first electrode connected to the carry output node NCR and a second electrode connected to the first control node Q1.

[0084] In an embodiment, the second capacitor C2 may include a first electrode receiving the high voltage VH and a second electrode connected to the first node N1.

[0085] In an embodiment, the third capacitor C3 may include a first electrode connected to the carry output node NCR and a second electrode connected to the second control node Q2.

[0086] In an embodiment, the individual circuit CID may include a plurality of scan buffer transistors TCB1 , TCB2 , TCB3 , and TCB4 and a scan holding transistor TCH.

[0087] In an embodiment, the scan buffer transistors TCB1, TCB2, TCB3 and TCB4 may output a plurality of scan clock signals SC_CK1, SC_CK2, SC_CK3 and SC_CK4 as a plurality of scan signals SC1, SC2, SC3 and SC4 in response to a voltage of the first control node Q1. The scan buffer transistors TCB1, TCB2, TCB3 and TCB4 may include a first scan buffer transistor TCB1, a second scan buffer transistor TCB2, a third scan buffer transistor TCB3 and a fourth scan buffer transistor TCB4.

[0088] In an embodiment, the first scan buffer transistor TCB1 may include a gate electrode connected to the first control node Q1 , a first electrode receiving the first scan clock signal SC_CK1 , and a second electrode connected to the first scan output node NSC1 from which the first scan signal SC1 is output.

[0089] In an embodiment, the second scan buffer transistor TCB2 may include a gate electrode connected to the first control node Q1, a first electrode receiving the second scan clock signal SC_CK2, and a second electrode connected to the second scan output node NSC2 from which the second scan signal SC2 is output.

[0090] In an embodiment, the third scan buffer transistor TCB3 may include a gate electrode connected to the first control node Q1, a first electrode receiving the third scan clock signal SC_CK3, and a second electrode connected to a third scan output node NSC3 from which the third scan signal SC3 is output.

[0091] In an embodiment, the fourth scan buffer transistor TCB4 may include a gate electrode connected to the first control node Q1, a first electrode receiving the fourth scan clock signal SC_CK4, and a second electrode connected to a fourth scan output node NSC4 from which the fourth scan signal SC4 is output.

[0092] In an embodiment, the scan holding transistor TCH may maintain the plurality of scan signals SC1, SC2, SC3, and SC4 at a first low voltage VSS1 in response to a voltage of the inverting control node QB. The first low voltage VSS1 may have a cut-off voltage level of the transistor. The scan holding transistor TCH may include a gate electrode connected to the inverting control node QB, a first electrode receiving the first low voltage VSS1, and a second electrode connected to the first to fourth scan output nodes NSC1, NSC2, NSC3, and NSC4.

[0093] In an embodiment, each of the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, TCB1, TCB2, TCB3, TCB4, and TCH included in the stage ST[k] may be an N-type transistor (e.g., an NMOS transistor). However, the present invention is not limited thereto, and in another embodiment, at least one of the transistors T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, T17, T18, TCB1, TCB2, TCB3, TCB4, and TCH may be a P-type transistor (e.g., a PMOS transistor).

[0094] Figure 4 It is used to describe the Figure 3 A timing diagram of the operation of stage ST[k] is shown in FIG.

[0095] In the examples and with reference to Figure 3 and Figure 4 , at the first time point TP1, the advanced signal CR[k-1] may transition from the cut-off voltage level (low voltage level) to the on-voltage level (high voltage level). The fourth transistor T4 may transmit the voltage having the on-voltage level of the advanced signal CR[k-1] to the first control node Q1 in response to the advanced signal CR[k-1] having the on-voltage level. The thirteenth transistor T13 may transmit the high voltage VH to the second control node Q2 in response to the advanced signal CR[k-1] having the on-voltage level. The seventh transistor T7 may transmit the second low voltage VSS2 to the inverting control node QB in response to the voltage having the on-voltage level of the first control node Q1.

[0096] In an embodiment, in a first time period P1 in which a voltage having a turn-on voltage level is applied to each of the first control node Q1 and the second control node Q2 and a voltage having a turn-off voltage level is applied to the inverting control node QB, first pulses PSC1, second pulses PSC2, third pulses PSC3 and fourth pulses PSC4 of the first to fourth scan signals SC1, SC2, SC3 and SC4 corresponding to the first scan clock signal SC_CK1, the second scan clock signal SC_CK2, the third scan clock signal SC_CK3 and the fourth scan clock signal SC_CK4, respectively, may be sequentially output from the first to fourth scan output nodes NSC1, NSC2, NSC3 and NSC4, respectively. In the first period P1, in response to the voltage having a turn-on voltage level of the first control node Q1, the first scan buffer transistor TCB1, the second scan buffer transistor TCB2, the third scan buffer transistor TCB3 and the fourth scan buffer transistor TCB4 can respectively output the first to fourth scan clock signals SC_CK1, SC_CK2, SC_CK3 and SC_CK4 as the first to fourth scan signals SC1, SC2, SC3 and SC4.

[0097] In an embodiment, in the first period P1, a pulse PCR of a carry signal CR[k] corresponding to the carry clock signal CR_CK may be output from the carry output node NCR. In the first period P1, the sixteenth transistor T16 may output the carry clock signal CR_CK as the carry signal CR[k] in response to the voltage of the second control node Q2 having a turn-on voltage level.

[0098] In an embodiment, at the second time point TP2, the last carry signal CR[k+1] may transition from the cut-off voltage level to the on-voltage level. The eighth transistor T8 may transmit the high voltage VH to the inverting control node QB in response to the last carry signal CR[k+1] having the on-voltage level. The ninth transistor T9 may transmit the second low voltage VSS2 to the first control node Q1 in response to the last carry signal CR[k+1] having the on-voltage level. The fourteenth transistor T14 may transmit the second low voltage VSS2 to the second control node Q2 in response to the voltage of the inverting control node QB having the on-voltage level.

[0099] In an embodiment, in a second period P2 in which a voltage having a cut-off voltage level is applied to each of the first control node Q1 and the second control node Q2 and a voltage having a turn-on voltage level is applied to the inversion control node QB, a first low voltage VSS1 may be output from the first to fourth scan output nodes NSC1, NSC2, NSC3, and NSC4. In the second period P2, in response to the voltage having the turn-on voltage level of the inversion control node QB, the scan holding transistor TCH may output the first low voltage VSS1 as the first to fourth scan signals SC1, SC2, SC3, and SC4.

[0100] Figure 5 is a diagram showing the embodiment including Figure 1 1 is a circuit diagram of an example of a pixel PX in the display device 100.

[0101] In the examples and with reference to Figure 5 , the pixel PX may include a first pixel transistor M1, a second pixel transistor M2, a third pixel transistor M3, a storage capacitor CST, and a light emitting element EL.

[0102] In an embodiment, the first pixel transistor M1 may include a gate electrode connected to the first pixel node NP1 , a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the second pixel node NP2 .

[0103] In an embodiment, the second pixel transistor M2 may include a gate electrode receiving the scan signal SC, a first electrode receiving the data signal DS, and a second electrode connected to the first pixel node NP1.

[0104] In an embodiment, the third pixel transistor M3 may include a gate electrode receiving the scan signal SC, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the second pixel node NP2.

[0105] In an embodiment, each of the transistors M1, M2, and M3 included in the pixel PX may be an N-type transistor. However, the present invention is not limited thereto, and in another embodiment, at least one of the transistors M1, M2, and M3 included in the pixel PX may be a P-type transistor.

[0106] In an embodiment, the storage capacitor CST may include a first electrode connected to the first pixel node NP1 and a second electrode connected to the second pixel node NP2.

[0107] In an embodiment, the pixel PX may include three transistors and one capacitor. However, the present invention is not limited thereto, and in another embodiment, the pixel PX may include two or four transistors and / or more than two capacitors.

[0108] In an embodiment, the light emitting element EL may include a first electrode connected to the second pixel node NP2 and a second electrode receiving the second power supply voltage ELVSS. In an embodiment, the light emitting element EL may be an organic light emitting diode. However, the present invention is not limited thereto, and in another embodiment, the light emitting element EL may be one of an inorganic light emitting diode, a micro light emitting diode, and a quantum dot light emitting diode.

[0109] Figure 6 is a diagram showing the embodiment including Figure 1 1 is a block diagram of an example of a gate driver 130 - 1 in a display device 100 .

[0110] In the examples and with reference to Figure 1 and Figure 6 , the gate driver 130-1 may include a plurality of stages ST[1], ST[2], . . . , ST[n / 4-1], ST[n / 4]. Figure 6 The gate driver 130-1 described with reference to Figure 2 Descriptions of elements that are substantially the same as or similar to the elements of the described gate driver 130 will be omitted.

[0111] In an embodiment, the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may receive the first to sixteenth clock signals CK1 to CK16, the first to sixth input signals S1 to S6, the first low voltage VSS1, the second low voltage VSS2, and the gate start signal STVP. In an embodiment, the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may output the first to nth scan signals SC[1] to SC[n] and the first to nth sensing signals SS[1] to SS[n]. In this case, the gate signals GS[1], GS[2], ... may include the first to nth scan signals SC[1] to SC[n] and the first to nth sensing signals SS[1] to SS[n].

[0112] In an embodiment, each of the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may output a plurality of scan signals and a plurality of sensing signals. In an embodiment, each of the stages ST[1], ST[2], ..., ST[n / 4-1], ST[n / 4] may output four scan signals and four sensing signals. For example, the first stage ST[1] can output the first to fourth scanning signals SC[1] to SC[4] and the first to fourth sensing signals SS[1] to SS[4], the second stage ST[2] can output the fifth to eighth scanning signals SC[5] to SC[8] and the fifth to eighth sensing signals SS[5] to SS[8], the n / 4-1th stage ST[n / 4-1] can output the n-7th to n-4th scanning signals SC[n-7] to SC[n-4] and the n-7th to n-4th sensing signals SS[n-7] to SS[n-4], and the n / 4th stage ST[n / 4] can output the n-3rd to nth scanning signals SC[n-3] to SC[n] and the n-3rd to nth sensing signals SS[n-3] to SS[n].

[0113] In an embodiment, the odd-numbered stages ST[1], ..., ST[n / 4-1] can receive the first to fourth clock signals CK1 to CK4 and the ninth to twelfth clock signals CK9 to CK12, and the even-numbered stages ST[2], ..., ST[n / 4] can receive the fifth to eighth clock signals CK5 to CK8 and the thirteenth to sixteenth clock signals CK13 to CK16.

[0114] Figure 7 is a diagram showing the embodiment including Figure 6 1 is a circuit diagram of an example of a stage ST- 1 [k] in a gate driver 130 - 1 .

[0115] In the examples and with reference to Figure 6 and Figure 7 , the stage ST-1[k] may include a common circuit CCM and an individual circuit CID. The common circuit CCM may control the voltage of the first control node Q1, the voltage of the second control node Q2, and the voltage of the inverting control node QB, and may output a carry signal CR[k] in response to the voltage of the second control node Q2 and the voltage of the inverting control node QB. The individual circuit CID may output a plurality of scan signals SC1, SC2, SC3, and SC4 and a plurality of sense signals SS1, SS2, SS3, and SS4 in response to the voltage of the first control node Q1 and the voltage of the inverting control node QB. Reference Figure 7 Description of level ST-1[k] with reference to Figure 3 Descriptions of elements that are substantially the same as or similar to the elements of the described stage ST[k] will be omitted.

[0116] In an embodiment, when Figure 7 The ST-1[k] level is Figure 6 When the first stage ST[1] is used, the sensing signals SS1, SS2, SS3, and SS4 may be first to fourth sensing signals SS[1] to SS[4], respectively. Figure 7 The ST-1[k] level is Figure 6 When the second stage ST[2] is used, the sensing signals SS1, SS2, SS3, and SS4 may be fifth to eighth sensing signals SS[5] to SS[8], respectively. Figure 7 The ST-1[k] level is Figure 6 When the n / 4-1th stage ST[n / 4-1] is used, the sensing signals SS1, SS2, SS3, and SS4 may be the n-7th to n-4th sensing signals SS[n-7] to SS[n-4], respectively. Figure 7 The ST-1[k] level is Figure 6 When the n / 4th stage ST[n / 4] is performed, the sensing signals SS1, SS2, SS3, and SS4 may be n-3th to nth sensing signals SS[n-3] to SS[n], respectively.

[0117] In an embodiment, when Figure 7 The ST-1[k] level is Figure 6 When one of the odd-numbered stages ST[1], . . . , ST[n / 4-1] is detected, the sensing clock signals SS_CK1, SS_CK2, SS_CK3, and SS_CK4 may be the ninth to twelfth clock signals CK9 to CK12, respectively. Figure 7 The ST-1[k] level is Figure 6 , ST[n / 4], the sensing clock signals SS_CK1, SS_CK2, SS_CK3, and SS_CK4 may be the thirteenth to sixteenth clock signals CK13 to CK16, respectively.

[0118] In an embodiment, the individual circuit CID may include a plurality of scan buffer transistors TCB1 , TCB2 , TCB3 , and TCB4 , a scan hold transistor TCH , a plurality of sense buffer transistors TSB1 , TSB2 , TSB3 , and TSB4 , and a sense hold transistor TSH .

[0119] In an embodiment, in response to the voltage of the first control node Q1, the sensing buffer transistors TSB1, TSB2, TSB3, and TSB4 may output a plurality of sensing clock signals SS_CK1, SS_CK2, SS_CK3, and SS_CK4 as a plurality of sensing signals SS1, SS2, SS3, and SS4. The sensing buffer transistors TSB1, TSB2, TSB3, and TSB4 may include a first sensing buffer transistor TSB1, a second sensing buffer transistor TSB2, a third sensing buffer transistor TSB3, and a fourth sensing buffer transistor TSB4.

[0120] In an embodiment, the first sensing buffer transistor TSB1 may include a gate electrode connected to the first control node Q1 , a first electrode receiving the first sensing clock signal SS_CK1 , and a second electrode connected to the first sensing output node NSS1 from which the first sensing signal SS1 is output.

[0121] In an embodiment, the second sensing buffer transistor TSB2 may include a gate electrode connected to the first control node Q1 , a first electrode receiving the second sensing clock signal SS_CK2 , and a second electrode connected to a second sensing output node NSS2 from which the second sensing signal SS2 is output.

[0122] In an embodiment, the third sensing buffer transistor TSB3 may include a gate electrode connected to the first control node Q1 , a first electrode receiving the third sensing clock signal SS_CK3 , and a second electrode connected to a third sensing output node NSS3 from which the third sensing signal SS3 is output.

[0123] In an embodiment, the fourth sensing buffer transistor TSB4 may include a gate electrode connected to the first control node Q1 , a first electrode receiving the fourth sensing clock signal SS_CK4 , and a second electrode connected to a fourth sensing output node NSS4 from which the fourth sensing signal SS4 is output.

[0124] In an embodiment, the sensing holding transistor TSH may hold the plurality of sensing signals SS1, SS2, SS3, and SS4 at a first low voltage VSS1 in response to a voltage of an inverting control node QB. The sensing holding transistor TSH may include a gate electrode connected to the inverting control node QB, a first electrode receiving the first low voltage VSS1, and a second electrode connected to first to fourth sensing output nodes NSS1, NSS2, NSS3, and NSS4.

[0125] Figure 8 is a diagram showing the embodiment including Figure 1 1 is a circuit diagram of an example of a pixel PX- 1 in the display device 100 .

[0126] In the examples and with reference to Figure 8 , the pixel PX-1 may include a first pixel transistor M1, a second pixel transistor M2, a third pixel transistor M3, a storage capacitor CST, and a light emitting element EL. Figure 8 The pixel PX-1 described with reference Figure 5 Description of elements that are substantially the same as or similar to the elements of the described pixel PX will be omitted.

[0127] In an embodiment, the third pixel transistor M3 may include a gate electrode receiving the sensing signal SS, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the second pixel node NP2.

[0128] Fig. 9 is a block diagram showing an electronic device 1000 according to an embodiment. Fig.10 According to an embodiment of the invention Fig. 9 FIG. 1 is a perspective view of an example in which the electronic device 1000 is implemented as a computer monitor.

[0129] In the examples and with reference to Fig. 9 and Fig.10 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (I / O) device 1040, a power supply 1050, and a display device 1060. The electronic device 1000 may further include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or communicating with other systems.

[0130] In an embodiment, Fig.10 As shown in , the electronic device 1000 can be implemented as a computer monitor. However, the present invention is not limited thereto, and according to another embodiment, the electronic device 1000 can be implemented as a television, a mobile phone, a video phone, a smart board, a tablet PC, a vehicle navigation, a laptop computer, or a head-mounted display, etc.

[0131] In an embodiment, the processor 1010 may perform a specific calculation or task. According to an embodiment, the processor 1010 may be a microprocessor or a central processing unit (CPU), etc. The processor 1010 may be connected to other components through an address bus, a control bus, and a data bus, etc. According to an embodiment, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. In an embodiment, the processor 1010 may process the first image data ( Figure 1 IMG1) and control signal ( Figure 1 CS) is provided to the display device 1060.

[0132] In an embodiment, the memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM) and / or a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM.

[0133] In an embodiment, the storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The I / O device 1040 may include an input device such as a keyboard, a keypad, a touch pad, a touch screen, or a mouse, and an output device such as a speaker or a printer. The power supply 1050 may supply power required for the operation of the electronic device 1000. The display device 1060 may be connected to other components through a bus or other communication links. The display device 1060 may correspond to Figure 1 A display device 100 is provided.

[0134] In an embodiment, in a gate driver included in the display device 1060, a separate circuit of a stage may include a scan holding transistor that holds a plurality of scan signals at a first low voltage, so that the area of ​​the gate driver can be reduced. Accordingly, the dead space of the display device 1060 can be reduced.

[0135] According to the embodiment, the display device may be applied to a display device included in a computer, a notebook computer, a mobile phone, a smart phone, a smart pad, a smart watch, a PMP, a PDA, an MP3 player, or the like.

[0136] Although the gate driver and the display device according to the embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by a person of ordinary skill in the relevant technical field without departing from the spirit of the technology.

[0137] Although some embodiments have been described, it will be readily appreciated by those skilled in the art that many modifications are possible without substantially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention. Therefore, it should be understood that the foregoing is an explanation of various embodiments and should not be construed as being limited to the disclosed specific embodiments, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the present invention. In addition, embodiments or parts of embodiments may be combined in whole or in part without departing from the scope of the present invention.

Claims

1. A gate driver comprising a plurality of stages, each of the plurality of stages comprising: A common circuit controls the voltage of the first control node, the voltage of the second control node and the voltage of the inverting control node; as well as a separate circuit that outputs a plurality of scan signals in response to the voltage of the first control node and the voltage of the inverting control node, Wherein, the separate circuit comprises: a plurality of scan buffer transistors outputting a plurality of scan clock signals as the plurality of scan signals in response to the voltage of the first control node; and A scan holding transistor holds the plurality of scan signals at a first low voltage in response to the voltage of the inversion control node.

2. The gate driver according to claim 1, wherein: The plurality of scan buffer transistors include: a first scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a first scan clock signal, and a second electrode connected to a first scan output node outputting a first scan signal; a second scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a second scan clock signal, and a second electrode connected to a second scan output node outputting a second scan signal; a third scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a third scan clock signal, and a second electrode connected to a third scan output node outputting a third scan signal; and a fourth scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a fourth scan clock signal, and a second electrode connected to a fourth scan output node outputting a fourth scan signal, and The scan holding transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the first low voltage, and a second electrode connected to the first scan output node to the fourth scan output node.

3. The gate driver according to claim 2, wherein: In a first period in which a voltage having a turn-on voltage level is applied to the first control node, first to fourth pulses corresponding to the first to fourth scan clock signals, respectively, are sequentially output from the first to fourth scan output nodes, respectively.

4. The gate driver according to claim 3, wherein: In a second period in which a voltage having a turn-on voltage level is applied to the inversion control node, the first low voltage is output from the first output node to the fourth output node.

5. The gate driver according to any one of claims 1 to 4, wherein: The separate circuit further comprises: a plurality of sensing buffer transistors outputting a plurality of sensing clock signals as a plurality of sensing signals in response to the voltage of the first control node; and A sense holding transistor holds the plurality of sense signals at the first low voltage in response to the voltage of the inversion control node.

6. The gate driver according to claim 5, wherein: The plurality of sensing buffer transistors include: a first sensing buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a first sensing clock signal, and a second electrode connected to a first sensing output node outputting a first sensing signal; a second sensing buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a second sensing clock signal, and a second electrode connected to a second sensing output node outputting a second sensing signal; a third sensing buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a third sensing clock signal, and a second electrode connected to a third sensing output node outputting a third sensing signal; and a fourth sensing buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a fourth sensing clock signal, and a second electrode connected to a fourth sensing output node outputting a fourth sensing signal, and The sensing holding transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the first low voltage, and a second electrode connected to the first sensing output node to the fourth sensing output node.

7. A display device, comprising: A display panel including a plurality of pixels; a data driver, providing a plurality of data signals to the display panel; as well as a gate driver including a plurality of stages for providing a plurality of scanning signals to the display panel, Wherein, each of the plurality of stages comprises: a common circuit that controls a voltage of the first control node, a voltage of the second control node, and a voltage of the inverting control node; and a separate circuit that outputs the plurality of scan signals in response to the voltage of the first control node and the voltage of the inverting control node, and Wherein, the separate circuit comprises: a plurality of scan buffer transistors outputting a plurality of scan clock signals as the plurality of scan signals in response to the voltage of the first control node; and A scan holding transistor holds the plurality of scan signals at a first low voltage in response to the voltage of the inversion control node.

8. The display device according to claim 7, wherein: The plurality of scan buffer transistors include: a first scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a first scan clock signal, and a second electrode connected to a first scan output node outputting a first scan signal; a second scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a second scan clock signal, and a second electrode connected to a second scan output node outputting a second scan signal; a third scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a third scan clock signal, and a second electrode connected to a third scan output node outputting a third scan signal; and a fourth scan buffer transistor including a gate electrode connected to the first control node, a first electrode receiving a fourth scan clock signal, and a second electrode connected to a fourth scan output node outputting a fourth scan signal, and The scan holding transistor includes a gate electrode connected to the inverting control node, a first electrode receiving the first low voltage, and a second electrode connected to the first scan output node to the fourth scan output node.

9. The display device according to claim 7, wherein: Each of the plurality of pixels comprises: a first pixel transistor including a gate electrode connected to a first pixel node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second pixel node; a second pixel transistor comprising a gate electrode receiving a scan signal among the plurality of scan signals, a first electrode receiving a data signal among the plurality of data signals, and a second electrode connected to the first pixel node; a third pixel transistor including a gate electrode, a first electrode receiving an initialization voltage, and a second electrode connected to the second pixel node; a storage capacitor including a first electrode connected to the first pixel node and a second electrode connected to the second pixel node; and The light emitting element includes a first electrode connected to the second pixel node and a second electrode receiving a second power supply voltage.

10. The display device according to claim 9, wherein: The gate electrode of the third pixel transistor receives the scan signal among the plurality of scan signals.

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