Grid driving circuit and driving method for realizing panel frequency division display

Abstract

The invention discloses a gate drive circuit for realizing panel frequency division display, which comprises a plurality of cascaded GOA units and a plurality of frequency division control units, the frequency division control units are uniformly distributed among the GOA units, the frequency division control units are controlled to be opened through frequency division control signals, a plurality of clock signals are respectively accessed to the GOA units, and the GOA units are connected with the frequency division control units. A gate drive signal of the upper-level GOA unit and a frequency division display signal of the frequency division control unit are input into the lower-level GOA unit, each GOA unit comprises a pull-up unit, a pull-up control unit, a pull-down control unit, a phase inverter, a pull-down maintaining unit, a Reset unit, a common end Q and a gate drive signal output end, the pull-up unit controls the gate drive signal output end to output a signal, and the pull-down control unit controls the pull-down maintaining unit to output the signal. The phase inverter and the pull-down maintaining unit maintain the potential of the common end Q and the potential of the gate driving signal output end, the pull-up control unit pulls up the potential of the common end Q and opens the pull-up unit, the pull-down control unit pulls down the potential of the common end Q and closes the pull-up unit, and the Reset unit maintains the potential of the common end and the potential of the gate driving signal output end.

Description

Technical Field

[0001] The present invention relates to the field of display driving technology, and in particular to a gate driving circuit and a driving method for display panel frequency division display. Background Art

[0002] The gate driver circuit used for display panel driving contains multiple cascaded GOA (Gate Driver on Array) units. The output signal generated by each GOA unit is not only used to drive the display panel, but also turns on the next GOA unit through level transmission. Due to the characteristics of the GOA unit level transmission, all GOA units output signals in sequence, and the refresh frequency of the entire display panel remains consistent.

[0003] The GOA unit uses a thin film transistor (TFT) circuit to output gate drive signals row by row. In common GOA level transmission circuits, the opening and closing of the gate signal is affected by the upper and lower gate drive signals. Within one frame, through the gate drive signal, all gate signals complete a potential rise and fall action. During the potential rise period, the thin film transistors of the corresponding row of pixels are turned on to complete the charging of the pixels.

[0004] In actual use, users usually watch videos, play games, etc. in a part of the screen, which has a higher requirement for refresh frequency, while the other part is the comment area or unused, which has a lower requirement for refresh frequency. Therefore, making the video, game and other areas with high refresh frequency requirements and the comment area and unused areas operate at different refresh frequencies can not only meet user needs, but also reduce the power consumption of the display panel. Summary of the invention

[0005] The purpose of the present invention is to overcome the defects and shortcomings of the prior art, and to provide a gate drive circuit and a drive method for realizing panel frequency division display, adding a frequency division control unit and an input frequency division control signal, so as to realize different display areas working at different refresh frequencies, and the display frequencies can be independent of each other, thereby reducing display power consumption.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A gate driving circuit for realizing frequency division display of a panel, comprising a plurality of cascaded GOA units, and a plurality of frequency division control units evenly distributed between the GOA units, a plurality of clock signals are respectively connected to the plurality of GOA units, the frequency division control unit is connected to an upper level GOA unit and a lower level GOA unit, the upper level GOA unit is used to turn on the lower level GOA unit during normal display, and the frequency division control unit is used to turn on the lower level GOA unit during frequency division display;

[0008] The GOA unit includes a pull-up unit, a pull-up control unit, a pull-down control unit, an inverter, a pull-down maintaining unit, a Reset unit, a common terminal Q, and a gate drive signal output terminal. The pull-up unit is used to control the gate drive signal output terminal to output a square wave signal to drive display and upper and lower level transmission. The inverter and the pull-down maintaining unit are used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during non-level transmission. The pull-up control unit is used to pull up the potential of the common terminal Q and turn on the pull-up unit. The pull-down control unit is used to pull down the potential of the common terminal Q and turn off the pull-up unit. The Reset unit is used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during non-display.

[0009] Multiple frequency division control units are turned on through frequency division control signals. By setting a specific clock signal, the turned-on frequency division control unit drives the lower-level GOA unit connected to it. The gate drive signal output by the upper-level GOA unit and the frequency division display signal output by the frequency division control unit are simultaneously input into the lower-level GOA unit for driving the frequency division display.

[0010] Furthermore, the frequency division control unit includes a frequency division control signal input terminal, an opening position signal input terminal, a first thin film transistor T1, a level transfer control signal input terminal, n second thin film transistors T2(1) to T2(n) and n frequency division display signal output terminals F(1) to F(n);

[0011] The gate of the first thin film transistor T1 is connected to the frequency division control signal input terminal, the drain of the first thin film transistor T1 is connected to the start bit signal input terminal, the source of the first thin film transistor T1 is connected to the level transfer control signal input terminal, and the gates and drains of the n second thin film transistors T2(1) to T2(n) are respectively connected to the level transfer control signal input terminal;

[0012] The source and drain electrodes of the n second thin film transistors T2(1) to T2(n) are connected to form a common terminal S1, the source electrode of the second thin film transistor T2(i) is connected to the frequency division display signal output terminal F(i), and the frequency division display signal output terminal F(i) is connected to the common terminal Q(i) of the i-th level GOA unit after the frequency division control unit, n≥1, i is a positive integer less than or equal to n.

[0013] Further, the GOA unit also includes an upper gate drive signal input terminal, a lower gate drive signal input terminal, a clock signal input terminal, a low potential signal input terminal, a high potential signal input terminal and a Reset signal input terminal, the upper gate drive signal input terminal is connected to the pull-up control unit, the lower gate drive signal input terminal is connected to the pull-down control unit, the clock signal input terminal is connected to the pull-up unit, the Reset signal input terminal is connected to the Reset unit, and the high potential signal input terminal is connected to the inverter;

[0014] The common terminal Q is respectively connected to the pull-up unit, the pull-up control unit, the pull-down control unit, the inverter, the pull-down maintaining unit and the Reset unit, the gate drive signal output terminal is respectively connected to the pull-up unit, the pull-down maintaining unit and the Reset unit, the low potential signal input terminal is respectively connected to the pull-down control unit, the inverter, the Reset unit and the pull-down maintaining unit, the pull-down control unit, the inverter and the Reset unit are respectively connected to the pull-up control unit, and the pull-down maintaining unit is respectively connected to the inverter and the Reset unit.

[0015] Furthermore, the frequency division control signal input terminal is used to receive the frequency division control signal STVD, the start bit signal input terminal is used to receive the clock signal, the frequency division display signal output terminal is used to output the frequency division display signal to start the lower-level GOA unit, and the frequency division control units at different positions are connected to different clock signals to realize the use of different clock signals to control the operation of different frequency division control units.

[0016] Furthermore, when the frequency division control signal STVD is at a low potential, the frequency division control signal STVD at a low potential turns off the first thin film transistor T1, the common terminal S1 is at a low potential, and the common terminal S1 at a low potential connects the gates of the second thin film transistors T2(1) to T2(n) and turns them off;

[0017] When the frequency division control signal STVD is at a high potential, the high potential frequency division control signal STVD turns on the first thin film transistor T1, and the high potential clock signal pulls up the potential of the common terminal S1 through the first thin film transistor T1, and the high potential common terminal S1 turns on the second thin film transistors T2(1)~T(n).

[0018] Furthermore, the number of clock signals connected to the GOA unit is an even number, the number of frequency division control units is less than or equal to the number of clock signals, and the number of second thin film transistors T2 and frequency division display signal output terminals is half of the number of clock signals.

[0019] A driving method for realizing panel frequency division display, applied to the gate driving circuit for realizing panel frequency division display according to any one of claims 1 to 5, characterized in that it comprises:

[0020] Before outputting the frequency division control signal, the clock signals CK(1) to CK(2n) become low potential after the upper GOA unit of the frequency division control unit displays the end. After the clock signal drops to low potential, the Reset signal becomes high potential. The high potential Reset signal turns on the Reset units of all GOA units, and the Reset units of the GOA units reduce the potential of the gate drive signal of the GOA unit and the common terminal Q point to a low potential.

[0021] After that, the Reset signal becomes a low level. After the Reset signal becomes a low level, the frequency division control signal outputs a high level signal. By setting the specific clock signal CK(m) to a high level, the corresponding frequency division control unit is turned on. The turned-on frequency division control unit drives the lower-level GOA unit connected to it, and sets the display frequency of the corresponding panel by setting the clock signal and the data signal.

[0022] Furthermore, when frequency division display is not performed, it includes:

[0023] The frequency division control signal STVD is at a low potential, the control signal input terminal of the frequency division control unit inputs a low potential to the gate of the first thin film transistor T1, the first thin film transistor T1 is in a closed state, the common terminal S1 connected to the gate of the second thin film transistor T2 is at a low potential, the second thin film transistor T2 is turned off, the frequency division display signal output terminal has no output signal, all GOA units of the gate drive circuit are normally transmitted, and the display area is displayed at the same frequency.

[0024] Furthermore, when frequency division display is performed, it includes:

[0025] After the upper GOA unit of the frequency division control unit outputs the gate drive signal, all clock signals CK(1) to CK(2n) output low potential, and the Reset signal outputs high potential, pulling down the potential of the common terminal Q and the gate drive signal output terminal in the GOA unit;

[0026] After the Reset signal changes from high potential to low potential, the frequency division control signal STVD and the specific clock signal CK(m) output high potential to the frequency division control unit, and the frequency division control unit outputs the frequency division display signal to turn on the lower GOA unit;

[0027] The frequency division control unit is connected to different clock signals, and controls the display of different areas by setting a specific clock signal with a high output potential. By matching the appropriate clock signal waveform and data signal waveform, the frequency division display of different parts can be realized.

[0028] A display panel comprises a display area and a non-display area, wherein the non-display area applies a gate drive circuit as described above, and when a driving method without frequency division display is used, the display panel displays at the same refresh frequency; when a driving method with frequency division display is used, the display refresh frequencies of different areas in the display panel are independent of each other.

[0029] Compared with the prior art, the present invention adds a frequency division control unit in the gate drive circuit of the display panel, and controls the refresh frequency of the gate drive signal output by the display area and the display area GOA unit through the frequency division control unit, so that the display panel operates at different refresh frequencies in different display areas separated by the frequency division control unit. When the frequency division control unit does not input the frequency division control signal, the gate drive signal of the upper GOA unit is normally input to the lower GOA unit, so that the entire display area operates at the same refresh frequency. The present invention realizes display of different display areas at different refresh frequencies through level transmission control, reduces the power consumption of the display panel, and improves the market competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of the structure of the display panel in Example 1.

[0031] Figure 2 Schematic diagram of the connection between the frequency division control unit and the GOA unit in Example 1.

[0032] Figure 3 Schematic diagram of the structure of the GOA unit in Example 1.

[0033] Figure 4 Schematic diagram of the connection between the frequency division control unit and the GOA unit in Example 1.

[0034] Figure 5 This is a schematic diagram of the signal waveform before the frequency division control unit in Example 1 works.

[0035] Figure 6 This is a schematic diagram of signal waveforms when the frequency division control unit in Example 1 is working.

[0036] Figure 7 This is a schematic diagram of the operation of the display panel in Example 2 when the display frequency is divided into 60 Hz and 120 Hz.

[0037] Figure 8 This is a schematic diagram of the operation of the display panel in Example 3 when displaying at 60 Hz and 90 Hz divided frequencies. DETAILED DESCRIPTION

[0038] The gate driving circuit and driving method for realizing frequency division display of a panel according to the present invention will be further described below in conjunction with the accompanying drawings and specific embodiments.

[0039] Example 1

[0040] See also Figure 1The present embodiment provides a display panel capable of frequency division display and a working method thereof. The display panel includes a GOA driving circuit (gate driving circuit) and display areas ① to ④. The GOA driving circuit (gate driving circuit) includes a plurality of GOA units and frequency division control units 1 to 3. The frequency division control units 1 to 3 are respectively located at the intersection of the dividing lines of the display areas ① to ④, and the frequency division control units 1 to 3 are respectively used to control the GOA units corresponding to the display areas ② to ④ to be turned on.

[0041] See also Figure 2 The frequency division control unit is turned on by the frequency division control signal line outputting the frequency division control signal STVD, and the frequency division display signal output by the frequency division control unit and the gate drive signal output by the upper GOA unit are simultaneously input into the lower GOA unit, wherein the frequency division control unit is used to turn on the lower GOA unit during frequency division display, and the upper GOA unit is used to turn on the lower GOA unit during normal display.

[0042] See also Figure 3 The GOA unit includes a pull-up unit, a pull-up control unit, a pull-down control unit, an inverter, a pull-down maintaining unit, a Reset unit, a common terminal Q(N), an upper gate drive signal G(N-1) input terminal, a lower gate drive signal G(N+1) input terminal, a gate drive signal G(N) output terminal, a clock signal CK(M) input terminal, a low potential signal VGL input terminal, a high potential signal VGH input terminal and a Reset signal input terminal, the upper gate drive signal G(N-1) input terminal is connected to the pull-up control unit, the lower gate drive signal G(N+1) input terminal is connected to the pull-down control unit, and the clock signal CK(M) input terminal is connected to the pull-up unit.

[0043] The Reset signal input terminal is connected to the Reset unit, the high potential signal VGH input terminal is connected to the inverter, the common terminal Q(N) is respectively connected to the pull-up unit, the pull-up control unit, the pull-down control unit, the inverter, the pull-down maintaining unit and the Reset unit, the gate drive signal G(N) output terminal is respectively connected to the pull-up unit, the pull-down maintaining unit and the Reset unit, the low potential signal VGL input terminal is respectively connected to the pull-down control unit, the inverter, the Reset unit and the pull-down maintaining unit, the pull-down control unit, the inverter and the Reset unit are respectively connected to the pull-up control unit, and the pull-down maintaining unit is respectively connected to the inverter and the Reset unit.

[0044] After the gate drive signal G(N-1) of the upper GOA unit is input into the GOA unit, the pull-up control unit pulls up the potential of the common terminal Q(N) and turns on the pull-up unit. Then the square wave signal output by the clock signal CK(M) is sent to the pull-up unit. The pull-up unit controls the gate drive signal G(N) output terminal to output a square wave signal for driving the panel display and the upper and lower levels. After the gate drive signal G(N) output terminal outputs a square wave, the gate drive signal G(N+1) of the lower GOA unit is input into the pull-down control unit, which pulls down the potential of the common terminal Q(N) and turns off the pull-up unit. The inverter and the pull-down maintenance unit work together to maintain the common terminal Q(N) and the gate drive signal G(N) output terminal at a low potential during the non-stage transmission period. The reset unit is used to maintain the common terminal Q(N) and the gate drive signal output terminal G(N) at a low potential during the non-display period of each frame.

[0045] See also Figure 4 The frequency division control unit includes a frequency division control signal input terminal, an enable signal input terminal, a first thin film transistor T1, a level transmission control signal input terminal, n second thin film transistors T2(1)~T2(n) and n frequency division display signal output terminals F(1)~F(n), the gate of the first thin film transistor T1 is connected to the frequency division control signal input terminal, the drain of the first thin film transistor T1 is connected to the enable signal input terminal, the source of the first thin film transistor T1 is connected to the level transmission control signal input terminal, and the gate and drain of the n second thin film transistors T2(1)~T2(n) are respectively connected to the level transmission control signal input terminal.

[0046] The source and drain electrodes of the n second thin film transistors T2(1) to T2(n) are connected to form a common terminal S1, the source electrode of the second thin film transistor T2(i) is connected to the frequency division display signal output terminal F(i), and the frequency division display signal output terminal F(i) is connected to the common terminal Q(i) of the i-th level GOA unit after the frequency division control unit, n≥1, i is a positive integer less than or equal to n. The number of clock signals connected to the GOA unit is an even number, the number of frequency division control units is less than or equal to the number of clock signals, and the number of second thin film transistors T2 and frequency division display signal output terminals is half of the number of clock signals.

[0047] The frequency division control signal input terminal is used to receive the frequency division control signal STVD, the start bit signal input terminal is used to receive the specific clock signal CK(m), the first thin film transistor T1 and the second thin film transistor T2(1)~T2(n) are used to convert the received frequency division control signal and clock signal into a frequency division display signal. The frequency division display signal output terminal is used to output the frequency division display signal to start the lower GOA unit, and the frequency division control units at different positions are connected to different clock signals to realize the use of different clock signals to control the operation of different frequency division control units.

[0048] When the frequency division control signal STVD is at a low potential, the low potential frequency division control signal STVD turns off the first thin film transistor T1, the common terminal S1 is at a low potential, and the low potential common terminal S1 is connected to the gates of the second thin film transistors T2(1) to T2(n) and turns them off. When the frequency division control signal STVD is at a high potential, the high potential frequency division control signal STVD turns on the first thin film transistor T1, the high potential clock signal pulls up the potential of the common terminal S1 through the first thin film transistor T1, and the high potential common terminal S1 turns on the second thin film transistors T2(1) to T(n).

[0049] When the first thin film transistor T1 of the frequency division control unit receives a high potential input signal of the frequency division control signal STVD, the source and drain of the first thin film transistor T1 are turned on, and the common terminal S1 is connected to the clock signal CK(m) through the first thin film transistor T1. When the clock signal CK(m) is at a low potential, the common terminal S1 is at a low potential, the gate and drain of the second thin film transistor T2(i) are connected to the low potential common terminal S1, the source and drain of the second thin film transistor T2(i) are not turned on, and the frequency division display signal output terminal F(i) is at a low potential. When the clock signal CK(m) is set to a high potential, the common terminal S1 is at a high potential, the gate and drain of the second thin film transistor T2(i) are connected to the high potential common terminal S1, the source and drain of the second thin film transistor T2(i) are turned on, and the frequency division display signal output terminal F(i) outputs a high potential signal.

[0050] When the frequency division control signal STVD and the clock signal CK(m) output high potential signals at the same time, the frequency division display signal output terminal F(i) outputs a high potential signal to the Q(k+i) point of the connected GOA unit, and the connected GOA unit outputs a gate drive signal G(k+i), where k is a positive integer less than or equal to the number of GOA units.

[0051] When the gate drive circuit is normally transmitted to the GOA unit connected to the frequency division control unit, since the second thin film transistor T2(i) is a diode structure with the gate and the drain connected, the second thin film transistor T2(i) is unidirectionally conducted, and the potential fluctuation of the common terminal Q(N+i) of the GOA unit will not affect the frequency division control unit. The clock signal CK(m) input to the frequency division control unit and the clock signal CK(M) input to the GOA unit connected to the frequency division control unit are different clock signals to avoid the connected GOA unit outputting the gate drive signal G(N) in advance during the operation of the frequency division control unit.

[0052] In this embodiment, when the display area is normally displayed, the circuit is normally transmitted, and the frequency division control signal STVD is at a low potential during the display period. Figure 5The figure shows the change of the potential of the frequency division control signal STVD, the common terminal S1 in the frequency division control unit and the common terminal Q(N) of the GOA unit connected thereto, and the gate drive signal G(N) over time: when the gate drive signal is transmitted to the GOA unit connected to the frequency division control unit, the frequency division control signal STVD always maintains a low potential; the first thin film transistor T1 and the second thin film transistor T2(i) are both in the off state, and the common terminal S1 maintains a low potential;

[0053] The potential of the common terminal Q(k+1) of the k+1th level GOA unit has two rising sections and two falling sections. The first rising section is driven by the gate drive signal of the upper level GOA unit, the second rising section and the first falling section come from the capacitive coupling effect of the rising and falling potential of the connected clock signal CK(m), and the second falling section is pulled down by the gate drive signal of the lower level GOA unit; the high potential common terminal Q(k+1) turns on the pull-up unit of the GOA unit, and the gate drive signal G(k+1) is connected to the clock signal CK(m) through the pull-up unit, and outputs Figure 5 Square wave signal; similarly, the potential change of the gate drive signal G(k+2)~G(k+n) is Figure 5 The square wave signal shown in FIG. 1 is a square wave signal, and the time difference between the rising edges of adjacent gate driving signals G(k+1) to G(k+n) is equal.

[0054] When the display area works in a frequency division display mode: all clock signals CK(m) remain at a low potential after the upper GOA unit of the frequency division control unit outputs a gate drive signal, and then the Reset signal outputs a high potential signal to clear the charge of the common terminal Q(N) and the gate drive signal G(N) in all GOA units; after the Reset signal potential drops to a low potential, the frequency division control signal STVD outputs a high potential signal to turn on the first thin film transistor T1 in the frequency division control unit, and the corresponding frequency division control unit can be turned on by controlling different clock signals CK(m) to output high potential signals; by setting the waveforms of the clock signal and the data signal, it is possible to control different areas to work at different refresh frequencies.

[0055] Figure 5The Reset signal outputs a high potential signal to clear the waveform changes of the common terminal Q(k) and the gate drive signal G(k) in the k-th level GOA unit. The gate drive signal output by the k-1-th level GOA unit pulls up the potential of the common terminal Q(k). The clock signal CK(m) connected to the k-th level GOA unit pulls up the voltage of the common terminal Q(k) for the second time through the capacitive coupling effect, and at the same time pulls up the potential of the gate drive signal G(k) through the pull-up unit of the GOA unit. After the potential of the clock signal CK(m) drops, the potential of the common terminal Q(k) is pulled down for the first time by the clock signal CK(m) due to the capacitive coupling effect, and the gate drive signal G(k) pulls down the potential to the low potential of the clock signal CK(m) through the pull-up unit. When the potential of the Reset signal rises, the potential of the common terminal Q(k) is reduced to the low potential of the low potential signal through the Reset unit.

[0056] Figure 6 The figure is a schematic diagram of the potential changes of each signal when the frequency division control unit is working. The frequency division control signal STVD and the clock signal CK(m) simultaneously output high potential signals to the frequency division control unit, and the frequency division control unit outputs high potential signals to the frequency division display signal output terminals F(1) to F(n). The common terminals Q(k+1) to Q(k+n) of the k+1 to k+n level GOA units are pulled up to a high potential by connecting to the frequency division display signal output terminals F(1) to F(n) respectively. The clock signals CK(m+1) to CK(m+n) are connected to the k+1 to k+n level GOA units respectively, and the clock signals CK(m+1) to CK(m+n) sequentially output high potential signals of the same width.

[0057] The gate drive signals G(k+1)~G(k+n) are connected to the clock signals CK(m+1)~CK(m+n) through the pull-up unit, and the gate drive signals G(k+1)~G(k+n) sequentially output high-potential signals having the same width as the high-potential signal width of the clock signal. Figure 6 Only the potential changes of the common terminals Q(k+1) and Q(k+2), the clock signals CK(m+1) and CK(m+2), and the gate drive signals G(k+1) and G(k+2) are reflected in the figure. The common terminals Q(N), the connected clock signals CK(M) and the gate drive signals G(N) of the k+3rd to k+nth level GOA units are similar to the examples and will not be elaborated here.

[0058] Example 2

[0059] Based on the first embodiment, this embodiment provides a working mode of displaying at a refresh rate of 60 Hz and 120 Hz. The structure of the display panel is the same as that of the first embodiment. Figure 1The display panel shown has a similar structure, including three groups of frequency division control units 1 to 3, a frequency division control signal STVD and four clock signals CK(1) to CK(4), wherein the clock signals CK(1) to CK(3) are connected to the frequency division control units 1 to 3 respectively, the lower-level GOA unit of the frequency division control unit 1 is connected to the clock signal CK(2), the lower-level GOA unit of the frequency division control unit 2 is connected to the clock signal CK(3), and the lower-level GOA unit of the frequency division control unit 3 is connected to the clock signal CK(4).

[0060] Figure 7 The working sequence of the GOA units corresponding to display areas ① to ④ and the timing settings of some signal lines are shown. During the first frame display time of 120 Hz, display areas ①, ③, and ④ are turned on in sequence. During the display period of display area ①, the high-voltage signals output by the clock signals CK(1) to CK(4) and the width of the gate drive signal G(N) output by the GOA units corresponding to display area ① match the refresh frequency of 60 Hz. During the display period of display areas ③ and ④, the high-voltage signals output by the clock signals CK(1) to CK(4) and the width of the gate drive signal G(N) output by the GOA units corresponding to display areas ③ and ④ match the refresh frequency of 120 Hz. After the display ends, the blanking period at the end of the frame begins.

[0061] During the 120 Hz display time of the second frame, display areas ②, ③, and ④ are turned on in sequence. During the display period of display area ②, the high potential signals output by the clock signals CK(1) to CK(4) and the width of the gate drive signal G(N) output by the GOA unit corresponding to display area ② match the refresh frequency of 60 Hz. During the display period of display areas ③ and ④, the high potential signals output by the clock signals CK(1) to CK(4) and the width of the gate drive signal G(N) output by the GOA unit corresponding to display areas ③ and ④ match the refresh frequency of 120 Hz. After the display ends, the blanking period at the end of the frame begins.

[0062] During the first frame of 120 Hz display, after the display area ① finishes working, the Reset signal, the frequency division control signal STVD and the clock signal CK(2) are output as in Example 1. Figure 5-6 The same signal as in the embodiment 1 clears the residual charge in the GOA unit and turns on the GOA unit corresponding to the display area ③. The reset signal clears the residual charge in the GOA unit during the blanking period at the end of the first frame. At the initial stage of the second frame 120Hz display, the frequency division control signal STVD and the clock signal CK(1) are output as in the embodiment 1. Figure 6The same signal as in Example 1 turns on the GOA unit corresponding to display area ②. During the second frame 120Hz display time, after display area ② finishes working, the Reset signal, the frequency division control signal STVD and the clock signal CK(2) are output as in Example 1. Figure 5-6 The same signal in the display area ③ clears the residual charge in the GOA unit and turns on the GOA unit corresponding to the display area ③.

[0063] Example 3

[0064] This embodiment provides a working mode of a display panel, which uses the same circuit structure as that of Embodiment 2 to realize display at refresh rates of 60 Hz and 90 Hz in different areas of the display panel. In this embodiment, display areas ① and ② of the display panel operate at a refresh rate of 90 Hz, and display areas ③ and ④ operate at a refresh rate of 60 Hz. Frequency division display in different display areas is realized by setting the signal output of the frequency division control signal STVD and the clock signals CK(1) to CK(4) in Embodiment 2.

[0065] Figure 8 The sequence of signal refresh times of different display areas in Example 3 is shown. In the first frame time calculated by 60Hz display, display area ①, display area ③, display area ②, display area ④, and display area ① are refreshed in sequence, followed by blanking time for non-display signal input. In the second frame time calculated by 60Hz display, display area ②, display area ③, display area ①, display area ④, and display area ② are refreshed in sequence, followed by blanking time for non-display signal input.

[0066] Taking the time of one frame displayed at 60Hz as the reference time, set the signal refresh time of display areas ① and ② to 1 / 15 of the reference time, and the signal refresh time of display areas ③ and ④ to 1 / 10 of the reference time. Under the signal refresh time setting, the signal refresh frequencies of display areas ① to ④ are completely consistent with the refresh frequencies of 60Hz and 90Hz during normal display.

[0067] In summary, the present invention adds a frequency division control unit to the gate drive circuit of the display panel, and controls the refresh frequency of the gate drive signal output by the display area and the display area GOA unit through the frequency division control unit, so that the display panel operates at different refresh frequencies in different display areas separated by the frequency division control unit. When the frequency division control unit does not input the frequency division control signal, the gate drive signal of the upper GOA unit is normally input to the lower GOA unit, so that the entire display area operates at the same refresh frequency. The present invention realizes display of different display areas at different refresh frequencies through level transmission control, reduces the power consumption of the display panel, and improves the market competitiveness of the product.

[0068] The above description is a detailed description of the preferred feasible embodiments of the present invention, but the embodiments are not intended to limit the scope of the patent application of the present invention. All equivalent changes or modified changes completed under the technical spirit disclosed by the present invention should fall within the patent scope covered by the present invention.

Claims

1. A gate driving circuit for realizing frequency division display of a panel, characterized in that: It includes multiple cascaded GOA units and multiple frequency division control units evenly distributed between the GOA units. Multiple clock signals are respectively connected to the multiple GOA units. The frequency division control unit is connected to the upper-level GOA unit and the lower-level GOA unit. The upper-level GOA unit is used to turn on the lower-level GOA unit during normal display, and the frequency division control unit is used to turn on the lower-level GOA unit during frequency division display. The GOA unit includes a pull-up unit, a pull-up control unit, a pull-down control unit, an inverter, a pull-down maintaining unit, a Reset unit, a common terminal Q, and a gate drive signal output terminal. The pull-up unit is used to control the gate drive signal output terminal to output a square wave signal to drive display and upper and lower level transmission. The inverter and the pull-down maintaining unit are used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during non-level transmission. The pull-up control unit is used to pull up the potential of the common terminal Q and turn on the pull-up unit. The pull-down control unit is used to pull down the potential of the common terminal Q and turn off the pull-up unit. The Reset unit is used to maintain the common terminal Q and the gate drive signal output terminal at a low potential during non-display. Multiple frequency division control units are turned on through frequency division control signals. By setting a specific clock signal, the turned-on frequency division control unit drives the lower-level GOA unit connected to it. The gate drive signal output by the upper-level GOA unit and the frequency division display signal output by the frequency division control unit are simultaneously input into the lower-level GOA unit for driving the frequency division display.

2. The gate driving circuit for realizing panel frequency division display according to claim 1, characterized in that: The frequency division control unit comprises a frequency division control signal input terminal, an opening position signal input terminal, a first thin film transistor T1, a level transfer control signal input terminal, n second thin film transistors T2(1) to T2(n) and n frequency division display signal output terminals F(1) to F(n); The gate of the first thin film transistor T1 is connected to the frequency division control signal input terminal, the drain of the first thin film transistor T1 is connected to the start bit signal input terminal, the source of the first thin film transistor T1 is connected to the level transfer control signal input terminal, and the gates and drains of the n second thin film transistors T2(1) to T2(n) are respectively connected to the level transfer control signal input terminal; The source and drain electrodes of the n second thin film transistors T2(1) to T2(n) are connected to form a common terminal S1, the source electrode of the second thin film transistor T2(i) is connected to the frequency division display signal output terminal F(i), and the frequency division display signal output terminal F(i) is connected to the common terminal Q(i) of the i-th level GOA unit after the frequency division control unit, n≥1, i is a positive integer less than or equal to n.

3. The gate driving circuit for realizing panel frequency division display according to claim 1, characterized in that: The GOA unit further includes an upper gate drive signal input terminal, a lower gate drive signal input terminal, a clock signal input terminal, a low potential signal input terminal, a high potential signal input terminal and a Reset signal input terminal, wherein the upper gate drive signal input terminal is connected to the pull-up control unit, the lower gate drive signal input terminal is connected to the pull-down control unit, the clock signal input terminal is connected to the pull-up unit, the Reset signal input terminal is connected to the Reset unit, and the high potential signal input terminal is connected to the inverter; The common terminal Q is respectively connected to the pull-up unit, the pull-up control unit, the pull-down control unit, the inverter, the pull-down maintaining unit and the Reset unit, the gate drive signal output terminal is respectively connected to the pull-up unit, the pull-down maintaining unit and the Reset unit, the low potential signal input terminal is respectively connected to the pull-down control unit, the inverter, the Reset unit and the pull-down maintaining unit, the pull-down control unit, the inverter and the Reset unit are respectively connected to the pull-up control unit, and the pull-down maintaining unit is respectively connected to the inverter and the Reset unit.

4. The gate driving circuit for realizing panel frequency division display according to claim 2, characterized in that: The frequency division control signal input terminal is used to receive the frequency division control signal STVD, the start bit signal input terminal is used to receive a specific clock signal, and the frequency division display signal output terminal is used to output the frequency division display signal to start the lower-level GOA unit. The frequency division control units at different positions are connected to different clock signals to realize the use of different clock signals to control the operation of different frequency division control units.

5. The gate driving circuit for realizing panel frequency division display according to claim 4, characterized in that: When the frequency division control signal STVD is at a low potential, the frequency division control signal STVD at a low potential turns off the first thin film transistor T1, the common terminal S1 is at a low potential, and the common terminal S1 at a low potential connects the gates of the second thin film transistors T2(1) to T2(n) and turns them off; When the frequency division control signal STVD is at a high potential, the high potential frequency division control signal STVD turns on the first thin film transistor T1, and the high potential clock signal pulls up the potential of the common terminal S1 through the first thin film transistor T1, and the high potential common terminal S1 turns on the second thin film transistors T2(1)~T(n).

6. The gate driving circuit for realizing panel frequency division display according to claim 2, characterized in that: The number of clock signals connected to the GOA unit is an even number, the number of frequency division control units is less than or equal to the number of clock signals, and the number of second thin film transistors T2 and frequency division display signal output terminals is half of the number of clock signals.

7. A driving method for realizing panel frequency division display, applied to the gate driving circuit for realizing panel frequency division display according to any one of claims 1 to 5, characterized in that: include: Before outputting the frequency division control signal, the clock signals CK(1) to CK(2n) become low potential after the upper GOA unit of the frequency division control unit displays the end. After the clock signal drops to low potential, the Reset signal becomes high potential. The high potential Reset signal turns on the Reset units of all GOA units, and the Reset units of the GOA units reduce the potential of the gate drive signal of the GOA unit and the common terminal Q point to a low potential. After that, the Reset signal becomes a low level. After the Reset signal becomes a low level, the frequency division control signal outputs a high level signal. By setting the specific clock signal CK(m) to a high level, the corresponding frequency division control unit is turned on. The turned-on frequency division control unit drives the lower-level GOA unit connected to it, and sets the display frequency of the corresponding panel by setting the clock signal and the data signal.

8. The driving method for realizing panel frequency division display according to claim 7, characterized in that: When no frequency division is performed, it includes: The frequency division control signal STVD is at a low potential, the control signal input terminal of the frequency division control unit inputs a low potential to the gate of the first thin film transistor T1, the first thin film transistor T1 is in a closed state, the common terminal S1 connected to the gate of the second thin film transistor T2 is at a low potential, the second thin film transistor T2 is turned off, the frequency division display signal output terminal has no output signal, all GOA units of the gate drive circuit are normally transmitted, and the display area is displayed at the same frequency.

9. The driving method for realizing panel frequency division display according to claim 7, characterized in that: When frequency division is performed, it includes: After the upper GOA unit of the frequency division control unit outputs the gate drive signal, all clock signals CK(1) to CK(2n) output low potential, and the Reset signal outputs high potential, pulling down the potential of the common terminal Q and the gate drive signal output terminal in the GOA unit; After the Reset signal changes from high potential to low potential, the frequency division control signal STVD and the specific clock signal CK(m) output high potential to the frequency division control unit, and the frequency division control unit outputs the frequency division display signal to turn on the lower GOA unit; The frequency division control unit is connected to different clock signals, and controls the display of different areas by setting a specific clock signal with a high output potential. By matching the appropriate clock signal waveform and data signal waveform, the frequency division display of different parts can be realized.

10. A display panel, comprising a display area and a non-display area, characterized in that: The gate driving circuit described in any one of claims 1 to 6 is applied to the non-display area. When the driving method described in claim 8 is used, the display panel displays at the same refresh frequency; when the driving method described in claim 9 is used, the display refresh frequencies of different areas in the display panel are independent of each other.

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