Display panel and display device

Abstract

The invention discloses a display panel and a display device. In the display panel, a grid electrode of a first transistor in a first sub-pixel is connected with a first scanning line, a grid electrode of a first transistor in a second sub-pixel is connected with a second scanning line, and grid electrodes of second transistors in the first sub-pixel and the second sub-pixel are connected with a third scanning line; in one picture refresh cycle, a first scanning signal on the first scanning line comprises a first effective level, a second scanning signal on the second scanning line comprises a second effective level, a third scanning signal on the third scanning line comprises a third effective level, and the starting moment of the second effective level is not earlier than the ending moment of the first effective level; the difference value between the first cut-off level and the first effective level of the first scanning signal is delta V1, the difference value between the second cut-off level and the second effective level of the second scanning signal is delta V2, the duration of the first effective level is t1, and the duration of the second effective level is t2; and delta V1 * t1 is less than delta V2 * t2.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] From the Cathode Ray Tube (CRT) era to the Liquid Crystal Display (LCD) era, and now to the Organic Light-Emitting Diode (OLED) era and the LED display era, the display industry has experienced decades of development and has changed with each passing day. The display industry is closely related to our lives, from traditional mobile phones, tablets, TVs and PCs to today's smart wearable devices, VR, car displays and other electronic devices, all of which are inseparable from display technology.

[0003] With the development of display technology, users have higher and higher requirements for display products. Therefore, how to optimize the display effect of display panels is a technical problem that those skilled in the art are committed to solving. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which can improve display effects.

[0005] On the one hand, an embodiment of the present application provides a display panel, including: a sub-pixel, the sub-pixel includes a driving transistor, a first transistor, and a second transistor, the first transistor is connected between a data line and a first electrode of the driving transistor, and the second transistor is connected between the second electrode of the driving transistor and a gate of the driving transistor; the sub-pixel includes a first sub-pixel and a second sub-pixel, the gate of the first transistor in the first sub-pixel is connected to a first scan line, the gate of the first transistor in the second sub-pixel is connected to a second scan line, and the gates of the second transistors in the first sub-pixel and the second sub-pixel are both connected to a third scan line; in a picture refresh cycle, the gate of the first transistor on the first scan line is connected to a first scan line, the gate of the first transistor in the second sub-pixel is connected to a second scan line, and the gates of the second transistors in the first sub-pixel and the second sub-pixel are both connected to a third scan line. A scanning signal includes a first effective level, a second scanning signal on a second scanning line includes a second effective level, a third scanning signal on a third scanning line includes a third effective level, a time period of the third effective level covers a time period of the first effective level and a time period of the second effective level, and a start time of the second effective level is not earlier than an end time of the first effective level; a difference between a first cutoff level and a first effective level of the first scanning signal is ΔV1, a difference between a second cutoff level and a second effective level of the second scanning signal is ΔV2, a duration of the first effective level is t1, and a duration of the second effective level is t2; |ΔV1|*t1<|ΔV2|*t2.

[0006] On the other hand, an embodiment of the present application provides a display device, including the display panel as described in the above embodiment.

[0007] According to the display panel and the display device provided by the embodiments of the present application, the first scan line is connected to the gate of the first transistor in the first sub-pixel, the second scan line is connected to the gate of the first transistor in the second sub-pixel, the third sub-pixel is connected to the gates of the second transistors in the first sub-pixel and the second sub-pixel, the signal on the first scan line is first at a valid level, and the signal on the second scan line is then at a valid level, and the signals on the first scan line and the second scan line satisfy the relationship |ΔV1|*t1<|ΔV2|*t2, which can increase the sufficiency of data voltage writing for the second sub-pixel, and / or directly increase the data voltage writing time of the second sub-pixel, thereby directly compensating for the brightness difference caused by the data voltage writing time of the first sub-pixel being longer than the data voltage writing time of the second sub-pixel.

[0008] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Other features, objects and advantages of the present application will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings, in which the same or similar reference numerals represent the same or similar features and the accompanying drawings are not drawn to scale.

[0010] Figure 1 A schematic diagram of a circuit structure of a sub-pixel in the related art is shown;

[0011] Figure 2 Show Figure 1 A timing diagram of

[0012] Figure 3 A schematic diagram showing the structure of a display panel provided in an embodiment of the present application is shown;

[0013] Figure 4 A schematic diagram of a circuit structure of a sub-pixel provided in an embodiment of the present application is shown;

[0014] Figure 5 A timing diagram of a display panel provided by an embodiment of the present application is shown;

[0015] Figure 6 Another schematic diagram of the structure of a display panel provided in an embodiment of the present application is shown;

[0016] Figure 7 A schematic diagram of a circuit structure of a shift register provided in an embodiment of the present application is shown;

[0017] Figure 8 Another timing diagram of a display panel provided by an embodiment of the present application is shown;

[0018] Fig. 9 Another timing diagram of the display panel provided by the embodiment of the present application is shown;

[0019] Fig.10 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0020] Fig.11 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0021] Fig.12 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0022] Fig.13 Another schematic diagram of a circuit structure of a sub-pixel provided in an embodiment of the present application is shown;

[0023] Fig.14 A schematic diagram showing a layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0024] Fig.15 Another schematic diagram showing a layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0025] Fig.16 A schematic diagram showing another layout structure of a local area of ​​a display panel provided in an embodiment of the present application;

[0026] Fig.17 Another structural schematic diagram of a display panel provided in an embodiment of the present application is shown;

[0027] Fig.18 A schematic diagram of the structure of a display device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only configured to explain the present application and are not configured to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0029] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0030] It should be understood that when describing the structure of a component, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Moreover, if the component is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0031] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0032] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the internal connection of two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the embodiments of the present application can be understood according to the specific circumstances.

[0033] It is obvious to those skilled in the art that various modifications and changes can be made in the present application without departing from the spirit or scope of the present application. Therefore, the present application is intended to cover modifications and changes of the present application that fall within the scope of the corresponding claims (technical solutions for protection) and their equivalents. It should be noted that the implementation methods provided in the embodiments of the present application can be combined with each other without contradiction.

[0034] Before describing the technical solutions provided by the embodiments of the present application, in order to facilitate the understanding of the embodiments of the present application, the present application first specifically describes the problems existing in the related art:

[0035] like Figure 1 As shown, the sub-pixel generally includes a driving transistor T3', a data writing transistor T2' and a threshold compensation transistor T4', the first electrode of the data writing transistor T2' is connected to the data line data, the second electrode of the data writing transistor T2' and the first electrode of the driving transistor T3' are connected to the node N2, the first electrode of the threshold compensation transistor T4' and the gate of the driving transistor T3' are connected to the node N1, and the first electrode of the threshold compensation transistor T4' and the second electrode of the driving transistor T3' are connected. The data writing transistor is used to write the data voltage to the gate of the driving transistor, and the threshold compensation transistor is used to compensate for the threshold voltage of the driving transistor. For example, the scanning signal connected to the gate of the data writing transistor T2' is called the SP signal, and the signal connected to the gate of the threshold compensation transistor is called the SN signal.

[0036] In the related art, in order to improve the afterimage problem of the OLED display panel under low-frequency driving, the same SP signal is used to drive one row of sub-pixels, and the same SN signal is used to drive two rows of sub-pixels. Figure 2 As shown, the i-th row of sub-pixels is connected to the SP(i) signal, the i+1-th row of sub-pixels is connected to the SP(i+1) signal, and the i-th row of sub-pixels and the i+1-th row of sub-pixels are connected to the SN signal. Figure 1 In the example, the low level of the SP signal is the effective level, and the low level of the SN signal is the effective level. The effective level refers to the level that can control the conduction of the transistor. The SP(i) signal is first at a low level, and the SP(i+1) signal is then at a low level. When the SP(i+1) signal is at a low level, since the SN signal is still at a valid level, the voltage of the node N2 in the i-th row of sub-pixels will still be written to the node N1, resulting in a difference in the writing time of the data voltages of the two rows of sub-pixels, resulting in different writing capabilities of the data voltages of the two rows of sub-pixels, resulting in a difference in the driving currents of the two rows of sub-pixels, resulting in a difference in brightness of the two rows of sub-pixels (for example, one row is bright and the other row is dark), which is prone to fine horizontal stripes.

[0037] In order to solve the above problems, embodiments of the present application provide a display panel and a display device. Various embodiments of the display panel and the display device will be described below in conjunction with the accompanying drawings.

[0038] An embodiment of the present application provides a display panel, which may be an organic light emitting diode (OLED) display panel.

[0039] Please refer to Figure 3 and Figure 4The display panel 100 includes a sub-pixel 10, and the sub-pixel 10 includes a driving transistor T3, a first transistor T1, and a second transistor T2. The first transistor T1 is connected between a data line data and a first electrode of the driving transistor T3, and the second transistor T2 is connected between a second electrode of the driving transistor T3 and a gate of the driving transistor T3.

[0040] Specifically, the first electrode of the first transistor T1 is connected to the data line data, and the first electrode of the first transistor T1 and the driving transistor T3 are connected to the node N2. The first electrode of the second transistor T2 and the gate of the driving transistor T3 are connected to the node N1, and the second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3. The first transistor T1 is used to write a data voltage to the driving transistor T3, and the second transistor T2 is used to compensate for the threshold voltage of the driving transistor T3. The first transistor T1 can also be called a data writing transistor, and the second transistor T2 can also be called a threshold compensation transistor.

[0041] The plurality of sub-pixels 10 are distributed in an array in a first direction X and a second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X is a row direction, and the second direction Y is a column direction. Of course, the row direction and the column direction can be interchanged.

[0042] The sub-pixel 10 includes a first sub-pixel 11 and a second sub-pixel 12, the gate of the first transistor T1 in the first sub-pixel 11 is connected to the first scan line S1, the gate of the first transistor T1 in the second sub-pixel 12 is connected to the second scan line S2, and the gates of the second transistor T2 in the first sub-pixel 11 and the second sub-pixel 12 are both connected to the third scan line S3.

[0043] As an example, the first scan line S1, the second scan line S2, and the third scan line S3 all extend along the first direction X, and the first sub-pixel 11 and the second sub-pixel 12 connected to the same third scan line S3 are adjacent to each other in the second direction Y. Taking the first direction X as the row direction as an example, the first scan line S1 is used to drive the pixel row where the first sub-pixel 11 is located, the second scan line S2 is used to drive the pixel row where the second sub-pixel 12 is located, and the third scan line S3 is used to drive the pixel row where the first sub-pixel 11 and the second sub-pixel 12 are located. In other words, the first scan line S1 is used to drive a row of sub-pixels, the second scan line S2 is used to drive a row of sub-pixels, and the third scan line S3 is used to drive at least two rows of sub-pixels.

[0044] Exemplarily, the pixel row where the first sub-pixel 11 is located is an odd-numbered row, and the pixel row where the second sub-pixel 12 is located is an even-numbered row.

[0045] like Figure 5As shown, in one picture refresh cycle, the first scan signal on the first scan line S1 includes a first effective level, the second scan signal on the second scan line S2 includes a second effective level, and the third scan signal on the third scan line S3 includes a third effective level. The period of the third effective level covers the period of the first effective level and the second effective level, and the start time of the second effective level is not earlier than the end time of the first effective level; the difference between the first cut-off level and the first effective level of the first scan signal is ΔV1, the difference between the second cut-off level and the second effective level of the second scan signal is ΔV2, the duration of the first effective level is t1, and the duration of the second effective level is t2; |ΔV1|*t1<|ΔV2|*t2.

[0046] As an example, |ΔV1|<|ΔV2|, and t1=t2.

[0047] As another example, |ΔV1|=|ΔV2|, and t1<t2.

[0048] As yet another example, |ΔV1|<|ΔV2|, and t1<t2.

[0049] It is understandable that the start time of the second effective level on the second scan line S2 is not earlier than the end time of the first effective level on the first scan line S1, and the first sub-pixel first writes the data voltage, and then the second sub-pixel writes the data voltage. As an example, the end time of the first effective level on the first scan line S1 and the start time of the second effective level on the second scan line S2 differ by 1H, H=1 / (F*n), F refers to the refresh frequency of the display panel, and n refers to the total number of rows of sub-pixels.

[0050] After the first scan signal on the first scan line S1 is switched from the first effective level to the first cut-off level, since the signal on the third scan line is still at a valid level, the level of the node N2 in the first sub-pixel 11 will still be written into the node N1, that is, the gate of the driving transistor in the first sub-pixel 11 will still be written with the data voltage until the driving transistor in the first sub-pixel 11 becomes in the cut-off state, and the writing of the data voltage is stopped.

[0051] In the case of |ΔV1|<|ΔV2|, the difference between the second cutoff level and the second effective level on the second scan line S2 is larger, so that the first transistor T1 in the second sub-pixel 12 is more fully opened, increasing the sufficiency of the data voltage writing of the second sub-pixel 12 to compensate for the brightness difference caused by the fact that the data voltage writing time of the first sub-pixel 11 is longer than the data voltage writing time of the second sub-pixel 12.

[0052] When t1<t2, it is equivalent to directly increasing the data voltage writing time of the second sub-pixel 12, thereby directly compensating for the brightness difference caused by the data voltage writing time of the first sub-pixel 11 being longer than the data voltage writing time of the second sub-pixel 12.

[0053] It should be noted that Figure 5 The effective level on the first scan line S1, the second scan line S2 and the third scan line S3 is a low level, and the cut-off level on the first scan line S1, the second scan line S2 and the third scan line S3 is a high level for illustration. In this case, the first transistor and the second transistor are P-type transistors. However, this is not intended to limit the present application. The transistor in the embodiment of the present application can be an N-type transistor or a P-type transistor. For an N-type transistor, the effective level is a high level and the cut-off level is a low level. That is, when the gate potential of the N-type transistor is a high level, the first pole and the second pole are connected, and when the gate potential of the N-type transistor is a low level, the first pole and the second pole are disconnected. For a P-type transistor, the effective level is a low level and the cut-off level is a high level. That is, when the gate potential of the P-type transistor is a low level, the first pole and the second pole are connected, and when the gate potential of the P-type transistor is a high level, the first pole and the second pole are disconnected.

[0054] It is understandable that t1 and t2 are both positive numbers. When the first transistor and the second transistor are P-type transistors, the first cut-off level and the second cut-off level are positive voltages, the first effective level and the second effective level are negative voltages, and ΔV1 and ΔV2 are positive numbers. When the first transistor and the second transistor are N-type transistors, the first cut-off level and the second cut-off level are negative voltages, the first effective level and the second effective level are positive voltages, and ΔV1 and ΔV2 are negative numbers.

[0055] In the present embodiment, the first scan line is connected to the gate of the first transistor in the first sub-pixel, the second scan line is connected to the gate of the first transistor in the second sub-pixel, and the third sub-pixel is connected to the gates of the second transistors in the first sub-pixel and the second sub-pixel. The signal on the first scan line is first at a valid level, and the signal on the second scan line is then at a valid level, and the signals on the first scan line and the second scan line satisfy the relationship |ΔV1|*t1<|ΔV2|*t2, which can increase the sufficiency of data voltage writing for the second sub-pixel, and / or directly increase the data voltage writing time of the second sub-pixel, thereby compensating for the brightness difference caused by the data voltage writing time of the first sub-pixel being longer than the data voltage writing time of the second sub-pixel.

[0056] In some embodiments, the display panel includes a scanning circuit. Figure 6 and Figure 7The scanning circuit includes a first scanning circuit 21, and the first scanning circuit 21 includes a shift register. The shift register includes a first shift register vsr1 and a second shift register vsr2.

[0057] The circuit structures of the first shift register vsr1 and the second shift register vsr2 may be the same. As an example, the circuit structures of the first shift register vsr1 and the second shift register vsr2 may be as follows: Figure 7 shown.

[0058] An output terminal OUT of the first shift register vsr1 is connected to the first scan line S1 and a first end of the first output transistor T81 , and a second end of the first output transistor T81 is connected to the first clock line 31 .

[0059] The output terminal OUT of the second shift register vsr2 is connected to the second scan line S2 and a first terminal of the second output transistor T82 , and the second terminal of the second output transistor T82 is connected to the second clock line 32 .

[0060] Exemplarily, to facilitate the description of the connection relationship between the first shift register vsr1 and the second shift register vsr2 and the clock line, taking the case where both the first shift register vsr1 and the second shift register vsr2 include a first clock terminal CK and a second clock terminal XCK as an example, the second end of the first output transistor T81 is connected to the second clock terminal XCK in the first shift register vsr1, and the second clock terminal XCK in the first shift register vsr1 is connected to the first clock line 31. The second end of the second output transistor T82 is connected to the second clock terminal XCK in the second shift register vsr2, and the second clock terminal XCK in the second shift register vsr2 is connected to the second clock line 32.

[0061] It is understandable that the first shift register vsr1 is used to provide a scan signal to the first transistor in the first sub-pixel, and the second shift register vsr2 is used to provide a scan signal to the first transistor in the second sub-pixel. For example, the first sub-pixel is an odd-row sub-pixel, and the second sub-pixel is an even-row sub-pixel. The first shift register vsr1 is used to drive the odd-row sub-pixels, and the second shift register vsr2 is used to drive the even-row sub-pixels.

[0062] For example, Figure 8 As shown, the difference between the third cutoff level and the third effective level of the first clock signal on the first clock line 31 is ΔV3, and the difference between the fourth cutoff level and the fourth effective level of the second clock signal on the second clock line 32 is ΔV4, |ΔV3|<|ΔV4|.

[0063] The first clock signal on the first clock line 31 is used to control the generation of the first scan signal on the first scan line S1. The difference between the cutoff level and the effective level on the first scan line S1 is equal to the difference between the cutoff level and the effective level on the first clock line 31. In other words, |ΔV1|=|ΔV3|.

[0064] The second clock signal on the second clock line 32 is used to control the generation of the second scan signal on the second scan line S2. The difference between the cutoff level and the effective level on the second scan line S2 is equal to the difference between the cutoff level and the effective level on the second clock line 32. In other words, |ΔV2|=|ΔV4|.

[0065] In this embodiment, the clock signal on the first clock line is used to control the generation of the first scanning signal on the first scanning line, and the clock signal on the second clock line is used to control the generation of the second scanning signal on the second scanning line. By differentially designing the difference between the cutoff level and the effective level on the first clock line and the difference between the cutoff level and the effective level on the second clock line, the difference between the cutoff level and the effective level on the first scanning line and the difference between the cutoff level and the effective level on the second scanning line can be differentiated.

[0066] In some embodiments, the high level on the first clock line 31 is lower than the high level on the second clock line 32 , and / or the low level on the first clock line 31 is higher than the low level on the second clock line 32 .

[0067] Taking the cutoff level as a high level and the effective level as a low level as an example, the third cutoff level on the first clock line 31 is less than the fourth cutoff level on the second clock line 32, and / or the third effective level on the first clock line 31 is greater than the fourth effective level on the second clock line 32.

[0068] For example, initially, the high and low levels of the first clock line and the second clock line are respectively the same.

[0069] As an example, the high level on the first clock line is pulled low, and the high level on the second clock line is pulled high; and / or, the low level on the first clock line is pulled high, and the low level on the second clock line is pulled low, so that the difference between the high level and the low level on the first clock line is greater than the difference between the high level and the low level on the second clock line.

[0070] As another example, the high level on the first clock line is pulled down and the high level on the second clock line is kept unchanged; and / or, the low level on the first clock line is pulled up and the low level on the second clock line is kept unchanged, so that the difference between the high level and the low level on the first clock line is greater than the difference between the high level and the low level on the second clock line.

[0071] As another example, the high level on the first clock line is kept unchanged, and the high level on the second clock line is pulled high; and / or, the low level on the first clock line is kept unchanged, and the low level on the second clock line is pulled low, so that the difference between the high level and the low level on the first clock line is greater than the difference between the high level and the low level on the second clock line.

[0072] In this embodiment, the high-level voltage value transmitted by the first clock line is smaller than the high-level voltage value transmitted by the second clock line, and / or the low-level voltage value transmitted by the first clock line is larger than the low-level voltage value transmitted by the second clock line, so that the difference between the high level and the low level on the first clock line is larger than the difference between the high level and the low level on the second clock line, thereby differentiating the difference between the cutoff level and the effective level on the first scan line and the difference between the cutoff level and the effective level on the second scan line.

[0073] In some embodiments, please refer to Figures 6 to 8 The display panel includes a scanning circuit, the scanning circuit includes a first scanning circuit 21, and the first scanning circuit 21 includes a shift register. The shift register includes a first shift register vsr1 and a second shift register vsr2.

[0074] The output terminal OUT of the first shift register vsr1 is connected to the first scan line S1 and the first end of the first output transistor T81, and the second end of the first output transistor T81 is connected to the first clock line 31. The output terminal OUT of the second shift register vsr2 is connected to the second scan line S2 and the first end of the second output transistor T82, and the second end of the second output transistor T82 is connected to the second clock line 32.

[0075] The duration of the third effective level on the first clock line 31 is t3, and the duration of the fourth effective level on the second clock line 32 is t4, where t3<t4.

[0076] In the drawings of the present application, the effective levels on the first scan line, the second scan line, the first clock line, and the second clock line are illustrated as low levels.

[0077] The first clock signal on the first clock line 31 is used to control the generation of the first scan signal on the first scan line S1, and the third effective level on the first clock line 31 is equal to the first effective level on the first scan line S1. In other words, t1=t3.

[0078] The second clock signal on the second clock line 32 is used to control the generation of the second scan signal on the second scan line S2. The fourth effective level on the second clock line 32 is equal to the second effective level on the second scan line S2. In other words, t2=t4.

[0079] For example, in an initial situation, the initial duration of the third effective level on the first clock line is equal to the initial duration of the fourth effective level on the second clock line.

[0080] As an example, the initial duration of the third effective level on the first clock line may be shortened, and the initial duration of the fourth effective level on the second clock line may be kept unchanged.

[0081] As another example, the initial duration of the third effective level on the first clock line may be kept unchanged, and the initial duration of the fourth effective level on the second clock line may be shortened.

[0082] As yet another example, an initial duration of the third effective level on the first clock line may be shortened, and an initial duration of the fourth effective level on the second clock line may be shortened.

[0083] In this embodiment, the clock signal on the first clock line is used to control the generation of the first scanning signal on the first scanning line, and the clock signal on the second clock line is used to control the generation of the second scanning signal on the second scanning line. By differentially designing the duration of the effective level on the first clock line and the duration of the effective level on the second clock line, the differentiation of the duration of the effective level on the first scanning line and the duration of the effective level on the second scanning line can be achieved.

[0084] Exemplarily, the delay corresponding to the first shift register may be increased, and / or the delay of the second shift register may be reduced, so that t3<t4.

[0085] In some embodiments, Fig. 9 As shown, the switching time between the high level and the low level on the first clock line 31 is t5, and the switching time between the high level and the low level on the second clock line 32 is t6, and t5>t6.

[0086] For example, the initial switching duration between the high level and the low level on the first clock line and the initial switching duration between the high level and the low level on the second clock line.

[0087] As an example, the initial switching time between the high level and the low level on the first clock line may be increased, and the initial switching time between the high level and the low level on the second clock line may be kept unchanged.

[0088] As another example, the initial switching time between the high level and the low level on the first clock line may be kept unchanged, and the initial switching time between the high level and the low level on the second clock line may be reduced.

[0089] As yet another example, the initial switching time between the high level and the low level on the first clock line may be increased, and the initial switching time between the high level and the low level on the second clock line may be decreased.

[0090] The longer the switching time between the high level and the low level on the clock line is, the shorter the time of the effective level on the clock line is. In this embodiment, the switching time between the high level and the low level on the first clock line is designed to be shorter than the switching time between the high level and the low level on the second clock line, so that the time of the effective level on the first clock line is shorter than the time of the effective level on the second clock line, and finally the time of the effective level on the first scan line is shorter than the time of the effective level on the second scan line.

[0091] In addition to adjusting the timing of the first clock line and the second clock line, the delay corresponding to the first shift register may be increased and / or the delay of the second shift register may be reduced by adjusting the physical structure so that t3<t4.

[0092] As an example, the line width of the first clock line 31 is smaller than the line width of the second clock line 32 .

[0093] The smaller the line width of the clock line, the greater the load of the clock line, which makes the signal delay on the clock line greater. In this embodiment, the line width of the first clock line is smaller and the line width of the second clock line is larger, so that the load of the first clock line is greater than the load of the second clock line, so that the duration of the third effective level on the first clock line is shorter than the duration of the fourth effective level on the second clock line.

[0094] Exemplarily, the line widths of the first clock line and the second clock line range from 2 to 20 um, and the line width of the first clock line is smaller than the line width of the second clock line.

[0095] The inventors have found through extensive research that the ratio of the line width of the second clock line to the line width of the first clock line can be designed to be between 1.1 and 1.5, so as to better improve the brightness difference between the first sub-pixel and the second sub-pixel.

[0096] As another example, Fig.10 As shown, the display panel further includes a compensation capacitor C1 , which is connected to the first clock line 31 .

[0097] The compensation capacitor C1 connected to the first clock line 31 constitutes the load of the first clock line 31, and the second clock line 32 does not add a compensation capacitor, so that the load of the first clock line is greater than the load of the second clock line, so that the duration of the third effective level on the first clock line is shorter than the duration of the fourth effective level on the second clock line.

[0098] The inventors have found through extensive research that the capacitance value of the compensation capacitor C1 can be designed to be 10% to 50% of the total capacitance value of the first clock line, so as to achieve a better improvement in the brightness difference between the first sub-pixel and the second sub-pixel. Exemplarily, the total capacitance on the first clock line includes the total capacitance value of the capacitance connected to the first clock line and the coupling capacitance between the first clock line and other signal lines.

[0099] As another example, Fig.11 As shown, the display panel includes a first signal line 41 , and a distance between the first clock line 31 and the first signal line 41 is smaller than a distance between the second clock line 32 and the first signal line 41 .

[0100] Exemplarily, the first signal line 41 includes but is not limited to a high level signal line, a low level signal line, a trigger signal line, and the like.

[0101] A coupling capacitor is formed between the first signal line 41 and the clock line. The larger the distance between the first signal line 41 and the clock line, the smaller the coupling capacitor therebetween. Conversely, the smaller the distance between the first signal line 41 and the clock line, the larger the coupling capacitor therebetween.

[0102] In this embodiment, the spacing between the first clock line and the first signal line is smaller, the spacing between the second clock line and the first signal line is larger, the coupling capacitance between the first clock line and the first signal line is larger, and the coupling capacitance between the second clock line and the first signal line is smaller, which is equivalent to the total capacitance value on the first clock line, reducing the total capacitance value on the first clock line, thereby increasing the load of the first clock line and reducing the load of the second clock line, so that the duration of the third effective level on the first clock line is shorter than the duration of the fourth effective level on the second clock line.

[0103] Through extensive research, the inventors found that the total capacitance value on the first clock line can be increased by 10% to 50% of its initial value, and the total capacitance value on the second clock line can be reduced by 10% to 50% of its initial value, so as to better improve the brightness difference problem between the first sub-pixel and the second sub-pixel.

[0104] The inventors also discovered through research that the spacing between the first clock line 31 and the first signal line 41 can be reduced from 3.5-4.5um to 2-2.5um, and the spacing between the second clock line 32 and the first signal line 41 can be maintained at 3.5-4.5um, so as to better improve the brightness difference between the first sub-pixel and the second sub-pixel.

[0105] In some embodiments, Figure 6 As shown, the first scanning circuit 21 includes a plurality of first shift registers vsr1 and a plurality of second shift registers vsr2, and the first shift registers vsr1 and the second shift registers vsr2 are cascaded.

[0106] A second shift register is cascaded between every two adjacent first shift registers, and a first shift register is cascaded between every two adjacent second shift registers. The signal outputted from the output end of the first shift register is used as a trigger signal for the second shift register of the next stage, and the signal outputted from the output end of the second shift register is used as a trigger signal for the first shift register of the next stage.

[0107] For example, the output terminal OUT of the first shift register vsr1_1 is connected to the input terminal IN of the second shift register vsr2_1, the output terminal OUT of the second shift register vsr2_1 is connected to the input terminal IN of the first shift register vsr1_2, the output terminal OUT of the first shift register vsr1_2 is connected to the input terminal IN of the second shift register vsr2_2, and so on. In addition, the input terminal IN of the first shift register vsr1_1 is connected to the trigger signal line STV.

[0108] The clock terminal CK of the first shift register is also connected to the second clock line 32 , and the clock terminal CK of the second shift register is also connected to the first clock line 31 .

[0109] In this embodiment, two clock lines are used to drive the first shift register and the second shift register. The differentiation of the scan signals on the first scan line and the second scan line can be achieved by only differentiating the signal timings on the two clock lines.

[0110] In other embodiments, Fig.12 As shown, the first scanning circuit 21 includes a plurality of first shift registers vsr1 and a plurality of second shift registers vsr2, and the first shift registers vsr1 and the second shift registers vsr2 are cascaded.

[0111] Fig.12 and Figure 6 The similarities are not repeated here, and the differences include: the clock terminal CK of the first shift register is also connected to the third clock line 33, the clock terminal CK of the second shift register is also connected to the fourth clock line 34, the third clock signal on the third clock line 33 and the first clock signal on the first clock line 31 are inverted signals, and the fourth clock signal on the fourth clock line 34 and the second clock signal on the second clock line 32 are inverted signals.

[0112] Exemplarily, the cutoff level on the third clock line 33 is equal to the cutoff level on the first clock line 31, and the effective level on the third clock line 33 is equal to the effective level on the first clock line 31. The duration of the effective level on the third clock line 33 is equal to the duration of the effective level on the first clock line 31.

[0113] The off level on the fourth clock line 34 and the off level on the second clock line 32, the valid level on the fourth clock line 34 and the valid level on the second clock line 32. The duration of the valid level on the fourth clock line 34 is equal to the duration of the valid level on the second clock line 32.

[0114] In this embodiment, two clock lines are used to drive the first shift register, and another two clock lines are used to drive the second shift register, so as to better ensure the differentiation of the scan signals on the first scan line and the second scan line.

[0115] like Figure 1 and Figure 2 As shown, the time for writing the data voltage to the gate of the driving transistor in the i-th row of sub-pixels is relatively long, resulting in different driving currents for the i-th row of sub-pixels and the i+1-th row of sub-pixels at the same target brightness, which leads to brightness differences between the two rows of sub-pixels. In addition to the differentiated design of the first scanning signal and the second scanning signal in the above example, the data voltages connected to the first sub-pixel and the second sub-pixel can also be differentiated.

[0116] In some embodiments, at the same target brightness, the data voltage connected to the first sub-pixel is not equal to the data voltage connected to the second sub-pixel.

[0117] For example, at the same target brightness, the data voltage connected to the first sub-pixel 11 is recorded as Vdata1, and the data voltage connected to the second sub-pixel 12 is recorded as Vdata2, Vdata1≠Vdata2. The magnitude relationship between Vdata1 and Vdata2 can be designed based on the relationship between the driving current and the data voltage.

[0118] The size of the data voltage will affect the size of the driving current. Therefore, by differentially designing the data voltages connected to the first sub-pixel and the second sub-pixel, the brightness difference caused by the data voltage writing time of the first sub-pixel being longer than the data voltage writing time of the second sub-pixel can be compensated.

[0119] In some embodiments, Figure 4 As shown, the driving transistor T3 is a P-type transistor. Under the same target brightness, the data voltage connected to the first sub-pixel is smaller than the data voltage connected to the second sub-pixel.

[0120] When the driving transistor is a P-type transistor, the driving current and the data voltage meet the relationship 1:

[0121] I=k1*(PVDD-Vdata) 2 (1)

[0122] The power supply voltage PVDD and the data voltage Vdata are both positive voltages, and Vdata is not greater than PVDD. The larger the data voltage Vdata is, the smaller the driving current I is, and the lower the brightness is.

[0123] Since the data voltage is written to the first sub-pixel before the second sub-pixel, after the first scanning signal connected to the first sub-pixel is switched from the effective level to the cut-off level, since the second transistor in the first sub-pixel is still turned on, the gate of the driving transistor in the first sub-pixel will still write the data voltage until the driving transistor in the first sub-pixel becomes cut-off, and the writing of the data voltage is stopped. In other words, when the driving transistor is a P-type transistor, the time for writing the data voltage to the first sub-pixel is longer than the time for writing the data voltage to the second sub-pixel, and the data voltage of the first sub-pixel is written more fully, resulting in a small driving current and low brightness of the first sub-pixel, and a large driving current and bright brightness of the second sub-pixel.

[0124] In the present embodiment, when the driving transistor is a P-type transistor, the data voltage connected to the first sub-pixel is designed to be smaller than the data voltage connected to the second sub-pixel. This can increase the driving current of the first sub-pixel and reduce the driving current of the second sub-pixel to compensate for the problem that the brightness of the first sub-pixel is dark due to the long data voltage writing time and the brightness of the second sub-pixel is bright due to the short data voltage writing time.

[0125] In some embodiments, Fig.13 As shown, the driving transistor T3 is an N-type transistor. Under the same target brightness, the data voltage connected to the first sub-pixel is greater than the data voltage connected to the second sub-pixel.

[0126] When the driving transistor is an N-type transistor, the driving current and the data voltage meet the relationship 2:

[0127] I=k2*(Vref-Vdata) 2 (2)

[0128] The reference voltage Vref is a negative voltage, and the data voltage Vdata is a positive voltage. The larger the data voltage Vdata is, the larger the driving current I is, and the higher the brightness is.

[0129] Since the data voltage is written to the first sub-pixel before the second sub-pixel, after the first scanning signal connected to the first sub-pixel is switched from the effective level to the cut-off level, since the second transistor in the first sub-pixel is still turned on, the gate of the driving transistor in the first sub-pixel will still write the data voltage until the driving transistor in the first sub-pixel becomes cut-off, and the writing of the data voltage is stopped. In other words, when the driving transistor is an N-type transistor, the time for writing the data voltage to the first sub-pixel is longer than the time for writing the data voltage to the second sub-pixel, and the data voltage of the first sub-pixel is written more fully, resulting in a large driving current of the first sub-pixel and a brighter brightness; a small driving current of the second sub-pixel and a darker brightness.

[0130] In the present embodiment, when the driving transistor is an N-type transistor, the data voltage connected to the first sub-pixel is designed to be greater than the data voltage connected to the second sub-pixel. This can reduce the driving current of the first sub-pixel and increase the driving current of the second sub-pixel to compensate for the problem that the brightness of the first sub-pixel is too bright due to the long data voltage writing time and the brightness of the second sub-pixel is too dark due to the short data voltage writing time.

[0131] In addition to the differentiated design of the first scanning signal and the second scanning signal, and the differentiated data voltages connected to the first sub-pixel and the second sub-pixel, the storage capacitors of the first sub-pixel and the second sub-pixel, the parasitic capacitors of the first sub-pixel and the second sub-pixel, the driving transistors of the first sub-pixel and the second sub-pixel, etc. can also be differentiated. The following is an exemplary introduction to these differentiated designs.

[0132] In some embodiments, Figure 4 or Fig.13 As shown, the sub-pixel further includes a storage capacitor Cst, a first plate of the storage capacitor Cst is connected to the gate of the driving transistor T3, and a second plate of the storage capacitor Cst is electrically connected to a fixed potential. Figure 4 As shown, the fixed potential is the power supply voltage PVDD, or, as Fig.13 As shown, the fixed potential is the reference voltage Vref.

[0133] The storage capacitor in the first sub-pixel 11 is recorded as the first storage capacitor Cst1, and the storage capacitor in the second sub-pixel 12 is recorded as the second storage capacitor Cst2. The overlapping area of ​​the two plates of the first storage capacitor Cst1 is not equal to the overlapping area of ​​the two plates of the second storage capacitor Cst2.

[0134] Exemplarily, the two plates of the first storage capacitor Cst1 and the two plates of the second storage capacitor Cst2 are respectively located in the same film layer.

[0135] It is understandable that the capacitance value of the first storage capacitor Cst1 is different from the capacitance value of the second storage capacitor Cst2.

[0136] The capacitance value of the storage capacitor affects the speed at which the data voltage is written into the gate of the driving transistor. The larger the capacitance value of the storage capacitor, the slower the data voltage is written; conversely, the smaller the capacitance value of the storage capacitor, the faster the data voltage is written.

[0137] In this embodiment, by differentially designing the capacitance values ​​of the storage capacitors of the first sub-pixel and the second sub-pixel, the brightness difference caused by the data voltage writing time length of the first sub-pixel being longer than the data voltage writing time length of the second sub-pixel can be compensated.

[0138] As an example, the driving transistor is a P-type transistor, and the overlapping area of ​​the two plates of the first storage capacitor Cst1 is greater than the overlapping area of ​​the two plates of the second storage capacitor Cst2. In this way, the data voltage written to the gate of the driving transistor in the first sub-pixel can be insufficient, and the gate voltage of the driving transistor in the first sub-pixel can be reduced, thereby increasing the brightness of the first sub-pixel to compensate for the problem that the brightness of the first sub-pixel is dark due to the long data voltage writing time, and the brightness of the second sub-pixel is bright due to the short data voltage writing time.

[0139] For example, Fig.14 As shown, the driving transistor T3 is a P-type transistor, the first storage capacitor Cst1 includes a first plate c11 and a second plate c12, the second storage capacitor Cst2 includes a third plate c23 and a fourth plate c24, and the overlapping area of ​​the first plate c11 and the second plate c12 is smaller than the overlapping area of ​​the third plate c23 and the fourth plate c24. The first plate c11 and the third plate c23 are located in the same film layer, and the second plate c12 and the fourth plate c24 are located in the same film layer.

[0140] In the case where the driving transistor is an N-type transistor, the overlapping area of ​​the two plates of the first storage capacitor Cst1 is smaller than the overlapping area of ​​the two plates of the second storage capacitor Cst2. In this way, the data voltage written into the gate of the driving transistor in the second sub-pixel can be insufficient, and the gate voltage of the driving transistor in the second sub-pixel can be reduced, thereby increasing the brightness of the second sub-pixel to compensate for the problem that the brightness of the first sub-pixel is too bright due to the long writing time of the data voltage, and the brightness of the second sub-pixel is too dark due to the short writing time of the data voltage.

[0141] In some embodiments, the channel width-to-length ratio of the driving transistor T3 in the first sub-pixel 11 is not equal to the channel width-to-length ratio of the driving transistor T3 in the second sub-pixel 12 .

[0142] The larger the channel width-to-length ratio of the driving transistor, the larger the driving current.

[0143] In this embodiment, by differentially designing the channel width-to-length ratios of the driving transistors of the first sub-pixel and the second sub-pixel, the brightness difference caused by the data voltage writing time length of the first sub-pixel being longer than the data voltage writing time length of the second sub-pixel can be compensated.

[0144] As an example, Fig.15 As shown, the driving transistor is a P-type transistor, and the channel width-to-length ratio of the driving transistor T3 in the first sub-pixel 11 is greater than the channel width-to-length ratio of the driving transistor T3 in the second sub-pixel 12. In this way, the data voltage written into the gate of the driving transistor in the first sub-pixel can be insufficient, and the gate voltage of the driving transistor in the first sub-pixel can be reduced, thereby increasing the brightness of the first sub-pixel to compensate for the problem that the brightness of the first sub-pixel is dark due to the long data voltage writing time, and the brightness of the second sub-pixel is bright due to the short data voltage writing time.

[0145] When the driving transistor is an N-type transistor, the channel width-to-length ratio of the driving transistor T3 in the first sub-pixel 11 is smaller than the channel width-to-length ratio of the driving transistor T3 in the second sub-pixel 12. In this way, the brightness of the second sub-pixel can be improved to compensate for the problem that the brightness of the first sub-pixel is too bright due to the long data voltage writing time, and the brightness of the second sub-pixel is too dark due to the short data voltage writing time.

[0146] In some embodiments, Fig.16 As shown, the display panel includes a connection line 50, the connection line 50 is connected to the gate of the driving transistor T3, and in the thickness direction of the display panel, the connection line 50 at least partially overlaps with the third scanning line S3. One end of the connection line 50 is connected to the gate of the driving transistor T3 through a via hole, and the other end of the connection line 50 is connected to the first electrode of the second transistor T2 through a via hole.

[0147] Exemplarily, the gate g3 of the driving transistor T3 is located on the first metal layer M1 , and the connecting line 50 is located on the second metal layer M2 .

[0148] The connection line 50 connected to the first sub-pixel 11 is marked as a first connection line 51, and the connection line 50 connected to the second sub-pixel 12 is marked as a second connection line 52. The overlapping area of ​​the first connection line 51 and the third scan line S3 is not equal to the overlapping area of ​​the second connection line 52 and the third scan line S3.

[0149] The connecting line 50 overlaps with the third scanning line S3, and the overlapping portion of the two constitutes a parasitic capacitor, which is connected to the gate of the driving transistor T3. The parasitic capacitors connected to the gates of the driving transistors of the first sub-pixel and the second sub-pixel are different. When the signal on the third scanning line S3 jumps, the gate potential of the driving transistor T3 jumps due to the coupling effect of the parasitic capacitor.

[0150] In this embodiment, by designing the parasitic capacitors connected to the gates of the driving transistors of the first sub-pixel and the second sub-pixel to be different, the brightness difference caused by the data voltage writing time length of the first sub-pixel being longer than the data voltage writing time length of the second sub-pixel can be compensated.

[0151] As an example, the driving transistor is a P-type transistor, the effective level at the upper end of the third scan line S3 is a low level, and the overlapping area between the first connection line 51 connected to the first sub-pixel 11 and the third scan line S3 is smaller than the overlapping area between the second connection line 52 connected to the second sub-pixel 12 and the third scan line S3.

[0152] When the third scan line S3 switches from a low level to a high level, the gate potential of the driving transistor is pulled up. Since the overlapping area between the first connection line 51 connected to the first sub-pixel 11 and the third scan line S3 is small, the gate potential of the driving transistor in the first sub-pixel 11 is pulled up to a small extent, thereby increasing the brightness of the first sub-pixel to compensate for the problem that the brightness of the first sub-pixel is dark due to the long data voltage writing time, and the brightness of the second sub-pixel is bright due to the short data voltage writing time.

[0153] As another example, the driving transistor is an N-type transistor, the effective level at the upper end of the third scan line S3 is a low level, and the overlapping area between the first connection line connected to the first sub-pixel 11 and the third scan line S3 is greater than the overlapping area between the second connection line connected to the second sub-pixel 12 and the third scan line S3.

[0154] When the third scan line S3 switches from a low level to a high level, the gate potential of the driving transistor is pulled up. Since the overlapping area of ​​the first connection line connected to the first sub-pixel 11 and the third scan line S3 is relatively large, the gate potential of the driving transistor in the first sub-pixel 11 is pulled up to a large extent, thereby reducing the brightness of the first sub-pixel to compensate for the problem that the brightness of the first sub-pixel is bright due to the long data voltage writing time, and the brightness of the second sub-pixel is dark due to the short data voltage writing time.

[0155] It should be noted that the above examples take the overlap between the third scan line and the connection line as an example. In other examples, other signal lines may overlap with the connection line. For example, the overlapping area between the first connection line and the second signal line is not equal to the overlapping area between the second connection line and the second signal line. The second signal line is a signal line other than the third scan line.

[0156] In some embodiments, Fig.16 As shown, the line width of the first connection line 51 connected to the first sub-pixel 11 is not equal to the line width of the second connection line 52 connected to the second sub-pixel 12 .

[0157] Exemplarily, the first connection line 51 and the second connection line 52 extend along the second direction Y, the line width of the first connection line 51 is its width in the first direction X, and the line width of the second connection line 52 is its width in the first direction X.

[0158] In this embodiment, the line width of the first connection line is not equal to the line width of the second connection line, so that the overlapping area of ​​the first connection line and the third scan line is different from the overlapping area of ​​the second connection line and the third scan line.

[0159] As an example, Fig.16 As shown, the driving transistor is a P-type transistor, the effective level at the upper end of the third scan line S3 is a low level, and the line width of the first connection line 51 connected to the first sub-pixel 11 is smaller than the line width of the second connection line 52 connected to the second sub-pixel 12.

[0160] As another example, the driving transistor is an N-type transistor, the effective level at the upper end of the third scan line S3 is a low level, and the line width of the first connection line 51 connected to the first sub-pixel 11 is greater than the line width of the second connection line 52 connected to the second sub-pixel 12.

[0161] It should be noted that Figures 14 to 16 In the layout shown, the transistors in the sub-pixels are illustrated as P-type transistors. The display panel includes a semiconductor layer Poly and a first metal layer M1, a capacitor metal layer MC, and a second metal layer M2 that are sequentially away from the semiconductor layer Poly, an insulating layer is included between different metal layers, and an insulating layer is included between the first metal layer M1 and the semiconductor layer Poly. Figures 14 to 16 In the figure, graphics with the same fill pattern represent structures located in the same film layer, and graphics with different fill patterns represent structures located in different film layers.

[0162] For example, please refer to Figure 4 and Fig.17 The display panel further includes a second scanning circuit 22, the second scanning circuit 22 includes a plurality of cascaded third shift registers vsr3, and the third shift register vsr3 is connected to the third scanning line S3 to which the first sub-pixel 11 and the second sub-pixel 12 are connected.

[0163] The display panel further includes a third scanning circuit 23 . The third scanning circuit 23 includes a plurality of cascaded fourth shift registers vsr4 . The fourth shift register vsr4 is connected to a fourth scanning line S4 to which the first sub-pixel 11 and the second sub-pixel 12 are connected.

[0164] The display panel further includes a fourth scanning circuit 24 . The fourth scanning circuit 24 includes a plurality of cascaded fifth shift registers vsr5 . The fifth shift register vsr5 is connected to the light emission control line Emit connected to the first sub-pixel 11 and the second sub-pixel 12 .

[0165] It should also be noted that the transistors in the embodiments of the present application can be N-type transistors or P-type transistors. In specific implementations, the gates of the above-mentioned transistors serve as their control electrodes, and, according to the signals of the gates of the transistors and their types, the first electrode can be used as the source electrode and the second electrode can be used as the drain electrode, or the first electrode can be used as the drain electrode and the second electrode can be used as the source electrode, without making any distinction here. In addition, the on-level and off-level in the embodiments of the present application are both general terms, the on-level refers to any level that can turn on the transistor, and the off-level refers to any level that can turn off / off the transistor.

[0166] The present application also provides a display device, including the display panel provided by the present application. Fig.18 , Fig.18 It is a structural schematic diagram of a display device provided in an embodiment of the present application. Fig.18 The provided display device 1000 includes the display panel 100 provided by any of the above embodiments of the present application. Fig.18 The embodiment only takes a mobile phone as an example to illustrate the display device 1000. It can be understood that the display device provided in the embodiment of the present application can be a wearable product, a computer, a television, a car display device, or other display devices with display functions, and the present application does not make specific restrictions on this. The display device provided in the embodiment of the present application has the beneficial effects of the display panel provided in the embodiment of the present application. For details, please refer to the specific description of the display panel in the above embodiments, and this embodiment will not be repeated here.

[0167] According to the embodiments described above in the present application, these embodiments do not describe all the details in detail, nor do they limit the present application to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and the modifications based on the present application. The present application is limited only by the claims and their full scope and equivalents.

Claims

1. A display panel, characterized in that: include: A sub-pixel, wherein the sub-pixel includes a driving transistor, a first transistor and a second transistor, wherein the first transistor is connected between a data line and a first electrode of the driving transistor, and the second transistor is connected between a second electrode of the driving transistor and a gate of the driving transistor; The sub-pixel includes a first sub-pixel and a second sub-pixel, a gate of the first transistor in the first sub-pixel is connected to a first scan line, a gate of the first transistor in the second sub-pixel is connected to a second scan line, and gates of the second transistors in the first sub-pixel and the second sub-pixel are both connected to a third scan line; In one picture refresh cycle, the first scan signal on the first scan line includes a first effective level, the second scan signal on the second scan line includes a second effective level, the third scan signal on the third scan line includes a third effective level, the period of the third effective level covers the period of the first effective level and the period of the second effective level, and the start time of the second effective level is not earlier than the end time of the first effective level; The difference between the first cutoff level and the first effective level of the first scanning signal is ΔV1, the difference between the second cutoff level and the second effective level of the second scanning signal is ΔV2, the duration of the first effective level is t1, and the duration of the second effective level is t2; |ΔV1|*t1<|ΔV2|*t2.

2. The display panel according to claim 1, characterized in that: The display panel includes a scanning circuit, the scanning circuit includes a first shift register and a second shift register, the output end of the first shift register is connected to the first scanning line and the first end of the first output transistor, the second end of the first output transistor is connected to the first clock line, the output end of the second shift register is connected to the second scanning line and the first end of the second output transistor, and the second end of the second output transistor is connected to the second clock line; A difference between a third cutoff high level and a third effective level of the first clock signal on the first clock line is ΔV3, a difference between a fourth cutoff level and a fourth effective level of the second clock signal on the second clock line is ΔV4, |ΔV3|<|ΔV4|.

3. The display panel according to claim 2, characterized in that: The high level on the first clock line is lower than the high level on the second clock line, and / or the low level on the first clock line is higher than the low level on the second clock line.

4. The display panel according to claim 1, characterized in that: The scanning circuit of the display panel comprises a first shift register and a second shift register, wherein the output end of the first shift register is connected to the first scanning line and the first end of the first output transistor, the second end of the first output transistor is connected to the first clock line, the output end of the second shift register is connected to the second scanning line and the first end of the second output transistor, and the second end of the second output transistor is connected to the second clock line; The duration of the third effective level on the first clock line is t3, and the duration of the fourth effective level on the second clock line is t4, t3<t4.

5. The display panel according to claim 4, characterized in that: The switching time between the high level and the low level on the first clock line is t5, and the switching time between the high level and the low level on the second clock line is t6, t5>t6.

6. The display panel according to claim 4, characterized in that: The line width of the first clock line is smaller than the line width of the second clock line.

7. The display panel according to claim 4, characterized in that: The display panel further includes a compensation capacitor connected to the first clock line.

8. The display panel according to claim 4, characterized in that: The display panel includes a first signal line, and a distance between the first clock line and the first signal line is smaller than a distance between the second clock line and the first signal line.

9. The display panel according to any one of claims 2 to 8, characterized in that: The scanning circuit includes a plurality of the first shift registers and a plurality of the second shift registers, and the first shift registers and the second shift registers are cascaded; The first shift register is further connected to the second clock line, and the second shift register is further connected to the first clock line.

10. The display panel according to any one of claims 2 to 8, characterized in that: The scanning circuit includes a plurality of the first shift registers and a plurality of the second shift registers, and the first shift registers and the second shift registers are cascaded; The first shift register is also connected to a third clock line, the second shift register is also connected to a fourth clock line, the third clock signal on the third clock line is an inverted signal of the first clock signal on the first clock line, and the fourth clock signal on the fourth clock line is an inverted signal of the second clock signal on the second clock line.

11. The display panel according to claim 1, characterized in that: At the same target brightness, the data voltage connected to the first sub-pixel is not equal to the data voltage connected to the second sub-pixel.

12. The display panel according to claim 11, characterized in that: The driving transistor is a P-type transistor. Under the same target brightness, the data voltage connected to the first sub-pixel is smaller than the data voltage connected to the second sub-pixel.

13. The display panel according to claim 11, characterized in that: The driving transistor is an N-type transistor. Under the same target brightness, the data voltage connected to the first sub-pixel is greater than the data voltage connected to the second sub-pixel.

14. The display panel according to claim 1, characterized in that: The sub-pixel further comprises a storage capacitor, a first plate of the storage capacitor is connected to the gate of the driving transistor, and a second plate of the storage capacitor is electrically connected to a fixed potential; An overlapping area of ​​two plates of the storage capacitor in the first sub-pixel is not equal to an overlapping area of ​​two plates of the storage capacitor in the second sub-pixel.

15. The display panel according to claim 1, characterized in that: The display panel comprises a connection line, the connection line is connected to the gate of the driving transistor, and in the thickness direction of the display panel, the connection line at least partially overlaps with the third scanning line; An overlapping area between the connection line connected to the first sub-pixel and the third scan line is not equal to an overlapping area between the connection line connected to the second sub-pixel and the third scan line.

16. The display panel according to claim 15, characterized in that: A line width of the connection line connected to the first sub-pixel is not equal to a line width of the connection line connected to the second sub-pixel.

17. The display panel according to claim 1, characterized in that: The channel width-to-length ratio of the driving transistor in the first sub-pixel is not equal to the channel width-to-length ratio of the driving transistor in the second sub-pixel.

18. The display panel according to claim 1, characterized in that: The first scan line, the second scan line, and the third scan line extend along a first direction, the first sub-pixel and the second sub-pixel are adjacent to each other in a second direction, and the first direction and the second direction intersect.

19. A display device, characterized in that: Comprising the display panel according to any one of claims 1 to 18.

Images