Bit allocation method, device and equipment for LED double-latch chip and medium

Abstract

The embodiment of the invention discloses a bit allocation method, device and equipment for an LED double-latch chip and a medium, and belongs to the technical field of LED display. The method comprises the following steps: determining a sub-frame scattering segment number according to a control parameter of a target double-latch chip; wherein the control parameters comprise frame frequency, clock frequency, data width, scanning number, synchronous reserved time and reserved width; determining a plurality of target gray level bits according to the gray level of the target double-latch chip, and determining the corresponding number of subframes associated with each target gray level bit based on the refresh rate of the target double-latch chip and the number of sub-frame scattering segments; and performing bit allocation on the target double-latch chip according to the corresponding number of the subframes, the refresh rate and the number of the scattered segments of the subframes. According to the technical scheme, the photographing and display effects of the double-latch chip can be effectively improved in a multi-bit scattering mode, and the problems that the photographing effect of the double-latch chip is poor and the display effect is not uniform are solved, so that the requirement of a user for the display effect is better met.

Description

Technical Field

[0001] The present invention relates to the field of LED display technology, and in particular to a bit allocation method, device, equipment and medium for an LED double latch chip. Background Art

[0002] LED (Light Emitting Diode) display technology plays a vital role in modern information dissemination and visual display with its high brightness, high definition, energy saving and environmental protection, and flexible display methods. As a column driver chip, the dual latch chip ensures the picture quality by providing stable current control and precise brightness adjustment, and promotes the further development of LED display technology.

[0003] For dual latch chips, the traditional display solution is to coordinate high-order data and low-order data. After the high-order data transmission is completed, the LE (data latch) signal is generated to latch the high-order data, and then the OE (display data enable) signal is turned on to start displaying the high-order data. While displaying the high-order data, the low-order data is transmitted. After the low-order data transmission is completed, the low-order data is latched and the low-order data is displayed. That is, the excess time for displaying the high-order data is used to transmit the low-order data.

[0004] However, the use of a dual latch method that combines high-order data with low-order data in pairs will result in a large difference between the high-order data and the low-order data. Due to the low refresh rate, obvious horizontal stripes are seen when taking pictures with a mobile phone or camera with a high frame rate, resulting in poor photography and uneven display effects, which cannot meet user needs for display effects. Summary of the invention

[0005] The present invention provides a bit allocation method, device, equipment and medium for an LED dual-latch chip, which can effectively improve the photographing and display effects of the dual-latch chip by using a multi-bit scattering method, solve the problems of poor photographing effect and uneven display effect of the dual-latch chip, so as to better meet the user's demand for display effect.

[0006] According to one aspect of the present invention, a bit allocation method for an LED dual latch chip is provided, the method comprising:

[0007] Determine the number of subframe fragmentation segments according to the control parameters of the target dual latch chip; wherein the control parameters include frame rate, clock frequency, data width, scan number, synchronization reserved time and reserved width;

[0008] Determine a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determine the corresponding number of subframes associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments;

[0009] The target dual latch chip is bit-allocated according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments.

[0010] According to another aspect of the present invention, a bit allocation device for an LED dual latch chip is provided, the device comprising:

[0011] A subframe scattering segment number determination module is used to determine the subframe scattering segment number according to the control parameters of the target dual latch chip; wherein the control parameters include frame frequency, clock frequency, data width, scan number, synchronization reserved time and reserved width;

[0012] A subframe corresponding number determination module, used to determine a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determine the corresponding number of subframes associated with each of the target grayscale bits based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments;

[0013] The chip bit allocation module is used to allocate bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments.

[0014] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0015] at least one processor; and,

[0016] a memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the bit allocation method of the LED dual latch chip described in any embodiment of the present invention.

[0018] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, wherein the computer instructions are used to enable a processor to implement the bit allocation method of the LED dual latch chip described in any embodiment of the present invention when executed.

[0019] The technical solution of the embodiment of the present invention determines the number of subframe scattering segments according to the control parameters of the target dual latch chip; wherein the control parameters include frame rate, clock frequency, data width, number of scans, synchronization reserved time and reserved width; multiple target grayscale bits are determined according to the grayscale level of the target dual latch chip, and the corresponding number of subframes associated with each target grayscale bit is determined based on the refresh rate of the target dual latch chip and the number of subframe scattering segments; bits are allocated to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe scattering segments. This technical solution can use a multi-bit scattering method to reduce the display time difference of different bit data, thereby effectively improving the photography and display effects of the dual latch chip, and solving the problems of poor photography effect and uneven display effect of the dual latch chip, so as to better meet the user's demand for display effect.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flow chart of a bit allocation method of an LED dual latch chip provided in accordance with the first embodiment of the present invention;

[0023] Figure 2 is a flow chart of a bit allocation method of an LED dual latch chip provided in accordance with the second embodiment of the present invention;

[0024] Figure 3 It is a structural schematic diagram of a bit allocation device of an LED dual latch chip provided according to the third embodiment of the present invention;

[0025] Figure 4 It is a structural schematic diagram of an electronic device for implementing a bit allocation method of an LED dual latch chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] Embodiment 1

[0029] Figure 1 This is a flowchart of a bit allocation method for a LED dual latch chip provided in the first embodiment of the present invention. This embodiment can be applied to the case where the photo taking and display effects of the dual latch chip are improved by multi-bit scattering. The method can be executed by a bit allocation device for the LED dual latch chip. The bit allocation device for the LED dual latch chip can be implemented in the form of hardware and / or software. The bit allocation device for the LED dual latch chip can be configured in an electronic device with data processing capabilities. Figure 1 As shown, the method includes:

[0030] S110, determining the number of subframe fragmentation segments according to the control parameters of the target dual latch chip.

[0031] Among them, the control parameters include frame rate, clock frequency, data width, number of scans, synchronization reserve time and reserved width. Specifically, the clock frequency refers to the clock frequency of the serial input clock, that is, the clock frequency corresponding to data transmission; the data width refers to the width of the module (display panel); the number of scans refers to the maximum number of rows carried by a set of data, which is generally related to the number of row chips; the synchronization reserve time refers to the rest time between frames, which can be understood as the fault tolerance time corresponding to the clock frequency; the reserved width can be understood as the fault tolerance width corresponding to the data width. The number of subframe fragmentation segments can be understood as the maximum number of segments that each subframe can be fragmented. Among them, the number of subframes (that is, the refresh rate) can be used to describe how many small subframes can be divided into a frame. For example, when the refresh rate is 16, that is, the number of subframes is 16, indicating that a frame can be divided into 16 small subframes.

[0032] It should be noted that each control parameter can be set according to actual needs, and this embodiment does not specifically limit this. For example, the control parameters can be set as follows: the frame rate is 60 Hz, the clock frequency is 12.5 MHz, the data width is 64, the number of scans is 32, the synchronization reservation time is 26667 ns, and the reserved width is 4. In addition, the higher the clock frequency, the larger the data volume, and the more segments each subframe can be broken up into.

[0033] In this embodiment, the control parameters of the target dual latch chip are first obtained, and then the number of subframe scattering segments is determined according to the control parameters of the target dual latch chip. Optionally, the number of subframe scattering segments is determined according to the control parameters of the target dual latch chip, including: determining a first parameter according to the difference between the reciprocal of the frame frequency and the synchronization reserved time; determining a second parameter according to the sum of the data width and the reserved width; determining a third parameter according to the reciprocal of the clock frequency, the scan number and the product of the second parameter; determining the number of subframe scattering segments according to the ratio of the first parameter to the third parameter.

[0034] The reciprocal of the frame rate is the display time of one frame, for example, when the frame rate is 60 Hz, the display time of one frame is 1 / 60 Hz = 16.6 ms. The reciprocal of the clock frequency is the clock cycle time, for example, when the clock frequency is 12.5 MHz, the clock cycle time is 1 / 12.5 MHz = 80 ns.

[0035] Exemplarily, the number of subframe fragmentation segments may be determined by the following formula:

[0036] ;

[0037] in, Indicates the number of subframe fragments. Indicates the inverse of the frame rate (i.e., one frame display time). Indicates the synchronization reserved time. Indicates the number of scans, Represents the inverse of the clock frequency (i.e., clock cycle time), Indicates the data width, Indicates the reserved width. Express Round down, Represents the first parameter, Represents the second parameter, Represents the third parameter.

[0038] Through such a setting, this solution can quickly determine the maximum number of segments that each subframe can be broken up into (ie, the number of subframe broken up segments).

[0039] S120, determining a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determining the corresponding number of subframes associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments.

[0040] In this embodiment, it is necessary to obtain the grayscale level of the target dual latch chip, and determine multiple target grayscale bits based on the grayscale level. Exemplarily, assuming that the grayscale level is 12 bits, it can be determined that each target grayscale bit is bit0, bit1, ..., bit10, bit11. After determining multiple target grayscale bits, the corresponding number of subframes associated with each target grayscale bit can be further determined based on the refresh rate of the target dual latch chip and the number of subframe scattering segments. Among them, the corresponding number of subframes can be used to describe how many subframes its associated target grayscale bit occupies in a frame of picture data. Exemplarily, assuming that the corresponding number of subframes associated with bit11 is 32, it means that bit11 occupies 32 subframes in a frame of picture data.

[0041] In this embodiment, optionally, the corresponding number of subframes associated with each target grayscale bit is determined based on the refresh rate of the target dual latch chip and the number of subframe scattered segments, including: determining the total number of segments corresponding to the refresh rate according to the product of the refresh rate and the number of subframe scattered segments; determining the corresponding number of subframes associated with each target grayscale bit based on preset restrictions; wherein the preset restrictions include that the corresponding number of subframes associated with the subsequent target grayscale bit in adjacent target grayscale bits is greater than or equal to the corresponding number of subframes associated with the previous target grayscale bit, The OE multiple corresponding to the subsequent target grayscale bit among adjacent target grayscale bits is greater than or equal to the OE multiple corresponding to the previous target grayscale bit, the sum of the corresponding numbers of subframes associated with each target grayscale bit is less than or equal to the total number of segments corresponding to the refresh rate, and the total OE width corresponding to the subsequent target grayscale bit among adjacent target grayscale bits is equal to twice the total OE width corresponding to the previous target grayscale bit. The total OE width is determined based on the product of the OE multiple, the corresponding number of subframes and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

[0042] Among them, the preset restriction condition may refer to the restriction condition for solving the corresponding number of subframes associated with the target grayscale bit, which is preset according to the actual situation. The previous target grayscale bit and the subsequent target grayscale bit may refer to the smaller target grayscale bit and the larger target grayscale bit in the adjacent target grayscale bits, respectively. Exemplarily, for the pair of adjacent target grayscale bits bit10 and bit11, since bit10<bit11, bit10 can be determined as the previous target grayscale bit, and bit11 can be determined as the subsequent target grayscale bit. OE is a display data enable signal, the minimum OE width may refer to the OE width corresponding to the unit light-emitting time, the OE multiple refers to the multiple of the minimum OE width, and the total OE width can be expressed as the product of the OE multiple, the corresponding number of subframes and the minimum OE width.

[0043] Specifically, when determining the corresponding number of subframes associated with each target grayscale bit, first multiply the refresh rate by the number of subframe fragmentation segments, and use the product as the total number of segments corresponding to the refresh rate. For example, assuming that the refresh rate is 16 and the number of subframe fragmentation segments is 6, it can be determined that the total number of segments corresponding to the refresh rate is 16×6=96.

[0044] After determining the total number of segments corresponding to the refresh rate, the corresponding number of subframes associated with each target grayscale bit can be determined based on the following four preset constraints: 1. The corresponding number of subframes associated with the subsequent target grayscale bit in the adjacent target grayscale bits is greater than or equal to the corresponding number of subframes associated with the previous target grayscale bit (for example, the corresponding number of subframes associated with bit11 ≥ the corresponding number of subframes associated with bit10); 2. The OE multiple corresponding to the subsequent target grayscale bit in the adjacent target grayscale bits is greater than or equal to the OE multiple corresponding to the previous target grayscale bit (for example, the OE multiple corresponding to bit11 ≥ the OE multiple corresponding to bit10); 3. The sum of the corresponding numbers of subframes associated with each target grayscale bit is less than or equal to the total number of segments corresponding to the refresh rate (for example, the target grayscale bit is bit0...bit11, and the total number of segments corresponding to the refresh rate is 96, then the sum of the corresponding numbers of subframes associated with bit0...bit11 is ≤96), thereby ensuring that the data corresponding to each target grayscale bit can be displayed in one frame; 4. The total OE width corresponding to the subsequent target grayscale bit in adjacent target grayscale bits is equal to twice the total OE width corresponding to the previous target grayscale bit (for example, the total OE width corresponding to bit11 = the total OE width corresponding to bit10 × 2).

[0045] For example, assuming that the grayscale level is 12 bits, the refresh rate is 16, and the number of subframe segments is 6, the corresponding number of subframes associated with each target grayscale bit (ie, bit0...bit11) is shown in Table 1:

[0046] Table 1 Correlation between target grayscale bits and corresponding number of subframes

[0047]

[0048] It should be noted that the data in Table 1 above are only used as an example and do not serve any limiting purpose. If multiple sets of association relationships between target grayscale bits and corresponding numbers of subframes are determined based on the above four preset constraints, a set of association relationships can be selected as the final association relationship in a random manner or other pre-set manner, and the corresponding number of subframes associated with each target grayscale bit can be determined based on the final association relationship.

[0049] In addition, in the fourth preset restriction condition mentioned above, only the two-fold relationship of the total OE width of adjacent target grayscale bits is used, and the total OE width = OE multiple × corresponding number of subframes × minimum OE width, where the OE multiple and the corresponding number of subframes may change with different target grayscale bits, but the minimum OE width corresponding to different target grayscale bits will always remain unchanged (equal to 1 when compared), and the minimum OE width needs to be calculated separately. At this time, in order to reduce the calculation complexity, there is no need to calculate the specific value of the minimum OE width, that is, there is no need to calculate the specific value of the total OE width of each target grayscale bit, only the product of the OE multiple of the adjacent target grayscale bits and the corresponding number of subframes needs to satisfy the two-fold relationship. Exemplarily, taking the above Table 1 as an example, the total OE width corresponding to bit11 = 64 × 32 × Toe, and the total OE width corresponding to bit10 = 64 × 16 × Toe, where Toe represents the minimum OE width. At this time, the ratio of the total OE width corresponding to bit11 and bit10 is 64×32×Toe / (64×16×Toe)=2, that is, the total OE width corresponding to bit11 is equal to twice the total OE width corresponding to bit10.

[0050] S130, performing bit allocation on the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments.

[0051] In this embodiment, after determining the corresponding number of subframes associated with each target grayscale bit, the target dual latch chip can be allocated bits according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments. Specifically, first determine the proportion of each target grayscale bit corresponding data in the total number of subframes according to the corresponding number of subframes associated with each target grayscale bit and the refresh rate, and then allocate bits to the target dual latch chip according to the proportion and the preset arrangement rule, so as to determine the grayscale bit data of each segment corresponding to the number of subframe fragmentation segments in each subframe. Among them, the preset arrangement rule can be used to describe the way in which the grayscale bit data of each segment corresponding to the number of subframe fragmentation segments in each subframe is arranged. Exemplarily, the preset arrangement rule can be set to alternately arrange high grayscale bit data and low grayscale bit data, and satisfy the minimum sum of the gaps between the grayscale bit data of each segment.

[0052] Exemplarily, taking the data in Table 1 above as an example, the corresponding number of subframes associated with bit11 is 32, which indicates that bit11 occupies 32 subframes in one frame of picture data. Since the refresh rate is 16 (that is, the number of subframes is 16), the corresponding number of subframes associated with bit11 is twice the refresh rate. At this time, two bits of data of bit11 need to be allocated in each subframe. The corresponding number of subframes associated with bit9 and bit10 is 16, which indicates that bit9 and bit10 both occupy 16 subframes in one frame of picture data, that is, the corresponding number of subframes associated with bit9 and bit10 is equal to the refresh rate. At this time, one bit9 and one bit10 data need to be allocated in each subframe. The corresponding number of subframes associated with bit7 and bit8 is 8, which indicates that bit7 and bit8 both occupy 8 subframes in one frame of picture data, that is, the corresponding number of subframes associated with bit7 and bit8 is half of the refresh rate. At this time, one bit7 and one bit8 data need to be allocated in every two subframes. In this case, the arrangement can be made in an odd-even frame manner. The corresponding number of subframes associated with bit6 is 4, which means that bit6 occupies 4 subframes in one frame of picture data, that is, the corresponding number of subframes associated with bit 6 is 1 / 4 of the refresh rate. At this time, one bit6 data needs to be allocated in every four subframes, and the arrangement of bit5-bit0 is similar.

[0053] For example, taking the grayscale level as 12 bits, the refresh rate as 16, and the number of subframe segments as 6, the grayscale bit data corresponding to each subframe can be determined in the following manner:

[0054]

[0055] Among them, the low bit represents one of bit0-bit6, bit7 / bit8 represents one of the two and is arranged in an odd-even frame. It can be understood that in the 16 subframes, the grayscale bit data corresponding to each subframe may be the same or different, which needs to be determined according to the actual situation.

[0056] The technical solution of the embodiment of the present invention determines the number of sub-frame scattering segments according to the control parameters of the target dual-latch chip; wherein the control parameters include frame rate, clock frequency, data width, number of scans, synchronization reserved time and reserved width; multiple target grayscale bits are determined according to the grayscale level of the target dual-latch chip, and the corresponding number of sub-frames associated with each target grayscale bit is determined based on the refresh rate of the target dual-latch chip and the number of sub-frame scattering segments; bits are allocated to the target dual-latch chip according to the corresponding number of sub-frames, the refresh rate and the number of sub-frame scattering segments. This technical solution can optimize the traditional two-segment grayscale bit combination into a multi-segment grayscale bit combination by using a multi-bit scattering method, thereby reducing the display time difference of different bit data, thereby effectively improving the photography and display effects of the dual-latch chip, and solving the problems of poor photography effect and uneven display effect of the dual-latch chip, so as to better meet the user's demand for display effect.

[0057] In this embodiment, optionally, the method for determining the minimum OE width includes: determining a first parameter based on the difference between the inverse of the frame frequency and the synchronization reserved time; determining a maximum OE multiple corresponding to the number of subframe fragmentation segments based on the bit allocation result; determining a fourth parameter based on the product of the scan number, the refresh rate and the maximum OE multiple; and determining the minimum OE width based on the ratio of the first parameter to the fourth parameter.

[0058] Specifically, when calculating the minimum OE width, first calculate the inverse of the frame rate (i.e., one frame display time), then subtract the inverse of the frame rate from the synchronization reservation time, and use the difference as the first parameter. Then, determine the maximum grayscale bit combination corresponding to the number of subframe fragmentation segments according to the bit allocation result, and add the OE multiples corresponding to the maximum grayscale bit combination and multiply by 2 to obtain the maximum OE multiple. Exemplarily, taking the grayscale level of 12bit and the number of subframe fragmentation segments of 6 as an example, the maximum grayscale bit combination can be determined to be bit11, bit6, bit11, bit8, bit10 and bit9. Combined with the data in Table 1 above, the maximum OE multiple can be calculated to be Toe_max=(64+16+64+32+64+32)×2=544. Then, multiply the scan number, refresh rate and maximum OE multiple to obtain the fourth parameter, and finally determine the ratio of the first parameter to the fourth parameter as the minimum OE width.

[0059] Through such a setting, the present scheme can quickly determine the minimum OE width of the target dual latch chip, so as to subsequently control the width of OE opening and closing based on the minimum OE width and the OE multiples and invalid OE multiples corresponding to each target grayscale bit, thereby controlling the display of each target grayscale bit data according to the width of OE opening and closing.

[0060] Embodiment 2

[0061] Figure 2 This is a flowchart of a bit allocation method for an LED dual latch chip provided in the second embodiment of the present invention. This embodiment is optimized based on the above embodiment. The specific optimization is: after allocating bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments, it also includes: using a preset conversion method to convert the data format of the bit allocation result to obtain scan table data; sending the scan table data to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

[0062] like Figure 2 As shown, the method of this embodiment specifically includes the following steps:

[0063] S210, determining the number of subframe fragmentation segments according to the control parameters of the target dual latch chip.

[0064] The control parameters include frame rate, clock frequency, data width, scan number, synchronization reserved time and reserved width.

[0065] S220, determining a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determining the corresponding number of subframes associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments.

[0066] S230, performing bit allocation on the target dual latch chip according to the corresponding number of subframes, the refresh rate, and the number of subframe fragmentation segments.

[0067] Among them, the specific implementation method of S210-S230 can refer to the relevant description of the above-mentioned embodiment 1, and will not be repeated here.

[0068] S240, converting the data format of the bit allocation result by using a preset conversion method to obtain scan table data.

[0069] The preset conversion method may refer to a data format conversion method preset according to actual needs, which may be specifically set based on the data receiving characteristics of the receiving card. For example, binary data that can be processed by a host computer (such as a PC) may be converted into hexadecimal data. For example, the converted scan table data is as follows:

[0070]

[0071] Among them, in the hexadecimal data, bits 15-12 represent the grayscale bit (such as bit11 corresponds to B in hexadecimal), bits 11-8 represent invalid OE multiples, bit 2 is the subframe end flag, and bit 0 is the frame end flag. Among them, the invalid OE multiple can be expressed as the difference between the maximum grayscale bit and the current grayscale bit. For example, taking the 12-bit grayscale level as an example, the maximum grayscale bit is bit11. If the current grayscale bit is bit6, it can be determined that the invalid OE multiple corresponding to bit6 is 11-6=5.

[0072] It should be noted that if the binary data obtained by direct host computer processing is transmitted, the data transmission speed may be slow due to the large amount of data transmission, and transmission resources may be wasted. In response to the above problems, this embodiment adopts a preset conversion method to convert the data format of the bit allocation result to obtain the scanning table data, thereby effectively reducing the data transmission amount, improving the data transmission efficiency, and reducing resource waste.

[0073] S250, sending the scan table data to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

[0074] In this embodiment, after obtaining the scan table data, the scan table data can be sent to the sending card through the serial port instruction, and then packaged into network port data by the sending card and forwarded to the receiving card. Exemplarily, the scan table data can be sent to the sending card in the format of RGB888 through the DVI interface. After receiving the network port data, the receiving card first parses the network port data to obtain the scan table data, and then outputs the corresponding data to the scan control module of the receiving card according to the corresponding grayscale bit. The scan control module can finally determine the width of OE opening and closing based on the grayscale bit and invalid OE multiple parsed from the scan table and the minimum OE width issued by the host computer, so as to control the display of each grayscale bit data based on the width of OE opening and closing.

[0075] The technical solution of the embodiment of the present invention is to convert the data format of the bit allocation result to obtain the scan table data by using a preset conversion method after the target dual latch chip is allocated bits according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments; the scan table data is sent to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card. This technical solution can effectively reduce the amount of data transmission, improve data transmission efficiency, and reduce resource waste by performing a data format conversion operation on the bit allocation result, and forward the converted data to the receiving card through the sending card so that the receiving card can control the display of each grayscale bit data.

[0076] Embodiment 3

[0077] Figure 3 This is a schematic diagram of the structure of a bit allocation device for a LED dual latch chip provided in the third embodiment of the present invention. The device can execute the bit allocation method for the LED dual latch chip provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. Figure 3 As shown, the device comprises:

[0078] The subframe scattering segment number determination module 310 is used to determine the subframe scattering segment number according to the control parameters of the target dual latch chip; wherein the control parameters include frame rate, clock frequency, data width, scan number, synchronization reserved time and reserved width;

[0079] A subframe corresponding number determination module 320 is used to determine a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determine the subframe corresponding number associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments;

[0080] The chip bit allocation module 330 is used to allocate bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments.

[0081] Optionally, the subframe fragmentation segment number determination module 310 is configured to:

[0082] Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time;

[0083] Determine a second parameter according to the sum of the data width and the reserved width;

[0084] determining a third parameter according to the product of the reciprocal of the clock frequency, the scan number and the second parameter;

[0085] The number of subframe fragmentation segments is determined according to the ratio of the first parameter to the third parameter.

[0086] Optionally, the subframe corresponding quantity determination module 320 is configured to:

[0087] Determine the total number of segments corresponding to the refresh rate according to the product of the refresh rate and the number of segments of the subframes;

[0088] Determine the corresponding number of subframes associated with each of the target grayscale bits based on a preset restriction condition;

[0089] Among them, the preset restriction conditions include that the corresponding number of subframes associated with the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the corresponding number of subframes associated with the previous target grayscale bits, the OE multiple corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the OE multiple corresponding to the previous target grayscale bits, the sum of the corresponding numbers of subframes associated with each target grayscale bit is less than or equal to the total number of segments corresponding to the refresh rate, and the total OE width corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is equal to twice the total OE width corresponding to the previous target grayscale bits, and the total OE width is determined based on the product of the OE multiple, the corresponding number of subframes and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

[0090] Optionally, the device further includes: a minimum OE width determination module, configured to:

[0091] Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time;

[0092] Determine the maximum OE multiple corresponding to the number of subframe fragmentation segments according to the bit allocation result;

[0093] Determine a fourth parameter according to the product of the scan number, the refresh rate and the maximum OE multiple;

[0094] The minimum OE width is determined according to the ratio of the first parameter to the fourth parameter.

[0095] Optionally, the device further comprises: a bit allocation result processing module, configured to:

[0096] After allocating bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments, converting the bit allocation result into a data format using a preset conversion method to obtain scan table data;

[0097] The scan table data is sent to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

[0098] The bit allocation device of an LED dual latch chip provided by an embodiment of the present invention can execute the bit allocation method of an LED dual latch chip provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0099] Embodiment 4

[0100] Figure 4A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0101] like Figure 4 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0102] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0103] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the bit allocation method of the LED dual latch chip.

[0104] In some embodiments, the bit allocation method of the LED dual latch chip can be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the bit allocation method of the LED dual latch chip described above can be performed. Alternatively, in other embodiments, the processor 11 can be configured to execute the bit allocation method of the LED dual latch chip in any other appropriate manner (for example, by means of firmware).

[0105] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0106] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0107] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0108] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0109] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0110] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0111] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0112] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A bit allocation method for an LED dual latch chip, characterized in that: The method comprises: Determine the number of subframe fragmentation segments according to the control parameters of the target dual latch chip; wherein the control parameters include frame rate, clock frequency, data width, scan number, synchronization reserved time and reserved width; Determine a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determine the corresponding number of subframes associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments; The target dual latch chip is allocated bits according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments.

2. The method according to claim 1, characterized in that The number of subframe fragmentation segments is determined according to the control parameters of the target dual latch chip, including: Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time; Determine a second parameter according to the sum of the data width and the reserved width; determining a third parameter according to the product of the reciprocal of the clock frequency, the scan number and the second parameter; The number of subframe fragmentation segments is determined according to the ratio of the first parameter to the third parameter.

3. The method according to claim 1, characterized in that: Determining the corresponding number of subframes associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments includes: Determine the total number of segments corresponding to the refresh rate according to the product of the refresh rate and the number of segments of the subframes; Determine the corresponding number of subframes associated with each of the target grayscale bits based on a preset restriction condition; Among them, the preset restriction conditions include that the corresponding number of subframes associated with the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the corresponding number of subframes associated with the previous target grayscale bits, the OE multiple corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the OE multiple corresponding to the previous target grayscale bits, the sum of the corresponding numbers of subframes associated with each target grayscale bit is less than or equal to the total number of segments corresponding to the refresh rate, and the total OE width corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is equal to twice the total OE width corresponding to the previous target grayscale bits, and the total OE width is determined based on the product of the OE multiple, the corresponding number of subframes and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

4. The method according to claim 3, characterized in that The minimum OE width is determined by: Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time; Determine the maximum OE multiple corresponding to the number of subframe fragmentation segments according to the bit allocation result; Determine a fourth parameter according to the product of the scan number, the refresh rate and the maximum OE multiple; The minimum OE width is determined according to the ratio of the first parameter to the fourth parameter.

5. The method according to any one of claims 1 to 4, characterized in that After allocating bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments, the method further includes: Using a preset conversion method to convert the bit allocation result into a data format to obtain scan table data; The scan table data is sent to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

6. A bit allocation device for a LED dual latch chip, characterized in that: The device comprises: A subframe scattering segment number determination module is used to determine the subframe scattering segment number according to the control parameters of the target dual latch chip; wherein the control parameters include frame frequency, clock frequency, data width, scan number, synchronization reserved time and reserved width; A subframe corresponding number determination module, used to determine a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determine the corresponding number of subframes associated with each of the target grayscale bits based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments; The chip bit allocation module is used to allocate bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments.

7. The device according to claim 6, characterized in that The subframe fragmentation segment number determination module is used to: Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time; Determine a second parameter according to the sum of the data width and the reserved width; determining a third parameter according to the product of the reciprocal of the clock frequency, the scan number and the second parameter; The number of subframe fragmentation segments is determined according to the ratio of the first parameter to the third parameter.

8. The device according to claim 6, characterized in that The subframe corresponding quantity determination module is used to: Determine the total number of segments corresponding to the refresh rate according to the product of the refresh rate and the number of segments of the subframes; Determine the corresponding number of subframes associated with each of the target grayscale bits based on a preset restriction condition; Among them, the preset restriction conditions include that the corresponding number of subframes associated with the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the corresponding number of subframes associated with the previous target grayscale bits, the OE multiple corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the OE multiple corresponding to the previous target grayscale bits, the sum of the corresponding numbers of subframes associated with each target grayscale bit is less than or equal to the total number of segments corresponding to the refresh rate, and the total OE width corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is equal to twice the total OE width corresponding to the previous target grayscale bits, and the total OE width is determined based on the product of the OE multiple, the corresponding number of subframes and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the bit allocation method for the LED dual latch chip according to any one of claims 1 to 5.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the bit allocation method of the LED dual latch chip according to any one of claims 1 to 5 when executed.

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