Pixel driving circuit and driving method thereof, display panel and display device

Abstract

The embodiment of the invention provides a pixel driving circuit and a driving method thereof, a display panel and a display device, relates to the technical field of display, and is used for solving the problem of residual images in the display field. The pixel driving circuit comprises a first light-emitting control sub-circuit, a first initialization sub-circuit, a driving sub-circuit and a second light-emitting control sub-circuit, the first light-emitting control sub-circuit is coupled with a first voltage signal end, a first node and a first light-emitting control end; the first initialization sub-circuit is coupled with an initialization signal end, a second node and a first scanning signal end; the driving sub-circuit is coupled with the first node, the second node and the third node; the second light-emitting control sub-circuit is coupled with the third node, the light-emitting device, the first light-emitting control end and the second light-emitting control end. The time at which the second light emission control signal jumps to the active level is earlier than the time at which the first light emission control signal jumps to the active level. The pixel driving circuit provided by the embodiment of the invention is used for driving the light-emitting device to emit light.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a pixel driving circuit and its driving method, a display panel, and a display device. Background Art

[0002] Currently, in display technology, due to the hysteresis effect of the driving transistors during the pixel driving process, a ghosting phenomenon occurs when switching from a black-and-white image to a 48-grayscale image after a period of time. This ghosting disappears after a short period, which is known as short-term ghosting. In currently used pixel driving circuits, the gate-source voltage VGS of the driving transistors during the initialization phase varies under different image switching conditions, causing the short-term ghosting phenomenon. Summary of the Invention

[0003] The purpose of this disclosure is to provide a pixel driving circuit and driving method thereof, a display panel, and a display device that can solve the problem of short-term image retention.

[0004] To achieve the above objectives, some embodiments of this disclosure provide the following technical solutions:

[0005] On one hand, a pixel driving circuit is provided. The pixel driving circuit includes a first light-emitting control subcircuit, a first initialization subcircuit, a driving subcircuit, and a second light-emitting control subcircuit. The first light-emitting control subcircuit is coupled to a first voltage signal terminal, a first node, and a first light-emitting control terminal; the first light-emitting control subcircuit is configured to turn on in response to a first light-emitting control signal from the first light-emitting control terminal, transmitting a first voltage signal from the first voltage signal terminal to the first node; the first initialization subcircuit is coupled to an initialization signal terminal, a second node, and a first scan signal terminal; the first initialization subcircuit is configured to turn on in response to a first scan signal from the first scan signal terminal, transmitting an initialization signal from the initialization signal terminal to the second node; the driving subcircuit is coupled to the first node, the second node, and the first light-emitting control terminal. The three nodes are coupled; the driving sub-circuit is configured to turn on in response to an electrical signal from the second node, transmitting an electrical signal from the first node to the third node; a second light-emitting control sub-circuit is coupled to the third node, the light-emitting device, the first light-emitting control terminal, and the second light-emitting control terminal, and is configured to turn on in response to the first light-emitting control signal and a second light-emitting control signal from the second light-emitting control terminal, transmitting an electrical signal from the third node to the light-emitting device; wherein the second light-emitting control signal transitions to an active level earlier than the first light-emitting control signal transitions to an active level.

[0006] In the pixel driving circuit provided in this disclosure, a first light-emitting control sub-circuit is provided, which is turned on in response to a first light-emitting control signal from the first light-emitting control terminal, and transmits a first voltage signal from the first voltage signal terminal to the first node. A first initialization sub-circuit is provided, which is turned on in response to a first scan signal from the first scan signal terminal, and transmits an initialization signal from the initialization signal terminal to the second node. A driving sub-circuit is provided, which is turned on in response to an electrical signal from the second node, and transmits an electrical signal from the first node to the third node. A second light-emitting control sub-circuit is provided, which is turned on in response to the first light-emitting control signal and a second light-emitting control signal from the second light-emitting control terminal, and transmits an electrical signal from the third node to the light-emitting device. The second light-emitting control signal transitions to an active level earlier than the first light-emitting control signal transitions to an active level. Furthermore, when the first light emission control sub-circuit and the first initialization sub-circuit are turned on, the driving sub-circuit receives the first voltage signal transmitted from the first voltage signal terminal and the initialization signal transmitted from the initialization signal terminal. At this time, the gate-source voltage of the transistor in the driving sub-circuit is a fixed value. This ensures that the initial state of the gate-source voltage of the transistor in the driving sub-circuit remains consistent each time the grayscale is refreshed, thereby avoiding the image retention problem caused by different grayscale images.

[0007] In some embodiments, the second light-emitting control sub-circuit includes a first transistor and a second transistor; the first terminal of the first transistor is coupled to the third node, and the second terminal of the first transistor is coupled to the light-emitting device; the control terminal of the second transistor is coupled to the first light-emitting control terminal, the first terminal of the second transistor is coupled to the second light-emitting control terminal, and the second terminal of the second transistor is coupled to the control terminal of the first transistor.

[0008] In some embodiments, the channel width of the second transistor in the second light-emitting control sub-circuit is greater than the channel length.

[0009] In some embodiments, the first light-emitting control sub-circuit includes: a third transistor, the control electrode of the third transistor being coupled to the first light-emitting control terminal, the first electrode of the third transistor being coupled to the first voltage signal terminal, and the second electrode of the third transistor being coupled to the first node; the driving sub-circuit includes: a fourth transistor, the control electrode of the fourth transistor being coupled to the second node, the first electrode of the fourth transistor being coupled to the first node, and the second electrode of the fourth transistor being coupled to the third node; the first initialization sub-circuit includes: a fifth transistor, the control electrode of the fifth transistor being coupled to the first scan signal terminal, the first electrode of the fifth transistor being coupled to the initialization signal terminal, and the second electrode of the fifth transistor being coupled to the second node.

[0010] In some embodiments, the channel width-to-length ratio of the first transistor in the first light-emitting control sub-circuit is the same as that of the third transistor, and both are greater than the channel width-to-length ratio of the fourth transistor; the light-emitting device is an OLED light-emitting device, and the channel width of the fourth transistor in the driving sub-circuit is less than the channel length; or, the light-emitting device is an MLED light-emitting device, and the channel width of the fourth transistor in the driving sub-circuit is greater than the channel length.

[0011] In some embodiments, the pixel driving circuit further includes a second initialization sub-circuit, a data writing sub-circuit, and a compensation sub-circuit; the second initialization sub-circuit is coupled to the initialization signal terminal, the light-emitting device, and the first scan signal terminal; the second initialization sub-circuit is configured to be turned on in response to a first scan signal from the first scan signal terminal, and to transmit an initialization signal from the initialization signal terminal to the light-emitting device; the data writing sub-circuit is coupled to the second scan signal terminal, the data signal terminal, and the first node; the data writing sub-circuit is configured to be turned on in response to a second scan signal from the second scan signal terminal, and to transmit a data signal from the data signal terminal to the first node; the compensation sub-circuit is coupled to the second scan signal terminal, the second node, and the third node; the compensation sub-circuit is configured to be turned on in response to a second scan signal from the second scan signal terminal, and to transmit a voltage from the second node to the third node.

[0012] In some embodiments, the second initialization sub-circuit includes: a sixth transistor, the control electrode of which is coupled to the first scan signal terminal, the first electrode of which is coupled to the initialization signal terminal, and the second electrode of which is coupled to the fourth node; the data writing sub-circuit includes: a seventh transistor, the control electrode of which is coupled to the second scan signal terminal, the first electrode of which is coupled to the data signal terminal, and the second electrode of which is coupled to the first node; the compensation sub-circuit includes: an eighth transistor, the control electrode of which is coupled to the second scan signal terminal, the first electrode of which is coupled to the second node, and the second electrode of which is coupled to the third node.

[0013] In some embodiments, the channel width of both the sixth transistor and the seventh transistor is greater than the channel length.

[0014] In some embodiments, the timing of the first scan signal transmitted by the first scan signal terminal is earlier than the timing of the second scan signal transmitted by the second scan signal terminal.

[0015] In some embodiments, the second light emission control signal and the first scan signal are inverted signals, and / or the first light emission control signal and the second scan signal are inverted signals.

[0016] On the other hand, a driving method for a pixel driving circuit is provided, including the pixel driving circuit as described in any of the preceding claims. A frame period includes: an initialization phase and an emission phase. The driving method includes:

[0017] During the initialization phase, the first light emission control sub-circuit of the pixel driving circuit is turned on in response to the first light emission control signal from the first light emission control terminal, and transmits the first voltage signal from the first voltage signal terminal to the first node.

[0018] The first initialization sub-circuit of the pixel driving circuit is turned on in response to the first scan signal from the first scan signal terminal, and transmits the initialization signal from the initialization signal terminal to the second node;

[0019] During the light-emitting phase, the first light-emitting control sub-circuit is turned on in response to a first light-emitting control signal from the first light-emitting control terminal, and the second light-emitting control sub-circuit is turned on in response to the first light-emitting control signal and the second light-emitting control signal from the second light-emitting control terminal, so as to form a path between the first voltage signal terminal and the light-emitting device, driving the light-emitting device to emit light.

[0020] In some embodiments, the pixel driving circuit further includes a data writing sub-circuit and a compensation sub-circuit; a frame period further includes a data writing phase between the initialization phase and the emission phase;

[0021] During the data writing phase, the data writing sub-circuit is turned on in response to a second scan signal from the second scan signal terminal, transmitting the data signal from the data signal terminal to the first node; the driving sub-circuit is turned on in response to an electrical signal from the second node, transmitting the electrical signal from the first node to the third node; the compensation sub-circuit is turned on in response to a second scan signal from the second scan signal terminal, transmitting the electrical signal from the third node to the second node to compensate the driving sub-circuit.

[0022] The beneficial effects that the pixel driving circuit driving method provided in this embodiment can achieve are the same as those that the pixel driving circuit described in the above embodiments can achieve, and will not be repeated here.

[0023] In another aspect, a display panel is provided, including a plurality of pixel driving circuits as described in any of the preceding claims, and a gate driving circuit; the gate driving circuit includes a plurality of cascaded shift register units, wherein the Nth shift register unit is electrically connected to the first scan signal terminal and the first light emission control signal terminal of the Nth row pixel driving circuit, and the (N+1)th shift register unit is electrically connected to the second scan signal terminal and the second light emission control signal terminal of the Nth row pixel driving circuit.

[0024] The beneficial effects that the display panel provided in this embodiment can achieve are the same as those that the pixel driving circuit provided in the above embodiment can achieve, and will not be repeated here.

[0025] In some embodiments, the shift register unit includes a scan signal generation circuit and an inverter; the scan signal generation circuit is electrically connected to the scan signal terminal; the scan signal generation circuit is configured to generate a scan signal and transmit it to the scan signal terminal; the inverter is electrically connected to the scan signal terminal and the light emission control signal terminal; the inverter is configured to invert the scan signal and transmit it as a light emission control signal to the light emission control signal terminal.

[0026] In another aspect, a display device is provided, comprising a display panel as described in any of the preceding claims.

[0027] The beneficial effects that the display device provided in this embodiment can achieve are the same as those that the display panel provided in the above embodiment can achieve, and will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] In the attached diagram:

[0030] Figure 1 A structural diagram of a display device provided in an embodiment of this disclosure;

[0031] Figure 2 A pixel arrangement diagram of a display panel provided in an embodiment of this disclosure;

[0032] Figure 3 A pixel architecture diagram of a display panel provided in an embodiment of this disclosure;

[0033] Figure 4A A structural diagram of a pixel driving circuit is provided for some embodiments of related technologies;

[0034] Figure 4B A timing diagram of a pixel driving circuit provided for some embodiments of related technologies;

[0035] Figure 5A This is a structural diagram of a display panel display state provided in an embodiment of the present disclosure;

[0036] Figure 5B Another screen display state structure diagram of the display panel provided in this embodiment of the present disclosure;

[0037] Figure 5C This is another structural diagram of a display panel display state provided in an embodiment of the present disclosure;

[0038] Figure 6A A graph showing the curves of current versus grayscale voltage in a pixel driving circuit provided in an embodiment of this disclosure;

[0039] Figure 6B A graph showing the curves of current versus grayscale voltage in a pixel driving circuit provided in an embodiment of this disclosure;

[0040] Figure 7 A pixel driving circuit diagram provided in an embodiment of this disclosure;

[0041] Figure 8 A timing control diagram for a pixel driving circuit provided in an embodiment of this disclosure;

[0042] Figure 9A A timing control diagram for a pixel driving circuit provided in an embodiment of this disclosure;

[0043] Figure 9B A timing control diagram for a pixel driving circuit provided in an embodiment of this disclosure;

[0044] Figure 9C A driving process diagram of a pixel driving circuit provided in an embodiment of this disclosure;

[0045] Figure 10A A timing control diagram for a pixel driving circuit provided in an embodiment of this disclosure;

[0046] Figure 10B A timing control diagram for a pixel driving circuit provided in an embodiment of this disclosure;

[0047] Figure 10C A driving process diagram of a pixel driving circuit provided in an embodiment of this disclosure;

[0048] Figure 11A A timing control diagram for a pixel driving circuit provided in an embodiment of this disclosure;

[0049] Figure 11B A timing control diagram for a pixel driving circuit provided in an embodiment of this disclosure;

[0050] Figure 11C A driving process diagram of a pixel driving circuit provided in an embodiment of this disclosure;

[0051] Figure 12 An equivalent circuit diagram of a shift register unit provided in an embodiment of this disclosure. DETAILED DESCRIPTION

[0052] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0053] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0054] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0055] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. The term "connected" should be interpreted broadly; for example, a "connection" can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection via an intermediate medium. The term "coupled," for example, indicates that two or more components have direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0056] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0057] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0058] As used herein, depending on the context, the term "if" may optionally be interpreted as meaning "when," "at," "in response to determination," or "in response to detection." Similarly, depending on the context, the phrase "if it is determined..." or "if [the stated condition or event] is optionally interpreted as meaning "when it is determined..." or "in response to determination..." or "when [the stated condition or event] is detected" or "in response to the detection of [the stated condition or event]."

[0059] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0060] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0061] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0062] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable range of deviation for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable range of deviation for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable range of deviation for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0063] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on another layer or substrate, or that there is an intermediate layer between the layer or element and another layer or substrate.

[0064] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as being limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched areas shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the areas of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0065] The transistors used in the circuits provided in the embodiments of this application can be thin-film transistors, field-effect transistors (e.g., oxide thin-film transistors), or other switching devices with the same characteristics. The embodiments of this application all use thin-film transistors as examples for illustration. Preferably, the thin-film transistors used in the embodiments of this disclosure can be oxide semiconductor transistors or low-temperature polycrystalline silicon (LTPS) thin-film transistors.

[0066] In this embodiment, the coupling methods of the drain and source of each transistor can be interchanged. Therefore, in this embodiment, the drain and source of each transistor are actually indistinguishable. Here, one of the two terminals of the transistor, excluding the control terminal (i.e., the gate), is called the drain, and the other is called the source. The thin-film transistor used in this embodiment can be an N-type transistor or a P-type transistor. In this embodiment, when an N-type thin-film transistor is used, its first terminal can be the source, and its second terminal can be the drain. In the following embodiments, the description uses an N-type thin-film transistor as an example, meaning that the thin-film transistor is turned on when the control terminal signal is high. It is conceivable that when a P-type transistor is used, the timing of the drive signal needs to be adjusted accordingly. Specific details are not elaborated here, but should be within the scope of protection of this invention.

[0067] In the circuits provided in the embodiments of this application, nodes do not represent actual existing components, but rather represent the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0068] In the circuits provided in the embodiments of this application, all transistors are P-type transistors, as an example, for explanation.

[0069] like Figure 1 As shown, some embodiments of this disclosure provide a display device 1000, which, by way of example, can be any display device that displays either moving (e.g., video) or stationary (e.g., still images) text or images. More specifically, the display device of the embodiments is contemplated to be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigators, cockpit controllers and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0070] The aforementioned display device 1000 may be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display device, a quantum dot light-emitting diode (QLED) display device, etc. The specific form of the aforementioned display device 1000 is not limited in the embodiments disclosed herein.

[0071] like Figure 1 As shown, the display device 1000 includes a display panel 100. For example... Figure 2 As shown, the display panel 100 includes a display area AA and a peripheral area BB located on at least one side of the display area AA.

[0072] The aforementioned display area AA includes multiple sub-pixels P. Each sub-pixel P is the smallest unit for displaying an image on the display panel 100. Each sub-pixel P can display a single color, such as red, green, or blue. By adjusting the brightness (grayscale) of different colored sub-pixels P, and through color combination and superposition, multiple colors can be displayed, thereby achieving full-color display of the display panel 100. For ease of explanation, the multiple sub-pixels P mentioned above are illustrated in a matrix arrangement. In this case, sub-pixels P arranged in a row along the horizontal direction X are called a row of sub-pixels, and sub-pixels P arranged in a row along the vertical direction Y are called a column of sub-pixels P. A row of sub-pixels P can be connected to one or more scan signal lines GL, a row of sub-pixels P can be connected to one or more light emission control signal lines EM, and a column of sub-pixels P can be connected to a data line DL. For example, as shown... Figure 3 As shown, one row of sub-pixels P is connected to two scan signal lines GL, one row of sub-pixels P is connected to the light emission control signal line EM, and one column of sub-pixels P is connected to one data line DL.

[0073] The sub-pixel P contains a light-emitting device L and a pixel driving circuit 10 for controlling the light-emitting device L to emit light.

[0074] Among them, the light-emitting device L can be an organic light-emitting diode (OLED), a micro organic light-emitting diode (Micro OLED), a quantum dot organic light-emitting diode (QLED), a mini light-emitting diode (Mini LED), or a micro light-emitting diode (Micro LED), etc.

[0075] The pixel driving circuit 10 is disposed on the substrate of the display panel 100. The scan signal line GL connected to the sub-pixel P is used to transmit the scan signal to the pixel driving circuit 10 of the sub-pixel P; the light emission control signal line EM connected to the sub-pixel P is used to transmit the light emission control signal to the pixel driving circuit 10 of the sub-pixel P; and the data line DL connected to the sub-pixel P is used to transmit the data signal data to the pixel driving circuit 10 of the sub-pixel P. The data signal data comes from the source driver S coupled to each data line DL.

[0076] It should be noted that the pixel driving circuit 10 includes multiple thin-film transistors. The control electrode of each thin-film transistor used in the pixel driving circuit 10 is the gate of the transistor, the first electrode is one of the source and drain of the thin-film transistor, and the second electrode is the other of the source and drain of the thin-film transistor. Since the source and drain of the thin-film transistor can be structurally symmetrical, their source and drain can be structurally indistinguishable. That is, the first electrode and the second electrode of the thin-film transistor in the embodiments of this disclosure can be structurally indistinguishable. For example, when the thin-film transistor is a P-type transistor, the first electrode is the source and the second electrode is the drain; when the thin-film transistor is an N-type transistor, the first electrode is the drain and the second electrode is the source.

[0077] Reference Figure 4A In some related embodiments, taking the 7T1C pixel driving circuit as an example, it typically consists of seven transistors and one capacitor, used to control the driving current of the light-emitting device. (Refer to...) Figure 4B The driving process of the aforementioned pixel driving circuit is as follows: one frame cycle includes an initialization phase t1, a data refresh and compensation phase t2, and an emission phase t3. The 7T1C pixel driving circuit requires at least one set of emission control driving units and one set of gate driving units to provide driving signals. Combined with... Figure 4A and Figure 4BIt can be seen that during each grayscale refresh, the gate-source voltage state of the driving transistor is affected by the previous frame. Because the grayscale of the previous frame is different, the driving transistor may be in different states during the initialization phase, leading to inconsistent gate-source voltage states. In other words, after the previous frame ends, residual charge may remain at the gate and source of the driving transistor, resulting in inconsistent gate-source voltage states. This inconsistency affects the driving current of the current frame, causing the image from the previous frame to remain in the subsequent frame, making it impossible to completely eliminate the difference in gate-source voltage.

[0078] Reference Figure 5A , Figure 5B and Figure 5C , Figure 5A H1 and H2 in the image represent two different grayscale levels. H1 corresponds to a white grayscale, and H2 corresponds to a black grayscale. When the image switches from a bright to a dark grayscale, for example, to a dark grayscale... Figure 5B When displaying a 48-level grayscale image, highlight information from the previous frame may remain in the subsequent frame, manifesting as a brief "ghosting" effect until it disappears. Figure 5C The image shown. (As shown) Figure 6A As shown, during the grayscale transition process, Figure 6A In the image, I represents gray level L0 and III represents gray level L255. When the two gray levels change to the intermediate gray level L48, L0 first goes from state I to state II, while L255 goes from state III to state IV and then to state VI. That is, due to the inconsistent state of the gate source voltage, the gray level changes of the two follow different paths, resulting in an uneven gray level change and obvious image retention.

[0079] The inventors of this application, through research, discovered, referring to... Figure 6B By unifying L0 and L255 into a single state V, and then following the same path to the intermediate state VI, image retention can be improved. State V is a fixed setting of the gate-source voltage before each frame refresh, and its value is greater than the gate-source voltage at L255.

[0080] Based on this, the pixel driving circuit of this application is described below. Under the control of the timing signal, the pixel driving circuit can ensure that the gate source voltage is a fixed value, thereby improving the above-mentioned afterimage state and enhancing the display effect of the display device.

[0081] Reference Figure 7Some embodiments of this application provide a pixel driving circuit 10 including a first light emission control sub-circuit 110, a first initialization sub-circuit 120, a driving sub-circuit 130, and a second light emission control sub-circuit 140. The first light emission control sub-circuit 110 is coupled to a first voltage signal terminal VDD, a first node N1, and a first light emission control terminal EM1; the first light emission control sub-circuit 110 is configured to be turned on in response to a first light emission control signal e1 from the first light emission control terminal EM1, and to transmit a first voltage signal from the first voltage signal terminal VDD to the first node N1.

[0082] The first initialization sub-circuit 120 is coupled to the initialization signal terminal Vinit, the second node N2 and the first scan signal terminal GT1; the first initialization sub-circuit 120 is configured to turn on in response to the first scan signal g1 from the first scan signal terminal GT1 and transmit the initialization signal from the initialization signal terminal GT1 to the second node N2.

[0083] The driving sub-circuit 130 is coupled to the first node N1, the second node N2 and the third node N3; the driving sub-circuit 130 is configured to turn on in response to an electrical signal from the second node N2 and transmit an electrical signal from the first node N1 to the third node N3.

[0084] The second light-emitting control sub-circuit 140 is coupled to the third node N3, the light-emitting device L, the first light-emitting control terminal EM1, and the second light-emitting control terminal EM2. The second light-emitting control sub-circuit 140 is configured to turn on in response to the first light-emitting control signal e1 and the second light-emitting control signal e2 from the second light-emitting control terminal EM2, and transmit the electrical signal of the third node N3 to the light-emitting device L. The second light-emitting control signal e2 transitions to an effective level earlier than the first light-emitting control signal e1 transitions to an effective level.

[0085] In the pixel driving circuit 10 provided in this disclosure, a first light-emitting control sub-circuit 110 is provided, which is turned on in response to a first light-emitting control signal e1 from the first light-emitting control terminal EM1, and transmits a first voltage signal from the first voltage signal terminal VDD to the first node N1. A first initialization sub-circuit 120 is provided, which is turned on in response to a first scan signal g1 from the first scan signal terminal GT1, and transmits an initialization signal from the initialization signal terminal Vinit to the second node N2. A driving sub-circuit 130 is provided, which is turned on in response to an electrical signal from the second node N2, and transmits an electrical signal from the first node N1 to the third node N3. A second light-emitting control sub-circuit 140 is provided, which is turned on in response to the first light-emitting control signal e1 and a second light-emitting control signal e2 from the second light-emitting control terminal EM2, and transmits an electrical signal from the third node N3 to the light-emitting device L. Referring to... Figure 8 The timing of the second light-emitting control signal e2 transitioning to an active level is earlier than the timing of the first light-emitting control signal e1 transitioning to an active level. This means that when stage T1 transitions to stage T2, the second light-emitting control signal e2 transitions to an active level, while the first light-emitting control signal e1 transitions to an active level when stage T2 transitions to stage T3. In other words, the timing of the second light-emitting control signal e2 transitioning from an inactive level to an active level is earlier than the timing of the first light-emitting control signal e1 transitioning from an inactive level to an active level. That is, the second light-emitting control signal e2 is inactive in stage T1, and the first light-emitting control signal e1 is inactive in stage T2. Additionally, refer to... Figure 8 The first light emission control signal e1 is at an effective level during stage T1, and the corresponding first scan signal g1 is also at an effective level during this period. At this time, the first light emission control sub-circuit 110 and the first initialization sub-circuit 120 are turned on. The driving sub-circuit 130 receives the first voltage signal transmitted from the first voltage signal terminal VDD and the initialization signal transmitted from the initialization signal terminal Vinit. At this time, the gate-source voltage of the transistor in the driving sub-circuit 130 is a fixed value. This ensures that the initial state of the gate-source voltage of the transistor in the driving sub-circuit 130 remains consistent during each grayscale refresh, thereby avoiding the image retention problem caused by different grayscale images.

[0086] The aforementioned effective level refers to the operating level. For example, if the transistor is a P-type transistor, the operating level is low, and the non-operating level is high. Of course, if the transistor is an N-type transistor, the operating level is high, and the non-operating level is low. In some embodiments of this disclosure, the transistor is described using a P-type transistor as an example, meaning that the aforementioned effective level is low.

[0087] In some embodiments, such as Figure 7 As shown, the second light-emitting control sub-circuit 140 includes a first transistor M1 and a second transistor M2; the first electrode of the first transistor M1 is coupled to the third node N3, and the second electrode of the first transistor M1 is coupled to the light-emitting device L; the control electrode of the second transistor M2 is coupled to the first light-emitting control terminal EM1, the first electrode of the second transistor M2 is coupled to the second light-emitting control terminal EM2, and the second electrode of the second transistor M2 is coupled to the control electrode of the first transistor M1.

[0088] For example, such as Figure 7 As shown, the second transistor M2 is turned on in response to the first light-emitting control signal of the first light-emitting control terminal EM1, and can transmit the second light-emitting control signal e2 of the second light-emitting control terminal EM2 to the control electrode of the first transistor M1. The first transistor M1 is turned on in response to the second light-emitting control signal e2, and can transmit the electrical signal of the third node N3 to the light-emitting device L to realize light emission.

[0089] In some embodiments, such as Figure 7 As shown, the first light-emitting control sub-circuit 110 includes a third transistor M3, the control electrode of the third transistor M3 is coupled to the first light-emitting control terminal EM1, the first electrode of the third transistor M3 is coupled to the first voltage signal terminal VDD, and the second electrode of the third transistor M3 is coupled to the first node N1; the driving sub-circuit 130 includes a fourth transistor M4, the control electrode of the fourth transistor M4 is coupled to the second node N2, the first electrode of the fourth transistor M4 is coupled to the first node N1, and the second electrode of the fourth transistor M4 is coupled to the third node N3; the first initialization sub-circuit 120 includes a fifth transistor M5, the control electrode of the fifth transistor M5 is coupled to the first scan signal terminal GT1, the first electrode of the fifth transistor M5 is coupled to the initialization signal terminal, and the second electrode of the fifth transistor M5 is coupled to the second node.

[0090] For example, the third transistor M3 is turned on in response to the first light emission control signal e1 from the first light emission control terminal EM1, and can transmit the first voltage signal from the first voltage signal terminal VDD to the first node N1; the fifth transistor M5 is turned on in response to the first scan signal g1 from the first scan signal terminal GT1, and transmits the initialization signal from the initialization signal terminal Vinit to the second node N2; the fourth transistor M4 is turned on in response to the electrical signal from the second node N2, and transmits the electrical signal from the first node N1 to the third node N3. That is, the first electrode of the fourth transistor M4 receives the first voltage signal from the first voltage signal terminal VDD, and the control electrode of the fourth transistor M4 receives the initialization signal from the initialization signal terminal Vinit. At this time, the voltage difference (i.e., the gate-source voltage) between the control electrode and the first electrode of the fourth transistor M4 is the difference between the initialization signal and the first voltage signal, which is a fixed value. This ensures that the initial state of the gate-source voltage of the fourth transistor M4 remains consistent each time grayscale is refreshed, so as to avoid the image retention problem caused by different grayscale images.

[0091] In some embodiments, continue to refer to Figure 7 The pixel driving circuit 10 further includes a second initialization sub-circuit 150, a data writing sub-circuit 160, and a compensation sub-circuit 170; the second initialization sub-circuit 150 is coupled to the initialization signal terminal Vinit, the light-emitting device L, and the first scan signal terminal GT1; the second initialization sub-circuit 150 is configured to be turned on in response to the first scan signal g1 from the first scan signal terminal GT1, and to transmit the initialization signal from the initialization signal terminal Vinit to the light-emitting device L.

[0092] The data writing sub-circuit 160 is coupled to the second scan signal terminal GT2, the data signal terminal Data, and the first node N1. The data writing sub-circuit 160 is configured to turn on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmit the data signal from the data signal terminal Data to the first node N1.

[0093] The compensation sub-circuit 170 is coupled to the second scan signal terminal GT2, the second node N2 and the third node N3; the compensation sub-circuit 170 is configured to turn on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmit the voltage from the second node N2 to the third node N3.

[0094] In some embodiments, the second initialization sub-circuit 150 includes: a sixth transistor M6, the control electrode of the sixth transistor M6 being coupled to the first scan signal terminal GT1, the first electrode of the sixth transistor M6 being coupled to the initialization signal terminal Vinit, and the second electrode of the sixth transistor M6 being coupled to the fourth node N4; the data writing sub-circuit 160 includes: a seventh transistor M7, the control electrode of the seventh transistor M7 being coupled to the second scan signal terminal GT2, the first electrode of the seventh transistor M7 being coupled to the data signal terminal Data, and the second electrode of the seventh transistor M7 being coupled to the first node N1; the compensation sub-circuit 170 includes: an eighth transistor M8, the control electrode of the eighth transistor M8 being coupled to the second scan signal terminal GT2, the first electrode of the eighth transistor M8 being coupled to the second node N2, and the second electrode of the eighth transistor M8 being coupled to the third node.

[0095] For example, the sixth transistor M6 is turned on in response to the first scan signal g1 from the first scan signal terminal GT1, and transmits the initialization signal from the initialization signal terminal Vinit to the light-emitting device L; the seventh transistor M7 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmits the data signal from the data signal terminal Data to the first node N1; the eighth transistor M8 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, and transmits the voltage from the second node N2 to the third node N3.

[0096] It should be noted that the control electrodes of both the fifth transistor M5 and the sixth transistor M6 are coupled to the first scan signal terminal GT1. Furthermore, the turn-on and turn-off times of the fifth transistor M5 can correspond to the turn-on and turn-off times of the sixth transistor M6 (at the same time, the sixth transistor M6 and the fifth transistor M5 are simultaneously turned on or off). Moreover, both transistors are of the same type (e.g., both the sixth transistor M6 and the fifth transistor M5 are P-type transistors). Therefore, the sixth transistor M6 and the fifth transistor M5 can use the same scan signal line. Compared to using different signal lines to control the turn-on or turn-off of the sixth transistor M6 and the fifth transistor M5 separately, sharing a signal line saves one scan signal line, simplifies the structure of the pixel driving circuit 10, and reduces the power consumption of the pixel driving circuit 10, which is beneficial for achieving a thinner and lighter display device.

[0097] Similarly, the control electrodes of both the seventh transistor M7 and the eighth transistor M8 are coupled to the second scan signal terminal GT2. Furthermore, the on and off times of the seventh transistor M7 can correspond to the on and off times of the eighth transistor M8 (at the same time, the seventh transistor M7 and the eighth transistor M8 are simultaneously on or simultaneously off), and both are of the same transistor type (e.g., both the seventh transistor M7 and the eighth transistor M8 are P-type transistors). Therefore, the seventh transistor M7 and the eighth transistor M8 can use the same scan signal line. Compared to using different signal lines to control the on or off of the seventh transistor M7 and the eighth transistor M8 separately, sharing a signal line saves one scan signal line, simplifies the structure of the pixel driving circuit 10, and reduces the power consumption of the pixel driving circuit 10, which is beneficial for achieving a thinner and lighter display device.

[0098] In some embodiments, such as Figure 7 and Figure 8 As shown, the timing of the first scan signal g1 transmitted by the first scan signal terminal GT1 is earlier than the timing of the second scan signal g2 transmitted by the second scan signal terminal GT2.

[0099] It should be noted that, as described above, the first scan signal terminal GT1 is used to couple the first initialization sub-circuit 120 and the second initialization sub-circuit 150. That is, during the initialization phase, both the first initialization sub-circuit 120 and the second initialization sub-circuit 150 can be turned on in response to the first scan signal of the first scan signal terminal GT1. The second scan signal terminal GT2 is used to couple the data writing sub-circuit 160 and the compensation sub-circuit 170. That is, during the compensation phase, the data writing sub-circuit 160 and the compensation sub-circuit 170 can be turned on in response to the second scan signal g2 transmitted by the second scan signal terminal GT2. Therefore, based on one frame period of the pixel driving circuit 10, the activation times of the first scan signal g1 and the second scan signal g2 are set to be different.

[0100] In some embodiments, refer to Figure 8 The second light emission control signal e2 and the first scan signal g1 are inverted signals, and / or the first light emission control signal e1 and the second scan signal g2 are inverted signals.

[0101] It should be noted that, referring to Figure 8 and combined Figure 7The second light-emitting control signal e2 is used to turn off the first transistor M1, and the first scan signal g1 is used to turn on the sixth transistor M6 and the fifth transistor M5. The sixth transistor M6 and the fifth transistor M5 need to be turned on during the initialization phase, while the second light-emitting control signal e2 only needs to turn on the first transistor M1 during the light-emitting phase. Therefore, in the same timing phase, the second light-emitting control signal e2 and the first scan signal g1 are set to be inverse signals. That is, when the second light-emitting control signal e2 is high, the first scan signal g1 is low, and when the second light-emitting control signal e2 is low, the first scan signal g1 is high. For example, during the initialization phase, the second light-emitting control signal e2 is high and the first scan signal g1 is low; during the light-emitting phase, the second light-emitting control signal e2 is low and the first scan signal g1 is high.

[0102] Similarly, the first light-emitting control signal e1 is used to control the conduction of the second transistor M2, and the second scanning signal g2 is used to control the conduction of the seventh transistor M7 and the eighth transistor M8. The seventh transistor M7 and the eighth transistor M8 need to be turned on during the compensation phase, while the first light-emitting control signal e1 only needs to turn on the second transistor M2 during the light-emitting phase. Therefore, in the same phase timing, the first light-emitting control signal e1 and the second scanning signal g2 are set to be inverse signals. That is, when the first light-emitting control signal e1 is high, the second scanning signal g2 is low, and when the first light-emitting control signal e1 is low, the second scanning signal g2 is high. For example, during the compensation phase, the first light-emitting control signal e1 is high and the second scanning signal g2 is low; during the light-emitting phase, the first light-emitting control signal e1 is low and the second scanning signal g2 is high.

[0103] In the pixel driving circuit 10 provided in the embodiments of this disclosure, the first node N1, the second node N2, and the third node N3 mentioned below do not represent actual existing components, but rather represent the junction points of related sub-circuits or electronic components in the circuit diagram. In other words, these nodes are equivalent to the junction points of related sub-circuits or electronic components in the circuit diagram.

[0104] The light-emitting device L in the pixel driving circuit described above can be an OLED light-emitting device or an MLED light-emitting device. However, since the driving current of the two devices is on the order of magnitude, for example, the driving current of an OLED light-emitting device is on the order of nA and the driving current of an MLED light-emitting device is on the order of μA, the channel length and channel width of the transistor in the corresponding pixel driving circuit 10 need to be adjusted according to the type of light-emitting device to ensure that the current in the pixel driving circuit 10 is compatible with the light-emitting device.

[0105] The following details the relationship between the channel length and channel width of the transistor in the pixel driving circuit 10.

[0106] In some embodiments, refer to Figure 7 The channel width of the second transistor M2 in the second light-emitting control sub-circuit 140 is greater than the channel length.

[0107] In some embodiments, refer to Figure 7 The channel widths of the sixth transistor M6 and the seventh transistor M7 are both greater than or equal to the channel length.

[0108] In some embodiments, refer to Figure 7 The channel width-to-length ratio of the first transistor in the first light-emitting control sub-circuit 110 is the same as that of the third transistor, and both are greater than the channel width-to-length ratio of the fourth transistor.

[0109] It should be noted that when the light-emitting device L is an OLED light-emitting device or an MLED light-emitting device, the above-mentioned configuration of setting the channel width of the second transistor M2 of the second light-emitting control sub-circuit 140 to be greater than the channel length, the channel width of the sixth transistor M6 and the seventh transistor M7 to be greater than or equal to the channel length, and the channel width-to-length ratio of the first transistor of the first light-emitting control sub-circuit 110 to be the same as the channel width-to-length ratio of the third transistor and both greater than the channel width-to-length ratio of the fourth transistor can all be used to adjust the corresponding current.

[0110] In other embodiments, the light-emitting device L is an OLED light-emitting device, and the channel width of the fourth transistor M4 of the driving sub-circuit 130 is less than the channel length; or, the light-emitting device L is an MLED light-emitting device, and the channel width of the fourth transistor M4 of the driving sub-circuit 130 is greater than the channel length.

[0111] It is understandable that the above-mentioned fourth transistor M4, when the type of light-emitting device L is different, adopts the above setting to ensure that the number of poles of the driving circuit matches the corresponding light-emitting device L.

[0112] The structure of the pixel driving circuit 10 is based on any of the above embodiments. For example... Figure 7 As shown, the pixel driving circuit 10 includes a first light emission control sub-circuit 110, a first initialization sub-circuit 120, a driving sub-circuit 130, a second light emission control sub-circuit 140, a second initialization sub-circuit 150, a data writing sub-circuit 160, and a compensation sub-circuit 170. Some embodiments of this disclosure provide a driving method for the pixel driving circuit 10.

[0113] like Figure 8 As shown, one frame cycle of the pixel driving circuit 10 includes: initialization phase T1, data writing phase T2, and light emission phase T3.

[0114] In some embodiments, refer to Figure 9A , Figure 9B and Figure 9C During the initialization phase T1, the first light emission control sub-circuit 110 of the pixel driving circuit 10 is turned on in response to the first light emission control signal e1 from the first light emission control terminal EM1, and transmits the first voltage signal from the first voltage signal terminal VDD to the first node N1; the first initialization sub-circuit 120 of the pixel driving circuit 10 is turned on in response to the first scan signal g1 from the first scan signal terminal GT1, and transmits the initialization signal from the initialization signal terminal Vinit to the second node N2.

[0115] During the luminescence stage, reference Figure 10A , Figure 10B and Figure 10C During the data writing phase T2, the data writing sub-circuit 160 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, transmitting the data signal from the data signal terminal Data to the first node N1; the driving sub-circuit 130 is turned on in response to the electrical signal from the second node N2, transmitting the electrical signal from the first node N1 to the third node N3; the compensation sub-circuit 170 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, transmitting the electrical signal from the third node N3 to the second node N2 to compensate the driving sub-circuit.

[0116] In some embodiments, refer to Figure 11A , Figure 11B and Figure 11C The first light-emitting control sub-circuit 110 is turned on in response to the first light-emitting control signal e1 from EM1, and the second light-emitting control sub-circuit 140 is turned on in response to the first light-emitting control signal e1 and the second light-emitting control signal e2 from the second light-emitting control terminal EM2, so as to form a path between the first voltage signal terminal VDD and the light-emitting device L, and drive the light-emitting device L to emit light.

[0117] For example, the following combination Figures 9A to 11C right Figure 7 The specific operation of the pixel driving circuit 10 shown will be described in detail. In the following description, the first transistor M1, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 in the pixel driving circuit 10 are P-type thin-film transistors. The first voltage signal transmitted at the first voltage signal terminal VDD is a high-level voltage, the second voltage signal transmitted at the second voltage signal terminal VSS is a low-level voltage, and the initialization signal at the initialization signal terminal Vinit is a low-level voltage, as illustrated in the following description. Those skilled in the art should understand that in the above-described pixel driving circuit 10, when the line between the first voltage signal terminal VDD and the second voltage signal terminal VSS is connected, the light-emitting device L emits light.

[0118] For example, in the description below, "0" represents a low level and "1" represents a high level.

[0119] like Figure 9A and Figure 9B As shown, during the initialization phase T1, e1 = 0, g1 = 0, e2 = 1, g2 = 1.

[0120] In this case, refer to Figure 9C The third transistor M3 is turned on in response to the first light-emitting control signal e1 from the first light-emitting control terminal EM1, transmitting the first voltage signal from the first voltage signal terminal VDD to the first node N1; the fifth transistor M5 is turned on in response to the first scan signal g1 from the first scan signal terminal GT1, transmitting the initialization signal from the initialization signal terminal Vinit to the second node N2. At the same time, the second transistor M2 is also turned on in response to the first light-emitting control signal e1 from the first light-emitting control terminal EM1, but the first transistor M1 is turned off in response to the second light-emitting control signal e2 from the second light-emitting control terminal EM2. Therefore, the line between the first voltage terminal VDD and the second voltage terminal VSS is open, and the light-emitting device L does not emit light. It should be noted that the first electrode of the fourth transistor M4 receives the first voltage signal from the first voltage signal terminal VDD, and the control electrode of the fourth transistor M4 receives the initialization signal from the initialization signal terminal Vinit. At this time, the voltage difference between the control electrode and the first electrode of the fourth transistor M4 (i.e., the gate-source voltage) is the difference between the initialization signal and the first voltage signal, which is a fixed value. This ensures that the initial state of the gate-source voltage of the fourth transistor M4 remains consistent each time grayscale is refreshed, so as to avoid the image retention problem caused by different grayscale images.

[0121] In the data writing phase T2, such as Figure 10A As shown, e1 = 0, g1 = 1, e2 = 1, g2 = 0, or as... Figure 10BAs shown, e1 = 1, g1 = 1, e2 = 1, g2 = 0.

[0122] In this case, refer to Figure 10C The seventh transistor M7 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, transmitting the data signal from the data signal terminal Data to the first node N1; the fourth transistor T4 is turned on in response to the electrical signal from the second node N2, transmitting the electrical signal from the first node N1 to the third node N3; the eighth transistor M8 is turned on in response to the second scan signal g2 from the second scan signal terminal GT2, transmitting the electrical signal from the third node N3 to the second node N2, so as to compensate the drive sub-circuit 130.

[0123] Based on the above, since the second scan signal terminal GT2 is simultaneously connected to both the seventh transistor M7 and the eighth transistor M8, that is, under the control of the second scan signal g2 at the second scan signal terminal GT2, both the seventh transistor M7 and the eighth transistor M8 can be simultaneously turned on. Figure 10A and Figure 10B The second scan signal g2 is low during this stage, therefore Figure 10C The pixel driving circuit 10 shown is in Figure 10A and Figure 10B Under the timing control shown, data writing can be achieved.

[0124] During the luminescence stage T3, as Figure 11A and Figure 11B As shown, e1 = 0, g1 = 0, e2 = 1, g2 = 1.

[0125] Reference Figure 11C In such Figure 11A and Figure 11B In the timing sequence shown, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7 and the eighth transistor M8 are all off, the second transistor M2 is turned on in response to the first light emission control signal e1 from EM1, and the first transistor M1 is turned on in response to the second light emission control signal e2 from the second light emission control terminal EM2, so as to form a path between the first voltage signal terminal VDD and the light-emitting device L, driving the light-emitting device L to emit light.

[0126] In some embodiments of the present disclosure, the display panel 100 provided, such as Figure 3 As shown, the display panel 100 includes a plurality of pixel driving circuits 10 and a gate driving circuit 20 as described in any of the above embodiments. The beneficial effects that the display panel 100 provided in this disclosure embodiment can achieve are the same as the beneficial effects that the pixel driving circuit 10 provided in the above embodiments can achieve, and will not be described again here.

[0127] The gate driving circuit 20 includes multiple cascaded shift register units 201, wherein the Nth shift register unit 201 is electrically connected to the first scan signal terminal GT1 and the first light emission control signal terminal EM1 of the Nth row pixel driving circuit 10, and the (N+1)th shift register unit is electrically connected to the second scan signal terminal GT2 and the second light emission control signal terminal EM2 of the Nth row pixel driving circuit.

[0128] In some embodiments, refer to Figure 12 The shift register unit 201 includes a scan signal generation circuit 30 and an inverter 40. The scan signal generation circuit 30 is electrically connected to the scan signal terminal and is configured to generate a scan signal and transmit it to the scan signal terminal. The inverter 40 is electrically connected to both the scan signal terminal and the light emission control signal terminal and is configured to invert the scan signal and transmit it as a light emission control signal to the light emission control signal terminal.

[0129] It should be noted that the above-mentioned scanning signal terminals include the first scanning signal terminal GT1 and the second scanning signal terminal GT2, and the light emission control signal terminals include the first light emission control signal terminal EM1 and the second light emission control signal terminal EM2.

[0130] In some embodiments, within the same shift register unit 201, when the scan signal generation circuit 30 generates the first scan signal terminal GT1, since the first scan signal terminal GT1 and the second light emission control signal e2 are inverted signals, the scan signal terminal connected to the inverter 40 transmits the first scan signal terminal GT1, and the light emission control signal terminal connected to the inverter 40 becomes the second light emission control signal terminal EM2, transmitting the second light emission control signal e2. Similarly, when the scan signal generation circuit 30 generates the second scan signal terminal GT2, since the second scan signal g2 and the first light emission control signal e1 are inverted signals, the scan signal terminal connected to the inverter 40 becomes the second scan signal terminal GT2, transmitting the second scan signal g2, and the light emission control signal terminal connected to the inverter 40 becomes the first light emission control signal terminal EM1, transmitting the second light emission control signal e2.

[0131] In some embodiments of the display device 1000 provided in this disclosure, such as Figure 1 and Figure 2 As shown, the display device 1000 includes the display panel 100 described in any of the above embodiments. The beneficial effects that the display device 1000 provided in the embodiments of this disclosure can achieve are the same as the beneficial effects that the display panel 100 provided in the above embodiments can achieve, and will not be repeated here.

[0132] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A pixel driving circuit, characterized in that: The pixel driving circuit is used to connect the light emitting device, and includes: A first light-emitting control subcircuit is coupled to the first voltage signal terminal, the first node and the first light-emitting control terminal; the first light-emitting control subcircuit is configured to be turned on in response to a first light-emitting control signal from the first light-emitting control terminal, and transmit the first voltage signal from the first voltage signal terminal to the first node; a first initialization sub-circuit coupled to the initialization signal terminal, the second node and the first scan signal terminal; the first initialization sub-circuit is configured to be turned on in response to a first scan signal from the first scan signal terminal, and transmit the initialization signal from the initialization signal terminal to the second node; a driving subcircuit coupled to the first node, the second node and the third node; the driving subcircuit is configured to be turned on in response to an electrical signal from the second node, and transmit the electrical signal from the first node to the third node; a second light-emitting control subcircuit coupled to the third node, the light-emitting device, the first light-emitting control terminal and the second light-emitting control terminal, the second light-emitting control subcircuit being configured to be turned on in response to the first light-emitting control signal and the second light-emitting control signal from the second light-emitting control terminal, and to transmit the electrical signal of the third node to the light-emitting device; The time when the second light-emitting control signal jumps to the valid level is earlier than the time when the first light-emitting control signal jumps to the valid level.

2. The pixel driving circuit according to claim 1, characterized in that: The second light emitting control subcircuit comprises: a first transistor, wherein a first electrode of the first transistor is coupled to the third node, and a second electrode of the first transistor is coupled to the light emitting device; A second transistor, wherein a control electrode of the second transistor is coupled to the first light emitting control terminal, a first electrode of the second transistor is coupled to the second light emitting control terminal, and a second electrode of the second transistor is coupled to the control electrode of the first transistor.

3. The pixel driving circuit according to claim 2, characterized in that: The channel width of the second transistor of the second light emitting control sub-circuit is greater than the channel length.

4. The pixel driving circuit according to any one of claims 1 to 3, characterized in that: The first light emitting control subcircuit comprises: a third transistor, a control electrode of the third transistor is coupled to the first light emitting control terminal, a first electrode of the third transistor is coupled to the first voltage signal terminal, and a second electrode of the third transistor is coupled to the first node; The driving subcircuit comprises: a fourth transistor, a control electrode of the fourth transistor is coupled to the second node, a first electrode of the fourth transistor is coupled to the first node, and a second electrode of the fourth transistor is coupled to the third node; The first initialization subcircuit includes: a fifth transistor, a control electrode of the fifth transistor is coupled to the first scan signal terminal, a first electrode of the fifth transistor is coupled to the initialization signal terminal, and a second electrode of the fifth transistor is coupled to the second node.

5. The pixel driving circuit according to claim 4, characterized in that: The channel width-to-length ratio of the first transistor of the first light-emitting control subcircuit is the same as the channel width-to-length ratio of the third transistor, and both are greater than the channel width-to-length ratio of the fourth transistor; The light emitting device is an OLED light emitting device, and the channel width of the fourth transistor of the driving subcircuit is smaller than the channel length; or, The light emitting device is an MLED light emitting device, and the channel width of the fourth transistor of the driving sub-circuit is greater than the channel length.

6. The pixel driving circuit according to claim 1, characterized in that: The pixel driving circuit further includes: a second initialization subcircuit coupled to the initialization signal terminal, the light emitting device and the first scan signal terminal; the second initialization subcircuit is configured to be turned on in response to a first scan signal from the first scan signal terminal, and transmit the initialization signal from the initialization signal terminal to the light emitting device; a data writing sub-circuit coupled to the second scanning signal terminal, the data signal terminal and the first node; the data writing sub-circuit is configured to be turned on in response to a second scanning signal from the second scanning signal terminal, and transmit the data signal from the data signal terminal to the first node; A compensation subcircuit is coupled to the second scan signal terminal, the second node and the third node; the compensation subcircuit is configured to be turned on in response to a second scan signal from the second scan signal terminal to transmit a voltage from the second node to the third node.

7. The pixel driving circuit according to claim 6, characterized in that: The second initialization sub-circuit comprises: a sixth transistor, a control electrode of the sixth transistor is coupled to the first scan signal terminal, a first electrode of the sixth transistor is coupled to the initialization signal terminal, and a second electrode of the sixth transistor is coupled to the fourth node; The data writing sub-circuit comprises: a seventh transistor, a control electrode of the seventh transistor is coupled to the second scanning signal terminal, a first electrode of the seventh transistor is coupled to the data signal terminal, and a second electrode of the seventh transistor is coupled to the first node; The compensation subcircuit includes: an eighth transistor, a control electrode of the eighth transistor is coupled to the second scan signal terminal, a first electrode of the eighth transistor is coupled to the second node, and a second electrode of the eighth transistor is coupled to the third node.

8. The pixel driving circuit according to claim 7, characterized in that: The channel widths of the sixth transistor and the seventh transistor are both greater than the channel lengths.

9. The pixel driving circuit according to any one of claims 6 to 8, characterized in that: The first scanning signal terminal transmits the first scanning signal at an earlier time than the second scanning signal terminal transmits the second scanning signal at an earlier time.

10. The pixel driving circuit according to claim 9, characterized in that: The second light emitting control signal and the first scanning signal are inverted signals to each other, and / or the first light emitting control signal and the second scanning signal are inverted signals to each other.

11. A driving method for a pixel driving circuit, characterized in that: A pixel driving circuit as claimed in any one of claims 1 to 10; A frame period includes: an initialization phase and a light-emitting phase; the driving method includes: During the initialization phase, The first light emitting control subcircuit of the pixel driving circuit is turned on in response to the first light emitting control signal from the first light emitting control terminal, and transmits the first voltage signal from the first voltage signal terminal to the first node; The first initialization sub-circuit of the pixel driving circuit is turned on in response to the first scanning signal from the first scanning signal terminal, and transmits the initialization signal from the initialization signal terminal to the second node; In the light-emitting phase, The first light-emitting control subcircuit is turned on in response to a first light-emitting control signal from the first light-emitting control terminal, and the second light-emitting control subcircuit is turned on in response to the first light-emitting control signal and a second light-emitting control signal from the second light-emitting control terminal, so as to form a path between the first voltage signal terminal and the light-emitting device to drive the light-emitting device to emit light.

12. The driving method of the pixel driving circuit according to claim 11, characterized in that: The pixel driving circuit further includes a data writing subcircuit and a compensation subcircuit; a frame period further includes a data writing phase between the initialization phase and the light emitting phase; In the data writing phase, The data writing sub-circuit is turned on in response to the second scanning signal from the second scanning signal terminal, and transmits the data signal from the data signal terminal to the first node; The driving subcircuit is turned on in response to the electrical signal from the second node, and transmits the electrical signal from the first node to the third node; The compensation sub-circuit is turned on in response to the second scan signal from the second scan signal terminal, and transmits the electrical signal from the third node to the second node to compensate the driving sub-circuit.

13. A display panel, characterized in that: comprising a plurality of pixel driving circuits as claimed in any one of claims 1 to 10, and a gate driving circuit; The gate driving circuit comprises a plurality of cascaded shift register units, wherein: The Nth shift register unit is electrically connected to the first scan signal terminal and the first light control signal terminal of the Nth row pixel driving circuit, and the N+1th shift register unit is electrically connected to the second scan signal terminal and the second light control signal terminal of the Nth row pixel driving circuit.

14. The display panel according to claim 13, characterized in that: The shift register unit comprises: A scanning signal generating circuit is electrically connected to the scanning signal terminal; the scanning signal generating circuit is configured to generate a scanning signal and transmit the scanning signal to the scanning signal terminal; An inverter is electrically connected to the scanning signal terminal and the light-emitting control signal terminal; the inverter is configured to invert the scanning signal and transmit it to the light-emitting control signal terminal as a light-emitting control signal.

15. A display device, characterized in that: include: A display panel as claimed in claim 13 or 14.

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