Array substrate and display panel

Abstract

The invention provides an array substrate and a display panel. The purpose that the actual size of a driving transistor and the actual area of a capacitor meet the design requirement is achieved. The array substrate comprises a substrate semiconductor layer and a plurality of conductive layers, and the conductive layers are stacked on the side, away from the substrate, of the semiconductor layer. The plurality of conductive layers comprise pixel circuits and a plurality of signal lines, the pixel circuits comprise driving transistors and first transistors, and the plurality of signal lines comprise power supply signal lines and first power supply connecting lines which are arranged in different layers; a first electrode of the first transistor is connected with a first electrode of the driving transistor, and a second electrode of the first transistor is electrically connected with a power signal line through a first power connecting line; the power supply signal lines extend along a first direction parallel to the substrate, the first power supply connecting lines extend along a second direction parallel to the substrate, and the second direction and the first direction are crossed; in the first direction, the driving transistor and the first power connecting line are located on the two sides of the first transistor respectively.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] In recent years, organic light-emitting display panels have gradually become the mainstream products in the display field. Due to their advantages such as high image quality, power saving, thin body and wide range of applications, they are widely used in various consumer electronic products such as mobile phones, televisions, laptops, desktop computers, etc.

[0003] However, in the array substrate of the current display panel, the actual size of the driving transistor and the actual area of ​​the capacitor cannot meet the design requirements. Summary of the invention

[0004] In order to solve the above technical problems, the present application is proposed. The embodiments of the present application provide an array substrate and a display panel, which achieve the purpose that the actual size of the driving transistor and the actual area of ​​the capacitor meet the design requirements.

[0005] In a first aspect, an embodiment of the present application provides an array substrate, the array substrate comprising a base substrate, a semiconductor layer and a plurality of conductive layers, the semiconductor layer being located on one side of the base substrate, and the plurality of conductive layers being stacked on a side of the semiconductor layer away from the base substrate; wherein the plurality of conductive layers comprise a pixel circuit and a plurality of signal lines, the pixel circuit comprising a driving transistor and a first transistor, the plurality of signal lines comprising a power signal line and a first power connection line arranged in different layers; the first electrode of the first transistor is connected to the first electrode of the driving transistor, and the second electrode of the first transistor is electrically connected to the power signal line through the first power connection line; the power signal line extends along a first direction parallel to the base substrate, the first power connection line extends along a second direction parallel to the base substrate, and the second direction intersects with the first direction; in the first direction, the driving transistor and the first power connection line are respectively located on both sides of the first transistor.

[0006] In combination with the first aspect, in certain implementations of the first aspect, the first electrode of the first transistor is connected to the first electrode of the driving transistor through a first conductive via, and the orthographic projection of the first conductive via on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate; preferably, the active portion of the driving transistor is located in the semiconductor layer, and the active portion has a symmetry axis in a first direction; preferably, the distance between the orthographic projection of the control electrode of the driving transistor on the substrate and the orthographic projection of the first conductive via on the substrate is greater than or equal to 0.9 microns.

[0007] In combination with the first aspect, in certain implementations of the first aspect, the second electrode of the first transistor is connected to the first power connection line through a second conductive via, the first power connection line is connected to the power signal line through a third conductive via, and the second conductive via and the third conductive via are arranged along the second direction.

[0008] Preferably, the second electrode includes a source electrode, and the first electrode includes a drain electrode.

[0009] Preferably, the second direction is perpendicular to the first direction.

[0010] In combination with the first aspect, in certain implementations of the first aspect, the multiple signal lines further include a jumper connection line, the pixel circuit further includes a second transistor, and the first electrode of the second transistor is electrically connected to the first electrode of the first transistor through the jumper connection line.

[0011] Preferably, the jumper connection line and the first power connection line are located in the same conductive layer.

[0012] Preferably, the first electrode of the second transistor is connected to the jumper connection line through a fourth conductive via.

[0013] Preferably, the plurality of signal lines further include a reference voltage signal line, and the reference voltage signal line is connected to the second electrode of the second transistor.

[0014] In combination with the first aspect, in certain implementations of the first aspect, the multiple signal lines also include a second power connection line, the pixel circuit also includes a capacitor, the first plate of the capacitor shares the control electrode of the driving transistor, the second plate of the capacitor is connected to the second power connection line, and the second power connection line is connected to the power signal line.

[0015] Preferably, the second electrode plate and the second power connection line are arranged in different layers, and the second electrode plate is connected to the second power connection line through the fifth conductive via and the sixth conductive via.

[0016] Preferably, in the first direction, the second power connection line and the first power connection line are respectively located on two sides of the first transistor.

[0017] Preferably, the second power connection line extends along the second direction.

[0018] In combination with the first aspect, in some implementations of the first aspect, the second power connection line and the first power connection line are located in the same conductive layer.

[0019] Preferably, the first power connection line and the second power connection line are arranged at intervals in the same conductive layer.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the multiple signal lines further include a data signal line, and the orthographic projection of the data signal line on the substrate at least partially overlaps with the orthographic projections of the first power connection line and the second power connection line on the substrate.

[0021] In combination with the first aspect, in certain implementations of the first aspect, the semiconductor layer and the multiple conductive layers include multiple pixel circuits, and the multiple pixel circuits are arranged along the second direction; at least one of the first power connection line and the second power connection line is located between adjacent pixel circuits in the second direction; preferably, at least one of the first power connection line and the second power connection line has a symmetry axis in the first direction; preferably, at least one of the first power connection line and the second power connection line connects adjacent pixel circuits in the second direction.

[0022] In combination with the first aspect, in certain implementations of the first aspect, the same second power connection line connects the second plate of the capacitor in the adjacent pixel circuit; and / or the same first power connection line connects the second electrode of the first transistor in the adjacent pixel circuit; preferably, the pixel circuit includes an 8T1C pixel circuit.

[0023] In a second aspect, an embodiment of the present application provides a display panel, and the display panel includes the array substrate provided by any of the above embodiments.

[0024] The array substrate provided in the embodiment of the present application includes a substrate substrate, a semiconductor layer and a plurality of conductive layers, the semiconductor layer is located on one side of the substrate substrate, and the plurality of conductive layers are stacked on the side of the semiconductor layer away from the substrate substrate; wherein the plurality of conductive layers include a pixel circuit and a plurality of signal lines, the pixel circuit includes a driving transistor and a first transistor, and the plurality of signal lines include a power signal line and a first power connection line arranged in different layers; the first electrode of the first transistor is connected to the first electrode of the driving transistor, the second electrode of the first transistor is connected to the first power connection line, and the first power connection line is connected to the power signal line; the power signal line extends along a first direction parallel to the substrate substrate, the first power connection line extends along a second direction parallel to the substrate substrate, and the second direction intersects with the first direction; in the first direction, the driving transistor and the first power connection line are respectively located on both sides of the first transistor. The present application realizes the connection between the power signal line and the second electrode of the first transistor through the first power connection line, and the driving transistor and the first power connection line are respectively located on both sides of the first transistor, that is, the position of the first power connection line will not limit the spacing between the first electrode of the first transistor and the driving transistor, that is, the spacing between the first electrode of the first transistor and the driving transistor is large enough, so that the actual size of the driving transistor and the actual area of ​​the capacitor can meet the design requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] By describing the embodiments of the present application in more detail in conjunction with the accompanying drawings, the above and other purposes, features and advantages of the present application will become more apparent. The accompanying drawings are used to provide a further understanding of the embodiments of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the present application and do not constitute a limitation of the present application. In the accompanying drawings, the same reference numerals generally represent the same components or steps.

[0026] Figure 1 The figure shows a schematic diagram of a top view structure of an array substrate provided by the related art.

[0027] Figure 2 Shown Figure 1 Schematic diagram of the enlarged structure of area A in the middle.

[0028] Figure 3 FIG. 1 is a schematic diagram of a top view of the structure of an array substrate provided in one embodiment of the present application.

[0029] Figure 4 Shown Figure 3 Schematic diagram of the enlarged structure of area B in the middle.

[0030] Figure 5 FIG. 1 is a circuit diagram of a pixel circuit provided in accordance with an embodiment of the present application.

[0031] Figure 6 Shown is a schematic top view of the structure of an array substrate provided in another embodiment of the present application.

[0032] Figure 7 Shown is a schematic top view of the structure of an array substrate provided in another embodiment of the present application.

[0033] Figure 8 Shown is a schematic structural diagram of a display panel provided in one embodiment of the present application.

[0034] Figure numerals: array substrate 100; pixel circuit 110; driving transistor DTFT; first transistor T1; second transistor T2; capacitor C; power signal line elvdd; first power connection line Line1; second power connection line Line2; jumper connection line Line3; reference voltage signal line Vref; data signal line Data; first direction F1; second direction F2; first conductive via K1; second conductive via K2; third conductive via K3; fourth conductive via K4; fifth conductive via K5; sixth conductive via K6; first connection line L1; active part a; display panel 10. DETAILED DESCRIPTION

[0035] Figure 1 FIG. 1 is a schematic diagram of a top view of an array substrate provided by a related art. Figure 1As shown, in the array substrate 100 provided by the related art, in order to realize the connection between the power signal line elvdd and the second electrode (such as the source) of the first transistor T1, the first connection line L1 located in the third metal layer is usually used to connect the power signal line elvdd and the second electrode of the first transistor T1, and the first connection line L1 is arranged vertically. The first electrode (such as the drain) of the first transistor T1 is located between the control electrode (such as the gate) of the driving transistor DTFT and the first connection line L1, and the first connection line L1 and the first electrode of the first transistor T1 are both located in the third metal layer. In order to ensure the safe spacing between different components in the third metal layer, the first electrode of the first transistor T1 needs to be arranged close to the control electrode of the driving transistor DTFT. This results in a smaller spacing between the first electrode of the first transistor T1 and the control electrode of the driving transistor DTFT, which in turn results in the actual size of the control electrode of the driving transistor DTFT being smaller than the design requirement size, and the actual area of ​​the capacitor C being smaller than the design requirement area, that is, the actual size of the driving transistor DTFT and the actual area of ​​the capacitor C cannot meet the design requirements.

[0036] For example, the width design requirement of the driving transistor DTFT is 2.7 microns, the length design requirement of the driving transistor DTFT is 18 microns, and the area design requirement of the capacitor C is 67 square microns, while in the array substrate 100 provided by the related art, the actual width of the driving transistor DTFT is 2.7 microns, the actual length of the driving transistor DTFT is 16 microns, and the actual area of ​​the capacitor C is 58 square microns. Therefore, the actual size of the driving transistor DTFT and the actual area of ​​the capacitor C cannot meet the design requirements.

[0037] Figure 2 Shown Figure 1 Schematic diagram of the enlarged structure of the local area. Figure 2 Shows Figure 1 The driving transistor in Figure 2 As shown, the active portion a of the driving transistor DTFT is severely distorted, and the active portion a of the driving transistor DTFT cannot be designed to be a symmetrical structure, thereby failing to achieve mass production.

[0038] In order to solve the above technical problems, the array substrate provided by the present application includes a substrate substrate, a semiconductor layer and a plurality of conductive layers, the semiconductor layer is located on one side of the substrate substrate, and the plurality of conductive layers are stacked on the side of the semiconductor layer away from the substrate substrate; wherein the plurality of conductive layers include a pixel circuit and a plurality of signal lines, the pixel circuit includes a driving transistor and a first transistor, and the plurality of signal lines include a power signal line and a first power connection line arranged in different layers; the first electrode of the first transistor is connected to the first electrode of the driving transistor, and the second electrode of the first transistor is electrically connected to the power signal line through the first power connection line; the power signal line extends along a first direction parallel to the substrate substrate, and the first power connection line extends along a second direction parallel to the substrate substrate, and the second direction intersects with the first direction; in the first direction, the driving transistor and the first power connection line are respectively located on both sides of the first transistor. The present application realizes the connection between the power signal line and the second electrode of the first transistor through the first power connection line, and the driving transistor and the first power connection line are respectively located on both sides of the first transistor, that is, the position of the first power connection line will not limit the spacing between the first electrode of the first transistor and the driving transistor, that is, the spacing between the first electrode of the first transistor and the driving transistor is large enough, so that the actual size of the driving transistor and the actual area of ​​the capacitor can meet the design requirements.

[0039] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0040] In addition, in order to better illustrate the present application, numerous specific details are provided in the following specific embodiments. It should be understood by those skilled in the art that the present application can also be implemented without certain specific details. In some examples, methods and means well known to those skilled in the art are not described in detail in order to highlight the subject matter of the present application.

[0041] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0042] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0043] Figure 3 FIG. 1 is a schematic diagram of a top view of an array substrate provided in an embodiment of the present application. Figure 3As shown, an embodiment of the present application provides an array substrate 100, the array substrate 100 includes a base substrate, a semiconductor layer and a plurality of conductive layers, the semiconductor layer is located on one side of the base substrate, and the plurality of conductive layers are stacked on a side of the semiconductor layer away from the base substrate; wherein the semiconductor layer and the plurality of conductive layers include a pixel circuit 110 and a plurality of signal lines, the pixel circuit 110 includes a driving transistor DTFT and a first transistor T1, the plurality of signal lines include a power signal line elvdd and a first power connection line Line1 arranged in different layers; the first electrode of the first transistor T1 is connected to the first electrode of the driving transistor DTFT, and the second electrode of the first transistor T1 is electrically connected to the power signal line elvdd through the first power connection line Line1; the power signal line elvdd extends along a first direction F1 parallel to the base substrate, the first power connection line Line1 extends along a second direction F2 parallel to the base substrate, and the second direction F2 intersects with the first direction F1; in the first direction F1, the driving transistor DTFT and the first power connection line Line1 are respectively located on both sides of the first transistor T1.

[0044] exist Figure 3 In the figure, the first direction F1 refers to the vertical direction, and the second direction F2 refers to the horizontal direction.

[0045] In actual application, the power signal line elvdd is connected to the second electrode of the first transistor T1 through the first power connection line Line1, thereby eliminating Figure 1 The first connection line L1 in the related technology shown, and the driving transistor DTFT and the first power connection line Line1 are respectively located on both sides of the first transistor T1, that is, the position of the first power connection line Line1 will not limit the distance between the first electrode of the first transistor T1 and the driving transistor DTFT, that is, the distance between the first electrode of the first transistor T1 and the driving transistor DTFT is large enough, so that the actual size of the driving transistor DTFT and the actual area of ​​the capacitor can meet the design requirements.

[0046] In one embodiment, the first electrode of the first transistor T1 is connected to the first electrode of the driving transistor DTFT through the first conductive via K1, and the orthographic projection of the first conductive via K1 on the substrate overlaps with the orthographic projection of the semiconductor layer on the substrate. Exemplarily, the overlapping area of ​​the orthographic projection of the first conductive via K1 on the substrate and the orthographic projection of the semiconductor layer on the substrate is greater than half of the orthographic projection area of ​​the first conductive via K1. Figure 1 As shown in the first connection line L1, there is enough space around the driving transistor DTFT to accommodate the first conductive via K1 without compressing the occupied space of the driving transistor DTFT, thereby avoiding distortion of the active portion a of the driving transistor DTFT located in the semiconductor layer.

[0047] Figure 4 Shown Figure 3 Schematic diagram of the enlarged structure of a local area. Figure 4 Shows Figure 3 The driving transistor DTFT and the first conductive via K1 in FIG. Figure 4 As shown, the active portion a of the driving transistor DTFT is located in the semiconductor layer, and the active portion a has a symmetry axis in the first direction F1, that is, the active portion a is a symmetrical structure, and the symmetry axis is parallel to the first direction F1. It can be seen that since the first conductive via K1 will not squeeze the driving transistor DTFT, the active portion a can be designed into a symmetrical structure, which is conducive to mass production.

[0048] In one embodiment, Figure 4 As shown, the distance D between the orthographic projection of the control electrode of the driving transistor DTFT on the substrate and the orthographic projection of the first conductive via K1 on the substrate is greater than or equal to 0.9 micrometers. For example, the distance D is 0.9 micrometers, 1 micrometer, 1.1 micrometers, etc. By setting the distance D to be greater than or equal to 0.9 micrometers, the signal interference between the control electrode of the driving transistor DTFT and the first conductive via K1 can be reduced, thereby improving reliability.

[0049] Figure 5 FIG. 1 is a circuit diagram of a pixel circuit provided by an embodiment of the present application. Figure 5 As shown, in some embodiments, the pixel circuit 110 includes an 8T1C pixel circuit, that is, the pixel circuit 110 provided in the embodiment of the present application includes eight transistors and a storage capacitor, wherein the eight transistors include a driving transistor DTFT, a first transistor T1 and a second transistor T2, and the present application does not provide detailed descriptions of other transistors.

[0050] The pixel circuit 110 composed of eight transistors and one storage capacitor has the following advantages: first, the brightness and color of each pixel can be controlled more finely, thereby achieving high resolution and detail display; second, more precise color control can be provided to help the display panel present more accurate colors and improve color reproduction; third, through the reasonable design and control of eight transistors and one storage capacitor, energy saving effects can be achieved, energy consumption can be reduced, and the energy efficiency performance of the display panel can be improved; fourth, the fast response speed helps to reduce image afterimages and blurring in dynamic scenes; fifth, the structure of this pixel circuit 110 is relatively simple and stable, easy to integrate and control, and improves the reliability and stability of the display panel; sixth, compared with other complex pixel circuits, the 8T1C pixel circuit provided in the embodiment of the present application has lower preparation costs and maintenance costs.

[0051] Figure 6 FIG. 2 is a schematic diagram of a top view of an array substrate provided by another embodiment of the present application. Figure 6 As shown, in the array substrate 100 provided in the embodiment of the present application, the second electrode of the first transistor T1 is connected to the first power connection line Line1 through the second conductive via K2, the first power connection line Line1 is connected to the power signal line elvdd through the third conductive via K3, and the second conductive via K2 and the third conductive via K3 are arranged along the second direction F2.

[0052] The embodiment of the present application realizes the connection between the power signal line elvdd and the second electrode of the first transistor T1 through the first power connection line Line1, the second conductive via K2 and the third conductive via K3. Figure 6 In the embodiment, the second conductive via K2 and the third conductive via K3 are arranged in a transverse direction, and the second conductive via K2 is located on the right side of the third conductive via K3.

[0053] Preferably, the second electrode includes a source electrode, and the first electrode includes a drain electrode.

[0054] Preferably, the second direction F2 is perpendicular to the first direction F1.

[0055] In one embodiment, Figure 6 As shown, in the array substrate 100 provided in the embodiment of the present application, the various signal lines further include a jumper connection line Line3, the pixel circuit 110 further includes a second transistor T2, and the first electrode of the second transistor T2 is electrically connected to the first electrode of the first transistor T1 through the jumper connection line Line3.

[0056] The embodiment of the present application realizes the connection between the first transistor T1 and the second transistor T2 through the jumper connection line Line3. Specifically, one end of the jumper connection line Line3 is connected to the first electrode of the second transistor T2, and the other end of the jumper connection line Line3 is connected to the first electrode of the first transistor T1.

[0057] In some embodiments, the plurality of conductive layers include a first metal layer, a second metal layer, a third metal layer, and a fourth metal layer stacked in a direction gradually away from the base substrate.

[0058] Preferably, the jumper connection line Line3 and the first power connection line Line1 are located in the same conductive layer. Specifically, the jumper connection line Line3 and the first power connection line Line1 are both located in the third metal layer. The power signal line elvdd is located in the fourth metal layer.

[0059] refer to Figure 6 Preferably, the first electrode of the second transistor T2 is connected to the jumper connection line Line3 through a fourth conductive via K4.

[0060] refer to Figure 5Preferably, the multiple signal lines further include a reference voltage signal line Vref, and the reference voltage signal line Vref is connected to the second electrode of the second transistor T2.

[0061] In actual application, after the second transistor T2 is turned on, the reference voltage signal in the reference voltage signal line Vref is transmitted from the second electrode of the second transistor T2 to the first electrode of the second transistor T2, and is further transmitted to the first electrode of the driving transistor DTFT and the first electrode of the first transistor T1, thereby utilizing the reference voltage signal in the reference voltage signal line Vref to initialize the first electrode of the driving transistor DTFT and the first electrode of the first transistor T1.

[0062] Figure 7 FIG. 2 is a schematic diagram of a top view of an array substrate provided by another embodiment of the present application. Figure 7 As shown, in the array substrate 100 provided in the embodiment of the present application, the multiple signal lines also include a second power connection line Line2, the pixel circuit 110 also includes a capacitor C, the first plate of the capacitor C shares the control electrode of the driving transistor DTFT, the second plate of the capacitor C is connected to the second power connection line Line2, and the second power connection line Line2 is connected to the power signal line elvdd.

[0063] The first electrode of the capacitor C and the control electrode of the driving transistor DTFT are both located in the first metal layer. The actual size of the driving transistor DTFT meets the design requirement size, so the actual area of ​​the capacitor C also meets the design requirement area.

[0064] In actual application, the actual width of the driving transistor DTFT obtained by the present application is 2.7 microns (equal to the width design requirement), the actual length of the driving transistor DTFT is 18 microns (equal to the length design requirement), and the actual area of ​​the capacitor C is 67 square microns (equal to the area design requirement). Therefore, the actual size of the driving transistor DTFT and the actual area of ​​the capacitor C provided by the present application meet the design requirements.

[0065] In some embodiments, a distance between the capacitor and the first electrode of the first transistor in the second direction is greater than 0.9 micrometers.

[0066] Preferably, the second electrode plate and the second power connection line Line2 are arranged in different layers, and the second electrode plate is connected to the second power connection line Line2 through the fifth conductive via K5 and the sixth conductive via K6.

[0067] The second electrode plate is located at the second metal layer, and the second power connection line Line2 is located at the third metal layer. The second power connection line Line2 is connected to the power signal line elvdd through the fifth conductive via K5.

[0068] It should be emphasized that the fifth conductive via K5 serves as a point for connecting the power signal line elvdd with the pixel circuit 110, and the first conductive via K1 and the second conductive via K2 together constitute another point for connecting the power signal line elvdd with the pixel circuit 110. Through these two connection points, the electrical conductivity performance of the array substrate 100 is improved.

[0069] Preferably, in the first direction F1, the second power connection line Line2 and the first power connection line Line1 are respectively located on both sides of the first transistor T1. Figure 7 In the vertical direction, the second power connection line Line2 is located above the first transistor T1, and the first power connection line Line1 is located below the first transistor T1.

[0070] Preferably, the second power connection line Line2 extends along the second direction F2. Figure 7 , the second power connection line Line2 extends horizontally.

[0071] In some embodiments, the second power connection line Line2 and the first power connection line Line1 are located in the same conductive layer. Specifically, the second power connection line Line2 and the first power connection line Line1 are both located in the third metal layer.

[0072] refer to Figure 7 Preferably, the first power connection line Line1 and the second power connection line Line2 are arranged at intervals in the same conductive layer.

[0073] refer to Figure 7 The multiple signal lines further include a data signal line Data, and the orthographic projection of the data signal line Data on the substrate at least partially overlaps with the orthographic projections of the first power connection line Line1 and the second power connection line Line2 on the substrate.

[0074] The data signal line Data extends vertically, and the first power connection line Line1 and the second power connection line Line2 both extend horizontally. That is, the orthographic projection of the data signal line Data on the substrate intersects with the orthographic projection of the first power connection line Line1 on the substrate, and the orthographic projection of the data signal line Data on the substrate intersects with the orthographic projection of the second power connection line Line2 on the substrate.

[0075] refer to Figure 7 In the array substrate 100 provided in the embodiment of the present application, the multiple conductive layers include a plurality of pixel circuits 110, and the plurality of pixel circuits 110 are arranged along the second direction F2; at least one of the first power connection line Line1 and the second power connection line Line2 is located between adjacent pixel circuits 110 in the second direction F2.

[0076] Multiple (may be two) pixel circuits 110 are arranged horizontally, and the same first power connection line Line1 connects two adjacent pixel circuits 110 to provide power supply voltage to the two adjacent pixel circuits 110 through the same first power connection line Line1; the same second power connection line Line2 also connects two adjacent pixel circuits 110 to provide power supply voltage to the two adjacent pixel circuits 110 through the same second power connection line Line2.

[0077] In one embodiment, at least one of the first power connection line Line1 and the second power connection line Line2 has a symmetry axis in the first direction F1.

[0078] In one embodiment, at least one of the first power connection line Line1 and the second power connection line Line2 connects adjacent pixel circuits 110 in the second direction F2.

[0079] refer to Figure 7 In the array substrate 100 provided in the embodiment of the present application, the same second power connection line Line2 connects the second plate of the capacitor C in the adjacent pixel circuit 110; and / or the same first power connection line Line1 connects the second electrode of the first transistor T1 in the adjacent pixel circuit 110.

[0080] In actual application, the first power connection line Line1 provides power voltage to the second electrode of the first transistor T1 in two adjacent pixel circuits 110 at the same time, and the second power connection line Line2 provides power voltage to the second plate of the capacitor C in two adjacent pixel circuits 110 at the same time.

[0081] Figure 8 FIG. 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present application. Figure 8 As shown, an embodiment of the present application provides a display panel 10, and the display panel 10 includes an array substrate 100 provided by any of the above embodiments. The technical principles and effects produced are similar and will not be repeated here.

[0082] It can be understood that the display panel 10 can be applied to a display device, which can be, for example, a mobile terminal, a tablet computer, a computer monitor, a television, a wearable device, an information query machine, or any other product or component with a display function.

[0083] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0084] It should also be noted that, in the present application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present application. Although multiple exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize some variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An array substrate, characterized in that: include: substrate substrate; A semiconductor layer, located on one side of the substrate; as well as A plurality of conductive layers are stacked on a side of the semiconductor layer away from the substrate; Wherein, the semiconductor layer and the plurality of conductive layers include a pixel circuit and a plurality of signal lines, the pixel circuit includes a driving transistor and a first transistor, and the plurality of signal lines include a power signal line and a first power connection line arranged in different layers; The first electrode of the first transistor is connected to the first electrode of the driving transistor, and the second electrode of the first transistor is electrically connected to the power signal line through the first power connection line; The power signal line extends along a first direction parallel to the base substrate, and the first power connection line extends along a second direction parallel to the base substrate, and the second direction intersects the first direction; in the first direction, the driving transistor and the first power connection line are respectively located on both sides of the first transistor.

2. The array substrate according to claim 1, characterized in that: The first electrode of the first transistor is connected to the first electrode of the driving transistor through a first conductive via, and an orthographic projection of the first conductive via on the base substrate overlaps with an orthographic projection of the semiconductor layer on the base substrate; Preferably, the active portion of the driving transistor is located in the semiconductor layer, and the active portion has a symmetry axis in the first direction; Preferably, a distance between an orthographic projection of the control electrode of the driving transistor on the substrate and an orthographic projection of the first conductive via on the substrate is greater than or equal to 0.9 micrometers.

3. The array substrate according to claim 1, characterized in that: The second electrode of the first transistor is connected to the first power connection line through a second conductive via, the first power connection line is connected to the power signal line through a third conductive via, and the second conductive via and the third conductive via are arranged along the second direction; Preferably, the second electrode includes a source electrode, and the first electrode includes a drain electrode; Preferably, the second direction is perpendicular to the first direction.

4. The array substrate according to claim 1, characterized in that: The plurality of signal lines further include a jumper connection line, the pixel circuit further includes a second transistor, and a first electrode of the second transistor is electrically connected to a first electrode of the first transistor through the jumper connection line; Preferably, the jumper connection line and the first power connection line are located in the same conductive layer; Preferably, the first electrode of the second transistor is connected to the jumper connection line through a fourth conductive via; Preferably, the plurality of signal lines further include a reference voltage signal line connected to the second electrode of the second transistor.

5. The array substrate according to claim 1, characterized in that: The plurality of signal lines further include a second power connection line, the pixel circuit further includes a capacitor, a first plate of the capacitor shares a control electrode of the driving transistor, a second plate of the capacitor is connected to the second power connection line, and the second power connection line is connected to the power signal line; Preferably, the second electrode plate and the second power connection line are arranged in different layers, and the second electrode plate is connected to the second power connection line through a fifth conductive via and a sixth conductive via; Preferably, in the first direction, the second power connection line and the first power connection line are respectively located on two sides of the first transistor; Preferably, the second power connection line extends along the second direction.

6. The array substrate according to claim 5, characterized in that: The second power connection line and the first power connection line are located in the same conductive layer; Preferably, the first power connection line and the second power connection line are arranged at intervals in the same conductive layer.

7. The array substrate according to claim 5, characterized in that: The plurality of signal lines further include a data signal line, and an orthographic projection of the data signal line on the base substrate at least partially overlaps with an orthographic projection of each of the first power connection line and the second power connection line on the base substrate.

8. The array substrate according to claim 5, characterized in that: The semiconductor layer and the plurality of conductive layers include a plurality of pixel circuits, and the plurality of pixel circuits are arranged along the second direction; at least one of the first power connection line and the second power connection line is at least located between adjacent pixel circuits in the second direction; Preferably, at least one of the first power connection line and the second power connection line has a symmetry axis in the first direction; Preferably, at least one of the first power connection line and the second power connection line connects the adjacent pixel circuits in the second direction.

9. The array substrate according to claim 8, characterized in that: The same second power connection line is connected to the second electrode plate of the capacitor in the adjacent pixel circuit; and / or The same first power connection line is connected to the second electrode of the first transistor in the adjacent pixel circuit; Preferably, the pixel circuit comprises an 8T1C pixel circuit.

10. A display panel, characterized in that: The invention comprises the array substrate according to any one of claims 1 to 9.

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