Gate drive circuit and display panel

Abstract

The present application discloses a gate drive circuit and a display panel, wherein the gate drive circuit includes a plurality of cascaded gate drive units, and the gate drive units include a node control module, a first frequency division module, a first output module, and a voltage regulation module. By adding a voltage regulation module linked to the first frequency division control line between the first node and the first output module, the signal in the first low-potential line or the signal in the first frequency division control line can be selected and transmitted to the fourth node according to the signal of the first node and the signal of the second node, so that the first frequency division control line can control the potential of the first node through the first frequency division module during the partitioned frequency division display, and then control the first output module to output the signal of the first low-potential line as the first gate control signal through the voltage regulation module, thereby improving the stability of the first gate control signal during the partitioned frequency division display.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a gate drive circuit and a display panel. Background Art

[0002] The gate drive circuit can control the display panel to have different refresh frequencies corresponding to different display areas, so as to realize the design of zone division and frequency division, thereby reducing power consumption.

[0003] However, during the zone-by-zone frequency display, the gate control signal output by the gate driving unit in the gate driving circuit is easily affected by the coupling of other signals, which reduces the stability of the gate control signal. Summary of the Invention

[0004] The present application provides a gate driving circuit and a display panel to alleviate the technical problem of poor stability of a gate control signal during a zone-by-zone frequency display.

[0005] In a first aspect, the present application provides a gate drive circuit, which includes a plurality of cascaded gate drive units, the gate drive units including a node control module, a first frequency division module, a first output module and a voltage regulation module, the node control module is electrically connected to the first clock line, the first control line, the first low potential line, the first high potential line, the first node and the second node; the first frequency division module is electrically connected to the first frequency division control line, the first node, the second node and the third node; the first output module is connected to the third node, the fourth node, the first low potential line and the second high potential line, and is configured to output at least one of the signal of the first low potential line and the signal of the second high potential line as a first gate control signal according to the signal of the third node and the signal of the fourth node; the voltage regulation module is electrically connected to the first node, the second node, the fourth node, the first low potential line and the first frequency division control line, and is configured to select the signal in the first low potential line or the signal in the first frequency division control line according to the signal of the first node and the signal of the second node and transmit it to the fourth node.

[0006] In a second aspect, the present application provides a display panel, which includes the above-mentioned gate driving circuit.

[0007] The gate drive circuit and display panel provided in the present application, by adding a voltage regulation module linked to the first frequency division control line between the first node and the first output module, can select the signal in the first low-potential line or the signal in the first frequency division control line according to the signal of the first node and the signal of the second node for transmission to the fourth node, so that during the partitioned frequency division display, the first frequency division control line can control the potential of the first node through the first frequency division module, and then control the first output module to output the signal of the first low-potential line as the first gate control signal through the voltage regulation module. Compared with the situation that the first low-potential line cannot output an active low potential as the first gate control signal through the first output module during the partitioned frequency division display, the low potential of the first gate control signal is in a suspended state, that is, a passive low potential, thereby improving the stability of the first gate control signal during the partitioned frequency division display. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The following detailed description of the specific embodiments of the present application in conjunction with the accompanying drawings will make the technical solutions and other beneficial effects of the present application apparent.

[0009] Figure 1 This is a circuit schematic diagram of the gate drive unit provided in an embodiment of the present application.

[0010] Figure 2 for Figure 1 The timing diagram of the gate drive unit when the partition frequency division function is turned on is shown.

[0011] Figure 3 for Figure 1 The timing diagram of the gate drive unit when the partition frequency division function is turned off is shown.

[0012] Figure 4 This is a schematic diagram of the circuit principle of the sub-pixel provided in an embodiment of the present application.

[0013] Figure 5 for Figure 4 Timing diagram of the sub-pixel shown. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0015] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance or implicitly indicating the number of the indicated technical features. The features specified as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0016] See also Figures 1 to 3 , this embodiment provides a gate driving circuit, which includes a plurality of cascaded gate driving units, such as Figure 1 As shown, the gate driving unit includes a node control module 11 , a first frequency dividing module 12 , a first output module 13 and a voltage regulating module 14 .

[0017] The node control module 11 is electrically connected to the first clock line, the first control line, the first low potential line, the first high potential line, the first node K, and the second node P[q].

[0018] The first frequency division module 12 is electrically connected to the first frequency division control line, the first node K, the second node P[q] and the third node W.

[0019] The first output module 13 is connected to the third node W, the fourth node G, the first low potential line and the second high potential line, and is configured to output at least one of the signals of the first low potential line and the second high potential line as the first gate control signal Nscan[q] based on the signal of the third node W and the signal of the fourth node G.

[0020] The voltage regulation module 14 is electrically connected to the first node K, the second node P[q], the fourth node G, the first low-potential line and the first frequency division control line, and is configured to select the signal in the first low-potential line or the signal in the first frequency division control line and transmit it to the fourth node G based on the signal of the first node K and the signal of the second node P[q].

[0021] It can be understood that the gate drive circuit provided in this embodiment, by adding a voltage regulation module 14 linked to the first frequency division control line between the first node K and the first output module 13, can select the signal in the first low-potential line or the signal in the first frequency division control line according to the signal of the first node K and the signal of the second node P[q] to be transmitted to the fourth node G, so that when the partitioned frequency division display is performed, the first frequency division control line can control the potential of the first node K through the first frequency division module 12, and then control the first output module 13 to output the signal of the first low-potential line as the first gate control signal Nscan[q] through the voltage regulation module 14. Compared with the case where the first low-potential line cannot output an active low potential as the first gate control signal Nscan[q] through the first output module 13 during the partitioned frequency division display, the low potential of the first gate control signal Nscan[q] is in a floating state (Floating), that is, a passive low potential, thereby improving the stability of the first gate control signal Nscan[q] during the partitioned frequency division display.

[0022] It should be noted that the first clock line is used to transmit the first clock signal ECK. The first control line is used to transmit the start signal STV or the signal of the second node p[q-1] in the previous gate drive unit. The first low-potential line is used to transmit the first low-potential signal NVGL. The first high-potential line is used to transmit the first high-potential signal PVGH. The first frequency division control line is used to transmit the first frequency division control signal NLF. The second high-potential line is used to transmit the second high-potential signal NVGH. Nscan[q] represents the first gate control signal Nscan[q] with a positive pulse.

[0023] The node control module 11 is configured to control the first low potential signal NVGL or the first high potential signal PVGH to be transmitted to the first node K according to the signal in the first control line and the first clock signal ECK, and to control the first low potential signal NVGL or the first high potential signal PVGH to be transmitted to the second node P[q] according to the signal of the first node K. The potential of the first node K is opposite to the potential of the second node P[q]. For example, when the first node K is at a high potential, the second node P[q] is at a low potential; or when the first node K is at a low potential, the second node P[q] is at a high potential.

[0024] The first frequency dividing module 12 is configured to control the signal of the first node K to be transmitted to the third node W according to the first frequency dividing control signal NLF and the signal of the second node P[q].

[0025] Before the voltage regulating module 14 is added, when the MFD function is turned off, the high potential and the low potential of the first gate control signal Nscan[q] are both provided by active signals, and the potential is stable. After the partition frequency determination (MFD) function is turned on, the first node K and the third node W are disconnected, the third node W is at a high potential, the fourth transistor T9 is disconnected, and the fourth transistor T9 cannot output the second high potential signal NVGH as the first gate control signal Nscan[q]; and at this time the first node K is at a low potential. Since the first node K is connected to the gate of the fifth transistor T10, the fifth transistor T10 is also disconnected, and the first output module 13 cannot output the signal in the first low potential line as the low potential of the first gate control signal Nscan[q]. At this time, the low potential of the first gate control signal Nscan[q] is derived from the passive holding potential and has poor stability. The first gate control signal Nscan[q] will be micro-short-circuited with other signals at high potential (such as gate control signals with negative pulses or initialization signals), which will cause the low potential of the first gate control signal Nscan[q] to be unable to be stably maintained.

[0026] In some embodiments, the voltage regulating module 14 includes at least one of a first regulating unit 141 , a second regulating unit 142 , and a third regulating unit 143 .

[0027] The first regulating unit 141 is electrically connected to the first node K and the fourth node G, and is configured to control the signal of the first node K to be transmitted to the fourth node G according to the signal of the first node K.

[0028] The second regulating unit 142 is electrically connected to the first node K, the fourth node G and the first frequency division control line, and is configured to control the signal of the first frequency division control line to be transmitted to the fourth node G according to the signal of the first node K.

[0029] The third regulating unit 143 is electrically connected to the second node P[q], the fourth node G and the first low potential line, and is configured to control the signal of the first low potential line to be transmitted to the fourth node G according to the signal of the second node P[q].

[0030] In some embodiments, the first regulating unit 141 includes a first transistor T28 , a first electrode of the first transistor T28 is electrically connected to a gate of the first transistor T28 and the first node K, and a second electrode of the first transistor T28 is electrically connected to the fourth node G.

[0031] It should be noted that the first electrode can be one of the source and the drain, and the second electrode can be the other of the source and the drain. For example, if the first electrode is the source, the second electrode can be the drain; or if the first electrode is the drain, the second electrode can be the source. The first transistor T28 is illustratively an N-channel oxide thin-film transistor, and can specifically be a dual-gate oxide thin-film transistor.

[0032] In some embodiments, the second regulating unit 142 includes a second transistor T29, a first electrode of the second transistor T29 is electrically connected to the first frequency division control line, a second electrode of the second transistor T29 is electrically connected to the fourth node G, and a gate of the second transistor T29 is electrically connected to the first node K; a channel type of the second transistor T29 is different from a channel type of the first transistor T28.

[0033] It should be noted that the second transistor T29 is exemplarily a P-channel polysilicon thin film transistor. The first transistor T28 and the second transistor T29 are turned on in a time-sharing manner.

[0034] In some embodiments, the third regulating unit 143 includes a third transistor T30, a first electrode of the third transistor T30 is electrically connected to the first low potential line, a second electrode of the third transistor T30 is electrically connected to the fourth node G, and a gate of the third transistor T30 is electrically connected to the second node P[q]; the channel type of the third transistor T30 is the same as the channel type of the first transistor T28.

[0035] It should be noted that the third transistor T30 is illustratively an N-channel oxide thin film transistor.

[0036] In some embodiments, the first output module 13 includes a fourth transistor T9 and a fifth transistor T10, wherein a first electrode of the fourth transistor T9 is electrically connected to the third node W, and a gate of the fourth transistor T9 is electrically connected to the second high potential line; a first electrode of the fifth transistor T10 is electrically connected to a second electrode of the fourth transistor T9 and is configured to output a first gate control signal Nscan[q], a second electrode of the fifth transistor T10 is electrically connected to the first low potential line, and a gate of the fifth transistor T10 is electrically connected to the fourth node G; wherein a channel type of the fourth transistor T9 is different from a channel type of the fifth transistor T10, and a channel type of the fourth transistor T9 is the same as a channel type of the second transistor T29.

[0037] It should be noted that this embodiment controls the switch of the fifth transistor T10 through the fourth node G, and can control the fifth transistor T10 to be turned on when the partition frequency division function is turned on, so that the first gate control signal Nscan[q] can actively output a low potential, thereby improving the stability of the low potential.

[0038] In some embodiments, such as Figure 1 As shown, the node control module 11 includes at least one of a sixth transistor T13, a seventh transistor T12, an eighth transistor T2, a ninth transistor T1 and a tenth transistor T3.

[0039] The control end of the sixth transistor T13 is configured to receive the corresponding start signal STV or the signal of the second node P[q-1] in the previous gate driving unit, and the input end of the sixth transistor T13 is electrically connected to the first low potential line or the second low potential line.

[0040] The control end of the seventh transistor T12 is electrically connected to the control end of the sixth transistor T13 , the input end of the seventh transistor T12 is electrically connected to the first high potential line, and the output end of the seventh transistor T12 is electrically connected to the output end of the sixth transistor T13 .

[0041] The control terminal of the eighth transistor T2 is configured to receive the first clock signal ECK, the input terminal of the eighth transistor T2 is electrically connected to the output terminal of the sixth transistor T13 , and the output terminal of the eighth transistor T2 is electrically connected to the first node K.

[0042] The control terminal of the ninth transistor T1 is electrically connected to the first node K, the input terminal of the ninth transistor T1 is electrically connected to the second low potential line, and the output terminal of the ninth transistor T1 is electrically connected to the second node P[q].

[0043] The control terminal of the tenth transistor T3 is electrically connected to the first node K, the input terminal of the tenth transistor T3 is electrically connected to the first high potential line, and the output terminal of the tenth transistor T3 is electrically connected to the second node P[q].

[0044] In some embodiments, such as Figure 1 As shown, the node control module 11 also includes an eleventh transistor T14, the control end of the eleventh transistor T14 is electrically connected to the second node P[q], the input end of the eleventh transistor T14 is electrically connected to the first low potential line, and the output end of the eleventh transistor T14 is electrically connected to the first node K.

[0045] It should be noted that, in this embodiment, when the second node P[q] is at a high potential, the potential of the first node K can be pulled down to the potential of the first low potential line, thereby improving working reliability.

[0046] In some embodiments, such as Figure 1 As shown, the first frequency dividing module 12 includes a first frequency dividing transistor T16 , a second frequency dividing transistor T11 and a first capacitor C2 .

[0047] The control terminal of the first frequency-dividing transistor T16 is electrically connected to the second node P[q], and the input terminal of the first frequency-dividing transistor T16 is connected to the first frequency-dividing control signal NLF.

[0048] The control end of the second frequency dividing transistor T11 is electrically connected to the output end of the first frequency dividing transistor T16 , the input end of the second frequency dividing transistor T11 is electrically connected to the first node K, and the output end of the second frequency dividing transistor T11 is electrically connected to the third node W.

[0049] A first end of the first capacitor C2 is electrically connected to the control end of the second frequency-dividing transistor T11 , and a second end of the first capacitor C2 is electrically connected to the output end of the second frequency-dividing transistor T11 .

[0050] In some embodiments, such as Figure 1 As shown, the gate driving unit also includes a second frequency division module 15, which is electrically connected to the second frequency division control line, the first node K, the second node P[q] and the fifth node M, and is configured to control the signal of the first node K to be transmitted to the fifth node M according to the second frequency division control signal PLF in the second frequency division control line and the signal of the second node P[q].

[0051] In some embodiments, the second frequency dividing module 15 includes a third frequency dividing transistor T20 , a fourth frequency dividing transistor T19 , and a second capacitor C3 .

[0052] The control terminal of the third frequency-dividing transistor T20 is electrically connected to the second node P[q], and the input terminal of the third frequency-dividing transistor T20 is connected to the second frequency-dividing control signal PLF.

[0053] The control end of the fourth frequency dividing transistor T19 is electrically connected to the output end of the third frequency dividing transistor T20 , the input end of the fourth frequency dividing transistor T19 is electrically connected to the first node K, and the output end of the fourth frequency dividing transistor T19 is electrically connected to the fifth node M.

[0054] A first end of the second capacitor C3 is electrically connected to the control end of the fourth frequency-dividing transistor T19 , and a second end of the second capacitor C3 is electrically connected to the output end of the fourth frequency-dividing transistor T19 .

[0055] Please continue reading Figure 1In some embodiments, the gate driving unit further includes a second output module 16, which is electrically connected to the second node P[q], the fifth node M, the second node P[q-2] of the q-2 stage gate driving unit, the second clock line, the first high potential line, and the second gate control line, and is configured to output the second gate control signal Pscan[q] in the second gate control line according to the signal of the second node P[q], the signal of the fifth node M, the second node P[q-2] of the q-2 stage gate driving unit, the second clock signal CK1 in the second clock line, and the first high potential signal PVGH in the first high potential line.

[0056] In some embodiments, such as Figure 1 As shown, the second output module 16 includes a first switch transistor T8 , a first output transistor T6 , a second output transistor T7 and a third capacitor C1 .

[0057] The control end of the first switch transistor T8 is electrically connected to the second node P[q-2] of the q-2th stage gate driving unit, the input end of the first switch transistor T8 is electrically connected to the fifth node M, and the output end of the first switch transistor T8 is electrically connected to the sixth node Q1.

[0058] The control terminal of the first output transistor T6 is electrically connected to the sixth node Q1 , the input terminal of the first output transistor T6 is configured to receive the second clock signal CK1 , and the output terminal of the first output transistor T6 is configured to output the second gate control signal Pscan[q].

[0059] The control terminal of the second output transistor T7 is electrically connected to the second node P[q], the input terminal of the second output transistor T7 is electrically connected to the first high potential line, and the output terminal of the second output transistor T7 is electrically connected to the output terminal of the first output transistor T6.

[0060] A first end of the third capacitor C1 is electrically connected to the control end of the first output transistor T6 , and a second end of the third capacitor C1 is electrically connected to the output end of the first output transistor T6 .

[0061] Please continue reading Figure 1In some embodiments, the gate driving unit further includes a third output module 17, which is electrically connected to the second node P[q], the fifth node M, the second node P[q-2] of the q-2 stage gate driving unit, the third clock line, the first high potential line, and the third gate control line, and is configured to output a third gate control signal Pscan[q+1] in the third gate control line based on the signal of the second node P[q], the signal of the fifth node M, the second node P[q-2] of the q-2 stage gate driving unit, the third clock signal CK2 in the third clock line, and the first high potential signal PVGH in the first high potential line.

[0062] In some embodiments, the third output module 17 includes a second switch transistor T23 , a third output transistor T24 , a fourth output transistor T25 , and a fourth capacitor C4 .

[0063] The control end of the second switch transistor T23 is electrically connected to the second node P[q-2] of the q-2th stage gate driving unit, the input end of the second switch transistor T23 is electrically connected to the fifth node M, and the output end of the second switch transistor T23 is electrically connected to the seventh node Q2.

[0064] The control terminal of the third output transistor T24 is electrically connected to the seventh node Q2 , the input terminal of the third output transistor T24 is configured to receive the third clock signal CK2 , and the output terminal of the third output transistor T24 is configured to output the third gate control signal Pscan[q+1].

[0065] The control terminal of the fourth output transistor T25 is electrically connected to the second node P[q], the input terminal of the fourth output transistor T25 is electrically connected to the first high potential line, and the output terminal of the fourth output transistor T25 is electrically connected to the output terminal of the third output transistor T24.

[0066] A first end of the fourth capacitor C4 is electrically connected to the control end of the third output transistor T24 , and a second end of the fourth capacitor C4 is electrically connected to the output end of the third output transistor T24 .

[0067] In some embodiments, the gate drive unit further includes a first control module 18, which is electrically connected to the first node K, the second node P[q], the first high potential line, and the fourth clock line, and is configured to control the signal transmission between the first high potential line and the first node K based on the fourth clock signal CK3 in the fourth clock line and the signal of the second node P[q].

[0068] In some embodiments, the first control module 18 includes a twelfth transistor T4 and a thirteenth transistor T5, the first electrode of the twelfth transistor T4 is electrically connected to the first node K, and the gate of the twelfth transistor T4 is connected to the fourth clock signal CK3; the first electrode of the thirteenth transistor T5 is electrically connected to the second electrode of the twelfth transistor T4, the gate of the thirteenth transistor T5 is electrically connected to the second node P[q], and the second electrode of the thirteenth transistor T5 is electrically connected to the first high potential line.

[0069] It should be noted that, in this embodiment, when the second node P[q] is at a low potential and the fourth clock signal CK3 is at a high potential, the twelfth transistor T4 and the thirteenth transistor T5 can be synchronously turned on to pull up the potential of the first node K to the potential of the first high potential line, thereby improving working reliability.

[0070] In some embodiments, the gate drive unit further includes a second control module 19, which is electrically connected to the third node W, the second node P[q], the first high potential line, and the fourth clock line, and is configured to control the signal transmission between the first high potential line and the third node W based on the fourth clock signal CK3 in the fourth clock line and the signal of the second node P[q].

[0071] In some embodiments, the second control module 19 includes a fourteenth transistor T17 and a fifteenth transistor T18, the first electrode of the fourteenth transistor T17 is electrically connected to the third node W, and the gate of the fourteenth transistor T17 is connected to the fourth clock signal CK3; the first electrode of the fifteenth transistor T18 is electrically connected to the second electrode of the fourteenth transistor T17, the gate of the fifteenth transistor T18 is electrically connected to the second node P[q], and the second electrode of the fifteenth transistor T18 is electrically connected to the first high potential line.

[0072] It should be noted that, in this embodiment, when the second node P[q] is at a low potential and the fourth clock signal CK3 is at a high potential, the fourteenth transistor T17 and the fifteenth transistor T18 can be synchronously turned on to pull up the potential of the third node W to the potential of the first high potential line, thereby improving working reliability.

[0073] In some embodiments, the gate drive unit further includes a third control module 20, which is electrically connected to the fifth node M, the second node P[q], the first high potential line, and the fourth clock line, and is configured to control signal transmission between the first high potential line and the fifth node M based on a fourth clock signal CK3 in the fourth clock line and a signal of the second node P[q].

[0074] In some embodiments, the third control module 20 includes a sixteenth transistor T21 and a seventeenth transistor T22, the first electrode of the sixteenth transistor T21 is electrically connected to the fifth node M, and the gate of the sixteenth transistor T21 is connected to the fourth clock signal CK3; the first electrode of the seventeenth transistor T22 is electrically connected to the second electrode of the sixteenth transistor T21, the gate of the seventeenth transistor T22 is electrically connected to the second node P[q], and the second electrode of the seventeenth transistor T22 is electrically connected to the first high potential line.

[0075] It should be noted that, in this embodiment, when the second node P[q] is at a low potential and the fourth clock signal CK3 is at a high potential, the sixteenth transistor T21 and the seventeenth transistor T22 can be synchronously turned on to pull up the potential of the fifth node M to the potential of the first high potential line, thereby improving working reliability.

[0076] Please continue reading Figure 1 The gate driving unit further includes a reset transistor T15, a control end of the reset transistor T15 is configured to receive a reset control signal Ctr, an input end of the reset transistor T15 is electrically connected to the first high potential line, and an output end of the reset transistor T15 is electrically connected to the first node K.

[0077] Optionally, the reset transistor T15 is configured to be enabled when the display device is powered on and / or during a blanking interval.

[0078] Optionally, each of the transistors may be one of an N-channel transistor and a P-channel transistor. The semiconductor of each of the transistors may be one of a silicon semiconductor and an oxide semiconductor.

[0079] Optionally, in some embodiments, the first transistor T28, the third transistor T30, the fifth transistor T10, the sixth transistor T13, the ninth transistor T1, the eleventh transistor T14, the twelfth transistor T4, the fourteenth transistor T17 and the sixteenth transistor T21 are N-channel transistors, and the other transistors are P-channel transistors.

[0080] In some embodiments, such as Figure 2 As shown, when the first frequency-division control signal NLF is at a high potential, the signal of the first node K is at a low potential to turn on the second transistor T29 and turn off the first transistor T28, the signal of the second node P[q] is at a high potential to turn off the third transistor T30, the signal of the third node W is at a high potential to turn off the fourth transistor T9, and the signal of the fourth node G is at a high potential to turn on the fifth transistor T10. The fifth transistor T10 outputs the signal in the first low potential line as the first gate control signal Nscan[q], so that the first gate control signal Nscan[q] is at an active low potential, i.e., VGL.

[0081] It should be noted that the first frequency division control signal NLF is at a high potential, i.e., VGH, to indicate that the frequency division function is enabled. Since the gate of the third transistor T30 is at a high potential at the second node P[q] and the source of the third transistor T30 is at a high potential at the fourth node G, the gate-source voltage difference, i.e., Vgs, of the third transistor T30 is not greater than its threshold voltage. Therefore, the third transistor T30 is turned off.

[0082] In some embodiments, such as Figure 3 As shown, when the first frequency-division control signal NLF is at a low potential, i.e., VGL, the signal of the first node K is at a low potential to turn on the second transistor T29 and turn off the first transistor T28, the signal of the second node P[q] is at a high potential to turn on the third transistor T30, the signal of the fourth node G is at a low potential to turn off the fifth transistor T10, and the signal of the third node W is at a low potential to turn on the fourth transistor T9. The fourth transistor T9 outputs the signal in the second high potential line as the first gate control signal Nscan[q], so that the first gate control signal Nscan[q] is at an active high potential, i.e., VGH.

[0083] The second gate control signal Pscan[q] outputs a negative pulse during a period when the signal at the first node K is at a low potential.

[0084] It should be noted that the first frequency division control signal NLF is at a low potential, i.e., VGL, which indicates that the frequency division function is turned off. Since the gate of the third transistor T30 is at a high potential of the second node P[q] and the source of the third transistor T30 is at a low potential of the fourth node G, the gate-source voltage difference, i.e., Vgs, of the third transistor T30 is greater than its threshold voltage. Therefore, the third transistor T30 is turned on.

[0085] In some embodiments, such as Figure 2 、 Figure 3 As shown, the signal of the first node K is at a high potential to turn on the first transistor T28 and turn off the second transistor T29; the second node P[q] is at a low potential to turn off the third transistor T30; the fourth node G is at a high potential to turn on the fifth transistor T10, and the fifth transistor T10 outputs the signal in the first low potential line as the first gate control signal Nscan[q], so that the first gate control signal Nscan[q] is at an active low potential, i.e., VGL.

[0086] It should be noted that, when the signal at the first node K is at a high potential, the first transistor T28 can control the fifth transistor T10 to normally output an active low potential, namely, VGL.

[0087] In some embodiments, the present embodiment provides a display panel, which includes the above-mentioned gate driving circuit.

[0088] It can be understood that since the display panel provided in this embodiment includes the above-mentioned gate drive circuit, it is also possible to add a voltage regulation module 14 linked to the first frequency division control line between the first node K and the first output module 13, and select the signal in the first low-potential line or the signal in the first frequency division control line according to the signal of the first node K and the signal of the second node P[q] to be transmitted to the fourth node G, so that during the partitioned frequency division display, the first frequency division control line can control the potential of the first node K through the first frequency division module 12, and then control the first output module 13 to output the signal of the first low-potential line as the first gate control signal Nscan[q] through the voltage regulation module 14. Compared with the case where the first low-potential line cannot output an active low potential as the first gate control signal Nscan[q] through the first output module 13 during the partitioned frequency division display, the low potential of the first gate control signal Nscan[q] is in a floating state (Floating), that is, a passive low potential, thereby improving the stability of the first gate control signal Nscan[q] during the partitioned frequency division display.

[0089] In some embodiments, the display panel further includes a plurality of sub-pixels distributed in an array.

[0090] like Figure 4 As shown, each sub-pixel includes a light-emitting device Di and a pixel driving circuit for driving the light-emitting device Di to emit light. The pixel driving circuit includes a driving transistor Tdr and a writing transistor Tda.

[0091] Optionally, the light emitting device Di may be an organic light emitting diode, a sub-millimeter light emitting diode, a micro light emitting diode, etc.

[0092] The driving transistor Tdr is electrically connected to the light emitting device Di between a first voltage terminal Vdd and a second voltage terminal Vss. The driving transistor Tdr is configured to generate a driving current to drive the light emitting device Di to emit light.

[0093] Optionally, the input terminal of the driving transistor Tdr is electrically connected to the first voltage terminal Vdd, the output terminal of the driving transistor Tdr is electrically connected to the anode of the light-emitting device Di, the cathode of the light-emitting device Di is electrically connected to the second voltage terminal Vss, and the voltage supplied by the first voltage terminal Vdd is greater than the voltage supplied by the second voltage terminal Vss.

[0094] The write transistor Tda is configured to transmit a data signal to the control terminal of the drive transistor Tdr. The input terminal of the write transistor Tda is configured to receive the corresponding data signal DS. The output terminal of the write transistor Tda is electrically connected to the input terminal of the drive transistor Tdr. The control terminal of the write transistor Tda is connected to the second gate control signal Pscan[q] output by the qth-stage gate drive unit. This allows the frequency at which multiple sub-pixels refresh display data, enabling the display panel to implement a zoned, frequency-divided display design.

[0095] The sub-pixel also includes a compensation transistor Tc, the input end of the compensation transistor Tc is electrically connected to the output end of the driving transistor Tdr, the output end of the compensation transistor Tc is electrically connected to the control end of the driving transistor Tdr, and the control end of the compensation transistor Tc is configured to receive the first gate control signal Nscan[q] output by the q-th level gate driving unit.

[0096] The sub-pixel includes a reset transistor Tr, an input end of the reset transistor Tr is electrically connected to the reset line VLr, an output end of the reset transistor Tr is electrically connected to the control end of the drive transistor Tdr, and the control end of the reset transistor Tr is configured to receive the first gate control signal Nscan[q-3] output by the q-3 gate drive unit.

[0097] Optionally, the compensation transistor Tc and the reset transistor Tr are silicon transistors or oxide transistors, and are p-type transistors or q-type transistors. Optionally, to reduce leakage from the control terminal of the drive transistor Tdr to the output terminal of the drive transistor Tdr and the reset line VLr, the compensation transistor Tc and the reset transistor Tr are oxide transistors. To be compatible with existing process technologies, the compensation transistor Tc and the reset transistor Tr are q-type transistors. It will be appreciated that the active layer of the oxide transistor includes indium gallium zinc oxide, etc.

[0098] Please continue reading Figure 4 The sub-pixel further includes a first initial transistor Ti1, a second initial transistor Ti2, a first light emission control transistor Te1, a second light emission control transistor Te2 and a storage capacitor Cst.

[0099] The input terminal of the first initial transistor Ti1 is configured to receive the first initial signal transmitted by the first initial line VL1, the output terminal of the first initial transistor Ti1 is electrically connected to the anode of the light emitting device Di, and the control terminal of the first initial transistor Ti1 is configured to receive the gate driving signal Pscan2.

[0100] An input terminal of the first light emission control transistor Te1 is electrically connected to the first voltage terminal Vdd, and an output terminal of the first light emission control transistor Te1 is electrically connected to an input terminal of the driving transistor Tdr.

[0101] The input end of the second light-emitting control transistor Te2 is electrically connected to the output end of the driving transistor Tdr, the output end of the second light-emitting control transistor Te2 is electrically connected to the anode of the light-emitting device Di, and the control end of the second light-emitting control transistor Te2 is electrically connected to the control end of the first light-emitting control transistor Te1 and is connected to the light-emitting control signal EM.

[0102] The input end of the second initial transistor Ti2 is configured to receive the second initial signal transmitted by the second initial line VL2, the output end of the second initial transistor Ti2 is electrically connected to the output end of the first light emitting control transistor Te1 and the input end of the driving transistor Tdr, and the control end of the second initial transistor Ti2 is configured to receive the gate driving signal Pscan2.

[0103] A first terminal of the storage capacitor Cst is electrically connected to the first voltage terminal Vdd, and a second terminal of the storage capacitor Cst is electrically connected to the control terminal of the driving transistor Tdr.

[0104] Optionally, the sub-pixel further includes a bootstrap capacitor Cboost, a first end of the bootstrap capacitor Cboost is electrically connected to the control end of the data transistor Tda, and a second end of the bootstrap capacitor Cboost is electrically connected to the control end of the driving transistor Tdr.

[0105] Figure 5 for Figure 4 The timing diagram of the sub-pixel shown in the figure. The working stages of each frame of the sub-pixel include:

[0106] The first stage: the light-emitting control signal EM is at a high potential, and the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are both turned off; the gate drive signal Pscan2 is at a low potential, turning on the first initial transistor Ti1 and the second initial transistor Ti2, and the first initial signal transmitted by the first initial line VL1 initializes the anode potential of the light-emitting device Di, and the second initial signal transmitted by the second initial line VL2 initializes the input potential of the driving transistor Tdr.

[0107] The second stage: the light-emitting control signal EM is at a high potential, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are both turned off; Nscan[q-3] is at a high potential, the reset transistor Tr is turned on, and the signal in the reset line VLr resets the gate potential of the driving transistor Tdr; Nscan[q] is at a low potential, and the compensation transistor Tc is turned off.

[0108] The third stage: the light-emitting control signal EM is at a high potential, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are both turned off; Nscan[q-3] is at a high potential, the reset transistor Tr is turned on, and the signal in the reset line VLr resets the gate potential of the driving transistor Tdr; Nscan[q] is at a high potential, the compensation transistor Tc is turned on, and the signal in the reset line VLr synchronously resets the potential of the source and / or drain of the driving transistor Tdr.

[0109] The fourth stage: the light-emitting control signal EM is at a high potential, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are both turned off; Nscan[q-3] is at a low potential, the reset transistor Tr is turned off; Nscan[q] is at a high potential, the compensation transistor Tc is turned on; Pscan[q] is at a low potential, wherein the write transistor Tda in the n-th row sub-pixel is turned on, and then, Pscan[q+1] is at a low potential, wherein the write transistor Tda in the n+1-th row sub-pixel is turned on, and the data signal DS passes through the write transistor Tda, the drive transistor Tdr and the compensation transistor Tc to the gate of the drive transistor Tdr.

[0110] The fifth stage: the light-emitting control signal EM is at a high potential, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are both turned off; the gate drive signal Pscan2 is at a low potential, the first initial transistor Ti1 and the second initial transistor Ti2 are turned on, the first initial signal transmitted by the first initial line VL1 initializes the anode potential of the light-emitting device Di, and the second initial signal transmitted by the second initial line VL2 initializes the input potential of the driving transistor Tdr.

[0111] The sixth stage: the light-emitting control signal EM is at a low potential, the first light-emitting control transistor Te1 and the second light-emitting control transistor Te2 are both turned on; Nscan[q-3] is at a low potential, the reset transistor Tr is turned off; Nscan[q] is at a low potential, the compensation transistor Tc is turned off; Pscan[q] is at a high potential, the write transistor Tda is turned off; the light-emitting device Di starts to emit light.

[0112] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0113] The above is a detailed introduction to the gate drive circuit and display panel provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A gate drive circuit, characterized in that: The gate driving circuit includes a plurality of cascaded gate driving units, each of which includes: a node control module, the node control module being electrically connected to the first clock line, the first control line, the first low-potential line, the first high-potential line, the first node, and the second node, and being configured to control the first low-potential signal in the first low-potential line or the first high-potential signal in the first high-potential line to be transmitted to the first node according to the signal in the first control line and the first clock signal in the first clock line, and to control the first low-potential signal or the first high-potential signal to be transmitted to the second node according to the signal in the first node; a first frequency division module, the first frequency division module being electrically connected to the first frequency division control line, the first node, the second node, and the third node, and being configured to control the transmission of the signal of the first node to the third node according to the first frequency division control signal in the first frequency division control line and the signal of the second node; a first output module, the first output module being connected to the third node, the fourth node, the first low-potential line, and the second high-potential line, and being configured to output at least one of the signal of the first low-potential line and the signal of the second high-potential line as a first gate control signal according to the signal of the third node and the signal of the fourth node; A voltage regulation module, which is electrically connected to the first node, the second node, the fourth node, the first low-potential line and the first frequency-division control line, and is configured to select a signal in the first low-potential line or a signal in the first frequency-division control line and transmit it to the fourth node based on a signal of the first node and a signal of the second node.

2. The gate drive circuit according to claim 1, wherein: The voltage regulation module includes: a first regulating unit, the first regulating unit being electrically connected to the first node and the fourth node and configured to control the signal of the first node to be transmitted to the fourth node according to the signal of the first node; a second regulating unit, the second regulating unit being electrically connected to the first node, the fourth node, and the first frequency-dividing control line, and being configured to control the signal of the first frequency-dividing control line to be transmitted to the fourth node according to the signal of the first node; The third regulating unit is electrically connected to the second node, the fourth node and the first low-potential line, and is configured to control the signal of the first low-potential line to be transmitted to the fourth node according to the signal of the second node.

3. The gate drive circuit according to claim 2, wherein: The first regulating unit includes a first transistor, a first electrode of the first transistor is electrically connected to the gate of the first transistor and the first node, and a second electrode of the first transistor is electrically connected to the fourth node.

4. The gate driving circuit according to claim 3, wherein: The second regulating unit includes a second transistor, a first electrode of the second transistor is electrically connected to the first frequency division control line, a second electrode of the second transistor is electrically connected to the fourth node, and a gate of the second transistor is electrically connected to the first node; A channel type of the second transistor is different from a channel type of the first transistor.

5. The gate driving circuit according to claim 4, wherein: The third regulating unit includes a third transistor, a first electrode of the third transistor is electrically connected to the first low potential line, a second electrode of the third transistor is electrically connected to the fourth node, and a gate of the third transistor is electrically connected to the second node; A channel type of the third transistor is the same as a channel type of the first transistor.

6. The gate driving circuit according to claim 5, wherein: The first output module includes: a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to the third node, and a gate of the fourth transistor is electrically connected to the second high potential line; a fifth transistor, wherein a first electrode of the fifth transistor is electrically connected to the second electrode of the fourth transistor and is configured to output the first gate control signal, a second electrode of the fifth transistor is electrically connected to the first low potential line, and a gate of the fifth transistor is electrically connected to the fourth node; The channel type of the fourth transistor is different from the channel type of the fifth transistor, and the channel type of the fourth transistor is the same as the channel type of the second transistor.

7. The gate driving circuit according to claim 6, wherein: When the signal of the first frequency division control line is at a high potential, the signal of the first node is at a low potential to turn on the second transistor, the signal of the fourth node is at a high potential to turn on the fifth transistor, and the signal of the third node is at a high potential to turn off the fourth transistor. The fifth transistor outputs the signal in the first low potential line as the first gate control signal.

8. The gate driving circuit according to claim 7, wherein: The signal of the first node is at a low level to turn off the first transistor, and the signal of the second node is at a high level to turn off the third transistor.

9. The gate driving circuit according to claim 6, wherein: When the signal of the first frequency division control line is at a low potential, the signal of the first node is at a low potential to turn on the second transistor, the signal of the fourth node is at a low potential to turn off the fifth transistor, and the signal of the third node is at a low potential to turn on the fourth transistor. The fourth transistor outputs the signal in the second high potential line as the first gate control signal.

10. The gate driving circuit according to claim 9, wherein: The signal of the first node is at a low level to turn off the first transistor, and the signal of the second node is at a high level to turn on the third transistor.

11. The gate driving circuit according to claim 6, wherein: The signal of the first node is at a high potential to turn on the first transistor and turn off the second transistor; the second node is at a low potential to turn off the third transistor; the fourth node is at a high potential to turn on the fifth transistor, and the fifth transistor outputs the signal in the first low potential line as the first gate control signal.

12. The gate drive circuit according to any one of claims 1 to 11, characterized in that: The gate drive circuit further includes: a second frequency division module, the second frequency division module being electrically connected to a second frequency division control line, the first node, the second node, and a fifth node, and being configured to control the transmission of the signal of the first node to the fifth node according to a second frequency division control signal in the second frequency division control line and a signal of the second node; A second output module, the second output module is electrically connected to the second node, the fifth node, the second node of the q-2-th level gate driving unit, the second clock line, the first high potential line and the second gate control line, and is configured to output the second gate control signal in the second gate control line according to the signal of the second node, the signal of the fifth node, the signal of the second node of the q-2-th level gate driving unit, the second clock signal in the second clock line, and the first high potential signal in the first high potential line.

13. The gate driving circuit according to claim 12, wherein: The gate drive circuit also includes a third output module, which is electrically connected to the second node, the fifth node, the second node of the q-2th level gate drive unit, the third clock line, the first high potential line and the third gate control line, and is configured to output the third gate control signal in the third gate control line according to the signal of the second node, the signal of the fifth node, the signal of the second node of the q-2th level gate drive unit, the third clock signal in the third clock line, and the first high potential signal in the first high potential line.

14. A display panel, characterized in that: The display panel includes the gate driving circuit according to any one of claims 1 to 13.

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