Display panel, display driving method and display device

Abstract

The present application belongs to the field of display driving technology, and specifically relates to a display panel, a display driving method and a display device, wherein the display panel includes N rows of scan lines, M columns of data lines and (N‑1) rows × M columns of pixel circuits; each pixel circuit includes a pixel unit and a control unit, and the control unit is used to charge the pixel unit through the data signal on the data line when it is in the on state; in the n-th row pixel circuit: the control end of the 2i‑1 column control unit is connected to the n-th row scan line, and the control end of the 2i column control unit is connected to the n+1-th row scan line; or, the control end of the 2i‑1 column control unit is connected to the n+1-th row scan line, and the control end of the 2i column control unit is connected to the n-th row scan line; the present application controls adjacent pixel units in the same row of pixel circuits through scan lines of different rows, performs mixed charging in units of sub-pixels in the HSR mode, and splits the mixed charging row into two adjacent rows to achieve a more delicate display effect.

Description

Technical Field

[0001] The present disclosure belongs to the field of display driving technology, and particularly relates to a display panel, a display driving method, and a display device. Background Art

[0002] With the rapid development of HSR (Hardware Super Resulation) technology, users have increasingly higher requirements for HSR technology displays, which also puts higher demands on HSR display circuits. The principle of HSR technology is to charge odd rows with normal data, and even rows with the previous row's data in the first half of the row and the next row's data in the second half of the row. Through this mixed charging method, the amount of data required for a frame is halved, achieving the effect of doubling the refresh rate while keeping the total data volume unchanged.

[0003] Since the traditional HSR display circuit performs mixed charging in units of rows, the display effect is reduced. Summary of the Invention

[0004] The present application provides a display panel, a display driving method and a display device, which solve the problem of poor picture display effect. The present application controls adjacent pixel units in the same row of pixel circuits through different rows of scan lines, performs mixed charging on a sub-pixel basis in HSR mode, and splits a mixed charging row into two adjacent rows to achieve a more delicate display effect.

[0005] In a first aspect, the present application provides a display panel, which includes: N rows of scan lines, M columns of data lines and (N-1) rows × M columns of pixel circuits; each pixel circuit includes a pixel unit and a control unit, the control unit including a control end, a first connection end and a second connection end; the first connection end of each control unit is electrically connected to the data line of the corresponding column, and the second connection end of each control unit is connected to the input end of the corresponding pixel unit; the control unit is used to charge the pixel unit through the data signal on the data line when it is in a conductive state; in the nth row pixel circuit: the control end of the 2i-1th column control unit is connected to the nth row scan line, and the control end of the 2i column control unit is connected to the n+1th row scan line; or, the control end of the 2i-1th column control unit is connected to the n+1th row scan line, and the control end of the 2i column control unit is connected to the nth row scan line; wherein i = [1, 2, 3, ..., M], n = [1, 2, ..., N-1], and N and M are both positive integers greater than 1.

[0006] Optionally, the control unit includes: N rows of scan lines, M columns of data lines and (N-1) rows × M columns of pixel circuits; each pixel circuit includes a pixel unit and a control unit, the control unit includes a control terminal, a first connection terminal and a second connection terminal; the first connection terminal of each control unit is electrically connected to the data line of the corresponding column, and the second connection terminal of each control unit is connected to the input terminal of the corresponding pixel unit; the control unit is used to charge the pixel unit through the data signal on the data line when it is in the on state; in the pixel circuit of the nth row: the 3i-2th column, the 3i-1th column and the control ends of the 3i-th column control unit are respectively connected to the n-th row scan line, and the control ends of the 3i+1-th column, 3i+2-th column and 3i+3-th column control units are respectively connected to the n+1-th row scan line; or the control ends of the 3i-2-th column, 3i-1-th column and 3i-th column control units are respectively connected to the n+1-th row scan line, and the control ends of the 3i+1-th column, 3i+2-th column and 3i+3-th column control units are respectively connected to the n-th row scan line; wherein, i = [1, 2, 3, ..., M], n = [1, 2, ..., N-1], and N and M are both positive integers greater than 1.

[0007] Optionally, the data line in the 2i-1th column outputs a corresponding data signal during the 2j-1th row scan start time period, and the data line in the 2ith column outputs a corresponding data signal during the 2jth row scan start time period;

[0008] Optionally, during the 2j-1 row scan start time period, the 3i-2 column, 3i-1 column, and 3i column data lines output corresponding data signals, and during the 2j row scan start time period, the 3i+1 column, 3i+2 column, and 3i+3 column data lines output corresponding data signals;

[0009] Optionally, the pixel unit in the 3m-2th column is a first color sub-pixel, the pixel unit in the 3m-1th column is a second color sub-pixel, and the pixel unit in the 3mth column is a third color sub-pixel; wherein,

[0010] Optionally, the control unit includes: a switching transistor, a gate of the switching transistor serves as a control terminal of the control unit, a first terminal of the switching transistor is connected to the data line, and a second terminal of the switching transistor is connected to the pixel unit.

[0011] Optionally, the pixel unit includes: a liquid crystal capacitor, and a pixel electrode of the liquid crystal capacitor is connected to the second end of the switch transistor.

[0012] Optionally, the pixel unit includes: a storage capacitor, a driving transistor and a light-emitting diode; the first end of the storage capacitor is connected to the second connection end of the control unit, the second end of the storage capacitor is connected to the power supply end, the control end of the driving transistor is connected to the first end of the storage capacitor, the first end of the driving transistor is connected to the second end of the storage capacitor, the anode of the light-emitting diode is connected to the second end of the driving transistor, and the cathode of the light-emitting diode is grounded.

[0013] In the second aspect, the present application provides a display driving method applied to a display panel, the display driving method comprising: obtaining a connection method between each control unit in the display panel and a scan line; generating a target data signal according to the connection method, so that in the HSR mode, the target data signal drives the display panel to perform mixed charging in units of sub-pixels.

[0014] In a second aspect, the present application provides a display device, comprising: a gate drive circuit for outputting a scan signal; a source drive circuit for outputting a data signal; and a display panel, wherein the scan line of the display panel is connected to the gate drive circuit, and the data line of the display panel is connected to the source drive circuit.

[0015] The technical solution provided by this application has at least the following beneficial effects:

[0016] This application controls adjacent pixel units in the same row of pixel circuits through different rows of scan lines, performs mixed charging on a sub-pixel basis in HSR mode, and splits a mixed charging row into two adjacent rows to achieve a more delicate display effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0018] Figure 1 The figure shows a schematic diagram of the HSR charging architecture in the related art.

[0019] Figure 2 The figure shows a schematic diagram of the data providing method of the HSR signal source in the related art.

[0020] Figure 3 Shown is a schematic structural diagram of a first display panel provided in an embodiment of the present application.

[0021] Figure 4Shown is a schematic structural diagram of a second display panel provided in an embodiment of the present application.

[0022] Figure 5 The figure shows a schematic diagram of the way in which a signal source provides data in a normal mode provided by an embodiment of the present application.

[0023] Figure 6 Shown is a normal mode charging timing diagram provided in an embodiment of the present application.

[0024] Figure 7 The figure shows a schematic diagram of the way in which a signal source provides data in the first HSR mode provided in an embodiment of the present application.

[0025] Figure 8 The figure shows a HSR mode charging timing diagram provided in an embodiment of the present application.

[0026] Figure 9 Shown is a schematic diagram of the first HSR charging architecture provided in an embodiment of the present application.

[0027] Figure 10 Shown is a schematic structural diagram of a third display panel provided in an embodiment of the present application.

[0028] Figure 11 Shown is a schematic structural diagram of a fourth display panel provided in an embodiment of the present application.

[0029] Figure 12 The figure shows a schematic diagram of the way in which the signal source provides data in the second HSR mode provided in an embodiment of the present application.

[0030] Figure 13 Shown is a schematic diagram of the second HSR charging architecture provided in an embodiment of the present application.

[0031] Figure 14 Shown is a circuit diagram of a pixel circuit provided in an embodiment of the present application.

[0032] Figure 15 The figure is a flow chart of a display driving method provided in an embodiment of the present application.

[0033] Description of reference numerals:

[0034] 100, display panel; 110, scan line; 120, data line; 130, pixel circuit; 131, control unit; 132, pixel unit;

[0035] T1, switching transistor; T2, driving transistor; Cc, storage capacitor; Cs, pixel capacitor; Ct, energy storage capacitor; OLED, light-emitting diode. DETAILED DESCRIPTION

[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art.

[0037] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner.In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps etc. can be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0038] The present application is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0039] The inventors have found that the HSR charging architecture and the HSR signal source in the related art provide data in the following ways: Figure 1 and Figure 2 As shown, the odd rows are charged with normal data, the even rows are charged with the previous row data in the first half of the row time, and the next row data in the second half of the row time. This hybrid charging method reduces the amount of data required for a frame by half, and achieves the effect of doubling the refresh rate without changing the total amount of data. However, hybrid charging in rows will result in a rough effect when displaying images with more prominent details. Figure 1 The “original” in the figure refers to the original data provided by the signal source, and the “mixed” refers to the mixture of the previous row of data and the next row of data.

[0040] In order to solve the above problems, the present application provides a display panel, which specifically includes the following embodiments:

[0041] Figure 3 FIG. 1 is a schematic structural diagram of a first display panel provided in an embodiment of the present application; FIG. Figure 3 As shown, the display panel 100 includes: N rows of scan lines 110, M columns of data lines 120, and pixel circuits 130 arranged in an array; wherein the number of columns of the pixel circuits 130 is M, and the number of rows is N-1; that is, the number of columns of the pixel circuits 130 in the display panel 100 is the same as the number of data lines 120, and the number of rows of the pixel circuits 130 is one row less than the number of scan lines 110. Figure 3The scan lines 110 and data lines 120 in FIG. 1 cross but are not connected. Figure 3 In the figure, G1, G2, G3, G4 and GN respectively represent the first row scan line 110, the second row scan line 110, the third row scan line 110, the fourth row scan line 110 and the Nth row scan line 110, and S1, S2, ..., SM respectively represent the first column data line 120, the second data line 120 and the Mth column data line 120.

[0042] In one embodiment, each pixel circuit 130 includes a pixel unit 132 and a control unit 131. The control unit 131 is used to input the data signal on the data line 120 into the pixel unit 132 when it is in a conductive state, thereby charging the pixel unit 132 through the data signal on the data line 120; on the contrary, when the control unit 131 is in an off state (i.e., a non-conductive state), the data signal on the data line 120 cannot be input into the pixel unit 132, thereby not charging the pixel unit 132; it should be noted that the display panel 100 can be a liquid crystal display (LCD) or an OLED (Organic Light-Emitting Diode) display; when the display panel 100 is a liquid crystal display, the pixel unit 132 includes liquid crystal molecules; when the display panel 100 is an OLED display, the pixel unit 132 includes a light-emitting diode.

[0043] like Figure 3 As shown, the control unit 131 includes a control end, a first connection end and a second connection end; the first connection end of each control unit 131 is electrically connected to the data line 120 of the corresponding column, and the second connection end of each control unit 131 is connected to the input end of the corresponding pixel unit.

[0044] like Figure 3 As shown, in the n-th row pixel circuit 130 , the control end of the 2i-1-th column control unit 131 is connected to the n-th row scan line 110 , and the control end of the 2i-th column control unit 131 is connected to the n+1-th row scan line 110 .

[0045] It should be noted that in this embodiment, n and i are variables, N and M are constants, the value range of the variable n is 1 to N-1, the value range of the variable i is 1 to M, and both N and M are positive integers greater than 1. In this embodiment, for the n-th row of pixel circuits 130, the control end of the odd-numbered column control unit 131 is connected to the n-th row of scan line 110, and the control end of the even-numbered column control unit 131 is connected to the n+1-th row of scan line 110. For example: for the 1st row of pixel circuits 130, the control ends of the 1st column control unit 131, the 3rd column control unit 131, the 5th column control unit 131, ..., the M-1th column control unit 131 are respectively connected to the 1st row of scan line 110, and the control ends of the 2nd column control unit 131, the 4th column control unit 131, the 6th column control unit 131, ..., the Mth column control unit 131 are respectively connected to the 2nd row of scan line 110.

[0046] Figure 4 The figure shows a structural schematic diagram of the second display panel provided in an embodiment of the present application. In this embodiment, the control end of the 2i-1 column control unit 131 is connected to the n+1 row scan line 110, and the control end of the 2i column control unit 131 is connected to the n row scan line 110.

[0047] It should be noted that Figure 3 and Figure 4 The similarity is that the control terminals of the control units 131 of the adjacent column pixel circuits 130 are connected to different scan lines 110 respectively. The difference is that for the n-th row pixel circuit 130, Figure 3 The odd columns in the nth row are connected to the scan line 110, Figure 4 In contrast, the display panel 100 connected to the (n+1)th row of scan lines 110 has the same other structures as those of the display panel 100 and will not be described in detail herein.

[0048] against Figure 3 and Figure 4 The pixel architecture is compatible with both normal mode and HSR mode. Figure 3 Let’s take this as an example to explain:

[0049] 1. In normal mode, the data signal gives data in the following way Figure 5 As shown, the normal mode charging timing is as follows Figure 6 As shown, during the period when the nth row of scan lines 110 is turned on, each column of data lines 120 outputs a corresponding data signal, that is, the signal source provides data with a resolution of M×N, and the image is displayed normally. The horizontal scan lines 110 are charged one by one, and the sub-pixels connected to them are turned on for charging in turn. In normal mode, the sub-pixels connected to each scan line 110 have corresponding data for charging, as shown in FIG. Figure 6As shown, for a column of sub-pixels in the panel, the sub-pixels connected to the scan lines 110 such as G1, G2, G3, ... have one-to-one corresponding data.

[0050] 2. In HSR mode, the data signal gives the data in the following way Figure 7 As shown, the HSR mode charging timing is as follows Figure 8 As shown, the data line 120 in the 2i-1 column outputs the corresponding data signal during the 2j-1 row scan start time period, and the data line 120 in the 2i column outputs the corresponding data signal during the 2j row scan start time period; in the HSR mode, only the sub-pixels connected to the odd-numbered scan lines 110 have the corresponding data, and the sub-pixels connected to the even-numbered scan lines 110 can only charge themselves with the data of the sub-pixels in the two rows before and after the same column, as shown in FIG. Figure 8 As shown, only the sub-pixels connected to G1, G3, G5... have corresponding data, while the sub-pixels connected to G2, G4, G6... do not, so the resulting display is as follows Figure 9 As shown, mixed charging is performed in sub-pixels, and one mixed-charged row is split into two adjacent rows to achieve a more delicate display effect.

[0051] It should also be noted that due to Figure 6 Only one row of sub-pixels is effectively charged at the same time. Figure 8 At the same time, two rows of sub-pixels can be effectively charged at the same time, so for one frame of picture, Figure 8 Charging time is only Figure 6 half, in the same amount of time, Figure 8 The frame refresh rate reaches Figure 6 twice as much.

[0052] In summary, the display panel 100 provided in this embodiment has at least the following beneficial effects:

[0053] In the present application, adjacent pixel units in the same row of pixel circuits 130 are controlled by different rows of scan lines 110, mixed charging is performed in units of sub-pixels in the HSR mode, and a mixed charging row is split into two adjacent rows to achieve a more delicate display effect.

[0054] Figure 10 FIG. 1 is a schematic diagram showing the structure of a third display panel provided in an embodiment of the present application. Figure 10 As shown, in the n-th row pixel circuit 130: the control ends of the 3i-2th column, 3i-1th column and 3i-th column control units 131 are respectively connected to the n-th row scan line 110, and the control ends of the 3i+1th column, 3i+2th column and 3i+3th column control units 131 are respectively connected to the n+1th row scan line 110.

[0055] Figure 11 FIG. 1 is a schematic structural diagram of a fourth display panel provided in an embodiment of the present application. Figure 11 As shown, in the n-th row pixel circuit 130: the control ends of the 3i-2th column, 3i-1th column and 3i-th column control units 131 are respectively connected to the n+1th row scan line 110, and the control ends of the 3i+1th column, 3i+2th column and 3i+3th column control units 131 are respectively connected to the n-th row scan line 110.

[0056] It should be noted that Figure 10 and Figure 11 The similarities are that the sub-pixels controlled by one scan line 110 present a rule of alternating up and down in units of three sub-pixels (ie one pixel), and the difference is that for the n-th row pixel circuit 130, Figure 10 The three sub-pixels in are connected to the n-th row scanning line 110, Figure 11 In contrast, the display panel 100 connected to the (n+1)th row of scan lines 110 has the same other structures as those of the display panel 100 and will not be described in detail herein.

[0057] It should be noted that Figure 10 In normal mode, the data source output mode, charging sequence and display screen are the same as Figure 3 The data source output mode in HSR mode is as follows: Figure 12 As shown, in the 2j-1 row scanning start time period, the 3i-2 column, 3i-1 column and 3i column data lines 120 output corresponding data signals, and in the 2j row scanning start time period, the 3i+1 column, 3i+2 column and 3i+3 column data lines 120 output corresponding data signals, and the display screen is as shown. Figure 13 shown.

[0058] In this embodiment, three pixel units in the same row of pixel circuits 130 are controlled by different rows of scan lines 110, and mixed charging is performed in units of three sub-pixels in the HSR mode. The mixed charging row is split into two adjacent rows to achieve a more delicate display effect.

[0059] for Figure 3 and Figure 10 By comparing the embodiments of Figure 3 Examples and Figure 10 Each embodiment has its own advantages and disadvantages. Figure 3 The embodiment is a sub-pixel HSR solution, the display effect is better than Figure 10 The embodiment is more delicate, but color shift may occur in some special cases; Figure 10 The embodiment is a pixel-level HSR solution, which will not cause color shift, but the display effect will be worse than Figure 3 The examples are slightly rougher; it can be seen that the Figure 3Examples and Figure 10 The embodiments can be applied to different application scenarios and different screen requirements.

[0060] In one embodiment, the pixel units in the 3m-2th column are first color sub-pixels, the pixel units in the 3m-1th column are second color sub-pixels, and the pixel units in the 3mth column are third color sub-pixels; wherein,

[0061]

[0062] It should be noted that in the above embodiments, color mixing is performed between two adjacent rows of pixels. In order to prevent the problem of color mixing of pixels of different colors, the colors of the pixel units in the same column are the same; the first color sub-pixel, the second color sub-pixel and the third color sub-pixel represent red sub-pixels, green sub-pixels and blue sub-pixels respectively.

[0063] In one embodiment of the present application, Figure 14 As shown, the control unit 131 includes: a switching transistor T1, the gate of the switching transistor serves as the control end of the control unit 131, the first end of the switching transistor T1 is connected to the data line 120, and the second end of the switching transistor T1 is connected to the pixel unit.

[0064] Figure 14 14a is a circuit diagram of the first pixel unit provided in an embodiment of the present application, wherein the pixel unit 132 includes: a storage capacitor Cc, a driving transistor T2 and a light-emitting diode OLED, wherein the first end of the storage capacitor Cc is connected to the output end Vo of the control unit 131, and the second end of the storage capacitor Cc is connected to the power supply end VDD; the control end of the driving transistor T2 is connected to the first end of the storage capacitor Cc, and the first end of the driving transistor T2 is connected to the second end of the storage capacitor Cc; the anode of the light-emitting diode OLED is connected to the second end of the driving transistor T2, and the cathode of the light-emitting diode OLED is grounded VSS.

[0065] In this embodiment, when the switch transistor T1 is in the on state, the storage capacitor Cc is charged by the data signal on the data line 120, and under the action of the driving voltage output by the power supply end, the driving transistor T2 outputs a corresponding driving current to drive the light emitting diode OLED to emit light.

[0066] Figure 1414b is a circuit diagram of the second pixel unit provided in an embodiment of the present application, wherein the pixel unit 132 includes: a liquid crystal capacitor, wherein the pixel electrode of the liquid crystal capacitor is connected to the second end of the switching transistor T1; wherein the liquid crystal capacitor Cs is generally formed by a pixel electrode, a common electrode, and liquid crystal molecules between the pixel electrode and the common electrode, and data signals of different sizes are applied to the pixel electrode to rotate the liquid crystal molecules to different angles, thereby realizing brightness adjustment of the pixel unit 132.

[0067] In this embodiment, the pixel unit 132 further includes an energy storage capacitor Ct, and the pixel electrode of the energy storage capacitor Ct is connected to the second end of the switch transistor T1 to maintain the charging voltage.

[0068] Figure 15 FIG. 1 is a flow chart of a display driving method provided by an embodiment of the present application; FIG. Figure 5 As shown, the display driving method applied to the display panel of the above embodiment specifically includes the following steps:

[0069] Step S100: Acquire the connection mode between each control unit and the scan line in the display panel.

[0070] Step S200 : generating a target data signal according to the connection mode, so that the target data signal drives the display panel to perform hybrid charging in units of sub-pixels in the HSR mode.

[0071] In this embodiment, the connection between each control unit and the scan line includes: Figure 3 、 Figure 4 、 Figure 10 and Figure 11 As shown, different connection methods correspond to different data sources giving data methods, that is, different data signals; when the connection method between each control unit and the scan line is determined, the corresponding target data signal can be obtained, so that the target data signal drives the display panel to perform mixed charging in units of sub-pixels to achieve a more delicate display effect; in addition, mixed charging in units of sub-pixels includes mixed charging in units of 1 sub-pixel and mixed charging in units of 3 sub-pixels.

[0072] As can be seen, the current industry optimization focus on HSR display technology is primarily on architectural compatibility. In reality, the HSR display effects of different products with the same architecture do not differ significantly. This solution, based on the principles of HSR technology, breaks through the constraints of traditional HSR technology by introducing a new data selection mode. Combined with a specific pixel architecture, this approach enables a new HSR display mode, significantly improving the technical issue of blurred details in traditional HSR display modes. Given similar panel materials and process levels, the display effect can theoretically reach industry-leading levels. Because this solution does not add additional hardware and its pixel architecture is uncomplicated, it does not increase production costs.

[0073] In one embodiment, the present application provides a display device, which includes: a gate driving circuit, a gate driving circuit and a display panel shown in the above embodiment; the gate driving circuit is used to output a scanning signal; the source driving circuit is used to output a data signal; the scanning line of the display panel is connected to the gate driving circuit, and the data line of the display panel is connected to the source driving circuit.

[0074] Furthermore, the terms "first," "second," "third," etc., are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first," "second," or "third" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0075] In the description of this specification, the reference terms "some embodiments", "exemplarily", etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0076] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent application.

Claims

1. A display panel, characterized in that: The display panel includes: N rows of scan lines, M columns of data lines and (N-1) rows×M columns of pixel circuits; Each pixel circuit includes a pixel unit and a control unit, the control unit including a control terminal, a first connection terminal, and a second connection terminal; the first connection terminal of each control unit is electrically connected to the data line of the corresponding column, and the second connection terminal of each control unit is connected to the input terminal of the corresponding pixel unit; the control unit is configured to charge the pixel unit through the data signal on the data line when in a conductive state; In the pixel circuit of the nth row: the control ends of the control units of the 3i-2th column, the 3i-1th column, and the 3ith column are respectively connected to the scan line of the nth row, and the control ends of the control units of the 3i+1th column, the 3i+2th column, and the 3i+3th column are respectively connected to the scan line of the n+1th row; or the control ends of the control units of the 3i-2th column, the 3i-1th column, and the 3ith column are respectively connected to the scan line of the n+1th row, and the control ends of the control units of the 3i+1th column, the 3i+2th column, and the 3i+3th column are respectively connected to the scan line of the nth row; Wherein, i=[1, 2, 3, ..., M], n=[1, 2, ..., N-1], and both N and M are positive integers greater than 1.

2. The display panel according to claim 1, wherein: During the 2j-1 row scan start time period, the 3i-2 column, 3i-1 column, and 3i column data lines output corresponding data signals, and during the 2j row scan start time period, the 3i+1 column, 3i+2 column, and 3i+3 column data lines output corresponding data signals; 3. The display panel according to claim 1, wherein: The pixel unit in the 3m-2th column is a first color sub-pixel, the pixel unit in the 3m-1th column is a second color sub-pixel, and the pixel unit in the 3mth column is a third color sub-pixel; wherein, 4. The display panel according to claim 3, wherein: The control unit comprises: A switching transistor, wherein the gate of the switching transistor serves as the control terminal of the control unit, a first terminal of the switching transistor is connected to the data line, and a second terminal of the switching transistor is connected to the pixel unit.

5. The display panel according to claim 4, wherein: The pixel unit includes: A liquid crystal capacitor, wherein a pixel electrode of the liquid crystal capacitor is connected to the second end of the switching transistor.

6. The display panel according to claim 4, wherein: The pixel unit includes: storage capacitor, driver transistor, and light-emitting diode; The first end of the storage capacitor is connected to the second connection end of the control unit, the second end of the storage capacitor is connected to the power supply end, the control end of the driving transistor is connected to the first end of the storage capacitor, the first end of the driving transistor is connected to the second end of the storage capacitor, the anode of the light-emitting diode is connected to the second end of the driving transistor, and the cathode of the light-emitting diode is grounded.

7. A display driving method, characterized in that: Applied to the display panel according to any one of claims 1 to 6, the display driving method comprises: Obtaining a connection mode between each control unit and a scan line in the display panel; A target data signal is generated according to the connection mode, so that in the HSR mode, the target data signal drives the display panel to perform hybrid charging in units of sub-pixels.

8. A display device, characterized in that: The display device comprises: A gate driving circuit for outputting a scanning signal; A source driving circuit, configured to output a data signal; The display panel according to any one of claims 1 to 6, wherein the scan lines of the display panel are connected to the gate drive circuit, and the data lines of the display panel are connected to the source drive circuit.

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