Display device

Abstract

The present disclosure relates to the technical field of display, and in particular to a display device, a display panel of the display device has pixel rows and scan line groups; each pixel row includes a plurality of switching transistors, each scan line group includes a first scan line electrically connected to odd-numbered switching transistors in the pixel row and a second scan line electrically connected to even-numbered switching transistors in the pixel row; a gate drive circuit includes a first sub-gate drive circuit electrically connected to the first scan line and a second sub-gate drive circuit electrically connected to the second scan line; the first sub-gate drive circuit is configured to load a first on-voltage or a first off-voltage to the first scan line; the second sub-gate drive circuit is configured to load a second on-voltage or a second off-voltage to the second scan line; the first on-voltage is different from the second on-voltage, and the first off-voltage is different from the second off-voltage; the display device can reduce the power consumption of the display panel and reduce the risk of transistor failure.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, in particular, to a display device. BACKGROUND

[0002] In the related art, a gate driving circuit (GOA) is used for driving, and the display panel is generally designed to have polarity inversion of a data control signal. At this time, based on the polarity inversion display mode of the display panel, the voltage loaded on the signal line connected with the gate driving circuit also needs to be adjusted synchronously between high and low voltage. In the case of a large high-low voltage difference, power loss is increased, and the transistor is prone to breakdown failure.

[0003] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0004] The purpose of the present disclosure is to overcome the shortcomings of the prior art, and to provide a display device that can reduce the power consumption of the display panel and reduce the risk of transistor failure.

[0005] According to one aspect of the present disclosure, a display device is provided, comprising a display panel having:

[0006] a plurality of pixel rows, each of which comprises a plurality of switch transistors arranged in a first direction in sequence and a sub-pixel electrically connected to the second end of the switch transistors one by one;

[0007] a plurality of scan line groups corresponding to the plurality of pixel rows one by one; each of the scan line groups comprises a first scan line electrically connected to the gate terminal of the odd-numbered switch transistor in the corresponding pixel row, and a second scan line electrically connected to the gate terminal of the even-numbered switch transistor in the corresponding pixel row;

[0008] a gate driving circuit comprising a first sub-gate driving circuit electrically connected to each of the first scan lines and a second sub-gate driving circuit electrically connected to each of the second scan lines;

[0009] The first sub-gate driving circuit is configured to load a first conduction voltage or a first turn-off voltage to the first scan line, the first conduction voltage being configured to turn on the electrically connected switch transistor, and the first turn-off voltage being configured to turn off the electrically connected switch transistor;

[0010] The second sub-gate driving circuit is configured to load a second turn-on voltage or a second turn-off voltage to the second scan line, the second turn-on voltage is configured to turn on the switch transistor electrically connected, and the second turn-off voltage is configured to turn off the switch transistor electrically connected.

[0011] The first turn-on voltage is different from the second turn-on voltage, and the first turn-off voltage is different from the second turn-off voltage.

[0012] In an embodiment of the present disclosure, the first turn-on voltage and the second turn-on voltage have the same timing, and the first turn-off voltage and the second turn-off voltage have the same timing.

[0013] In an embodiment of the present disclosure, at least one of an absolute value of a voltage difference between the first turn-on voltage and the second turn-off voltage and an absolute value of a voltage difference between the second turn-on voltage and the first turn-off voltage is greater than an absolute value of a voltage difference between the first turn-on voltage and the first turn-off voltage, and greater than an absolute value of a voltage difference between the second turn-on voltage and the second turn-off voltage.

[0014] In an embodiment of the present disclosure, the display panel has a plurality of sub-pixel regions arranged in an array;

[0015] The first scan line and the second scan line do not overlap with the sub-pixel region.

[0016] In an embodiment of the present disclosure, the first scan line and the second scan line are respectively located on two sides of the pixel row.

[0017] In an embodiment of the present disclosure, the display panel has a plurality of sub-pixel regions arranged in an array;

[0018] One of the first scan line and the second scan line overlaps with the sub-pixel region.

[0019] In an embodiment of the present disclosure, distances between the first scan line and the second scan line arranged adjacently are equal.

[0020] In an embodiment of the present disclosure, the display panel has an array substrate and a counter substrate, and has a liquid crystal layer located between the array substrate and the counter substrate;

[0021] The first scan line and the second scan line are located on the array substrate, and the counter substrate has a black matrix.

[0022] A normal projection of the black matrix on the liquid crystal layer covers a normal projection of the first scan line on the liquid crystal layer and covers a normal projection of the second scan line on the liquid crystal layer.

[0023] In one embodiment of the present disclosure, the display panel further comprises a first signal line group for controlling the first sub-gate driving circuit and a second signal line group for controlling the second sub-gate driving circuit.

[0024] The first sub-gate driving circuit outputs the first on-voltage or the first off-voltage according to a signal provided by the first signal line group; and the second sub-gate driving circuit outputs the second on-voltage or the second off-voltage according to a signal provided by the second signal line group.

[0025] In one embodiment of the present disclosure, the display device further comprises a driving module electrically connected with the first signal line group and the second signal line group.

[0026] The driving module is configured to, in a first working mode, load a first signal to the first signal line group and load a second signal to the second signal line group.

[0027] In a second working mode, load a third signal to the first signal line group and load a fourth signal to the second signal line group.

[0028] The voltage value of the first on-voltage output by the first sub-gate driving circuit according to the first signal is the same as the voltage value of the second on-voltage output by the second sub-gate driving circuit according to the fourth signal.

[0029] The voltage value of the first off-voltage output by the first sub-gate driving circuit according to the first signal is the same as the voltage value of the second off-voltage output by the second sub-gate driving circuit according to the fourth signal.

[0030] The voltage value of the first on-voltage output by the first sub-gate driving circuit according to the third signal is the same as the voltage value of the second on-voltage output by the second sub-gate driving circuit according to the second signal.

[0031] The voltage value of the first off-voltage output by the first sub-gate driving circuit according to the third signal is the same as the voltage value of the second off-voltage output by the second sub-gate driving circuit according to the second signal.

[0032] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, further serve to explain the principles of the disclosure. It is to be understood that the drawings are designed solely for purposes of illustration to be used in conjunction with the description in specifying the present embodiments. As such, other drawings, having different numbers and labels from those of the drawing figures being discussed, can represent other embodiments consistent with the present disclosure, which can be understood clearly and entirely by those skilled in the art from a study of the drawings, the disclosure, and the detailed description of the application.

[0034] Figure 1 For an embodiment of the present disclosure, a structural schematic diagram of a display device.

[0035] Figure 2 For an embodiment of the present disclosure, a structural schematic diagram of a display panel.

[0036] Figure 3 For an embodiment of the present disclosure, a schematic diagram of a display area and a non-display area.

[0037] Figure 4 For an embodiment of the present disclosure, a schematic diagram of a part of structure and a trace in a display area.

[0038] Figure 5 For an embodiment of the present disclosure, a schematic diagram of a part of structure of a first array substrate.

[0039] Figure 6 For an embodiment of the present disclosure, a schematic diagram of a part of structure of a second array substrate.

[0040] Figure 7 For an embodiment of the present disclosure, a schematic diagram of a circuit connection mode of a display panel.

[0041] Figure 8 For an embodiment of the present disclosure, a schematic diagram of a first scan line layout of a display panel.

[0042] Figure 9 For an embodiment of the present disclosure, a schematic diagram of a second scan line layout of a display panel.

[0043] Figure 10 For an embodiment of the present disclosure, a schematic diagram of a time sequence of a gate scan signal output by a first sub-gate driving circuit and a second sub-gate driving circuit. DETAILED DESCRIPTION

[0044] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments should not be construed as limiting all example embodiments. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout. The drawings are diagrammatic and schematic representations of the example embodiments, and should not be construed as limiting the scope of example embodiments as described herein.

[0045] Although relative terms are used herein, such as "upper", "lower", to describe one component's relationship to another component of the icon, these terms are used herein for convenience only and are not necessarily limiting. It is to be understood that if the icon were turned over, such that the "upper" component were now a "lower" component, for example, the icons would function identically on the icon. When a structure is "on" another structure, it can be directly on the other structure or "indirectly" on the other structure via one or more intervening structures.

[0046] The terms "a", "an", "the" and "at least one" are used to mean one or more elements / constituents / etc.; the terms "comprises", "comprising", "includes" and "including" are used to mean either an open-ended process, such that other elements / constituents / etc. can be added, or a specific limitation, such that any elements / constituents / etc. not specifically recited are not present; "first", "second", and / or the like are merely labels to distinguish one constituent, element, etc. from another, and are not a limitation on the number of these constituents, elements, etc.

[0047] A structure A is located on a side of a structure B away from a structure C, which can be understood as the structure A is formed on a side of the structure B away from the structure C.

[0048] In the present application, unless otherwise explicitly specified and limited, the term "connected" should be interpreted broadly, for example, "connected" can be fixedly connected, or detachably connected, or integrated; can be directly connected, or indirectly connected through an intermediate medium.

[0049] In the embodiments of the present disclosure, a thin film transistor (TFT) includes an active layer, a gate insulating layer and a gate which are stacked. The active layer is located in a semiconductor layer, and the active layer includes a channel region and a source and a drain located on both sides of the channel region respectively. The channel region maintains a semiconductor property, and the source and the drain are both conductive. In the embodiments of the present disclosure, the functions of the source and the drain are sometimes exchanged with each other, i.e., the drain and the source can be exchanged with each other, in the case of using transistors with opposite polarities or in the case of changing the current direction in circuit operation. In the embodiments of the present disclosure, for any one transistor, one of the source and the drain is referred to as a first electrode of the transistor, and the other is referred to as a second electrode of the transistor.

[0050] The embodiments of the present disclosure provide a display device, which is a liquid crystal display device. Referring to Figure 1 , the liquid crystal display device includes a liquid crystal display module MDL and a driving module CTR for driving the liquid crystal display module MDL. The liquid crystal display module MDL includes a backlight module BLU and a display panel PNL which are stacked in sequence, and the driving module CTR can control the backlight module BLU and the display panel PNL, for example, the driving module CTR can control the backlight brightness of the backlight module BLU and control the light transmittance of the sub-pixel area PA of the display panel PNL, so as to make the display device display a picture.

[0051] In an embodiment of the present disclosure, referring to Figure 1 , the backlight module BLU can be a direct type backlight source. The direct type backlight source includes a lamp plate, and the lamp plate has array-distributed lamp areas, and each lamp area has one or more synchronously controlled light emitting elements (for example, Mini LED or Micro LED). Under the control of the driving module CTR, the light emitting brightness of each lamp area can be independently controlled to cooperate with the picture displayed by the display panel PNL, so as to improve the display effect of the display device. In an example, the driving module CTR controls the light emitting brightness of each lamp area by controlling the duty cycle of each light emitting element when emitting light.

[0052] In an embodiment of the present disclosure, referring to Figure 2 , the display panel PNL includes an array substrate ARR and an opposite substrate OS which are oppositely arranged, and includes a liquid crystal layer LC which is sandwiched between the array substrate ARR and the opposite substrate OS. The display panel PNL also has a frame sealant FSA surrounding the liquid crystal layer LC. The array substrate ARR is used to drive the deflection of the liquid crystal molecules of the liquid crystal layer LC to control the light transmittance and realize gray scale display. The opposite substrate OS can have a color film layer (not shown in the figure), so that the light transmitted through the liquid crystal layer LC forms corresponding colored light after penetrating through the opposite substrate OS, thereby realizing full-color display.

[0053] In one embodiment of the present disclosure, see Figure 3 The display panel PNL includes a display area AA and a peripheral area BB located outside the display area AA. The peripheral area BB can be a continuous annular area surrounding the display area AA or a discontinuous area surrounding the display area AA. The display area AA can be used to emit light to display images, while the peripheral area BB does not emit light.

[0054] In one embodiment of the present disclosure, see Figure 1 and Figure 2 The array substrate ARR is the substrate facing the backlight unit BLU. By changing the signal and voltage on the array substrate ARR, the rotation direction of the liquid crystal molecules in the liquid crystal layer LC is controlled, thereby controlling whether the polarized light of each pixel is emitted or not, thereby achieving the display purpose. Figures 4-6 In the display area AA, the array substrate ARR has a plurality of scan lines GL and a plurality of data lines DL located on one side of the base substrate SBT. In this example, the scan lines GL are arranged in the row direction, and the data lines DL are arranged in the column direction. The plurality of scan lines GL and the plurality of data lines DL intersect in the extension direction, defining a plurality of sub-pixel areas PA, and the sub-pixels PP and the pixel driving circuit can be located in the sub-pixel areas PA. In this example, the pixel driving circuit can be a thin film transistor serving as a switching transistor SW, and the sub-pixel PP can include a pixel electrode PIXP and a common electrode COMP, and the pixel electrode PIXP and the common electrode COMP at least partially meet and overlap to form a capacitor. The array substrate ARR can also be provided with a common voltage line (not shown in the figure) extending in the row direction. The second pole of the switching transistor SW is electrically connected to the data line DL, the first pole of the switching transistor SW is electrically connected to the pixel electrode PIXP, the gate of the switching transistor SW is electrically connected to the scan line GL, and the common electrode COMP is electrically connected to the common voltage line. During operation, the common voltage line can apply a common voltage to the common electrode COMP; the switching transistor SW can respond to the scan signal applied to the scan line GL and apply the drive voltage on the data line DL to the pixel electrode PIXP. In this way, by controlling the electric field strength between the pixel electrode PIXP and the common electrode COMP, the degree of twisting or tilting of the liquid crystal molecules within the corresponding range of the pixel electrode PIXP can be adjusted, thereby adjusting the polarization direction of the polarized light passing through the liquid crystal molecules, and ultimately adjusting the light output rate of the display panel PNL within the corresponding range of the pixel electrode PIXP, thereby achieving brightness control of the sub-pixel PP. In this disclosure, the sub-pixel area PA refers to the area controlled by the same switching transistor.

[0055] In one embodiment of the present disclosure, see Figure 4The opposite substrate OS is provided with a color filter unit (not shown in the color filter unit diagram) and a black matrix BM surrounding the color filter unit. The black matrix BM needs to cover the metal traces such as data traces DL, common voltage traces and scan lines GL to avoid light reflection of these metal traces. In addition, the edge electric field is formed between the traces such as data traces DL and scan lines GL and the electrodes such as common electrode COMP and pixel electrode P1XP, which can cause the liquid crystal molecules at the edge of the common electrode COMP and pixel electrode P1XP to deflect disorderly, and further easily cause abnormal light reflection at the edge of the pixel. In order to ensure the normal display of the display panel PNL, the black matrix BM needs to cover the edge of the common electrode COMP or pixel electrode P1XP.

[0056] In an embodiment of the present disclosure, the materials of the pixel electrode P1XP and the common electrode COMP are both indium tin oxide (ITO), i.e., both the pixel electrode P1XP and the common electrode COMP are transparent electrodes. It can be understood that in some other embodiments of the present disclosure, the material of at least one of the pixel electrode P1XP and the common electrode COMP can also be other conductive materials, especially other transparent conductive metal oxide materials.

[0057] Referring to Figure 5 With Figure 6 The array substrate ARR includes a substrate substrate SBT, a gate layer GT, a gate insulating layer GI, a semiconductor layer, a source-drain metal layer, a passivation layer and a pixel electrode layer which are stacked. In this example, the gate layer GT, the semiconductor layer and the source-drain metal layer form a switching transistor SW, which is a bottom-gate type thin film transistor. In an example, the gate layer GT is provided with a side branch part which can serve as a gate of the switching transistor SW. The semiconductor layer forms an active layer of the switching transistor SW, which includes a channel region of the switching transistor SW and a first electrode of the switching transistor SW and a second electrode of the switching transistor SW located on both sides of the channel region. A plurality of pixel electrodes P1XP are provided in the pixel electrode layer, and a certain gap is reserved between any two adjacent pixel electrodes P1XP. The source-drain metal layer forms data traces DL, and first and second connecting lines; the first connecting line is used to electrically connect the data traces DL and the first electrode of the switching transistor SW, and the second connecting line is used to electrically connect the second electrode of the switching transistor SW and the pixel electrode P1XP. The passivation layer has a connection via hole exposing a local area of the second connecting line. The pixel electrode P1XP is electrically connected to the second connecting line through the connection via hole. It can be understood that the array substrate ARR can also include other film layers, such as an alignment layer provided on the upper surface (the surface farthest from the substrate substrate SBT) of the array substrate ARR, etc.

[0058] In an example, the material of the active layer of the thin film transistor can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor.

[0059] It can be understood that, in other embodiments of the present disclosure, the switching transistor SW can also be a top-gate type thin film transistor. For example, see Figure 6 The array substrate includes a substrate substrate SBT, a semiconductor layer, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer, a source-drain metal layer, a passivation layer, and a pixel electrode layer which are stacked.

[0060] In an embodiment of the present disclosure, the array substrate ARR further has a common electrode layer having a common electrode, and the pixel electrode at least partially meets and overlaps with the common electrode to form a capacitor.

[0061] In another embodiment of the present disclosure, the display panel PNL further has an alignment layer. Specifically, the upper surface of the array substrate ARR (the surface of the array substrate ARR away from the substrate substrate SBT) is provided with a first alignment layer, and the lower surface of the opposite substrate OS (the surface of the opposite substrate OS close to the substrate substrate SBT) is provided with a second alignment layer, the first alignment layer is formed on the first transparent conductive film (as the pixel electrode layer), and the second alignment layer is formed on the second transparent conductive film (as the common electrode layer), and a polarizing sheet is arranged on the side of the array substrate ARR and the opposite substrate OS away from each other.

[0062] In an example, the opposite substrate OS is a user-facing substrate. In order to ensure the appearance of the entire display screen, display or display device, the polarizing sheet arranged on the opposite substrate OS can extend outward to the edge of the opposite substrate OS. In this way, the side of the opposite substrate OS facing the user will not have a conspicuous step due to the presence of the polarizing sheet, and the appearance of the display screen, display or display device can be improved. Of course, the polarizing sheet arranged on the array substrate ARR can only cover the area of the array substrate ARR inside the frame sealant FSA, so that the material of the polarizing sheet can be saved and the cost can be reduced. After the backlight module emits light, the light passes through the polarizing sheet on the array substrate ARR and irradiates onto the array substrate ARR, and then transmits through the array substrate ARR, rotates through the liquid crystal layer LC, and then transmits through the opposite substrate OS, and then transmits through the polarizing sheet on the opposite substrate OS, thereby displaying the picture.

[0063] In an embodiment of the present disclosure, the deflection properties of the two polarizing sheets can be consistent. Of course, they can also be inconsistent, for example, perpendicular to each other.

[0064] In an embodiment of the present disclosure, the material of the first and second transparent conductive films can be indium tin oxide (ITO).

[0065] In an embodiment of the present disclosure, the display panel PNL further has a driving assembly located in the peripheral region BB of the display panel PNL, the peripheral region BB has a first sub-peripheral region arranged along the extension direction of the scan lines GL, and a second sub-peripheral region arranged along the extension direction of the data lines DL, the driving assembly includes a gate driving circuit and a source driving circuit (not shown in the figure), wherein the gate driving circuit is located in the first sub-peripheral region, and the gate driving circuit is electrically connected with the scan lines GL for loading the scan signals to the scan lines GL, and the source driving circuit is located in the second sub-peripheral region, and the source driving circuit is electrically connected with the data lines for loading the driving voltage to the data lines.

[0066] In the related art, in order to reduce display crosstalk and screen flicker phenomenon, the data signal is generally controlled in a polarity inversion manner to control the display of the display panel, that is, the data signal has two polarities of positive and negative relative to the common voltage (generally the common voltage is close to 0v), and the data signals of the two polarities are alternately arranged in the display area. For example, the longitudinal data signal is sequentially positive frame, negative frame, positive frame, negative frame… from left to right, which alternately changes to offset the coupling effect of the data signal on other signals. However, the data signal has two polarity types of positive frame and negative frame, which results in that the voltage variation range of the data signal is twice as large as the variation range of a single polarity (such as only a single positive frame or only a single negative frame).

[0067] For example, assuming a single positive frame, the data voltage of the sub-pixel ranges from 0 gray scale to 255 gray scale, with a variation range of 5v; while the data voltage variation range of the polarity inversion is -5v~+5v, with a voltage variation of 10v. The gate scanning signal of each row needs to simultaneously open all the switch transistors in a row, and the data signals of the positive frame and the negative frame are simultaneously written into different sub-pixels. Taking the N-type switch transistor as an example, at this time, the gate-source (gate and source) voltage difference Vgs of the N-type switch transistor needs to be much larger than the threshold voltage Vth to charge the sub-pixel more quickly, that is, the maximum voltage of the gate voltage compared to the data voltage is better; and in most of the time of a frame after the sub-pixel is charged, the N-type switch transistor needs the gate scanning signal to output the off voltage to keep the switch transistor in the off state, at this time, the gate-source voltage difference Vgs of the switch transistor needs to be much smaller than the threshold voltage Vth to better prevent the switch transistor from leaking and causing flickering and other display defects, that is, the minimum voltage of the off voltage compared to the data voltage is better. At this time, due to the polarity inversion of the data voltage, the variation range of the positive frame and the negative frame of the data voltage is large, which causes the voltage difference between the start voltage and the off voltage of the gate voltage in a frame to be large; for example, the data voltage varies from -5v to +5v, the start voltage needs to be much larger than +5v, assuming that the start voltage = +10v, and the off voltage needs to be much smaller than -5v, assuming that the off voltage = -10v. In this case, the high and low voltage difference of the signal line is large, which increases the power loss, and the larger voltage difference between the start voltage and the off voltage is also easy to cause the switch transistor to break down and fail.

[0068] To solve the above problems, in the present disclosure, referring to Figure 4 and Figure 7, and the other scan line GL is connected with all the even-numbered sub-pixels PP (all the sub-pixels PP in the odd-numbered positions are in positive inversion or in negative inversion, all the sub-pixels PP in the even-numbered positions are in positive inversion or in negative inversion, and the inversion of the sub-pixels PP in the odd-numbered positions is different from the inversion of the sub-pixels PP in the even-numbered positions, and it can be understood that when the sub-pixels PP in the odd-numbered positions are in positive inversion, the sub-pixels PP in the even-numbered positions are in negative inversion; when the sub-pixels PP in the odd-numbered positions are in negative inversion, the sub-pixels PP in the even-numbered positions are in positive inversion), and each scan line GL is independently connected with a gate drive circuit GOA. In this way, the voltage loaded on the corresponding scan line GL by the gate drive circuit GOA can be set based on the corresponding connected sub-pixels PP (positive inversion or negative inversion), and it can be understood that the voltage loaded on the corresponding scan line GL only needs to meet the on-voltage and off-voltage of the positive inversion or the on-voltage and off-voltage of the negative inversion of the sub-pixels PP connected by the scan line GL, and does not need to be limited by the sub-pixels PP of the entire pixel row. At this time, the output voltage of the gate drive circuit GOA connected by the corresponding scan line GL can be adjusted to achieve the purposes of reducing power consumption and reducing the probability of breakdown of the switching transistor SW by using this characteristic.

[0069] In an example, the display panel PNL has a plurality of pixel rows and a plurality of scan line groups. The plurality of pixel rows are arranged in sequence along a second direction DV, each pixel row includes a plurality of switching transistors SW arranged in sequence along a first direction DH and a sub-pixel PP electrically connected to the second end SWD of the switching transistor one by one; the plurality of scan line groups correspond to the plurality of pixel rows one by one. In other words, each pixel row is correspondingly provided with a scan line group; each scan line group includes two scan lines GL, one of which is defined as a first scan line GL1 and the other is defined as a second scan line GL2. In an example, the first scan line GL1 is electrically connected to the odd-numbered switching transistor gate end SWG in the corresponding pixel row, and the second scan line GL2 is electrically connected to the even-numbered switching transistor gate end SWG in the corresponding pixel row. Of course, in other examples, the first scan line GL1 can be electrically connected to the even-numbered switching transistor gate end SWG in the corresponding pixel row, and the second scan line GL2 can be electrically connected to the odd-numbered switching transistor gate end SWG in the corresponding pixel row.

[0070] In this example, the display panel further includes a gate drive circuit GOA, as shown in Figure 7The gate driving circuit GOA includes a first sub-gate driving circuit GOA1 and a second sub-gate driving circuit GOA2. The first sub-gate driving circuit GOA1 includes a plurality of first shift registers connected in cascade, and the second sub-gate driving circuit GOA2 includes a plurality of second shift registers connected in cascade. In one example, the plurality of first shift registers are connected in one-to-one correspondence with a plurality of first scan lines GL1, and the plurality of second shift registers are connected in one-to-one correspondence with a plurality of second scan lines GL2. In another example, the plurality of first shift registers are connected in one-to-one correspondence with the plurality of second scan lines GL2, and the plurality of second shift registers are connected in one-to-one correspondence with the plurality of first scan lines GL1.

[0071] In the present disclosure, the case where the plurality of first shift registers are connected in one-to-one correspondence with the plurality of first scan lines GL1 and the plurality of second shift registers are connected in one-to-one correspondence with the plurality of second scan lines GL2 (the first sub-gate driving circuit GOA1 is connected with each of the first scan lines GL1, and the second sub-gate driving circuit GOA2 is connected with each of the second scan lines GL2) is described as an example.

[0072] In this example, the first sub-gate drive circuit GOA1 (each first shift register) is used to load the first on-voltage VA1 or the first off-voltage VB1 to the first scan line GL1, wherein the first on-voltage VA1 is used to turn on the electrically connected switching transistor SW, and the first off-voltage VB1 is used to turn off the electrically connected switching transistor SW; the second sub-gate drive circuit GOA2 (each second shift register) is used to load the second on-voltage VA2 or the second off-voltage VB2 to the second scan line GL2, the second on-voltage VA2 is used to turn on the electrically connected switching transistor SW, and the second off-voltage VB2 is used to turn off the electrically connected switching transistor SW, wherein the first on-voltage VA1 is different from the second on-voltage VA2, and the first off-voltage VB1 is different from the second off-voltage VB2. In other words, in the present disclosure, after the positive inversion sub-pixel PP and the negative inversion sub-pixel PP are controlled separately, the corresponding second sub-gate drive circuit GOA2 and the first sub-gate drive circuit GOA1 are set to output different on-voltage and off-voltage based on the voltage required by the switching transistor SW connected to the positive inversion sub-pixel PP and the voltage required by the switching transistor SW connected to the negative inversion sub-pixel PP, respectively. In this way, the voltage difference between the on-voltage and the off-voltage of the switching transistor SW can be reduced, the power consumption is reduced, and the risk of the switching transistor SW being broken down is reduced. For example, assuming that the positive driving voltage range is 0v~+5v, the second on-voltage VA2=+10v and the second off-voltage VB2=-5v can be set to ensure the charging rate and leakage protection level consistent with the conventional solution. The corresponding voltage difference between the on-voltage and the off-voltage of the switching transistor SW is only 15V, which can be reduced by 5V compared with the 20V of the prior art; and assuming that the negative driving voltage range is -5v~0v, the first on-voltage VA1=+5v and the first off-voltage VB1=-10v can be set to ensure the charging rate and leakage protection level consistent with the conventional solution. The corresponding voltage difference between the on-voltage and the off-voltage of the switching transistor SW is only 15V, which can be reduced by 5V compared with the 20V of the prior art. As can be seen from the above example, the present disclosure utilizes positively inverted sub-pixels PP and negatively inverted sub-pixels PP connected to the first scan line GL1 and the second scan line GL2, respectively. Together with the first sub-gate drive circuit GOA1 and the second sub-gate drive circuit GOA2, this reduces the voltage difference between the off-state voltage and the on-state voltage, thereby reducing power consumption and minimizing the risk of breakdown in the switching transistor SW. In the present disclosure, the on-state voltage and the off-state voltage can be determined based on the actual range of the drive voltage and the actual charging effect.

[0073] Based on the above example, in the present disclosure, at least one of the absolute value of the voltage difference between the first turn-on voltage VA1 and the second turn-off voltage VB2 and the absolute value of the voltage difference between the second turn-on voltage VA2 and the first turn-off voltage VB1 is greater than the absolute value of the voltage difference between the first turn-on voltage VA1 and the first turn-off voltage VB1 and greater than the absolute value of the voltage difference between the second turn-on voltage VA2 and the second turn-off voltage VB2. With the scheme in the present disclosure, the voltage difference can be reduced by setting, the power consumption is reduced, and the probability of the switch transistor SW being broken down is reduced. In an example, the absolute value of the voltage difference between the first turn-on voltage VA1 and the second turn-off voltage VB2 is greater than the absolute value of the voltage difference between the first turn-on voltage VA1 and the first turn-off voltage VB1 and greater than the absolute value of the voltage difference between the second turn-on voltage VA2 and the second turn-off voltage VB2. The absolute value of the voltage difference between the second turn-on voltage VA2 and the first turn-off voltage VB1 is greater than the absolute value of the voltage difference between the first turn-on voltage VA1 and the first turn-off voltage VB1 and greater than the absolute value of the voltage difference between the second turn-on voltage VA2 and the second turn-off voltage VB2. In the present disclosure, the voltage difference of the turn-on voltage and the turn-off voltage of all the switch transistors SW in the entire display panel PNL can be adjusted (the voltage difference of the turn-on voltage and the turn-off voltage of the switch transistor SW is reduced), and the power consumption can be further reduced, and the performance of the entire display panel PNL is improved. In which, the first turn-on voltage VA1 is 10V in the above example, and the second turn-off voltage VB2 is -10V in the above example.

[0074] In an embodiment of the present disclosure, referring to Figure 10 , the first turn-on voltage VA1 and the second turn-on voltage VA2 have the same timing, and the first turn-off voltage VB1 and the second turn-off voltage VB2 have the same timing. In this way, the writing time of each sub-pixel PP in each sub-pixel row is not affected, and the stability of the display panel PNL is ensured.

[0075] In an embodiment of the present disclosure, referring to Figure 8In other words, the orthogonal projection of the first scan line GL1 on the substrate SBT does not coincide with the orthogonal projection of the sub-pixel area PA on the substrate SBT. And the orthogonal projection of the second scan line GL2 on the substrate SBT does not coincide with the orthogonal projection of the sub-pixel area PA on the substrate SBT. In this way, neither the first scan line GL1 nor the second scan line GL2 interferes with the light emission of the sub-pixels PP in the sub-pixel area PA, and the aperture ratio of the display panel PNL can be ensured. In an example, the first scan line GL1 and the second scan line GL2 are distributed on both sides of the corresponding pixel row (in other words, there is one first scan line GL1 and one second scan line GL2 between any two adjacent pixel rows, and the first scan line GL1 and the second scan line GL2 correspond to different pixel rows). In this way, the arrangement of each row of sub-pixels PP and switching transistors SW can be facilitated, and the arrangement of the first scan line GL1 and the second scan line GL2 can be facilitated. In this example, the first scan line GL1 and the second scan line GL2 can be arranged on the same layer, simplifying the manufacturing process. In addition, the distance between the first scan line GL1 and the second scan line GL2 is relatively close, and in the later stage, one black matrix BM can be used to cover the first scan line GL1 and the second scan line GL2, and the pixel aperture ratio is better.

[0076] In another embodiment of the present disclosure, referring to Figure 9 , one of the first scan line GL1 and the second scan line GL2 overlaps the sub-pixel area PA. In other words, one of the first scan line GL1 and the second scan line GL2 crosses the sub-pixel area PA, increasing the distance between the first scan line GL1 and the second scan line GL2. In this way, it is beneficial to reduce the parasitic capacitance of the gate scan signal output by the first sub-gate drive circuit GOA1 and the gate scan signal output by the second sub-gate drive circuit GOA2 due to the excessively close distance. In an embodiment, the second scan line GL2 crosses the sub-pixel area PA. In another embodiment, the first scan line GL1 crosses the sub-pixel area PA.

[0077] In an embodiment of the present disclosure, the distance between any two adjacent first scan lines GL1 and second scan lines GL2 is equal. In this way, the stability of the gate scan signal can be further ensured.

[0078] In an embodiment of the present disclosure, the black matrix BM covers the first scan line GL1 and the second scan line GL2. In other words, the orthogonal projection of the black matrix BM on the liquid crystal layer LC covers the orthogonal projection of the first scan line GL1 on the liquid crystal layer LC and the orthogonal projection of the second scan line GL2 on the liquid crystal layer LC. In this way, the influence of the metal wiring on the display effect of light reflection can be reduced.

[0079] In an embodiment of the present disclosure, the display panel PNL further comprises a first signal line group SS1 for controlling the first sub-gate drive circuit GOA1 and a second signal line group SS2 for controlling the second sub-gate drive circuit GOA2; the first sub-gate drive circuit GOA1 outputs a first on-voltage VA1 or a first off-voltage VB1 according to a signal provided by the first signal line group SS1; the second sub-gate drive circuit GOA2 outputs a second on-voltage VA2 or a second off-voltage VB2 according to a signal provided by the second signal line group SS2. In the present disclosure, the first signal line group SS1 (CK signal) and the second signal line group SS2 (CK signal) of the first sub-gate drive circuit GOA1 and the second sub-gate drive circuit GOA3 are independent, and the two first signal line groups SS1 and the second signal line group SS2 can be adjusted separately to adapt to the on-voltage and off-voltage of the switching transistor corresponding to the positive and negative inversion sub-pixel, and to adapt to the on-voltage and off-voltage of the switching transistor corresponding to the negative inversion sub-pixel. In this way, the on-voltage and off-voltage of the whole can be set to be relatively high for the writing (switching transistor on) and maintaining (switching transistor off) of the positive frame driving voltage, so as to reduce the voltage difference between the off-voltage VB and the on-voltage VA to reduce power consumption and reduce the risk of switching transistor breakdown.

[0080] In this example, the driving module CTR is electrically connected with the first signal line group SS1 and the second signal line group SS2; the driving module CTR is configured to, in a first working mode, load a first signal to the first signal line group SS1; load a second signal to the second signal line group SS2; in a second working mode, load a third signal to the first signal line group SS1; load a fourth signal to the second signal line group SS2; wherein the voltage value of the first on-voltage VA1 output by the first sub-gate drive circuit GOA1 according to the first signal is the same as the voltage value of the second on-voltage VA2 output by the second sub-gate drive circuit GOA2 according to the fourth signal; the voltage value of the first off-voltage VB1 output by the first sub-gate drive circuit GOA1 according to the first signal is the same as the voltage value of the second off-voltage VB2 output by the second sub-gate drive circuit GOA2 according to the fourth signal; the voltage value of the first on-voltage VA1 output by the first sub-gate drive circuit GOA1 according to the third signal is the same as the voltage value of the second on-voltage VA2 output by the second sub-gate drive circuit GOA2 according to the second signal; the voltage value of the first off-voltage VB1 output by the first sub-gate drive circuit GOA1 according to the third signal is the same as the voltage value of the second off-voltage VB2 output by the second sub-gate drive circuit GOA2 according to the second signal.

[0081] In this example, the driving module CTR is electrically connected with the first signal line group SS1 and the second signal line group SS2; the driving module CTR is configured to, in a first working mode, load a first signal to the first signal line group SS1; load a second signal to the second signal line group SS2; in a second working mode, load a third signal to the first signal line group SS1; load a fourth signal to the second signal line group SS2; wherein the voltage value of the first on-voltage VA1 output by the first sub-gate drive circuit GOA1 according to the first signal is the same as the voltage value of the second on-voltage VA2 output by the second sub-gate drive circuit GOA2 according to the fourth signal; the voltage value of the first off-voltage VB1 output by the first sub-gate drive circuit GOA1 according to the first signal is the same as the voltage value of the second off-voltage VB2 output by the second sub-gate drive circuit GOA2 according to the fourth signal; the voltage value of the first on-voltage VA1 output by the first sub-gate drive circuit GOA1 according to the third signal is the same as the voltage value of the second on-voltage VA2 output by the second sub-gate drive circuit GOA2 according to the second signal; the voltage value of the first off-voltage VB1 output by the first sub-gate drive circuit GOA1 according to the third signal is the same as the voltage value of the second off-voltage VB2 output by the second sub-gate drive circuit GOA2 according to the second signal. Figure 7The first signal line group SS1 includes a first sub-signal line SS11 and a second sub-signal line SS12, and the second signal line group SS2 includes a third sub-signal line SS21 and a fourth sub-signal line SS22, wherein the first sub-signal line SS11 is connected to the first shift register of the pixel rows located at odd positions, and the second sub-signal line SS12 is connected to the first shift register of the pixel rows located at even positions. The third sub-signal line SS21 is connected to the second shift register of the pixel rows located at odd positions, and the fourth sub-signal line SS22 is connected to the second shift register of the pixel rows located at even positions. In the first operating mode, the driving module CTR is configured to, in the first operating mode, load the first signal to the first sub-signal line SS11 and the second sub-signal line SS12, see Figure 10 ( Figure 10 In the two timing diagrams corresponding to GOA1, one is the first sub-signal line SS11 and the other is the second sub-signal line SS12. The first signal timings loaded on the first sub-signal line SS11 and the second sub-signal line SS12 are opposite. The second signal is loaded on the third sub-signal line SS21 and the fourth sub-signal line SS22. The first signal timings loaded on the third sub-signal line SS21 and the fourth sub-signal line SS22 are opposite. Figure 10 In the two timing diagrams corresponding to GOA2, one of them is the third sub-signal line SS21, and the other is the fourth sub-signal line SS22). And so on, the sub-pixel inversion lighting is satisfied, which will not be elaborated here. In the present disclosure, in order to prevent the flickering phenomenon caused by liquid crystal excitation, it is generally set to reverse the driving voltage polarity between frames, that is, the current frame driving voltage polarity is positive, negative, positive, negative..., and the signal polarity of the next frame is negative, positive, negative, positive..., the on-voltage and off-voltage settings of the first sub-gate driving circuit GOA1 and the second sub-gate driving circuit GOA2 can be reversed along with the inter-frame conversion, that is, the on-voltage and off-voltage settings of the first sub-gate driving circuit GOA1 and the second sub-gate driving circuit GOA2 can be swapped with each other.

[0082] In one embodiment of the present disclosure, a gate drive circuit GOA is provided on both sides of the display panel PNL along the scan line GL, and the gate drive circuits GOA on both sides have the same structure. It is understood that the display panel PNL is dual-sided driven. The dual-sided drive approach allows for more precise control of the orientation of the liquid crystal molecules, thereby achieving higher brightness and contrast under the same light source, reducing light leakage, and improving display quality.

[0083] In the present disclosure, the first sub-gate driving circuit GOA1 and the second sub-gate driving circuit GOA2 are arranged, and are matched with the first signal line group SS1 and the second signal line group SS2 respectively, so as to realize the arrangement of the turn-on voltage and the turn-off voltage loaded on the first signal line group SS1 and the turn-on voltage and the turn-off voltage loaded on the second signal line group SS2 respectively, to match the writing and holding of the corresponding data signals (different polarities), and the signals loaded on the first scan line GL1 and the second scan line GL2 of the same pixel row are still kept to be opened and closed at the same time, so that the normal writing time of each row of pixels will not be compressed, and the pixel charging rate will not be affected, while the voltage difference between the turn-on voltage and the turn-off voltage of the first sub-gate driving circuit GOA1 and the second sub-gate driving circuit GOA2 can be effectively reduced, which can effectively reduce the power consumption of the display device. In addition, the turn-on voltage and the turn-off voltage of the first sub-gate driving circuit GOA1 and the second sub-gate driving circuit GOA2 can be adjusted separately, so as to reduce the voltage difference between the turn-on voltage and the turn-off voltage, and the failure risk of the switching transistor SW can be reduced.

[0084] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses or adaptive changes of this disclosure that follow the general principles thereof and include known equivalents or technical possibilities within the scope of the present disclosure. The specification and examples are only considered to be exemplary, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display device, characterized by comprising: The display panel comprises: a plurality of pixel rows, each of which comprises a plurality of switch transistors arranged in sequence along a first direction and a sub-pixel electrically connected to a second end of the switch transistors; a plurality of scan line groups corresponding to the plurality of pixel rows; each of the scan line groups comprises a first scan line electrically connected to gate terminals of odd-numbered switch transistors in the corresponding pixel row and a second scan line electrically connected to gate terminals of even-numbered switch transistors in the corresponding pixel row; a gate drive circuit comprising a first sub-gate drive circuit electrically connected to each of the first scan lines and a second sub-gate drive circuit electrically connected to each of the second scan lines; the first sub-gate drive circuit is configured to load a first on-voltage or a first off-voltage on the first scan line, the first on-voltage being configured to turn on the electrically connected switch transistors, and the first off-voltage being configured to turn off the electrically connected switch transistors; the second sub-gate drive circuit is configured to load a second on-voltage or a second off-voltage on the second scan line, the second on-voltage being configured to turn on the electrically connected switch transistors, and the second off-voltage being configured to turn off the electrically connected switch transistors; the first on-voltage is different from the second on-voltage, and the first off-voltage is different from the second off-voltage; at least one of an absolute value of a voltage difference between the first on-voltage and the second off-voltage and an absolute value of a voltage difference between the second on-voltage and the first off-voltage is greater than an absolute value of a voltage difference between the first on-voltage and the first off-voltage and greater than an absolute value of a voltage difference between the second on-voltage and the second off-voltage.

2. The display device according to claim 1, wherein the first on-voltage and the second on-voltage have the same timing, and the first off-voltage and the second off-voltage have the same timing.

3. The display device according to claim 1, wherein the display panel comprises a plurality of sub-pixel regions arranged in an array; the first scan line and the second scan line do not overlap with the sub-pixel regions.

4. The display device according to claim 3, wherein the first scan line and the second scan line are respectively located on two sides of the corresponding pixel row.

5. The display device according to claim 1, wherein the display panel comprises a plurality of sub-pixel regions arranged in an array; one of the first scan line and the second scan line overlaps with the sub-pixel regions.

6. The display device according to claim 5, wherein a distance between the first scan line and the second scan line arranged adjacently is equal.

7. The display device of claim 1, wherein: the display panel comprises an array substrate, an opposite substrate, and a liquid crystal layer between the array substrate and the opposite substrate; the first scan line and the second scan line are located on the array substrate, and the opposite substrate comprises a black matrix; a normal projection of the black matrix on the liquid crystal layer covers a normal projection of the first scan line on the liquid crystal layer and a normal projection of the second scan line on the liquid crystal layer.

8. The display device according to claim 1, wherein the display panel further comprises a first signal line group for controlling the first sub-gate drive circuit and a second signal line group for controlling the second sub-gate drive circuit. The first sub-gate driving circuit outputs the first on-voltage or the first off-voltage according to a signal provided by the first signal line group; and the second sub-gate driving circuit outputs the second on-voltage or the second off-voltage according to a signal provided by the second signal line group.

9. The display device according to claim 8, wherein The display device further comprises a driving module electrically connected with the first signal line group and the second signal line group; The driving module is configured to, in a first working mode, load a first signal to the first signal line group and load a second signal to the second signal line group; In a second working mode, load a third signal to the first signal line group and load a fourth signal to the second signal line group; The voltage value of the first on-voltage output by the first sub-gate driving circuit according to the first signal is the same as the voltage value of the second on-voltage output by the second sub-gate driving circuit according to the fourth signal; The voltage value of the first off-voltage output by the first sub-gate driving circuit according to the first signal is the same as the voltage value of the second off-voltage output by the second sub-gate driving circuit according to the fourth signal; The voltage value of the first on-voltage output by the first sub-gate driving circuit according to the third signal is the same as the voltage value of the second on-voltage output by the second sub-gate driving circuit according to the second signal; The voltage value of the first off-voltage output by the first sub-gate driving circuit according to the third signal is the same as the voltage value of the second off-voltage output by the second sub-gate driving circuit according to the second signal.

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