Preparation method of conductive interconnection structure
By using deionized water in the wet cleaning process of semiconductor structures, the anti-reflective coating film quality changes and spin-coated carbon coating void defects caused by wet cleaning in traditional processes are solved, the morphology of the through holes and the connectivity of metal interconnects is improved, and the yield of the device is improved.
Patent Information
- Application Number
- CN202510039631.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-09
- Publication Date
- 2025-05-06
AI Technical Summary
In the back-end metal wire preparation process of traditional field effect transistors, wet cleaning causes changes in the film quality of the bottom NFDARC layer, affecting subsequent dielectric material filling, forming void defects, resulting in small lateral size of the through holes and breaking the circuit of the metal interconnection line.
After etching the second hard mask layer and the first hard mask layer to form a plurality of first openings, a wet cleaning process is performed on the formed semiconductor structure, deionized water is used as the cleaning solution to avoid changes in the anti-reflective coating film, improve the filling performance of the spin-coated carbon coating, and prevent void defects.
By avoiding the membrane changes of the anti-reflective coating and the hollow defects of the spin-coated carbon coating, the morphology and lateral dimensions of the through holes are improved, the metal interconnection circuit breaking problem is solved, and the device yield is improved.
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Figure CN119943756A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to a method for preparing a conductive interconnect structure. Background Art
[0002] As the process nodes of field effect transistors continue to shrink significantly, the line width and size (pitch) of the back end of line (BEOL) also decrease sharply. The previously negligible small residual byproducts can also cause line disconnection (open circuit) problems, affecting the final yield of the chip.
[0003] In the current traditional process flow of preparing back-end metal lines of field effect transistors, after etching the hard mask layer on the intermediate metal layer, there is usually a step of wet cleaning the semiconductor structure using DHF (diluted hydrofluoric acid) to remove the byproducts formed in the previous etching process. However, in this process, the film quality of the bottom NFDARC layer (nitrogen-free anti-reflective coating) changes, and the film quality of the NFDARC layer changes from hydrophilic to hydrophobic, thereby affecting the subsequent dielectric material filling of the grooves in the hard mask layer and forming void defects in the dielectric material. In the subsequent wet cleaning after the partial etching of the through hole to form the opening, due to the presence of void defects in the groove below the opening, the cleaning solution will penetrate the front layer and drill into the bottom, resulting in an abnormal profile of the hard mask layer on the side wall of the groove. As a result, in the final step of forming the through hole by integrated etching, the lateral size of the through hole formed is very small, which makes it difficult to fill the metal material in the through hole, resulting in the problem of metal interconnection (especially the metal line at the through hole position) disconnection. Summary of the invention
[0004] The present application provides a method for preparing a conductive interconnect structure, which can solve the problem of metal interconnect line disconnection in the back-end metal line preparation process of a traditional field effect transistor.
[0005] The present application provides a method for preparing a conductive interconnect structure, comprising:
[0006] A semiconductor structure is provided, the semiconductor structure at least comprising: a substrate, an intermediate metal layer, an etch stop layer, a first buffer dielectric layer and a low-K dielectric layer, the intermediate metal layer is located in the substrate, the etch stop layer covers the substrate and the intermediate metal layer, the first buffer dielectric layer covers the etch stop layer, and the low-K dielectric layer covers the first buffer dielectric layer;
[0007] forming an anti-reflection coating, wherein the anti-reflection coating covers the low-K dielectric layer;
[0008] forming a first hard mask layer and a second hard mask layer in sequence, wherein the first hard mask layer covers the anti-reflective coating layer, and the second hard mask layer covers the first hard mask layer;
[0009] Etching the second hard mask layer and the first hard mask layer to the surface of the anti-reflective coating to form a plurality of first openings;
[0010] Performing a wet cleaning process on the semiconductor structure after forming the first opening, wherein the cleaning solution is deionized water;
[0011] forming a spin-on carbon coating, wherein the spin-on carbon coating fills the first opening and covers the second hard mask layer;
[0012] forming a low temperature oxidation layer, a first oxygen-doped silicon carbide layer and a cap layer in sequence, wherein the low temperature oxidation layer covers the spin-on carbon coating, the first oxygen-doped silicon carbide layer covers the low temperature oxidation layer, and the cap layer covers the first oxygen-doped silicon carbide layer;
[0013] Etching the cap layer and the first oxygen-doped silicon carbide layer to the surface of the low-temperature oxide layer to form a plurality of second openings, wherein at least part of the second openings are located directly above the first openings;
[0014] performing a wet cleaning process on the semiconductor structure after forming the second opening;
[0015] According to the second opening, the low-temperature oxide layer, the spin-on carbon coating, the anti-reflective coating, the low-K dielectric layer, the first buffer dielectric layer and the etch stop layer at the bottom of the second opening are etched to the surface of the intermediate metal layer by an integrated etching process to form a through hole;
[0016] A metal material layer is formed, wherein the metal material layer fills the through hole, wherein the metal material layer is interconnected with the intermediate metal layer to form a conductive interconnection structure.
[0017] Optionally, in the method for preparing the conductive interconnect structure, during the wet cleaning process performed on the semiconductor structure after the first opening is formed, the cleaning time lasts for 30s to 300s; the flow rate of the deionized water is 200sccm to 2000sccm; and the process temperature is 20°C to 120°C.
[0018] Optionally, in the preparation method of the conductive interconnect structure, during the wet cleaning process of the semiconductor structure after the second opening is formed, the cleaning time lasts for 30s to 300s; the cleaning solution is hydrofluoric acid, and the flow rate of the hydrofluoric acid is 200sccm to 2000sccm; the process temperature is 20°C to 120°C.
[0019] Optionally, in the method for preparing the conductive interconnect structure, the metal material layer is formed by an electrochemical plating process.
[0020] Optionally, in the method for preparing the conductive interconnect structure, the metal material layer is made of copper.
[0021] Optionally, in the method for preparing the conductive interconnect structure, the first hard mask layer is a titanium nitride layer, and the second hard mask layer is a second buffer dielectric layer.
[0022] Optionally, in the method for preparing the conductive interconnect structure, the etch stop layer includes: an aluminum nitride layer, a second oxygen-doped silicon carbide layer and an aluminum oxide layer stacked in sequence, the aluminum nitride layer covers the substrate and the intermediate metal layer, the second oxygen-doped silicon carbide layer covers the aluminum nitride layer, and the aluminum oxide layer covers the second oxygen-doped silicon carbide layer.
[0023] Optionally, in the method for preparing the conductive interconnect structure, a PECVD process is adopted and TEOS is introduced as a silicon source to form the first buffer dielectric layer.
[0024] The technical solution of this application has at least the following advantages:
[0025] The present application provides a method for preparing a conductive interconnect structure. In the preparation method, after etching a second hard mask layer and a first hard mask layer to form a plurality of first openings, a wet cleaning process is performed on the semiconductor structure after the first openings are formed, and deionized water is used as a wet cleaning solution, so that the film quality of the anti-reflective coating at the bottom of the first openings can be prevented from changing, the filling performance of the spin-on carbon coating to fill the first openings is improved, and the spin-on carbon coating is prevented from generating void defects, thereby preventing the chemical solution used in the wet cleaning process performed on the semiconductor structure after the second openings are formed from entering the spin-on carbon coating and causing the first hard mask layer profile on the side wall of the first opening to be abnormal, so that the morphology and lateral size of the through hole formed by subsequent integrated etching will not be affected by the profile of the first hard mask layer and the void defects of the spin-on carbon coating, thereby improving the open circuit (disconnection) defects of the back-end metal interconnect line and improving the yield of the device. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0027] Figure 1 is a flow chart of a method for preparing a conductive interconnect structure according to an embodiment of the present invention;
[0028] Figure 2-Figure 8 is a schematic diagram of a semiconductor structure in each process step of preparing a conductive interconnect structure according to an embodiment of the present invention;
[0029] The reference numerals are described as follows:
[0030] 10-substrate, 11-intermediate metal layer, 20-etching stop layer, 21-aluminum nitride layer, 22-second oxygen-doped silicon carbide layer, 23-aluminum oxide layer, 30-first buffer dielectric layer, 40-low K dielectric layer, 50-anti-reflective coating, 61-first hard mask layer, 62-second hard mask layer, 71-first opening, 72-second opening, 73-through hole, 80-spin-on carbon coating, 91-low-temperature oxide layer, 92-first oxygen-doped silicon carbide layer, 93-cap layer, 94-spin-on carbon coating II, 95-metal material layer. DETAILED DESCRIPTION
[0031] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in this application. Obviously, the described embodiments are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0032] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", and "third" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance.
[0033] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, it can also be the internal connection of two components, it can be a wireless connection, or it can be a wired connection. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.
[0034] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.
[0035] The present application provides a method for preparing a conductive interconnect structure. Figure 1 , Figure 1 is a flow chart of a method for preparing a conductive interconnect structure according to an embodiment of the present invention, wherein the method for preparing a conductive interconnect structure comprises:
[0036] First, perform step S1: refer to Figure 2 , Figure 2 It is a schematic diagram of a semiconductor structure after a second hard mask layer is formed in an embodiment of the present application, and a semiconductor structure is provided, which includes at least: a substrate 10, an intermediate metal layer 11, an etch stop layer 20, a first buffer dielectric layer 30 and a low-K (dielectric constant) dielectric layer 40, wherein the intermediate metal layer 11 is located in the substrate 10, the etch stop layer 20 covers the substrate 10 and the intermediate metal layer 11, the first buffer dielectric layer 30 covers the etch stop layer 20, and the low-K dielectric layer 40 covers the first buffer dielectric layer 30.
[0037] Preferably, the etch stop layer 20 includes: an aluminum nitride layer 21, a second oxygen-doped silicon carbide layer (ODC) 22 and an aluminum oxide layer 23 stacked in sequence, the aluminum nitride layer 21 covers the substrate 10 and the intermediate metal layer 11, the second oxygen-doped silicon carbide layer 22 covers the aluminum nitride layer 21, and the aluminum oxide layer 23 covers the second oxygen-doped silicon carbide layer 22.
[0038] Furthermore, the first buffer dielectric layer 30 is a silicon oxide film layer. In this embodiment, a PECVD (plasma enhanced chemical vapor deposition) process can be used and TEOS (tetraethyl orthosilicate) can be introduced as a silicon source to form the first buffer dielectric layer 30 .
[0039] Then, execute step S2: continue to refer to Figure 2 , an anti-reflection coating 50 is formed, and the anti-reflection coating 50 covers the low-K dielectric layer 40.
[0040] In this embodiment, the anti-reflection coating 50 is a nitrogen-free anti-reflection coating (NFDARC).
[0041] Next, execute step S3: continue to refer to Figure 2 , a first hard mask layer 61 and a second hard mask layer 62 are formed in sequence, wherein the first hard mask layer 61 covers the anti-reflective coating 50 , and the second hard mask layer 62 covers the first hard mask layer 61 .
[0042] Preferably, the first hard mask layer 61 is a titanium nitride layer; the second hard mask layer 62 is a second buffer dielectric layer, wherein the second buffer dielectric layer is a silicon oxide film layer, wherein, in this embodiment, a PECVD (plasma enhanced chemical vapor deposition) process can be used and TEOS (tetraethyl orthosilicate) can be introduced as a silicon source to form the second buffer dielectric layer (second hard mask layer 62).
[0043] Further, step S4 is performed: refer to Figure 3 , Figure 3 Schematic diagram of the semiconductor structure after the first opening is formed in the embodiment of the present application. The second hard mask layer 62 and the first hard mask layer 61 are etched to the surface of the anti-reflective coating 50 to form a plurality of first openings 71 .
[0044] In this embodiment, a dry etching process is used to etch the second hard mask layer 62 and the first hard mask layer 61 to the surface of the anti-reflective coating 50 to form a plurality of first openings 71 .
[0045] Next, step S5 is performed: the semiconductor structure ( Figure 3 A wet cleaning process is performed on the semiconductor structure shown in the figure, wherein the cleaning solution is deionized water.
[0046] Preferably, during the wet cleaning process performed on the semiconductor structure after the first opening 71 is formed, the cleaning time lasts for 30s to 300s; the flow rate of the deionized water is 200sccm to 2000sccm; and the process temperature is 20°C to 120°C.
[0047] Further, step S6 is performed: refer to Figure 4 , Figure 4 Schematic diagram of the semiconductor structure after the cap layer is formed in the embodiment of the present application, and a spin-on carbon coating (SOC) 80 is formed, and the spin-on carbon coating 80 fills the first opening 71 and covers the second hard mask layer 62. In the present application, after etching the second hard mask layer 62 and the first hard mask layer 61 to form a plurality of first openings 71, a wet cleaning process is performed on the semiconductor structure after the first openings 71 are formed and deionized water is used as a wet cleaning solution, which can prevent the film quality of the anti-reflective coating 50 at the bottom of the first opening 71 from changing, and prevent the film quality of the anti-reflective coating 50 from changing from hydrophilic to hydrophobic. Therefore, using deionized water as a wet cleaning solution to perform a wet cleaning process on the semiconductor structure after the first openings 71 are formed can improve the filling performance of the spin-on carbon coating 80 in filling the first openings 71, and prevent the spin-on carbon coating 80 from generating void defects.
[0048] Next, execute step S7: continue to refer to Figure 4, a low temperature oxide layer (LTO) 91, a first oxygen-doped silicon carbide layer 92 and a cap layer 93 are formed in sequence, wherein the low temperature oxide layer 91 covers the spin-on carbon coating 80, the first oxygen-doped silicon carbide layer 92 covers the low temperature oxide layer 91, and the cap layer 93 covers the first oxygen-doped silicon carbide layer 92.
[0049] Herein, a low temperature oxide layer (LTO) 91 may be formed by a low temperature oxidation process.
[0050] In this embodiment, the cap layer 93 may be made of silicon dioxide.
[0051] Furthermore, after the cap layer 93 is formed, a second spin-on carbon coating 94 is formed on the surface of the cap layer 93 . In subsequent steps, the second spin-on carbon coating 94 is used as a photoresist to etch the cap layer 93 and the first oxygen-doped silicon carbide layer 92 to form a second opening 72 .
[0052] Further, step S8 is performed: refer to Figure 5 , Figure 5 It is a schematic diagram of the semiconductor structure after forming multiple second openings in an embodiment of the present application, wherein the cap layer 93 and the first oxygen-doped silicon carbide layer 92 are etched to the surface of the low-temperature oxide layer 91 to form multiple second openings 72, and at least some of the second openings 72 are located directly above the first openings 71.
[0053] For further reference, Figure 6 , Figure 6 It is a schematic diagram of the semiconductor structure after the remaining spin-on carbon coating layer 2 and the cap layer are removed according to an embodiment of the present application. After the second opening 72 is formed, the remaining spin-on carbon coating layer 2 94 and the cap layer 93 are removed.
[0054] Next, step S9 is performed: performing a wet cleaning process on the semiconductor structure after the second opening 72 is formed.
[0055] Preferably, after forming the second opening 72, the semiconductor structure ( Figure 6 During the wet cleaning process of the semiconductor structure shown in the figure, the cleaning time lasts for 30s to 300s; the cleaning solution is hydrofluoric acid, and the flow rate of the hydrofluoric acid is 200sccm to 2000sccm; the process temperature is 20°C to 120°C.
[0056] Further, step S10 is performed: refer to Figure 7 , Figure 7is a schematic diagram of a semiconductor structure after a through hole is formed in an embodiment of the present application. According to the second opening 72, the low temperature oxide layer 91, the spin-on carbon coating 80, the anti-reflective coating 50, the low-K dielectric layer 40, the first buffer dielectric layer 30 and the etch stop layer 20 at the bottom of the second opening 72 are etched to the surface of the intermediate metal layer 11 by an integrated etching process to form a through hole 73. In the process of forming the through hole 73 by integrated etching, the low temperature oxide layer 91, the spin-on carbon coating 80, the second hard mask layer 62 and the first hard mask layer 61 are gradually and completely etched away.
[0057] It is worth noting that the deposition of the spin-on carbon coating (SOC) 80, the low temperature oxide layer (LTO) 91, the first oxygen-doped silicon carbide layer 92 and the cap layer 93, as the mask layer for etching the through hole 73, can reduce the aspect ratio. Specifically, the cap layer 93 and the first oxygen-doped silicon carbide layer 92 are used as hard mask etching layers. After photolithography and etching, multiple second openings (partial through holes) 72 are formed in the cap layer 93 and the first oxygen-doped silicon carbide layer 92, and stop on the low temperature oxide layer (LTO) 91, that is, the low temperature oxide layer 91 plays the role of etching stop. Finally, the all-in-one (AIO, all in) one) etching method, the low-temperature oxide layer 91, the spin-on carbon coating 80, the anti-reflective coating 50, the low-K dielectric layer 40, the first buffer dielectric layer 30 and the etch stop layer 20 are etched down together to the surface of the intermediate metal layer 11. After the integrated etching, the low-temperature oxide layer 91, the spin-on carbon coating 80, the second hard mask layer 62 and the first hard mask layer 61 are all etched away, resulting in a reduction in the depth of the through hole 73. Only the anti-reflective coating 50, the low-K dielectric layer 40, the first buffer dielectric layer 30 and the etch stop layer 20 remain, so the integrated etching of the through hole 73 reduces the aspect ratio. The above etching process is equivalent to etching the top of the through hole 73 in the first step of multiple second opening etching, and then in the integrated etching process, the low-temperature oxide layer 91 and the spin-on carbon coating 80 are gradually etched away by utilizing the selectivity of each layer etching, and the height of the through hole 73 is etched in the anti-reflective coating 50, the low-K dielectric layer 40, the first buffer dielectric layer 30 and the etch stop layer 20, so the integrated etching of the through hole 73 reduces the depth-to-width ratio of the etching.
[0058] Finally, execute step S11: refer to Figure 8 , Figure 8 It is a schematic diagram of the semiconductor structure after the metal material layer is formed in an embodiment of the present application. The metal material layer 95 is formed by an electrochemical plating process, and the metal material layer 95 fills the through hole 73 and covers the anti-reflective coating 50, wherein the metal material layer 95 is interconnected with the intermediate metal layer 11 to form a conductive interconnection structure.
[0059] In this embodiment, the metal material layer 95 is made of copper.
[0060] In the present application, since deionized water is used as a wet cleaning solution to perform a wet cleaning process on the semiconductor structure after the first opening 71 is formed, the void defects in the spin-on carbon coating 80 are avoided. Therefore, in the process of performing a wet cleaning process on the semiconductor structure after the second opening is formed, it is also possible to avoid the chemical solution (diluted hydrofluoric acid in this embodiment) used in the wet cleaning process of step S9 from entering the voids / gaps in the spin-on carbon coating 80, thereby causing the first hard mask layer 61 on the side wall of the first opening 71 to have an abnormal profile, so that the morphology and lateral dimensions of the through hole 73 formed by the subsequent integrated etching will not be affected by the profile of the first hard mask layer 61 and the void defects of the spin-on carbon coating 80, thereby solving the problem of short circuit (disconnection) of the back-end metal interconnect line and improving the yield of the device.
[0061] Furthermore, the method for preparing the conductive interconnect structure may also include step S12: grinding and removing the metal material layer 95 on the surface of the anti-reflective coating 50 so that the upper surface of the metal material layer 95 in the through hole 73 is flush with the upper surface of the anti-reflective coating surface 50, so as to planarize the metal material layer 95 in the through hole 73.
[0062] Preferably, a chemical mechanical polishing (CMP) process may be used to polish and remove the metal material layer 95 on the surface 50 of the anti-reflective coating, so as to planarize the metal material layer 95 in the through hole 73 .
[0063] Obviously, the above embodiments are merely examples for the purpose of clear explanation, and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection created by this application.
Claims
1. A method for preparing a conductive interconnect structure, characterized in that: include: A semiconductor structure is provided, the semiconductor structure at least comprising: a substrate, an intermediate metal layer, an etch stop layer, a first buffer dielectric layer and a low-K dielectric layer, the intermediate metal layer is located in the substrate, the etch stop layer covers the substrate and the intermediate metal layer, the first buffer dielectric layer covers the etch stop layer, and the low-K dielectric layer covers the first buffer dielectric layer; forming an anti-reflection coating, wherein the anti-reflection coating covers the low-K dielectric layer; forming a first hard mask layer and a second hard mask layer in sequence, wherein the first hard mask layer covers the anti-reflective coating layer, and the second hard mask layer covers the first hard mask layer; Etching the second hard mask layer and the first hard mask layer to the surface of the anti-reflective coating to form a plurality of first openings; Performing a wet cleaning process on the semiconductor structure after forming the first opening, wherein the cleaning solution is deionized water; forming a spin-on carbon coating, wherein the spin-on carbon coating fills the first opening and covers the second hard mask layer; forming a low temperature oxidation layer, a first oxygen-doped silicon carbide layer and a cap layer in sequence, wherein the low temperature oxidation layer covers the spin-on carbon coating, the first oxygen-doped silicon carbide layer covers the low temperature oxidation layer, and the cap layer covers the first oxygen-doped silicon carbide layer; Etching the cap layer and the first oxygen-doped silicon carbide layer to the surface of the low-temperature oxide layer to form a plurality of second openings, wherein at least part of the second openings are located directly above the first openings; performing a wet cleaning process on the semiconductor structure after forming the second opening; According to the second opening, the low-temperature oxide layer, the spin-on carbon coating, the anti-reflective coating, the low-K dielectric layer, the first buffer dielectric layer and the etch stop layer at the bottom of the second opening are etched to the surface of the intermediate metal layer by an integrated etching process to form a through hole; A metal material layer is formed, wherein the metal material layer fills the through hole, wherein the metal material layer is interconnected with the intermediate metal layer to form a conductive interconnection structure.
2. The method for preparing a conductive interconnect structure according to claim 1, characterized in that: In the process of performing a wet cleaning process on the semiconductor structure after forming the first opening, the cleaning time lasts for 30s to 300s; the flow rate of the deionized water is 200sccm to 2000sccm; and the process temperature is 20°C to 120°C.
3. The method for preparing a conductive interconnect structure according to claim 1, characterized in that: During the wet cleaning process of the semiconductor structure after the second opening is formed, the cleaning time lasts for 30s to 300s; the cleaning solution is hydrofluoric acid, and the flow rate of the hydrofluoric acid is 200sccm to 2000sccm; the process temperature is 20°C to 120°C.
4. The method for preparing a conductive interconnect structure according to claim 1, characterized in that: The metal material layer is formed by an electrochemical plating process.
5. The method for preparing a conductive interconnect structure according to claim 1, characterized in that: The material of the metal material layer is copper.
6. The method for preparing a conductive interconnect structure according to claim 1, characterized in that: The first hard mask layer is a titanium nitride layer, and the second hard mask layer is a second buffer dielectric layer.
7. The method for preparing a conductive interconnect structure according to claim 1, characterized in that: The etch stop layer comprises: an aluminum nitride layer, a second oxygen-doped silicon carbide layer and an aluminum oxide layer stacked in sequence, the aluminum nitride layer covers the substrate and the intermediate metal layer, the second oxygen-doped silicon carbide layer covers the aluminum nitride layer, and the aluminum oxide layer covers the second oxygen-doped silicon carbide layer.
8. The method for preparing a conductive interconnect structure according to claim 1, characterized in that: The first buffer dielectric layer is formed by adopting a PECVD process and introducing TEOS as a silicon source.