Packaging structure, packaging method, chip stacking structure and electronic equipment

Abstract

The invention relates to a packaging structure, a packaging method, a chip stacking structure and electronic equipment, the packaging structure comprises a first chip and a second chip which are stacked with each other, the first chip is internally provided with a first element, and the active surface of the second chip and the active surface of the first chip are oppositely arranged; wherein an electric connection area and a clearance area are arranged between the first chip and the second chip, the first chip and the second chip are electrically connected through the electric connection area, and the clearance area is used for reducing signal interference of the second chip on the first element. According to the packaging structure, the electric connection area and the clearance area are arranged between the first chip and the second chip, the first chip and the second chip are electrically connected through the electric connection area, and the clearance area is used for reducing signal interference of the second chip on the first element, so that the signal quality of the first element is improved, and the signal quality of the packaging structure is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure, a packaging method, a chip stacking structure and an electronic device. Background Art

[0002] Three-dimensional stacked chips can not only achieve high-density vertical interconnection between chips through hybrid bonding and other methods to improve the equivalent two-dimensional integration density of chips, but also integrate heterogeneous integration at different process nodes to improve the functional density of the system and meet the growing computing power requirements. However, stacking chips with high integration density results in a small distance between chips, and high-speed signals inside different chips will interfere with each other, affecting the integrity of high-speed signals. Summary of the invention

[0003] In a first aspect, the present disclosure provides a packaging structure to improve the signal quality of the packaging structure.

[0004] The packaging structure disclosed in the present invention includes a first chip and a second chip stacked on each other, wherein a first element is arranged in the first chip, and the second chip is arranged opposite to the active surface of the first chip; wherein an electrical connection area and a clearance area are arranged between the first chip and the second chip, the first chip and the second chip are electrically connected through the electrical connection area, and the clearance area is used to reduce the signal interference of the second chip on the first element.

[0005] Optionally, an orthographic projection of the clearance area in a direction toward the first element at least partially covers the first element.

[0006] Optionally, an area of ​​a positive projection of the clearance zone in a direction toward the first element is larger than an area of ​​a region where the first element is located.

[0007] Optionally, the first chip includes multiple wiring layers, the multiple wiring layers are arranged along the thickness direction of the packaging structure, at least one of the wiring layers is a top layer, the top layer is arranged closer to the second chip than the remaining wiring layers in the thickness direction of the packaging structure, and the first element is at least partially arranged on the top layer.

[0008] Optionally, in the electrical connection area, the first chip and the second chip are connected by hybrid bonding.

[0009] Optionally, a minimum distance between an edge of an orthographic projection of the clearance area in a direction toward the first element and the first element is greater than or equal to 5 μm.

[0010] Optionally, the area of ​​the clearance zone is less than or equal to 0.08 mm 2 .

[0011] Optionally, there are plural first elements and plural clearance areas, and the clearance area is provided corresponding to at least one first element.

[0012] Optionally, at least one of the clearance areas is arranged corresponding to at least two of the first elements.

[0013] Optionally, the distance between two adjacent clearance areas is greater than or equal to 20 μm.

[0014] Optionally, a shape of an orthographic projection of the first element in a direction toward the clearance area is consistent with a shape of the clearance area.

[0015] Optionally, the orthographic projection of the first element in a direction toward the clearance area is polygonal, and the clearance area is polygonal.

[0016] Optionally, the first chip includes a logic chip, the second chip includes a memory chip, or both the first chip and the second chip are logic chips.

[0017] In a second aspect, the present disclosure provides a packaging method.

[0018] The packaging method disclosed in the present invention is used to form any of the packaging structures described above, and the packaging method includes:

[0019] Disposing a first component on a first chip;

[0020] stacking the first chip and the second chip, wherein the second chip is arranged opposite to the active surface of the first chip;

[0021] An electrical connection area and a clearance area are provided between the first chip and the second chip. The first chip and the second chip are electrically connected via the electrical connection area. The clearance area is used to reduce signal interference of the second chip on the first element.

[0022] Optionally, the first chip is provided with a first element including:

[0023] At least one wiring layer is formed on the active surface of the first chip, and the wiring layer is arranged along the thickness direction of the packaging structure; the first element is formed through the at least one wiring layer.

[0024] Optionally, at least one of the wiring layers is a top layer, the top layer is arranged closer to the second chip than the remaining wiring layers in the thickness direction of the packaging structure, and the first element is at least partially arranged on the top layer.

[0025] In the present disclosure, the first element can be formed by a related process, such as a patterning process. For example, when the first element is an inductor element, it can be formed by etching, photolithography, and the like on the wiring layer, which will not be described in detail in the present disclosure.

[0026] In a third aspect, the present disclosure provides a chip stacking structure.

[0027] The chip stacking structure disclosed in the present invention comprises a substrate and a packaging structure, wherein the packaging structure is arranged on the substrate, and the packaging structure comprises the packaging structure according to any one of claims 1 to 13.

[0028] In a fourth aspect, the present disclosure provides an electronic device.

[0029] The electronic device disclosed in the present invention comprises a printed circuit board and any one of the above-mentioned packaging structures, wherein the printed circuit board is connected to the packaging structure.

[0030] The packaging structure disclosed in the present invention provides an electrical connection area and a clearance area between a first chip and a second chip, and the first chip and the second chip are electrically connected via the electrical connection area. The clearance area is used to reduce the signal interference of the second chip on the first element, thereby improving the signal quality of the first element and improving the signal quality of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a cross-sectional view of a packaging structure according to an embodiment of the present disclosure.

[0032] Figure 2 is a cross-sectional view of a chip according to another embodiment of the present disclosure.

[0033] Figure 3 yes Figure 2 Enlarged view of point A in the middle.

[0034] Figure 4 It is a schematic structural diagram of a clearance area of ​​a chip according to another embodiment of the present disclosure.

[0035] Figure 5 It is a schematic structural diagram of a clearance area and an inductor element of a chip according to another embodiment of the present disclosure.

[0036] Figure 6 and Figure 7 This is a simulation diagram provided by yet another embodiment of the present disclosure.

[0037] Reference numerals:

[0038] 10. Packaging structure;

[0039] 1. first chip; 11. first component; 12. electrical connection area; 13. clearance area; 14. wiring layer; 141. top layer; 101. first electrical connection member; 102. first through hole;

[0040] 2. second chip; 201. second electrical connection member; 202. second through hole;

[0041] 100. Packaging structure; 1001. First chip; 1002. Second chip; 1003. Inductor element. DETAILED DESCRIPTION

[0042] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, but should not be understood as limiting the present disclosure.

[0043] Figure 1 A package structure 100 is disclosed in one embodiment of the present disclosure. Figure 1 In the example, the inductor element 1003 needs to be provided with a clearance area of ​​a certain size to prevent other routings from affecting the Q value and inductance value of the inductor element 1003. Since the active surfaces of the first packaging structure 1001 and the second packaging structure 1002 in the packaging structure 100 are connected by a hybrid bonding method, the spacing between the first packaging structure 1001 and the second packaging structure 1002 is only a few microns. The inductor element 1003 of the first packaging structure 1001 cannot achieve a clearance area that meets the requirements, and the second packaging structure 1002 will generate signal interference to the inductor element 1003 of the first packaging structure 1001, reduce the signal quality of the inductor element 1003, and further affect the operation of the first packaging structure 1001, especially in high-speed scenarios, such as when the transmission speed reaches more than 10BPS, the inductor element 1003 is more susceptible to the influence of the second packaging structure 1002. Therefore, how to improve the signal quality of the inductor element 1003 in the first packaging structure 1001 is a technical problem that needs to be solved urgently.

[0044] like Figures 2 to 5 As shown, the package structure 10 of the embodiment of the present disclosure includes a first chip 1 and a second chip 2 stacked on each other, and the second chip 2 is arranged opposite to the active surface of the first chip 1. An electrical connection area 12 and a clearance area 13 are arranged between the first chip 1 and the second chip 2, and the first chip 1 and the second chip 2 are electrically connected through the electrical connection area 12. A first component 11 is arranged in the first chip 1, and the clearance area 13 is used to reduce the signal interference of the second chip 2 on the first component 11.

[0045] It should be noted that the chip in the embodiment of the present disclosure can be a crystal grain (also referred to as a particle or a bare chip) (die) or a chip wafer. It can be understood that after growing an epitaxial layer on a wafer, the chip wafer is formed, and the chip wafer is cut to obtain a bare chip (die). Crystal grains can be bonded to each other (die-to-die bonding, D2D bonding). The bonding of chip wafers is called wafer-to-wafer bonding (wafer-to-wafer bonding, W2W bonding). Multiple crystal grains are stacked on a chip wafer, and such a structure can be called crystal grain-to-wafer bonding (die-to-wafer bonding, D2W bonding). The package disclosed in the present disclosure can also be at least one of chip-to-wafer (Chip to Wafer, C2W) bonding, die-to-wafer (Die to Wafer, D2C) bonding, and chip-to-chip (Chip to Chip, C2C) bonding.

[0046] The present disclosure does not limit the number of chips stacked in the chip stacking structure, and the number of chips stacked can be set according to application requirements. In addition, the above-mentioned chip can be a memory chip, a logic chip or a chip with other functions.

[0047] The packaging structure 10 of the embodiment of the present disclosure sets an electrical connection area 12 and a clearance area 13 between the first chip 1 and the second chip 2, and the first chip 1 and the second chip 2 are electrically connected through the electrical connection area 12, and the clearance area 13 is used to reduce the signal interference of the second chip 2 on the first element 11, thereby improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0048] Optionally, the first chip 1 includes a logic chip, and the second chip 2 includes a memory chip. Alternatively, both the first chip 1 and the second chip 2 are logic chips.

[0049] Among them, the logic chip can be an application chip, and the memory chip can be a dynamic random access memory chip.

[0050] In the present disclosure, the first element 11 indicates an element having a specific function. Optionally, the first element 11 includes one of an inductor, a sensor, and a capacitor.

[0051] For example, the first element 11 is an inductor, which is in a packaging structure and is easily interfered by signals in high-speed scenarios.

[0052] By setting a clearance area, the influence of the second chip 2 on the components of the first chip that are easily affected by the second chip can be reduced or even avoided, thereby improving the signal quality of the packaging structure 10 .

[0053] In order to make the technical solution of the present disclosure easier to understand, the technical solution of the present disclosure is further described below by taking the thickness direction of the packaging structure 10 as being consistent with the up-down direction. Figure 2 and Figure 3 shown.

[0054] For example, the first chip 1 is disposed on the lower side of the second chip 2 , and the clearance area 13 is disposed on the upper side of the first element 11 .

[0055] Alternatively, if Figure 2 and Figure 3 As shown, the first chip 1 includes a plurality of wiring layers 14, and the plurality of wiring layers 14 are arranged along the thickness direction of the package structure 10. At least one wiring layer 14 is a top layer 141, and the top layer 141 is arranged closer to the second chip 2 than the remaining wiring layers 14 in the thickness direction of the package structure 10. The first element 11 is at least partially arranged on the top layer 141.

[0056] The first element 11 is at least partially disposed on the top layer 141 , which can be understood as: a portion of the first element 11 is disposed on the top layer 141 , and another portion of the first element 11 is disposed on other wiring layers 14 except the top layer 141 ; or, the first element 11 is entirely disposed on the top layer 141 .

[0057] For example, the plurality of wiring layers 14 are arranged in the up-down direction, one of the wiring layers 14 is a top layer 141 , and the top layer 141 is located at the uppermost side among the plurality of wiring layers 14 .

[0058] In the embodiment of the present disclosure, among the plurality of wiring layers 14 , the wiring layer 14 closer to the second chip 2 has a greater thickness and a smaller resistance.

[0059] By at least partially disposing the first element 11 on the top layer 141 , the parasitic resistance of the first element 11 can be reduced, thereby increasing the Q value of the first element 11 , further improving the signal quality of the first element 11 , and improving the signal quality of the packaging structure 10 .

[0060] Alternatively, if Figure 2 and Figure 3 As shown, the first chip 1 and the second chip 2 are connected by hybrid bonding.

[0061] For example, Figure 2 and Figure 3As shown, the first chip 1 is provided with a plurality of first electrical connectors 101, the second chip 2 is provided with a plurality of second electrical connectors 201, the first chip 1 is provided with a first through hole 102, and the first electrical connector 101 extends to the circuit of the first chip 1 through the first through hole 102. The second chip 2 is provided with a second through hole 202, and the second electrical connector 201 extends to the circuit of the second chip 2 through the second through hole 202. The second electrical connector 201 corresponds to the first electrical connector 101 one by one and is electrically connected, so that the first chip 1 and the second chip 2 are connected by a hybrid bonding method. Among them, the first electrical connector 101 and the second electrical connector 201 are both arranged in the electrical connection area 12, and the first electrical connector 101 and the second electrical connector 201 are not arranged in the clearance area 13.

[0062] The first chip 1 and the second chip 2 are connected by hybrid bonding, so that a higher density and a larger bandwidth of the package structure 10 can be achieved.

[0063] Alternatively, if Figure 2 , Figure 3 and Figure 5 As shown, the orthographic projection of the clearance area 13 in the direction toward the first element 11 at least partially covers the first element 11 .

[0064] Among them, the orthographic projection of the clearance area 13 in the direction toward the first element 11 at least partially covers the first element 11, which can be understood as: the orthographic projection of the clearance area 13 in the direction toward the first element 11 completely covers the first element 11; or, a part of the orthographic projection of the clearance area 13 in the direction toward the first element 11 covers the first element 11, and the other part of the orthographic projection of the clearance area 13 in the direction toward the first element 11 does not cover the first element 11.

[0065] It is understandable that both the first electrical connector 101 and the second electrical connector 201 are conductive members, which may cause signal interference to the first element 11 .

[0066] By at least partially covering the first element 11 with the orthographic projection of the clearance area 13 in the direction toward the first element 11 , the clearance area of ​​the first element 11 can be increased, and the signal quality of the first element 11 and the signal quality of the packaging structure 10 can be further improved.

[0067] Alternatively, if Figure 2 , Figure 3 and Figure 5 As shown, the area of ​​the orthographic projection of the clearance area 13 in the direction toward the first element 11 is larger than the area where the first element 11 is located. In other words, the orthographic projection of the clearance area 13 in the direction toward the first element 11 not only covers the entire first element 11, but also covers the edge area of ​​the first element 11, so as to cover more signals generated by the first element 11.

[0068] Optionally, a minimum distance between an edge of an orthographic projection of the clearance area 13 in a direction toward the first element 11 and the first element 11 is greater than or equal to 5 μm.

[0069] In the present disclosure, the minimum distance between the edge of the orthographic projection of the clearance area 13 in the direction of the first element 11 and the first element 11 indicates: the shortest straight-line distance between the orthographic projections of the clearance area 13 and the first element 11 on the plane where the first element 11 is located. Figure 5 As shown, the shortest distance J between the first element 11 and the clearance area 13 is 5 μm.

[0070] Taking the first element as an inductor as an example, the distance between the edge of the clearance area 13 in the direction of the normal projection toward the first element 11 and the first element 11 will affect the inductance value (L value) and Q value of the inductor element. Figure 6 As shown, the horizontal axis is the minimum distance between the edge of the normal projection of the clearance area 13 in the direction toward the first element 11 and the first element 11, and the vertical axis is the inductance value (L value) of the inductor element. Figure 7 As shown, the abscissa is the shortest straight line distance of the orthogonal projections of the clearance area 13 and the first element 11 on the plane in the direction toward the first element 11, and the ordinate is the Q value of the inductor. It can be seen that the minimum distance between the edge of the orthogonal projection of the clearance area 13 in the direction toward the first element 11 and the first element 11 is greater than 5μm, which can well reduce the signal of the second chip 2 and ensure the performance of the first element 11.

[0071] By setting the orthographic projection of the clearance area 13 in the direction toward the first chip 1 to be larger than the area where the first element 11 is located, the clearance area of ​​the first element 11 can be increased, further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0072] Alternatively, if Figure 5 As shown, the number of the first elements 11 and the clearance area 13 are both multiple, and the clearance area 13 is arranged corresponding to at least one first element 11 .

[0073] For example, Figure 5 As shown, the number of the first elements 11 is nine, and the number of the clearance areas 13 is five. A portion of the clearance areas 13 is arranged corresponding to two first elements 11, and a portion of the clearance areas 13 is arranged corresponding to one first element 11.

[0074] By providing a plurality of first elements 11 and a plurality of clearance areas 13 , a plurality of first elements 11 can be integrated on the same first chip 1 , thereby improving the integration level of the packaging structure 10 .

[0075] Alternatively, if Figure 5 As shown, at least one clearance area 13 is provided corresponding to at least two first elements 11 .

[0076] For example, Figure 5 As shown, four clearance areas 13 are arranged corresponding to two first elements 11 .

[0077] It is understandable that the clearance area 13 is not provided with the first electrical connector 101 and the second electrical connector 201, resulting in that the first chip 1 and the second chip 2 cannot be connected through the first electrical connector 101 and the second electrical connector 201 in the clearance area 13, affecting the connection stability of the first chip 1 and the second chip 2.

[0078] By providing at least one clearance area 13 corresponding to at least two first elements 11 , the number of clearance areas 13 can be reduced, thereby improving the connection stability between the first chip 1 and the second chip 2 and improving the reliability of the packaging structure 10 .

[0079] As described above, the first electrical connector 101 and the second electrical connector 201 are not provided in the clearance area 13, resulting in that the first chip 1 and the second chip 2 cannot be connected through the first electrical connector 101 and the second electrical connector 201 in the clearance area 13, thereby reducing the connection area between the first chip 1 and the second chip 2 and reducing the connection stability between the first chip 1 and the second chip 2.

[0080] Optionally, the distance between two adjacent clearance areas 13 is greater than or equal to 20 μm. Preferably, the distance between two adjacent clearance areas 103 is 100 μm, which can avoid excessive density between the clearance areas 103 and affect the connection stability between the first chip 1 and the second chip 2, and improve the reliability of the packaging structure 10.

[0081] By setting the distance between two adjacent clearance areas 13 to be greater than or equal to 20 μm, the spacing between two adjacent unconnected areas between the first chip 1 and the second chip 2 can be reduced, thereby improving the connection stability between the first chip 1 and the second chip 2 and improving the reliability of the packaging structure 10 .

[0082] Optionally, the area of ​​the clearance zone 13 is less than or equal to 0.08 mm 2 Preferably, the area of ​​the clearance area 13 is 0.0625 mm 2 When the clearance area 13 is smaller than the value described in the embodiment of the present disclosure, the connection stability between the first chip 1 and the second chip 2 can be better ensured.

[0083] As described above, the clearance area 13 is not provided with the first electrical connector 101 and the second electrical connector 201, resulting in that the first chip 1 and the second chip 2 cannot be connected through the first electrical connector 101 and the second electrical connector 201 in the clearance area 13, affecting the connection stability of the first chip 1 and the second chip 2.

[0084] By setting the area of ​​the clearance area 13 to be less than or equal to 0.08 mm 2 , the area of ​​the unconnected region between the first chip 1 and the second chip 2 can be reduced, the connection stability between the first chip 1 and the second chip 2 can be improved, and the reliability of the packaging structure 10 can be improved.

[0085] Alternatively, if Figure 5 As shown, the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is consistent with the shape of the clearance area 13 .

[0086] Among them, the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is consistent with the shape of the clearance area 13, which can be understood as: the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is the same as the shape of the clearance area 13, or the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is substantially the same as the shape of the clearance area 13.

[0087] For example, Figure 5 As shown, the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is a rectangle, and the shape of the clearance area 13 is also a rectangle; or, the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is an octagon, and the shape of the clearance area 13 is also an octagon.

[0088] By setting the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 to be consistent with the shape of the clearance area 13, when the area of ​​the clearance area 13 is small, the corresponding first element 11 can be covered. In this way, the connection stability between the first chip 1 and the second chip 2 can be improved, and the reliability of the packaging structure 10 can be improved.

[0089] Alternatively, if Figure 4 and Figure 5 As shown, the orthographic projection of the first element 11 in the direction toward the clearance area 13 is polygonal, and the clearance area 13 is polygonal.

[0090] For example, Figure 5 As shown, the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is a rectangle, and the shape of the clearance area 13 is also a rectangle; or, the shape of the orthographic projection of the first element 11 in the direction toward the clearance area 13 is an octagon, and the shape of the clearance area 13 is also an octagon.

[0091] By setting the orthographic projection of the first element 11 in the direction toward the clearance area 13 and the clearance area 13 to be polygonal, the processing and manufacturing of the packaging structure 10 is facilitated.

[0092] The packaging structure 10 of the embodiment of the present disclosure can increase the clearance area of ​​the first element 11, improve the signal quality of the first element 11, and improve the signal quality of the packaging structure 10 by setting a clearance area 13 between the first chip 1 and the second chip 2, and the clearance area 13 is set corresponding to the first element 11.

[0093] The packaging method of the embodiment of the present disclosure includes:

[0094] A first component 11 is provided on the first chip 1;

[0095] Stacking the first chip 1 and the second chip 2, wherein the second chip 2 is arranged opposite to the active surface of the first chip 1;

[0096] An electrical connection area 12 and a clearance area 13 are provided between the first chip 1 and the second chip 2 . The first chip 1 and the second chip 2 are electrically connected via the electrical connection area 12 . The clearance area 13 is used to reduce signal interference of the second chip 2 on the first element 11 .

[0097] In some embodiments, the first chip 1 is provided with the first element 11 including:

[0098] At least one wiring layer 14 is formed on the active surface of the first chip 1 , and the wiring layer 14 is arranged along the thickness direction of the package structure 10 ; the first component 11 is formed by the at least one wiring layer 14 .

[0099] In some embodiments, at least one wiring layer 14 is a top layer 141 , which is disposed closer to the second chip 2 than the remaining wiring layers 14 in the thickness direction of the package structure 10 , and the first component 11 is at least partially disposed on the top layer 141 .

[0100] The chip stacking structure in the embodiment of the present disclosure includes a substrate and a packaging structure 10 disposed on the substrate, and the packaging structure is the packaging structure 10 described in any of the above embodiments.

[0101] The electronic device printed circuit board and packaging structure 10 of the embodiment of the present disclosure, the packaging structure 10 is the packaging structure 10 described in any of the above embodiments, and the printed circuit board is connected to the packaging structure 10.

[0102] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0103] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0104] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0105] In the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0106] In the present disclosure, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0107] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are illustrative and cannot be construed as limitations on the present disclosure. Changes, modifications, substitutions and variations of the above embodiments by those of ordinary skill in the art are all within the scope of protection of the present disclosure.

Claims

1. A packaging structure, characterized in that: The invention comprises a first chip and a second chip stacked on each other, wherein the first chip is provided with a first component, The second chip is arranged opposite to the active surface of the first chip; An electrical connection area and a clearance area are provided between the first chip and the second chip. The first chip and the second chip are electrically connected via the electrical connection area, and the clearance area is used to reduce signal interference of the second chip on the first element.

2. The packaging structure according to claim 1, characterized in that: An orthographic projection of the clearance area in a direction toward the first element at least partially covers the first element.

3. The packaging structure according to claim 2, characterized in that: An area of ​​an orthographic projection of the clearance zone in a direction toward the first element is larger than an area where the first element is located.

4. The packaging structure according to claim 1, characterized in that: A minimum distance between an edge of an orthographic projection of the clearance area in a direction toward the first element and the first element is greater than or equal to 5 μm.

5. The packaging structure according to claim 1, characterized in that: The first chip includes multiple wiring layers, and the multiple wiring layers are arranged along the thickness direction of the packaging structure. At least one of the wiring layers is a top layer, and the top layer is arranged closer to the second chip than the remaining wiring layers in the thickness direction of the packaging structure. The first element is at least partially arranged on the top layer.

6. The packaging structure according to claim 1, characterized in that: In the electrical connection region, the first chip and the second chip are connected by hybrid bonding.

7. The packaging structure according to any one of claims 1 to 6, characterized in that: The area of ​​the clearance zone is less than or equal to 0.08 mm 2 .

8. The packaging structure according to any one of claims 1 to 6, characterized in that: The number of the first elements and the clearance areas are both plural, and the clearance area is arranged corresponding to at least one of the first elements.

9. The packaging structure according to claim 8, characterized in that: At least one of the clearance areas is disposed corresponding to at least two of the first elements.

10. The packaging structure according to claim 9, characterized in that: The distance between two adjacent clearance areas is greater than or equal to 20 μm.

11. The packaging structure according to any one of claims 1 to 6, characterized in that: A shape of an orthographic projection of the first element in a direction toward the clearance area is consistent with a shape of the clearance area.

12. The packaging structure according to claim 11, characterized in that: The orthographic projection of the first element in a direction toward the clearance area is a polygon, and the clearance area is a polygon.

13. The packaging structure according to claim 1, characterized in that: The first chip includes a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

14. A packaging method, characterized in that: The packaging method is used to form a packaging structure according to any one of claims 1 to 13, and the packaging method comprises: Disposing a first component on a first chip; stacking the first chip and the second chip, wherein the second chip is arranged opposite to the active surface of the first chip; An electrical connection area and a clearance area are provided between the first chip and the second chip. The first chip and the second chip are electrically connected via the electrical connection area. The clearance area is used to reduce signal interference of the second chip on the first element.

15. The packaging method according to claim 14, characterized in that: The first chip is provided with a first element comprising: At least one wiring layer is formed on the active surface of the first chip, and the wiring layer is arranged along the thickness direction of the packaging structure; the first element is formed through the at least one wiring layer.

16. The packaging method according to claim 15, characterized in that: At least one of the wiring layers is a top layer, the top layer is arranged closer to the second chip than the other wiring layers in the thickness direction of the packaging structure, and the first element is at least partially arranged on the top layer.

17. A chip stacking structure, characterized in that: The invention comprises a substrate and a packaging structure, wherein the packaging structure is arranged on the substrate, and the packaging structure comprises the packaging structure according to any one of claims 1 to 13.

18. An electronic device, characterized in that: The invention comprises a printed circuit board and the packaging structure according to any one of claims 1 to 13, wherein the printed circuit board is connected to the packaging structure.

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