Packaging structure, electronic equipment, chip stacking structure and packaging method

Abstract

The invention relates to a packaging structure, electronic equipment, a chip stacking structure and a packaging method, the packaging structure comprises a first chip, a second chip and a metal layer, the first chip and the second chip are stacked with each other, the active surface of the second chip and the active surface of the first chip are oppositely arranged, and a first element is arranged in the first chip; the metal layer is arranged on the side, facing the second chip, of the first element, the metal layer is used for reducing interference of signals of the second chip on the first element, and the metal density of the area where the metal layer is located ranges from 20% to 70%. According to the packaging structure, the metal layer is arranged on the side, facing the second chip, of the first element, the metal density of the area where the metal layer is located is set to be 20%-70%, interference of signals of the second chip on the first element is reduced through the metal layer, and therefore the signal quality of the first element can be improved, and the signal quality of the packaging structure can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a packaging structure, an electronic device, a chip stacking structure and a packaging method. Background Art

[0002] Three-dimensional stacked chips can not only achieve high-density vertical interconnection between chips through hybrid bonding and other methods to improve the equivalent two-dimensional integration density of chips, but also integrate heterogeneous integration at different process nodes to improve the functional density of the system and meet the growing computing power requirements. However, stacking chips with high integration density results in a small distance between chips, and high-speed signals inside different chips will interfere with each other, affecting the integrity of high-speed signals. Summary of the invention

[0003] In a first aspect, the present disclosure provides a packaging structure to improve the signal quality of a chip.

[0004] The packaging structure disclosed in the present invention includes a first chip, a second chip and a metal layer stacked on each other, wherein the second chip is arranged opposite to the active surface of the first chip, and a first element is arranged in the first chip; the metal layer is arranged on the side of the first element facing the second chip, and the metal layer is used to reduce the interference of the signal of the second chip on the first element, and the metal density of the area where the metal layer is located is 20% to 70%.

[0005] Optionally, the metal density of the area where the metal layer is located is 30% to 50%.

[0006] Optionally, the metal layer is connected to a low-speed signal, a power supply or a ground.

[0007] Optionally, the area where the metal layer is located is polygonal.

[0008] Optionally, an orthographic projection of the metal layer in a direction toward the first chip at least partially covers the first element.

[0009] Optionally, an area of ​​an orthographic projection of the metal layer in a direction toward the first chip is larger than an area of ​​a region where the first element is located.

[0010] Optionally, the metal layer includes at least one first metal portion and at least one second metal portion.

[0011] Optionally, the first metal part and the second metal part are both comb-shaped; and / or the first metal part includes a plurality of first metal strips arranged side by side, and the second metal part includes a plurality of second metal strips arranged side by side), and the first metal strips and the second metal strips are arranged alternately and at intervals in sequence.

[0012] Optionally, the width of the first metal strip and the second metal strip is 0.4 μm to 12.5 μm; and / or the spacing between the first metal strip and the second metal strip is 0.4 μm to 25 μm.

[0013] Optionally, the metal layer has a rectangular pulse signal waveform.

[0014] Optionally, the metal layer includes multiple metal parts, and the multiple metal parts are evenly arranged along the circumference of a preset rectangular frame. The metal part includes multiple V-shaped metal strips. The multiple metal strips of the same metal part are arranged at intervals along the inner and outer directions, and the length of the metal strip located on the outer side is smaller than the length of the metal strip located on the inner side.

[0015] Optionally, the number of the metal parts is four, and the angle of the metal strips is 90°.

[0016] Optionally, the metal layer is provided by reusing a wiring layer of the second chip.

[0017] Optionally, an electrical connection area and a clearance area are provided between the first chip and the second chip, and an orthographic projection of the clearance area in a direction toward the first element covers the first element.

[0018] Optionally, an area of ​​a positive projection of the clearance zone in a direction toward the first element is larger than an area of ​​a region where the first element is located.

[0019] Optionally, a minimum distance between an edge of a normal projection of the clearance area in a direction toward the first element and the first element is greater than or equal to 5 μm.

[0020] Optionally, the first chip includes multiple first wiring layers, the multiple first wiring layers are arranged along the thickness direction of the chip, at least one of the first wiring layers is a first top layer, the first top layer is arranged closer to the second chip than the other first wiring layers in the thickness direction of the chip, and the first element is at least partially arranged on the first top layer.

[0021] Optionally, the second chip includes multiple second wiring layers, the multiple second wiring layers are arranged along the thickness direction of the chip, at least one second wiring layer is a second top layer, the second top layer is arranged closer to the first chip than the other second wiring layers in the thickness direction of the chip, and the metal layer is at least partially arranged on the second top layer.

[0022] Optionally, the first chip is a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

[0023] Optionally, the first element includes at least one of an inductor, a sensor and a capacitor.

[0024] In a second aspect, the present disclosure provides a chip stacking structure.

[0025] The chip stacking structure disclosed in the present invention comprises a substrate and a packaging structure, wherein the packaging structure is the packaging structure described in any of the above embodiments, and the packaging structure is arranged on the substrate.

[0026] In a third aspect, the present disclosure provides a packaging method.

[0027] The packaging method disclosed in the present invention is used to form the packaging structure described in any of the above embodiments, and the packaging method includes:

[0028] Disposing a first component on a first chip;

[0029] Disposing a metal layer on the second chip;

[0030] The first chip and the second chip are stacked, wherein the metal layer is arranged on a side of the second chip close to the first chip, the second chip is arranged opposite to the active surface of the first chip, and the metal layer is used to reduce the signal interference of the second chip on the first element;

[0031] The metal density of the area where the metal layer is located is 20% to 70%.

[0032] Optionally, providing a first element on the first chip includes:

[0033] forming at least one first wiring layer on the active surface of the first chip, wherein the first wiring layer is arranged along the thickness direction of the package structure;

[0034] The first element is formed by at least one of the first wiring layers.

[0035] Optionally, the packaging method includes:

[0036] At least one of the first wiring layers is a first top layer, which is arranged closer to the second chip than the other first wiring layers in the thickness direction of the package structure, and the first element is at least partially arranged in the first top layer.

[0037] Optionally, providing a metal layer on the second chip includes:

[0038] forming at least one second wiring layer on the active surface of the second chip, wherein the second wiring layer is arranged along the thickness direction of the package structure;

[0039] The metal layer is formed through at least one second wiring layer.

[0040] In the present disclosure, the formation of the first top layer, the second top layer or the shielding layer can be achieved through relevant processes, such as a graphic process, which is not elaborated in the present disclosure.

[0041] In a fourth aspect, the present disclosure provides an electronic device.

[0042] The electronic device disclosed in the present invention comprises a printed circuit board and a chip packaging structure, wherein the chip packaging structure is the packaging structure described in any of the above embodiments, and the printed circuit board is connected to the packaging structure.

[0043] The packaging structure disclosed in the present invention, by arranging a metal layer on the side of the first element facing the second chip and setting the metal density of the area where the metal layer is located to 20% to 70%, uses the metal layer to reduce the interference of the signal of the second chip on the first element, thereby improving the signal quality of the first element and the signal quality of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 is a cross-sectional view of a packaging structure according to an embodiment of the present disclosure.

[0045] Figure 2 FIG. 4 is a partial cross-sectional view of a packaging structure according to an embodiment of the present disclosure.

[0046] Figure 3 is a cross-sectional view of a packaging structure according to another embodiment of the present disclosure.

[0047] Figure 4 yes Figure 3 Enlarged view of point A in the middle.

[0048] Figure 5 It is a schematic structural diagram of a metal layer of a packaging structure according to another embodiment of the present disclosure.

[0049] Figure 6 It is a schematic structural diagram of a metal layer and a first element of a packaging structure according to another embodiment of the present disclosure.

[0050] Figure 7 It is a structural schematic diagram of a metal layer of a packaging structure of yet another embodiment of the present disclosure.

[0051] Figure 8 It is a structural schematic diagram of a metal layer of a packaging structure of another embodiment of the present disclosure.

[0052] Fig. 9 It is a structural schematic diagram of a metal layer of a packaging structure of another embodiment of the present disclosure.

[0053] Fig.10 It is a structural schematic diagram of the electrical connection area and the clearance area of ​​the packaging structure of another embodiment of the present disclosure.

[0054] Fig.11 It is a structural schematic diagram of an electrical connection area, a clearance area and a first element of a packaging structure of another embodiment of the present disclosure.

[0055] Fig.12 and Fig.13 This is a simulation diagram provided by yet another embodiment of the present disclosure.

[0056] Reference numerals:

[0057] 10. Packaging structure;

[0058] 1. first chip; 11. first component; 12. second circuit; 13. first electrical connector; 14. first through hole; 101. first wiring layer; 1011. first top layer; 102. electrical connection area; 103. clearance area;

[0059] 2. second chip; 21. metal layer; 211. first metal part; 2111. first metal strip; 212. second metal part; 2121. second metal strip; 213. metal part; 2131. metal strip; 22. first circuit; 23. third circuit; 24. second electrical connection; 25. second through hole; 201. second wiring layer; 2011. second top layer;

[0060] 100. Packaging structure; 1001. First chip; 1002. Second chip; 1003. Inductor element; 1004. Circuit. DETAILED DESCRIPTION

[0061] Embodiments of the present disclosure are described in detail below, and examples of the embodiments are shown in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present disclosure, but should not be understood as limiting the present disclosure.

[0062] like Figure 1 and Figure 2 A package structure 100 is disclosed in one embodiment of the present disclosure. Figure 1 and Figure 2In the example, the inductor element 1003 needs to be provided with a clearance area of ​​a certain size to prevent other routing lines from affecting the Q value and inductance value of the inductor element 1003. Since the active surfaces of the first chip 1001 and the second chip 1002 in the packaging structure 100 are connected by a hybrid bonding method, the spacing L between the first chip 1001 and the second chip 1002 is only a few microns. The inductor element 1003 of the first chip 1001 cannot achieve a clearance area that meets the requirements, and the line 1004 on the second chip 1002 will interfere with the inductor element 1003 of the first chip 1001, reduce the signal quality of the inductor element 1003, and further affect the operation of the first chip 1001, especially in high-speed scenarios, such as when the transmission speed reaches more than 10BPS, the inductor element 1003 is more susceptible to the influence of the second chip 1002. Therefore, how to improve the signal quality of the inductor element 1003 in the first chip 1001 is a technical problem that needs to be solved urgently.

[0063] like Figures 3 to 6 As shown, the package structure 10 of the embodiment of the present disclosure includes a first chip 1 and a second chip 2 stacked on each other and a metal layer 21, and the second chip 2 is arranged opposite to and connected to the active surface of the first chip 1. A first component 11 is arranged in the first chip 1, and the metal layer 21 is arranged on the side of the first component 11 facing the second chip 2. Among them, the metal layer 21 is used to reduce the interference of the signal of the second chip 2 on the first component 11, and the metal density of the area where the metal layer 21 is located is 20% to 70%.

[0064] Among them, Figure 5 As shown, the area in the dotted line frame is the area where the metal layer 21 is located, and the ratio of the area of ​​the metal layer 21 to the area of ​​the dotted line frame is the metal density of the area where the metal layer 21 is located.

[0065] It should be noted that the chip in the embodiment of the present disclosure can be a grain (also referred to as a particle or a bare chip) (die) or a chip wafer. It is understandable that after the epitaxial layer is grown on the wafer, the chip wafer is formed, and the chip wafer is cut to obtain a bare chip (die). Grains can be bonded to each other (die-to-die bonding, D2D bonding). The bonding of chip wafers is called wafer-to-wafer bonding (wafer-to-wafer bonding, W2W bonding). Multiple grains are stacked on a chip wafer, and such a structure can be called grain-to-wafer bonding (die-to-wafer bonding, D2W bonding). The package disclosed in the present disclosure can also be at least one of chip-to-wafer (Chip to Wafer, C2W) bonding, die-to-wafer (Die to Wafer, D2C) bonding, and chip-to-chip (Chip to Chip, C2C) bonding.

[0066] The present disclosure does not limit the number of chips stacked in the chip stacking structure, and the number of chips stacked can be set according to application requirements. In addition, the above-mentioned chip can be a memory chip, a logic chip or a chip with other functions.

[0067] The packaging structure 10 of the embodiment of the present disclosure arranges the metal layer 21 on the side of the first element 11 facing the second chip 2, and sets the metal density of the area where the metal layer 21 is located to 20% to 70%. The metal layer 21 is used to reduce the interference of the signal of the second chip 2 on the first element 11, thereby improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0068] Optionally, the first chip 1 includes a logic chip, and the second chip 2 includes a memory chip; or, both the first chip 1 and the second chip 2 are logic chips.

[0069] Among them, the logic chip can be an application chip, and the memory chip can be a dynamic random access memory chip.

[0070] Optionally, the first element 11 comprises.

[0071] It is understandable that the first component may also be other functional devices affected by the second chip, such as sensors, capacitors, etc.

[0072] In the present disclosure, the inductor element is very susceptible to the influence of the second chip 2. The present application scheme can be preferably used in the scenario where the first element 11 is an inductor. By providing the shielding element 21, the signal interference of the second chip 2 on the inductor, sensor or capacitor can be reduced or even avoided, thereby improving the signal quality of the packaging structure 10.

[0073] Optionally, the metal layer 21 is connected to a low-speed signal, a power source or a ground.

[0074] When the metal layer 21 is connected to a low-speed signal or power supply, the metal layer 21 is used as a circuit. When the metal layer 21 is grounded, it is not used as an electrical component such as a circuit.

[0075] By connecting the metal layer 21 to a low-speed signal, a power source or a ground, the metal layer 21 can be used to more effectively reduce interference caused by the signal of the second chip 2 on the first element 11 , further improving the signal quality of the package structure 10 .

[0076] In order to make the technical solution of the present disclosure easier to understand, the technical solution of the present disclosure is further described below by taking the thickness direction of the packaging structure 10 as being consistent with the up-down direction. Figure 3 and Figure 4 shown.

[0077] For example, the first chip 1 is disposed on the lower side of the second chip 2 , the first element 11 is disposed on the lower side of the metal layer 21 , and the first element 11 and the metal layer 21 are disposed correspondingly in the up-and-down direction.

[0078] Optionally, the metal density of the area where the metal layer 21 is located is 30% to 50%.

[0079] For example, the metal density of the area where the metal layer 21 is located is 40%.

[0080] By setting the metal density of the area where the metal layer 21 is located to 30% to 50%, the processing and manufacturing of the metal layer 21 is facilitated, and the metal layer 21 can be used to effectively reduce the interference of the signal of the second chip 2 on the first element 11, further improving the signal quality of the packaging structure 10.

[0081] Optionally, the metal layer 21 is electrically connected to a low-speed signal or a power source, and the metal layer 21 forms a circuit.

[0082] By electrically connecting the metal layer 21 to a low-speed signal or power supply, the metal layer 21 can be used as a circuit, so that the metal layer 21 can not only be used to reduce the interference of the signal of the second chip 2 on the first element 11, but also can be used as a circuit, so that the metal layer 21 integrates multiple functions, which is beneficial to improving the integration of the packaging structure 10.

[0083] Alternatively, if Figure 6 As shown, the orthographic projection of the metal layer 21 in the direction toward the first chip 1 at least partially covers the first component 11 .

[0084] Among them, the orthographic projection of the metal layer 21 in the direction toward the first chip 1 at least partially covers the first element 11, which can be understood as: the orthographic projection of the metal layer 21 in the direction toward the first chip 1 covers the first element 11 as a whole; or, the orthographic projection of the metal layer 21 in the direction toward the first chip 1 partially covers the first element 11, and the other part of the orthographic projection of the metal layer 21 in the direction toward the first chip 1 does not cover the first element 11.

[0085] For example, the downward orthographic projection of the metal layer 21 covers the entire first element 11 .

[0086] By setting the orthographic projection of the metal layer 21 in the direction toward the first chip 1 to at least partially cover the entire first element 11 , the signal shielding effect of the metal layer 21 can be improved, further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10 .

[0087] Alternatively, if Figure 6As shown, the area of ​​the orthographic projection of the metal layer 21 in the direction toward the first chip 1 is larger than the area of ​​the region where the first element 11 is located. In other words, the orthographic projection of the metal layer 21 in the direction toward the first chip 1 not only covers the first element 11, but also covers the edge of the first element 11, so as to cover more signals generated by the first element 11.

[0088] By making the area of ​​the metal layer 21's orthographic projection toward the first chip 1 larger than the area of ​​the first element 11 , the signal shielding effect of the metal layer 21 can be further improved, the signal quality of the first element 11 can be further improved, and the signal quality of the packaging structure 10 can be improved.

[0089] Alternatively, if Figures 5 to 9 As shown, the area where the metal layer 21 is located is polygonal.

[0090] For example, Figures 5 to 9 As shown, the area where the metal layer 21 is located is rectangular. Of course, the area where the metal layer 21 is located can also be in the shape of a triangle, a pentagon, a hexagon, an octagon, etc.

[0091] By setting the area where the metal layer 21 is located to be polygonal, the processing and manufacturing of the metal layer 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10.

[0092] Alternatively, if Figures 5 to 7 As shown, the metal layer 21 includes at least one metal portion 213 , and the metal portion 213 is in a comb-teeth shape.

[0093] For example, Figure 5 and Figure 6 As shown, the metal layer 21 includes two metal parts 213 , and both metal parts 213 are in a comb-tooth shape.

[0094] By configuring the metal portion 213 of the metal layer 21 to be comb-shaped, the metal layer 21 is utilized to effectively reduce interference of the signal of the second chip 2 on the first element 11 , thereby further improving the signal quality of the package structure 10 .

[0095] Alternatively, if Figure 5 and Figure 6 As shown, the metal layer 21 includes a plurality of metal parts 213, at least one metal part 213 is a first metal part 211, and at least one metal part 213 is a second metal part 212. Both the first metal part 211 and the second metal part 212 are in a comb-tooth shape.

[0096] By setting the metal layer 21 to include at least one first metal part 211 and at least one second metal part 212, and the first metal part 211 and the second metal part 212 are both set to be comb-tooth shaped, the metal layer 21 is used to effectively reduce the interference of the signal of the second chip 2 on the first element 11, thereby further improving the signal quality of the packaging structure 10.

[0097] Alternatively, if Figure 5 and Figure 6 As shown, the first metal part 211 includes a plurality of first metal strips 2111 arranged side by side, and the second metal part 212 includes a plurality of second metal strips 2121 arranged side by side. The first metal strips 2111 and the second metal strips 2121 are arranged alternately and at intervals.

[0098] For example, Figure 5 and Figure 6 As shown, the first metal part 211 is arranged at the front side of the second metal part 212, and a plurality of first metal strips 2111 and a plurality of second metal strips 2121 are arranged alternately and at intervals along the left-right direction. Figure 5 and Figure 6 As shown, the left and right directions are Figure 5 and Figure 6 shown.

[0099] By setting the metal layer 21 to the above structure, the interference of the signal of the second chip 2 on the first element 11 can be effectively reduced, and the signal quality of the first element 11 and the signal quality of the packaging structure 10 can be further improved.

[0100] Alternatively, if Figure 5 and Figure 6 As shown, the width of the first metal strip 2111 and the second metal strip 2121 is 0.4 μm to 12.5 μm.

[0101] For example, Figure 5 As shown, the width of the first metal strip 2111 and the second metal strip 2121 are both K1, and K1 is 1.8 μm.

[0102] By setting the width of the first metal strip 2111 and the second metal strip 2121 to 0.4 μm to 12.5 μm, the processing and manufacturing of the metal layer 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which is beneficial to reducing the cost of the packaging structure 10 .

[0103] Alternatively, if Figure 5 and Figure 6 As shown, the distance between the first metal strip 2111 and the second metal strip 2121 is 0.4 μm to 25 μm.

[0104] For example, Figure 5 As shown, the distance between the first metal strip 2111 and the second metal strip 2121 is K2, and K2 is 2.7 μm.

[0105] By setting the spacing between the first metal strip 2111 and the second metal strip 2121 to 0.4 μm to 25 μm, the processing and manufacturing of the metal layer 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which is beneficial to reducing the cost of the packaging structure 10 .

[0106] Alternatively, if Figure 8 As shown, the metal layer 21 includes a plurality of metal parts 213, and the plurality of metal parts 213 are evenly arranged along the circumference of the preset rectangular frame, and the metal part 213 includes a plurality of V-shaped metal strips 2131. The plurality of metal strips 2131 of the same metal part 213 are arranged in an interval manner along the inner and outer directions, and the length of the metal strip 2131 located on the outer side is less than the length of the metal strip 2131 located on the inner side. Figure 8 The dotted box in is the preset rectangular box.

[0107] Herein, inward can be understood as: a direction close to the center of the rectangular frame within the plane where the metal layer 21 is located; outward can be understood as: a direction away from the center of the rectangular frame within the plane where the metal layer 21 is located.

[0108] By setting the metal layer 21 to the above structure, the interference of the signal of the second chip 2 on the first element 11 can be effectively reduced, and the signal quality of the first element 11 and the signal quality of the packaging structure 10 can be further improved.

[0109] Alternatively, if Figure 8 As shown, the number of the metal parts 213 is four, and the included angle of the metal strips 2131 is 90°.

[0110] By setting the number of metal parts 213 to four and the angle of the metal strip 2131 to 90°, the processing and manufacturing of the metal layer 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10 , which helps to reduce the cost of the packaging structure 10 .

[0111] Alternatively, if Fig. 9 As shown, the metal layer 21 presents a rectangular pulse signal waveform.

[0112] By setting the metal layer 21 to the above structure, the interference of the signal of the second chip 2 on the first element 11 can be effectively reduced, and the signal quality of the first element 11 can be further improved, and the signal quality of the package structure 10 can be improved. In addition, the metal layer 21 is set to have a rectangular pulse signal waveform, which can also facilitate the processing and manufacturing of the metal layer 21, thereby facilitating the processing and manufacturing of the package structure 10, which is conducive to reducing the cost of the package structure 10.

[0113] Alternatively, if Figure 3 and Figure 4 As shown, the metal layer 21 is disposed on the second chip 2 .

[0114] By setting the metal layer 21 on the second chip 2, the distance between the metal layer 21 and the first element 11 is larger, thereby further reducing the interference of the metal layer 21 on the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0115] Alternatively, if Figure 3 and Figure 4 As shown, the first chip 1 is provided with a plurality of first electrical connectors 13 , and the second chip 2 is provided with a plurality of second electrical connectors 24 , and the second electrical connectors 24 are connected to the first electrical connectors 13 .

[0116] like Figure 3 As shown, the first chip 1 is provided with a first through hole 14, and the first electrical connection member 13 extends to the circuit of the first chip 1 through the first through hole 14. The second chip 2 is provided with a second through hole 25, and the second electrical connection member 24 extends to the circuit of the second chip 2 through the second through hole 25. That is, the first chip 1 and the second chip 2 are connected by hybrid bonding.

[0117] Alternatively, if Figure 3 and Figure 4 As shown, an electrical connection area 102 and a clearance area 103 are provided between the first chip 1 and the second chip 2. Fig.11 As shown, the orthographic projection of the clearance area 103 in the direction toward the first element 11 covers the first element 11 .

[0118] The first electrical connector 13 and the second electrical connector 24 are both disposed in the electrical connection area 102 .

[0119] It is understandable that both the first electrical connector 13 and the second electrical connector 24 are conductive members, which may also interfere with the first element 11 .

[0120] By covering the first element 11 with the orthographic projection of the clearance area 103 in the direction toward the first element 11, the orthographic projections of the first electrical connector 13 and the second electrical connector 24 in the direction toward the first element 11 will not cover the first element 11, thereby reducing the interference of the first electrical connector 13 and the second electrical connector 24 on the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the packaging structure 10.

[0121] Optionally, at the edge of the orthographic projection of the clearance area 103 in the direction toward the first elements 11 , the minimum distance between the first elements 11 is greater than or equal to 5 μm.

[0122] In the present disclosure, the minimum distance between the edge of the orthographic projection of the clearance area 103 in the direction toward the first element 11 and the first element 11 is greater than or equal to: the shortest straight line distance between the orthographic projections of the clearance area 103 and the first element 11 on the plane where the first element 11 is located. Fig.11 As shown, the shortest distance J between the first element 11 and the clearance area 103 is 5 μm.

[0123] Taking the first element 11 as an inductor as an example, the distance between the edge of the positive projection of the clearance area 103 on the first element 11 and the first element 11 will affect the inductance value (L value) and Q value of the inductor element. Fig.12 As shown, the horizontal axis is the minimum distance between the edge of the positive projection of the clearance area 103 on the first element 11 and the first element 11, and the vertical axis is the inductance value (L value) of the inductor element. Fig.13 As shown, the abscissa is the shortest straight line distance between the orthographic projections of the clearance area 103 and the first element 11 on the plane where the first element 11 is located, and the ordinate is the Q value of the inductor element. It can be seen that the minimum distance between the edge of the orthographic projection of the clearance area 103 on the first element 11 and the first element 11 is greater than 5μm, which can well reduce the signal of the second chip 2 and ensure the performance of the first element 11.

[0124] Alternatively, if Fig.10 and Fig.11 As shown, the number of the first elements 11 and the clearance area 103 are both multiple, and the clearance area 103 is arranged corresponding to at least one first element 11.

[0125] For example, Fig.11 As shown, the number of the first elements 11 is nine, and the number of the clearance areas 103 is five. A portion of the clearance areas 103 is arranged corresponding to two first elements 11, and a portion of the clearance areas 103 is arranged corresponding to one first element 11.

[0126] By providing a plurality of first elements 11 and a plurality of clearance areas 103 , a plurality of first elements 11 can be integrated on the same first chip 1 , thereby improving the integration level of the packaging structure 10 .

[0127] Alternatively, if Fig.10 and Fig.11 As shown, the first element 11 is polygonal and the clearance area 103 is polygonal.

[0128] For example, Fig.11 As shown, when the first element 11 is rectangular, the corresponding clearance area 103 is also rectangular. When the first element 11 is octagonal, the corresponding clearance area 103 is also octagonal.

[0129] It is understandable that the first electrical connector 13 and the second electrical connector 24 are not provided in the clearance area 103, resulting in that the first chip 1 and the second chip 2 cannot be connected through the first electrical connector 13 and the second electrical connector 24 in the clearance area 103, thereby reducing the connection area between the first chip 1 and the second chip 2 and reducing the connection stability between the first chip 1 and the second chip 2.

[0130] By setting the first element 11 and the clearance area 103 to be polygonal, the clearance area 103 can cover the corresponding first element 11 when the area is small. In this way, the connection stability between the first chip 1 and the second chip 2 can be improved, and the reliability of the packaging structure 10 can be improved.

[0131] Alternatively, if Figure 8 As shown, the area of ​​the orthographic projection of the clearance area 103 in the direction toward the first element 11 is larger than the area of ​​the region where the first element 11 is located.

[0132] By setting the orthographic projection coverage of the clearance area 103 in the direction toward the first element 11 to be larger than the area where the first element 11 is located, the signal shielding effect of the metal layer 21 can be improved, further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0133] Alternatively, if Fig.11 As shown, the distance D between two adjacent clearance areas 103 is greater than or equal to 20 μm.

[0134] As described above, the clearance area 103 is not provided with the first electrical connector 13 and the second electrical connector 24 , which reduces the connection area of ​​the first chip 1 and the second chip 2 in the clearance area 103 and reduces the connection stability of the first chip 1 and the second chip 2 .

[0135] By setting the distance between two adjacent clearance areas 103 to be greater than or equal to 20 μm, preferably 100 μm, it is possible to avoid excessive density between the clearance areas 103 that affects the connection stability between the first chip 1 and the second chip 2 , thereby improving the reliability of the packaging structure 10 .

[0136] Optionally, the area of ​​the clearance area 103 is less than or equal to 0.08 mm 2 Preferably, the area of ​​the clearance area 103 is 0.0625 mm 2 When the clearance area 103 is smaller than the value described in the embodiment of the present disclosure, the connection stability between the first chip 1 and the second chip 2 can be better ensured.

[0137] As described above, the clearance area 103 is not provided with the first electrical connector 13 and the second electrical connector 24, resulting in that the first chip 1 and the second chip 2 cannot be connected by hybrid bonding in the clearance area 103, affecting the connection stability of the first chip 1 and the second chip 2.

[0138] By setting the area of ​​the clearance area 103 to be less than or equal to 0.08 mm 2 , the area of ​​the unconnected region between the first chip 1 and the second chip 2 can be reduced, the connection stability between the first chip 1 and the second chip 2 can be improved, and the reliability of the packaging structure 10 can be improved.

[0139] Alternatively, if Figure 3 and Figure 4 As shown, the first chip 1 includes a plurality of first wiring layers 101, and the plurality of first wiring layers 101 are arranged along the thickness direction of the package structure 10. At least one first wiring layer 101 is a first top layer 1011, and the first top layer 1011 is arranged closer to the second chip 2 than the remaining first wiring layers 101 in the thickness direction of the package structure 10. The first element 11 is at least partially arranged on the first top layer 1011.

[0140] Among them, the first element 11 is at least partially arranged on the first top layer 1011, which can be understood as: a part of the first element 11 is arranged on the first top layer 1011, and another part of the first element 11 is arranged on other first wiring layers 101 except the first top layer 1011; or, the first element 11 is arranged in its entirety on the first top layer 1011.

[0141] For example, a plurality of first wiring layers 101 are arranged in the up-down direction, one of the first wiring layers 101 is a first top layer 1011, and the first top layer 1011 is located at the uppermost side among the plurality of first wiring layers 101.

[0142] In the embodiment of the present disclosure, among the plurality of first wiring layers 101 , the first wiring layer 101 closer to the second chip 2 has a greater thickness and a smaller resistance.

[0143] By arranging the first element 11 on the first top layer 1011 , the parasitic resistance of the first element 11 can be reduced, thereby increasing the Q value of the first element 11 , further improving the signal quality of the first element 11 , and improving the signal quality of the packaging structure 10 .

[0144] Alternatively, if Figure 3 and Figure 4As shown, the second chip 2 includes a plurality of second wiring layers 201, and the plurality of second wiring layers 201 are arranged along the thickness direction of the package structure 10. At least one second wiring layer 201 is a second top layer 2011, and the second top layer 2011 is arranged closer to the first chip 1 than the remaining second wiring layers 201 in the thickness direction of the package structure 10. The metal layer 21 is at least partially arranged on the second top layer 2011.

[0145] Among them, the metal layer 21 is at least partially arranged on the second top layer 2011, which can be understood as: a part of the metal layer 21 is arranged on the second top layer 2011, and another part of the metal layer 21 is arranged on other second wiring layers 201 except the second top layer 2011; or, the metal layer 21 is entirely arranged on the second top layer 2011.

[0146] For example, the plurality of second wiring layers 201 are arranged in the up-down direction, one of the second wiring layers 201 is the second top layer 2011 , and the second top layer 2011 is located at the bottom of the plurality of second wiring layers 201 .

[0147] It can be understood that, among the plurality of second top layers 2011 , the second wiring layer 201 closer to the first chip 1 has a greater thickness.

[0148] By setting the metal layer 21 on the second top layer 2011, on the one hand, the signal shielding effect of the metal layer 21 can be improved, thereby further improving the signal quality of the first component 11 and the signal quality of the packaging structure 10; on the other hand, the remaining second wiring layer 201 away from the first component 11 can be used as a line, thereby improving the integration of the second chip 2, thereby improving the integration of the packaging structure 10.

[0149] Alternatively, if Figure 3 As shown, the second chip 2 includes a first circuit 22 , and the first circuit 22 is arranged on a side of the metal layer 21 away from the first component 11 in the thickness direction of the package structure 10 .

[0150] By arranging the first circuit 22 of the second chip 2 on the side of the metal layer 21 away from the first component 11 , the interference of the first circuit 22 on the first component 11 can be reduced, thereby improving the signal quality of the first component 11 and the signal quality of the packaging structure 10 .

[0151] Alternatively, if Figure 3 As shown, the first chip 1 further includes a second circuit 12 , which is arranged on at least one side of the first element 11 in a preset direction, and the preset direction is perpendicular to the thickness direction of the packaging structure 10 .

[0152] In order to make the technical solution of the present disclosure easier to understand, the following takes the preset direction and the left-right direction as an example to further describe the technical solution of the present disclosure. Figure 3 and Figure 4 shown.

[0153] For example, the second line 12 is located on both left and right sides of the first element 11 in the left-right direction.

[0154] By arranging the second circuit 12 on at least one side of the first element 11 in a preset direction, compared with arranging the second circuit 12 on a side of the first element 11 away from the metal layer 21 in the preset direction, the interference of the second circuit 12 on the first element 11 can be reduced, thereby further improving the signal quality of the first element 11 and the signal quality of the packaging structure 10.

[0155] Alternatively, if Figure 3 As shown, the second chip 2 further includes a third circuit 23 . The third circuit 23 is arranged on at least one side of the metal layer 21 in a preset direction. The preset direction is perpendicular to the thickness direction of the package structure 10 .

[0156] For example, the third lines 23 are located on both left and right sides of the first element 11 in the left-right direction.

[0157] By arranging the third line 23 on at least one side of the metal layer 21 in a preset direction, the integration level of the second chip 2 can be further improved, thereby improving the integration level of the packaging structure 10 .

[0158] The packaging method of the embodiment of the present disclosure is used to form the packaging structure 10 of any of the above embodiments.

[0159] The packaging method of the embodiment of the present disclosure includes:

[0160] A first component 11 is provided on the first chip 1;

[0161] A metal layer 21 is provided on the second chip 2;

[0162] The first chip 1 and the second chip 2 are stacked, wherein the metal layer 21 is arranged on a side of the second chip 2 close to the first chip 1, the second chip 2 is arranged opposite to the active surface of the first chip 1, and the metal layer 21 is used to reduce the signal interference of the second chip 2 on the first element 11;

[0163] The metal density of the area where the metal layer 21 is located is 20% to 70%.

[0164] In some embodiments, a first element 11 is provided on the first chip 1, including:

[0165] At least one first wiring layer 101 is formed on the active surface of the first chip 1, and the first wiring layer 101 is arranged along the thickness direction of the package structure 10;

[0166] By at least one first wiring layer 101, a first element is formed.

[0167] In some embodiments, the packaging method includes:

[0168] At least one first wiring layer 101 is a first top layer 1011 . The first top layer 1011 is arranged closer to the second chip 2 than the other first wiring layers 101 in the thickness direction of the package structure 10 . The first element 11 is at least partially arranged in the first top layer 1011 .

[0169] In some embodiments, a metal layer 21 is provided on the second chip 2, including:

[0170] At least one second wiring layer 201 is formed on the active surface of the second chip 2, and the second wiring layer 201 is arranged along the thickness direction of the package structure 10;

[0171] The metal layer 21 is formed through at least one second wiring layer 201 .

[0172] The chip stacking structure of the embodiment of the present disclosure includes a substrate and a packaging structure 10 disposed on the substrate, and the packaging structure is the packaging structure 10 described in any of the above embodiments.

[0173] The electronic device of the embodiment of the present disclosure includes a printed circuit board and a packaging structure 10 . The packaging structure 10 is the packaging structure 10 described in any of the above embodiments. The printed circuit board is connected to the packaging structure 10 .

[0174] In the description of the present disclosure, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0175] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, "plurality" means at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0176] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0177] In the present disclosure, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0178] In the present disclosure, the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the described specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, unless they are contradictory.

[0179] Although the embodiments of the present disclosure have been shown and described above, it is to be understood that the above embodiments are illustrative and cannot be construed as limitations on the present disclosure. Changes, modifications, substitutions and variations of the above embodiments by those of ordinary skill in the art are all within the scope of protection of the present disclosure.

Claims

1. A packaging structure, characterized in that: include: A first chip and a second chip stacked on each other, wherein the second chip is arranged opposite to an active surface of the first chip, and a first component is arranged in the first chip; a metal layer, disposed on a side of the first element facing the second chip, the metal layer being used to reduce interference of the signal of the second chip on the first element, The metal density of the area where the metal layer is located is 20% to 70%.

2. The packaging structure according to claim 1, characterized in that: The metal density of the area where the metal layer is located is 30% to 50%.

3. The packaging structure according to claim 1, characterized in that: The metal layer is connected to a low-speed signal, a power supply or a ground.

4. The packaging structure according to claim 1, characterized in that: The area where the metal layer is located is polygonal.

5. The packaging structure according to claim 1, characterized in that: An orthographic projection of the metal layer in a direction toward the first chip at least partially covers the first component.

6. The packaging structure according to claim 5, characterized in that: An area of ​​an orthographic projection of the metal layer in a direction toward the first chip is larger than an area of ​​a region where the first element is located.

7. The packaging structure according to claim 1, characterized in that: The metal layer includes at least one first metal portion and at least one second metal portion.

8. The packaging structure according to claim 7, characterized in that: The first metal part and the second metal part are both in a comb-tooth shape; and / or, The first metal part includes a plurality of first metal strips arranged side by side, and the second metal part includes a plurality of second metal strips arranged side by side. The first metal strips and the second metal strips are arranged alternately and at intervals in sequence.

9. The packaging structure according to claim 8, characterized in that: The width of the first metal strip and the second metal strip is 0.4 μm to 12.5 μm; and / or The distance between the first metal strip and the second metal strip is 0.4 μm to 25 μm.

10. The packaging structure according to claim 1, characterized in that: The metal layer presents a rectangular pulse signal waveform.

11. The packaging structure according to claim 1, characterized in that: The metal layer includes multiple metal parts, and the multiple metal parts are evenly arranged along the circumference of a preset rectangular frame. The metal part includes multiple V-shaped metal strips. The multiple metal strips of the same metal part are arranged at intervals along the inner and outer directions, and the length of the metal strip located on the outer side is smaller than the length of the metal strip located on the inner side.

12. The packaging structure according to claim 11, characterized in that: The number of the metal parts is four, and the included angle of the metal strips is 90°.

13. The packaging structure according to any one of claims 1 to 12, characterized in that: The metal layer is provided by reusing the wiring layer of the second chip.

14. The packaging structure according to claim 13, characterized in that: An electrical connection area and a clearance area are provided between the first chip and the second chip, and the orthographic projection of the clearance area in a direction toward the first element covers the first element.

15. The packaging structure according to claim 14, characterized in that: An area of ​​an orthographic projection of the clearance zone in a direction toward the first element is larger than an area where the first element is located.

16. The packaging structure according to claim 15, characterized in that: A minimum distance between an edge of a normal projection of the clearance area in a direction toward the first element and the first element is greater than or equal to 5 μm.

17. The packaging structure according to claim 13, characterized in that: The first chip includes multiple first wiring layers, which are arranged along the thickness direction of the chip. At least one of the first wiring layers is a first top layer, which is closer to the second chip than the other first wiring layers in the thickness direction of the chip, and the first element is at least partially arranged in the first top layer.

18. The packaging structure according to claim 13, characterized in that: The second chip includes multiple second wiring layers, which are arranged along the thickness direction of the chip, at least one of the second wiring layers is a second top layer, and the second top layer is arranged closer to the first chip than the other second wiring layers in the thickness direction of the chip, and the metal layer is at least partially arranged on the second top layer.

19. The packaging structure according to any one of claims 1 to 12, characterized in that: The first chip is a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

20. The packaging structure according to any one of claims 1 to 12, characterized in that: The first element includes at least one of an inductor, a sensor, and a capacitor.

21. A chip stacking structure, characterized in that: include: substrate; A packaging structure, wherein the packaging structure is the packaging structure according to any one of claims 1 to 20, and the packaging structure is arranged on the substrate.

22. A packaging method, characterized in that: The packaging method is used to form the packaging structure according to any one of claims 1 to 20, and the packaging method comprises: Disposing a first component on a first chip; Disposing a metal layer on the second chip; The first chip and the second chip are stacked, wherein the metal layer is arranged on a side of the second chip close to the first chip, the second chip is arranged opposite to the active surface of the first chip, and the metal layer is used to reduce the signal interference of the second chip on the first element; The metal density of the area where the metal layer is located is 20% to 70%.

23. The packaging method according to claim 22, characterized in that: The first chip is provided with a first element, comprising: forming at least one first wiring layer on the active surface of the first chip, wherein the first wiring layer is arranged along the thickness direction of the package structure; The first element is formed by at least one of the first wiring layers.

24. The packaging method according to claim 23, characterized in that: include: At least one of the first wiring layers is a first top layer, which is arranged closer to the second chip than the other first wiring layers in the thickness direction of the package structure, and the first element is at least partially arranged in the first top layer.

25. The packaging method according to claim 22, characterized in that: The step of providing a metal layer on the second chip includes: forming at least one second wiring layer on the active surface of the second chip, wherein the second wiring layer is arranged along the thickness direction of the package structure; The metal layer is formed through at least one second wiring layer.

26. An electronic device, characterized in that: include: Printed circuit boards; A packaging structure, wherein the packaging structure is the packaging structure according to any one of claims 1 to 20, and the printed circuit board is connected to the packaging structure.

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