Package structure, electronic device, chip stacking structure, and packaging method

Abstract

The present disclosure relates to a packaging structure, an electronic device, a chip stacking structure and a packaging method, the packaging structure comprising a first chip and a second chip stacked with each other and a metal layer, the second chip being arranged opposite to an active surface of the first chip, the first chip being provided with a first element; the metal layer being arranged on a side of the first element facing the second chip, the metal layer being used to reduce interference of a signal of the second chip on the first element, a metal density of an area where the metal layer is located being 20%-70%. The packaging structure of the present disclosure, by arranging the metal layer on a side of the first element facing the second chip and setting the metal density of the area where the metal layer is located as 20%-70%, reduces the interference of the signal of the second chip on the first element by using the metal layer, so that the signal quality of the first element and the signal quality of the packaging structure can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, specifically to a packaging structure, electronic device, chip stacking structure, and packaging method. Background Technology

[0002] Three-dimensional stacked chips can not only achieve high-density vertical interconnection between chips through methods such as hybrid bonding, increasing the equivalent two-dimensional integration density of chips, but also integrate heterogeneous integration at different process nodes, improving the functional density of the system and meeting the ever-increasing computing power demands. However, stacking chips with high integration results in small distances between chips, causing high-speed signals within different chips to interfere with each other and affecting the integrity of high-speed signals. Summary of the Invention

[0003] Firstly, this disclosure proposes a packaging structure to improve the signal quality of a chip.

[0004] The packaging structure disclosed herein includes a first chip and a second chip stacked on top of each other, and a metal layer. The second chip is disposed opposite to the active surface of the first chip, and a first element is disposed within the first chip. The metal layer is disposed on the side of the first element facing the second chip, and the metal layer is used to reduce the interference of the signal from the second chip to the first element. The metal density in the region where the metal layer is located is 20% to 70%.

[0005] Optionally, the metal density in the region where the metal layer is located is 30% to 50%.

[0006] Optionally, the metal layer may be connected to a low-speed signal, a power supply, or ground.

[0007] Optionally, the area containing the metal layer is polygonal.

[0008] Optionally, the metal layer at least partially covers the first element in its orthogonal projection toward the first chip.

[0009] Optionally, the area of ​​the metal layer projected orthogonally toward the first chip is larger than the area of ​​the region where the first element is located.

[0010] Optionally, the metal layer includes at least one first metal portion and at least one second metal portion.

[0011] Optionally, both the first metal portion and the second metal portion are comb-shaped; and / or, the first metal portion includes a plurality of first metal strips arranged side by side, and the second metal portion includes a plurality of second metal strips arranged side by side, wherein the first metal strips and the second metal strips are arranged alternately and at intervals.

[0012] Optionally, the width of the first metal strip and the second metal strip is 0.4 μm to 12.5 μm; and / or, the spacing between the first metal strip and the second metal strip is 0.4 μm to 25 μm.

[0013] Optionally, the metal layer is in the form of a rectangular pulse signal waveform.

[0014] Optionally, the metal layer includes a plurality of metal parts, which are evenly arranged around a preset rectangular frame. Each metal part includes a plurality of V-shaped metal strips, which are spaced apart in the inward and outward directions. The length of the metal strips on the outer side is less than the length of the metal strips on the inner side.

[0015] Optionally, the number of metal parts is four, and the included angle of the metal strips is 90°.

[0016] Optionally, the metal layer is provided by reusing the wiring layer of the second chip.

[0017] Optionally, an electrical connection area and a clearance area are provided between the first chip and the second chip, and the clearance area covers the first element in the orthographic projection toward the first element.

[0018] Optionally, the area of ​​the clearance zone projected orthographically toward the first element is larger than the area of ​​the region where the first element is located.

[0019] Optionally, the minimum distance between the edge of the clearance area projected orthogonally toward the first element and the first element is greater than or equal to 5 μm.

[0020] Optionally, the first chip includes a plurality of first wiring layers arranged along the thickness direction of the chip, at least one of the first wiring layers being a first top layer, the first top layer being disposed closer to the second chip relative to the other first wiring layers in the thickness direction of the chip, and the first element being disposed at least partially on the first top layer.

[0021] Optionally, the second chip includes a plurality of second wiring layers arranged along the thickness direction of the chip, at least one of the second wiring layers being a second top layer, the second top layer being disposed closer to the first chip relative to the other second wiring layers in the thickness direction of the chip, and the metal layer being disposed at least partially on the second top layer.

[0022] Optionally, the first chip is a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

[0023] Optionally, the first element includes at least one of an inductor, a sensor, and a capacitor.

[0024] Secondly, this disclosure proposes a chip stacking structure.

[0025] The chip stacking structure disclosed herein includes a substrate and a packaging structure, wherein the packaging structure is the packaging structure described in any of the above embodiments, and the packaging structure is disposed on the substrate.

[0026] Thirdly, this disclosure proposes an encapsulation method.

[0027] The packaging method disclosed herein is used to form the packaging structure described in any of the above embodiments, the packaging method comprising:

[0028] The first component is set on the first chip;

[0029] A metal layer is placed on the second chip;

[0030] The first chip and the second chip are stacked, wherein the metal layer is disposed on the side of the second chip closer to the first chip, and the second chip is disposed opposite to the active surface of the first chip. The metal layer is used to reduce the signal interference of the second chip to the first component.

[0031] The metal density in the region where the metal layer is located is 20% to 70%.

[0032] Optionally, setting the first element on the first chip includes:

[0033] At least one first wiring layer is formed on the active surface of the first chip, and the first wiring layer is arranged along the thickness direction of the package structure.

[0034] The first element is formed through at least one of the first wiring layers.

[0035] Optionally, the encapsulation method includes:

[0036] At least one of the first wiring layers is a first top layer, and the first top layer is disposed closer to the second chip in the thickness direction of the package structure than the remaining first wiring layers, and the first element is at least partially disposed on the first top layer.

[0037] Optionally, the step of setting a metal layer on the second chip includes:

[0038] At least one second wiring layer is formed on the active surface of the second chip, and the second wiring layer is arranged along the thickness direction of the package structure.

[0039] The metal layer is formed by at least one second wiring layer.

[0040] In this disclosure, the formation of the aforementioned first top layer, second top layer, or shielding layer can be achieved through relevant processes, such as patterning processes, which will not be elaborated in this disclosure.

[0041] Fourthly, this disclosure proposes an electronic device.

[0042] The electronic device disclosed herein includes a printed circuit board and a chip packaging structure, wherein the chip packaging structure is the packaging structure described in any of the above embodiments, and the printed circuit board is connected to the packaging structure.

[0043] The packaging structure disclosed herein improves the signal quality of the first component and the overall signal quality of the packaging structure by placing a metal layer on the side of the first component facing the second chip and setting the metal density in the area where the metal layer is located to 20% to 70%. Attached Figure Description

[0044] Figure 1 This is a cross-sectional view of the packaging structure according to an embodiment of this disclosure.

[0045] Figure 2 This is a partial cross-sectional view of the packaging structure according to an embodiment of this disclosure.

[0046] Figure 3 This is a cross-sectional view of the packaging structure according to another embodiment of this disclosure.

[0047] Figure 4 yes Figure 3 Enlarged view of point A in the middle.

[0048] Figure 5 This is a schematic diagram of the metal layer of the encapsulation structure according to another embodiment of the present disclosure.

[0049] Figure 6 This is a schematic diagram of the metal layer and the first element of the packaging structure according to another embodiment of the present disclosure.

[0050] Figure 7 This is a schematic diagram of the metal layer of the packaging structure according to another embodiment of the present disclosure.

[0051] Figure 8 This is a schematic diagram of the metal layer of the packaging structure in another embodiment of the present disclosure.

[0052] Figure 9 This is a schematic diagram of the metal layer of the packaging structure in another embodiment of the present disclosure.

[0053] Figure 10 This is a schematic diagram of the electrical connection area and clearance area of ​​the packaging structure according to another embodiment of the present disclosure.

[0054] Figure 11 This is a schematic diagram of the electrical connection area, clearance area, and first element of the packaging structure according to another embodiment of the present disclosure.

[0055] Figure 12 and Figure 13 This is a simulation diagram provided in another embodiment of the present disclosure.

[0056] Figure label:

[0057] 10. Packaging structure;

[0058] 1. First chip; 11. First component; 12. Second circuit; 13. First electrical connector; 14. First via; 101. First wiring layer; 1011. First top layer; 102. Electrical connection area; 103. Clearance area;

[0059] 2. Second chip; 21. Metal layer; 211. First metal part; 2111. First metal strip; 212. Second metal part; 2121. Second metal strip; 213. Metal part; 2131. Metal strip; 22. First circuit; 23. Third circuit; 24. Second electrical connector; 25. Second through-hole; 201. Second wiring layer; 2011. Second top layer;

[0060] 100. Package structure; 1001. First chip; 1002. Second chip; 1003. Inductor; 1004. Circuit. Detailed Implementation

[0061] Embodiments of this disclosure are described in detail below, with examples of these embodiments illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this disclosure, and should not be construed as limiting it.

[0062] like Figure 1 and Figure 2 The present disclosure provides an embodiment of the encapsulation structure 100. Figure 1 and Figure 2In the example, inductor 1003 requires a certain size of clearance area to prevent other traces from affecting its Q value and inductance. Because the active surfaces of the first chip 1001 and the second chip 1002 in the package structure 100 are connected by a hybrid bonding method, the distance L between the first chip 1001 and the second chip 1002 is only a few micrometers. The inductor 1003 in the first chip 1001 cannot achieve the required clearance area, and the traces 1004 on the second chip 1002 will interfere with the inductor 1003 in the first chip 1001, reducing the signal quality of the inductor 1003 and further affecting the operation of the first chip 1001. This is especially true in high-speed scenarios, such as transmission speeds exceeding 10 BPS, where the inductor 1003 is more susceptible to the influence of the second chip 1002. Therefore, improving the signal quality of the inductor 1003 in the first chip 1001 is a pressing technical problem that needs to be solved.

[0063] like Figures 3 to 6 As shown, the packaging structure 10 of this embodiment includes a first chip 1 and a second chip 2 stacked on top of each other, and a metal layer 21. The second chip 2 is disposed opposite to and connected to the active surface of the first chip 1. A first element 11 is disposed within the first chip 1, and the metal layer 21 is disposed on the side of the first element 11 facing the second chip 2. The metal layer 21 is used to reduce the interference of the signal from the second chip 2 on the first element 11, and the metal density in the region where the metal layer 21 is located is 20% to 70%.

[0064] Among them, such as Figure 5 As shown, the area within the dashed box represents the region where metal layer 21 is located, and the ratio of the area of ​​metal layer 21 to the area of ​​the dashed box represents the metal density of the region where metal layer 21 is located.

[0065] It should be noted that the chip in the embodiments of this disclosure can be a die (also called a particle or bare chip) or a chip wafer. It is understood that after growing an epitaxial layer on a wafer, the chip wafer is formed, and the chip wafer is then diced to obtain a bare chip. Dies can be bonded to each other (die-to-die bonding, D2D bonding). Chip-wafer bonding is called wafer-to-wafer bonding (W2W bonding). Multiple dies stacked on a chip wafer constitute a structure called die-to-wafer bonding (D2W bonding). The packaging of this disclosure can also be at least one of chip-to-wafer (C2W) bonding, die-to-wafer (D2C) bonding, and chip-to-chip (C2C) bonding.

[0066] This disclosure does not limit the number of chips stacked in the chip stacking structure; the number of chips stacked can be set according to application needs. Furthermore, the aforementioned chips can be memory chips, logic chips, or chips with other functionalities.

[0067] The packaging structure 10 of this disclosure improves the signal quality of the first element 11 and improves the signal quality of the packaging structure 10 by disposing a metal layer 21 on the side of the first element 11 facing the second chip 2 and setting the metal density of the area where the metal layer 21 is located to 20% to 70%. The metal layer 21 reduces the interference of the signal of the second chip 2 to the first element 11, thereby improving the signal quality of the first element 11.

[0068] Optionally, the first chip 1 includes a logic chip and the second chip 2 includes a memory chip; or, both the first chip 1 and the second chip 2 are logic chips.

[0069] Among them, the logic chip can be an application chip, and the memory chip can be a dynamic random access memory chip.

[0070] Optionally, the first element 11 includes...

[0071] It is understandable that the first component could also be other functional devices affected by the second chip, such as sensors, capacitors, etc.

[0072] In this disclosure, the inductor is highly susceptible to the influence of the second chip 2. The solution of this application is preferably used in scenarios where the first element 11 is an inductor. By providing the shielding element 21, the signal interference of the second chip 2 on the inductor, sensor, or capacitor can be reduced or even avoided, thereby improving the signal quality of the package structure 10.

[0073] Optionally, the metal layer 21 can be connected to a low-speed signal, a power supply, or ground.

[0074] When metal layer 21 is connected to a low-speed signal or power supply, it is used as a circuit. When metal layer 21 is grounded, it is not used as a circuit or other electrical component.

[0075] By connecting the metal layer 21 to a low-speed signal, a power supply, or ground, the interference of the signal from the second chip 2 to the first component 11 can be reduced more effectively, thereby further improving the signal quality of the package structure 10.

[0076] To make the technical solution of this disclosure easier to understand, the following description further illustrates the technical solution of this disclosure, taking the case where the thickness direction of the packaging structure 10 is consistent with the vertical direction. Wherein, the vertical direction is as follows... Figure 3 and Figure 4 As shown.

[0077] For example, the first chip 1 is disposed below the second chip 2, the first element 11 is disposed below the metal layer 21, and the first element 11 and the metal layer 21 are disposed correspondingly in the vertical direction.

[0078] Optionally, the metal density in the region where the metal layer 21 is located is 30% to 50%.

[0079] For example, the metal density in the region where metal layer 21 is located is 40%.

[0080] By setting the metal density in the area where the metal layer 21 is located to 30% to 50%, the metal layer 21 can be easily processed and manufactured. At the same time, the metal layer 21 can be used to effectively reduce the interference of the signal of the second chip 2 to the first component 11, thereby further improving the signal quality of the package structure 10.

[0081] Optionally, the metal layer 21 is electrically connected to a low-speed signal or power supply, and the metal layer 21 forms a circuit.

[0082] By electrically connecting the metal layer 21 to a low-speed signal or power supply, the metal layer 21 can be used as a circuit. This allows the metal layer 21 to not only reduce the interference of the signal from the second chip 2 to the first component 11, but also to be used as a circuit. This integrates multiple functions into the metal layer 21, which is beneficial to improving the integration of the package structure 10.

[0083] Optionally, such as Figure 6 As shown, the metal layer 21 at least partially covers the first element 11 in the orthogonal projection toward the first chip 1.

[0084] Wherein, the orthographic projection of the metal layer 21 in the direction toward the first chip 1 at least partially covers the first element 11, which can be understood as: the orthographic projection of the metal layer 21 in the direction toward the first chip 1 completely covers the first element 11; or, a portion of the orthographic projection of the metal layer 21 in the direction toward the first chip 1 covers the first element 11, and another portion of the orthographic projection of the metal layer 21 in the direction toward the first chip 1 does not cover the first element 11.

[0085] For example, the downward projection of the metal layer 21 covers the entire first element 11.

[0086] By setting the orthogonal projection of the metal layer 21 in the direction toward the first chip 1 to at least partially cover the entire first element 11, the signal shielding effect of the metal layer 21 can be improved, the signal quality of the first element 11 can be further improved, and the signal quality of the package structure 10 can be improved.

[0087] Optionally, such as Figure 6As shown, the area of ​​the metal layer 21 projected in the direction toward the first chip 1 is larger than the area of ​​the region where the first element 11 is located. That is, the projected area of ​​the metal layer 21 in the direction toward the first chip 1 not only covers the first element 11, but also covers the edge of the first element 11, so as to cover more of the signal generated by the first element 11.

[0088] By making the area of ​​the metal layer 21 projected in the direction toward the first chip 1 larger than the area of ​​the region where the first element 11 is located, the signal shielding effect of the metal layer 21 can be further improved, the signal quality of the first element 11 can be further improved, and the signal quality of the package structure 10 can be improved.

[0089] Optionally, such as Figures 5 to 9 As shown, the area where the metal layer 21 is located is polygonal.

[0090] For example, such as Figures 5 to 9 As shown, the area containing metal layer 21 is rectangular. Of course, the area containing metal layer 21 can also be triangular, pentagonal, hexagonal, octagonal, or other shapes.

[0091] By setting the area where the metal layer 21 is located to be polygonal, the processing and manufacturing of the metal layer 21 is facilitated, thereby facilitating the processing and manufacturing of the packaging structure 10.

[0092] Optionally, such as Figures 5 to 7 As shown, the metal layer 21 includes at least one metal portion 213, which is comb-shaped.

[0093] For example, such as Figure 5 and Figure 6 As shown, the metal layer 21 includes two metal portions 213, both of which are comb-shaped.

[0094] By setting the metal portion 213 of the metal layer 21 to a comb shape, the interference of the signal from the second chip 2 to the first element 11 is effectively reduced by the metal layer 21, thereby further improving the signal quality of the package structure 10.

[0095] Optionally, such as Figure 5 and Figure 6 As shown, the metal layer 21 includes a plurality of metal portions 213, at least one metal portion 213 being a first metal portion 211, and at least one metal portion 213 being a second metal portion 212. Both the first metal portion 211 and the second metal portion 212 are comb-shaped.

[0096] By configuring the metal layer 21 to include at least one first metal portion 211 and at least one second metal portion 212, and both the first metal portion 211 and the second metal portion 212 to be comb-shaped, the interference of the signal from the second chip 2 to the first element 11 is effectively reduced by the metal layer 21, thereby further improving the signal quality of the package structure 10.

[0097] Optionally, such as Figure 5 and Figure 6 As shown, the first metal part 211 includes a plurality of first metal strips 2111 arranged side by side, and the second metal part 212 includes a plurality of second metal strips 2121 arranged side by side. The first metal strips 2111 and the second metal strips 2121 are arranged alternately and at intervals.

[0098] For example, such as Figure 5 and Figure 6 As shown, a first metal part 211 is disposed on the front side of a second metal part 212, and multiple first metal strips 2111 and multiple second metal strips 2121 are arranged alternately and at intervals in the left-right direction. The front-back direction is as follows: Figure 5 and Figure 6 As shown, the left and right directions are as follows Figure 5 and Figure 6 As shown.

[0099] By setting the metal layer 21 to the above structure, the interference of the signal of the second chip 2 to the first element 11 can be effectively reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the package structure 10 can be improved.

[0100] Optionally, such as Figure 5 and Figure 6 As shown, the widths of the first metal strip 2111 and the second metal strip 2121 are 0.4μm to 12.5μm.

[0101] For example, such as Figure 5 As shown, the width of both the first metal strip 2111 and the second metal strip 2121 is K1, and K1 is 1.8μm.

[0102] By setting the width of the first metal strip 2111 and the second metal strip 2121 to 0.4μm to 12.5μm, the metal layer 21 is facilitated in processing and manufacturing, which in turn facilitates the processing and manufacturing of the packaging structure 10 and helps to reduce the cost of the packaging structure 10.

[0103] Optionally, such as Figure 5 and Figure 6 As shown, the distance between the first metal strip 2111 and the second metal strip 2121 is 0.4μm to 25μm.

[0104] For example, such as Figure 5 As shown, the distance between the first metal strip 2111 and the second metal strip 2121 is K2, and K2 is 2.7μm.

[0105] By setting the spacing between the first metal strip 2111 and the second metal strip 2121 to 0.4μm to 25μm, the metal layer 21 is facilitated in processing and manufacturing, which in turn facilitates the processing and manufacturing of the packaging structure 10 and helps to reduce the cost of the packaging structure 10.

[0106] Optionally, such as Figure 8 As shown, the metal layer 21 includes multiple metal portions 213, which are uniformly arranged circumferentially along a preset rectangular frame. Each metal portion 213 includes multiple V-shaped metal strips 2131. The metal strips 2131 of the same metal portion 213 are spaced apart in the inward and outward directions, with the length of the outermost metal strip 2131 being shorter than the length of the innermost metal strip 2131. Figure 8 The dashed box in the image is a preset rectangle.

[0107] In this context, "inward" can be understood as the direction closer to the center of the rectangle within the plane containing metal layer 21; "outward" can be understood as the direction farther from the center of the rectangle within the plane containing metal layer 21.

[0108] By setting the metal layer 21 to the above structure, the interference of the signal of the second chip 2 to the first element 11 can be effectively reduced, the signal quality of the first element 11 can be further improved, and the signal quality of the package structure 10 can be improved.

[0109] Optionally, such as Figure 8 As shown, there are four metal parts 213, and the included angle of the metal strips 2131 is 90°.

[0110] By setting the number of metal parts 213 to four and the included angle of metal strips 2131 to 90°, the processing and manufacturing of metal layer 21 is facilitated, thereby facilitating the processing and manufacturing of packaging structure 10 and helping to reduce the cost of packaging structure 10.

[0111] Optionally, such as Figure 9 As shown, the metal layer 21 exhibits a rectangular pulse signal waveform.

[0112] By configuring the metal layer 21 as described above, the interference of the signal from the second chip 2 on the first element 11 can be effectively reduced, further improving the signal quality of the first element 11 and the signal quality of the package structure 10. Furthermore, configuring the metal layer 21 as a rectangular pulse signal waveform facilitates its fabrication, thereby simplifying the fabrication of the package structure 10 and reducing its cost.

[0113] Optionally, such as Figure 3 and Figure 4 As shown, metal layer 21 is disposed on the second chip 2.

[0114] By placing the metal layer 21 on the second chip 2, the distance between the metal layer 21 and the first element 11 is larger, thereby further reducing the interference of the metal layer 21 on the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the package structure 10.

[0115] Optionally, such as Figure 3 and Figure 4 As shown, the first chip 1 is provided with a plurality of first electrical connectors 13, and the second chip 2 is provided with a plurality of second electrical connectors 24, and the second electrical connectors 24 are interconnected with the first electrical connectors 13.

[0116] like Figure 3 As shown, the first chip 1 has a first through-hole 14, and the first electrical connector 13 extends through the first through-hole 14 to the circuit of the first chip 1. The second chip 2 has a second through-hole 25, and the second electrical connector 24 extends through the second through-hole 25 to the circuit of the second chip 2. That is, the first chip 1 and the second chip 2 are connected by a hybrid bonding method.

[0117] Optionally, such as Figure 3 and Figure 4 As shown, an electrical connection area 102 and a clearance area 103 are provided between the first chip 1 and the second chip 2. Figure 11 As shown, the orthographic projection of the clearance area 103 in the direction toward the first element 11 covers the first element 11.

[0118] The first electrical connector 13 and the second electrical connector 24 are both located in the electrical connection area 102.

[0119] It is understandable that both the first electrical connector 13 and the second electrical connector 24 are conductive components, which will also interfere with the first element 11.

[0120] By covering the first element 11 with the orthographic projection of the clearance area 103 in the direction toward the first element 11, the orthographic projections of the first electrical connector 13 and the second electrical connector 24 in the direction toward the first element 11 will not cover the first element 11, thereby reducing the interference of the first electrical connector 13 and the second electrical connector 24 to the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the package structure 10.

[0121] Optionally, the clearance area 103 is the edge of the orthographic projection in the direction toward the first element 11, and the minimum distance between the first elements 11 is greater than or equal to 5 μm.

[0122] In this disclosure, the minimum distance between the edge of the clearance area 103 in the orthographic projection toward the first element 11 and the first element 11 is greater than or equal to the shortest straight-line distance between the orthographic projections of the clearance area 103 and the first element 11 onto the plane containing the first element 11. Figure 11 As shown, the shortest distance J between the first element 11 and the clearance area 103 is 5μm.

[0123] Taking the first element 11 as an inductor as an example, the distance between the edge of the clearance area 103 projected onto the first element 11 and the first element 11 affects the inductance value (L value) and Q value of the inductor. For example... Figure 12 As shown, the horizontal axis represents the minimum distance between the edge of the clearance area 103 projected onto the first element 11 and the first element 11, and the vertical axis represents the inductance value (L value) of the inductor. Figure 13 As shown, the horizontal axis represents the shortest straight-line distance between the orthographic projections of the clearance area 103 and the first element 11 onto the plane containing the first element 11, and the vertical axis represents the Q value of the inductor. It can be seen that the minimum distance between the edge of the orthographic projection of the clearance area 103 onto the first element 11 and the first element 11 is greater than 5μm, which effectively reduces the signal of the second chip 2 and ensures the performance of the first element 11.

[0124] Optionally, such as Figure 10 and Figure 11 As shown, there are multiple first elements 11 and multiple clearance areas 103, and each clearance area 103 is provided for at least one first element 11.

[0125] For example, such as Figure 11 As shown, there are nine first elements 11 and five clearance areas 103. Some clearance areas 103 are configured to correspond to two first elements 11, and some clearance areas 103 are configured to correspond to one first element 11.

[0126] By setting multiple first elements 11 and multiple clearance areas 103, multiple first elements 11 can be integrated on the same first chip 1, thereby improving the integration of the package structure 10.

[0127] Optionally, such as Figure 10 and Figure 11 As shown, the first element 11 is polygonal, and the clearance area 103 is polygonal.

[0128] For example, such as Figure 11 As shown, when the first element 11 is rectangular, the corresponding clearance area 103 is also rectangular. When the first element 11 is octagonal, the corresponding clearance area 103 is also octagonal.

[0129] It is understandable that the absence of a first electrical connector 13 and a second electrical connector 24 in the clearance area 103 results in the inability of the first chip 1 and the second chip 2 to be connected through the first electrical connector 13 and the second electrical connector 24 at the clearance area 103, thereby reducing the connection area of ​​the first chip 1 and the second chip 2 and reducing the connection stability of the first chip 1 and the second chip 2.

[0130] By making both the first element 11 and the clearance area 103 polygonal, the corresponding first element 11 can be covered even with a small area of ​​clearance area 103. This improves the connection stability between the first chip 1 and the second chip 2, and enhances the reliability of the package structure 10.

[0131] Optionally, such as Figure 8 As shown, the area of ​​the clearance area 103 projected in the direction toward the first element 11 is greater than the area of ​​the region where the first element 11 is located.

[0132] By setting the orthogonal projection coverage of the clearance area 103 in the direction toward the first element 11 to be greater than the area of ​​the region where the first element 11 is located, the signal shielding effect of the metal layer 21 can be improved, the signal quality of the first element 11 can be further improved, and the signal quality of the package structure 10 can be improved.

[0133] Optionally, such as Figure 11 As shown, the distance D between two adjacent clearance zones 103 is greater than or equal to 20 μm.

[0134] As described above, the absence of the first electrical connector 13 and the second electrical connector 24 in the clearance area 103 reduces the connection area of ​​the first chip 1 and the second chip 2 in the clearance area 103, thereby reducing the connection stability of the first chip 1 and the second chip 2.

[0135] By setting the distance between two adjacent clearance areas 103 to be greater than or equal to 20 μm, preferably 100 μm, the density between clearance areas 103 can be avoided from being too high, which would affect the connection stability between the first chip 1 and the second chip 2 and improve the reliability of the packaging structure 10.

[0136] Optionally, the area of ​​the clearance zone 103 is less than or equal to 0.08 mm. 2 Preferably, the area of ​​the clearance zone 103 is 0.0625 mm². 2 When the clearance area 103 is smaller than the value described in the embodiments of this disclosure, the connection stability between the first chip 1 and the second chip 2 can be better guaranteed.

[0137] As described above, the absence of a first electrical connector 13 and a second electrical connector 24 in the clearance area 103 results in the inability of the first chip 1 and the second chip 2 to be connected via a hybrid bonding method in the clearance area 103, thus affecting the connection stability of the first chip 1 and the second chip 2.

[0138] By setting the area of ​​the clearance zone 103 to be less than or equal to 0.08 mm 2 This can reduce the area of ​​the unconnected region between the first chip 1 and the second chip 2, improve the connection stability of the first chip 1 and the second chip 2, and improve the reliability of the packaging structure 10.

[0139] Optionally, such as Figure 3 and Figure 4 As shown, the first chip 1 includes a plurality of first wiring layers 101, which are arranged along the thickness direction of the package structure 10. At least one first wiring layer 101 is a first top layer 1011, which is disposed closer to the second chip 2 in the thickness direction of the package structure 10 than the other first wiring layers 101. A first element 11 is at least partially disposed on the first top layer 1011.

[0140] Wherein, the first element 11 is at least partially disposed on the first top layer 1011, which can be understood as: a part of the first element 11 is disposed on the first top layer 1011, and another part of the first element 11 is disposed on other first wiring layers 101 other than the first top layer 1011; or, the first element 11 is entirely disposed on the first top layer 1011.

[0141] For example, multiple first wiring layers 101 are arranged in a vertical direction. One of the first wiring layers 101 is the first top layer 1011, and the first top layer 1011 is located at the top of the multiple first wiring layers 101.

[0142] In this embodiment of the disclosure, among the plurality of first wiring layers 101, the first wiring layer 101 closer to the second chip 2 has a larger thickness and a smaller resistance.

[0143] By placing the first element 11 in the first top layer 1011, the parasitic resistance of the first element 11 can be reduced, thereby increasing the Q value of the first element 11, further improving the signal quality of the first element 11, and improving the signal quality of the package structure 10.

[0144] Optionally, such as Figure 3 and Figure 4As shown, the second chip 2 includes a plurality of second wiring layers 201, which are arranged along the thickness direction of the package structure 10. At least one second wiring layer 201 is a second top layer 2011, which is disposed closer to the first chip 1 in the thickness direction of the package structure 10 than the other second wiring layers 201. A metal layer 21 is at least partially disposed on the second top layer 2011.

[0145] The metal layer 21 is at least partially disposed on the second top layer 2011, which can be understood as: a part of the metal layer 21 is disposed on the second top layer 2011, and another part of the metal layer 21 is disposed on other second wiring layers 201 other than the second top layer 2011; or, the metal layer 21 is entirely disposed on the second top layer 2011.

[0146] For example, multiple second wiring layers 201 are arranged in a vertical direction. One of the second wiring layers 201 is the second top layer 2011, and the second top layer 2011 is located at the bottom of the multiple second wiring layers 201.

[0147] It is understandable that among the multiple second top layers 2011, the thickness of the second wiring layer 201 that is closer to the first chip 1 is greater.

[0148] By setting the metal layer 21 on the second top layer 2011, on the one hand, the signal shielding effect of the metal layer 21 can be improved, thereby further improving the signal quality of the first element 11 and the signal quality of the package structure 10; on the other hand, the remaining second wiring layer 201 far away from the first element 11 can be used as a line, improving the integration of the second chip 2 and thus improving the integration of the package structure 10.

[0149] Optionally, such as Figure 3 As shown, the second chip 2 includes a first line 22, which is disposed on the side of the metal layer 21 away from the first element 11 in the thickness direction of the package structure 10.

[0150] By placing the first line 22 of the second chip 2 on the side of the metal layer 21 away from the first element 11, the interference of the first line 22 to the first element 11 can be reduced, thereby improving the signal quality of the first element 11 and the signal quality of the package structure 10.

[0151] Optionally, such as Figure 3 As shown, the first chip 1 also includes a second line 12, which is disposed on at least one side of the first element 11 in a preset direction, the preset direction being perpendicular to the thickness direction of the package structure 10.

[0152] To make the technical solution of this disclosure easier to understand, the following description further illustrates the technical solution of this disclosure using the example of a preset direction that is consistent with the left and right directions. Wherein, the left and right directions are as follows... Figure 3 and Figure 4 As shown.

[0153] For example, the second line 12 is located on the left and right sides of the first element 11 in the left-right direction.

[0154] By arranging the second line 12 in a preset direction on at least one side of the first element 11, compared to arranging the second line 12 in a preset direction on the side of the first element 11 away from the metal layer 21, the interference of the second line 12 on the first element 11 can be reduced, thereby further improving the signal quality of the first element 11 and the signal quality of the package structure 10.

[0155] Optionally, such as Figure 3 As shown, the second chip 2 also includes a third line 23, which is disposed on at least one side of the metal layer 21 in a preset direction, the preset direction being perpendicular to the thickness direction of the packaging structure 10.

[0156] For example, the third line 23 is located on the left and right sides of the first element 11 in the left-right direction.

[0157] By placing the third line 23 on at least one side of the metal layer 21 in a preset direction, the integration of the second chip 2 can be further improved, thereby improving the integration of the package structure 10.

[0158] The packaging method of this disclosure is used to form the packaging structure 10 of any of the above embodiments.

[0159] The encapsulation method of this disclosure includes:

[0160] A first element 11 is disposed on the first chip 1;

[0161] A metal layer 21 is disposed on the second chip 2;

[0162] The first chip 1 and the second chip 2 are stacked, wherein a metal layer 21 is disposed on the side of the second chip 2 close to the first chip 1, and the second chip 2 is disposed opposite to the active surface of the first chip 1. The metal layer 21 is used to reduce the signal interference of the second chip 2 to the first element 11.

[0163] The metal density in the region where metal layer 21 is located is 20% to 70%.

[0164] In some embodiments, a first element 11 is disposed on the first chip 1, including:

[0165] At least one first wiring layer 101 is formed on the active surface of the first chip 1, and the first wiring layer 101 is arranged along the thickness direction of the package structure 10.

[0166] A first element is formed through at least one first wiring layer 101.

[0167] In some embodiments, the encapsulation method includes:

[0168] At least one first wiring layer 101 is a first top layer 1011, which is disposed closer to the second chip 2 in the thickness direction of the package structure 10 than the other first wiring layers 101, and the first element 11 is at least partially disposed in the first top layer 1011.

[0169] In some embodiments, a metal layer 21 is provided on the second chip 2, including:

[0170] At least one second wiring layer 201 is formed on the active surface of the second chip 2, and the second wiring layer 201 is arranged along the thickness direction of the package structure 10.

[0171] A metal layer 21 is formed through at least one second wiring layer 201.

[0172] The chip stacking structure of this disclosure includes a substrate and a packaging structure 10 disposed on the substrate, wherein the packaging structure is the packaging structure 10 described in any of the above embodiments.

[0173] The electronic device of this disclosure includes a printed circuit board and a package structure 10, wherein the package structure 10 is the package structure 10 described in any of the above embodiments, and the printed circuit board is connected to the package structure 10.

[0174] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0175] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0176] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between components; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0177] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can mean that the first and second features are in direct contact, or that the first and second features are in indirect contact through an intermediate medium. Furthermore, "above," "on top of," and "over" the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0178] In this disclosure, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to a specific feature, structure, material, or characteristic described in connection with that embodiment or example, which is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0179] Although embodiments of the present disclosure have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Any changes, modifications, substitutions and variations made to the above embodiments by those skilled in the art are within the scope of protection of the present disclosure.

Claims

1. A packaging structure, characterized in that, include: A first chip and a second chip are stacked on top of each other, with the active surface of the second chip facing the active surface of the first chip, and a first element is disposed within the first chip; A metal layer is disposed on the side of the first component facing the second chip. The metal layer is used to reduce interference from the signal from the second chip to the first component. The metal density in the region where the metal layer is located is 20% to 70%; A clearance area is provided between the first chip and the second chip. The clearance area covers the first element in the orthographic projection toward the first element. The first chip includes a plurality of first wiring layers. The plurality of first wiring layers are arranged along the thickness direction of the chip. Among the plurality of first wiring layers, the first wiring layer closer to the second chip has a larger thickness. At least one first wiring layer is a first top layer. The first top layer is disposed closer to the second chip in the thickness direction of the chip than the other first wiring layers. The first element is at least partially disposed on the first top layer.

2. The packaging structure according to claim 1, characterized in that, The metal density in the region where the metal layer is located is 30% to 50%.

3. The packaging structure according to claim 1, characterized in that, The metal layer is connected to a low-speed signal, a power supply, or ground.

4. The packaging structure according to claim 1, characterized in that, The area containing the metal layer is polygonal.

5. The packaging structure according to claim 1, characterized in that, The metal layer, when projected orthogonally toward the first chip, at least partially covers the first element.

6. The packaging structure according to claim 5, characterized in that, The area of ​​the metal layer projected orthogonally toward the first chip is greater than the area of ​​the region where the first element is located.

7. The packaging structure according to claim 1, characterized in that, The metal layer includes at least one first metal portion and at least one second metal portion.

8. The packaging structure according to claim 7, characterized in that, Both the first metal portion and the second metal portion are comb-shaped; and / or, The first metal part includes a plurality of first metal strips arranged side by side, and the second metal part includes a plurality of second metal strips arranged side by side, wherein the first metal strips and the second metal strips are arranged alternately and at intervals.

9. The packaging structure according to claim 8, characterized in that, The widths of the first metal strip and the second metal strip are 0.4 μm to 12.5 μm; and / or The spacing between the first metal strip and the second metal strip is 0.4 μm to 25 μm.

10. The packaging structure according to claim 1, characterized in that, The metal layer exhibits a rectangular pulse signal waveform.

11. The packaging structure according to claim 1, characterized in that, The metal layer includes multiple metal parts, which are evenly arranged around a preset rectangular frame. Each metal part includes multiple V-shaped metal strips, which are spaced apart in the inward and outward directions. The length of the metal strips on the outer side is shorter than the length of the metal strips on the inner side.

12. The packaging structure according to claim 11, characterized in that, The number of metal parts is four, and the included angle of the metal strips is 90°.

13. The packaging structure according to any one of claims 1-12, characterized in that, The metal layer is provided by reusing the wiring layer of the second chip.

14. The packaging structure according to claim 13, characterized in that, An electrical connection area is provided between the first chip and the second chip.

15. The packaging structure according to claim 14, characterized in that, The area of ​​the clearance zone projected orthogonally toward the first element is greater than the area of ​​the region where the first element is located.

16. The packaging structure according to claim 15, characterized in that, The minimum distance between the edge of the clearance area projected orthogonally toward the first element and the first element is greater than or equal to 5 μm.

17. The packaging structure according to claim 13, characterized in that, The second chip includes a plurality of second wiring layers arranged along the thickness direction of the chip, at least one of the second wiring layers being a second top layer, the second top layer being disposed closer to the first chip in the thickness direction of the chip than the other second wiring layers, and the metal layer being disposed at least partially on the second top layer.

18. The packaging structure according to any one of claims 1-12, characterized in that, The first chip is a logic chip, and the second chip includes a memory chip; or, both the first chip and the second chip are logic chips.

19. The packaging structure according to any one of claims 1-12, characterized in that, The first element includes at least one of an inductor, a sensor, and a capacitor.

20. A chip stacking structure, characterized in that, include: substrate; The packaging structure is the packaging structure according to any one of claims 1-19, and the packaging structure is disposed on the substrate.

21. A packaging method, characterized in that, The encapsulation method is used to form the encapsulation structure according to any one of claims 1-19, the encapsulation method comprising: The first component is set on the first chip; A metal layer is placed on the second chip; The first chip and the second chip are stacked, wherein the metal layer is disposed on the side of the second chip closer to the first chip, and the second chip is disposed opposite to the active surface of the first chip. The metal layer is used to reduce the signal interference of the second chip to the first component. The metal density in the region where the metal layer is located is 20% to 70%.

22. The packaging method according to claim 21, characterized in that, The step of setting the first element on the first chip includes: At least one first wiring layer is formed on the active surface of the first chip, and the first wiring layer is arranged along the thickness direction of the package structure. The first element is formed through at least one of the first wiring layers.

23. The packaging method according to claim 22, characterized in that, include: At least one of the first wiring layers is a first top layer, and the first top layer is disposed closer to the second chip in the thickness direction of the package structure than the remaining first wiring layers, and the first element is at least partially disposed on the first top layer.

24. The packaging method according to claim 21, characterized in that, The step of setting a metal layer on the second chip includes: At least one second wiring layer is formed on the active surface of the second chip, and the second wiring layer is arranged along the thickness direction of the package structure. The metal layer is formed by at least one second wiring layer.

25. An electronic device, characterized in that, include: Printed circuit boards; The packaging structure is the packaging structure according to any one of claims 1-19, and the printed circuit board is connected to the packaging structure.

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