Over-current dead zone wave sealing circuit and energy storage power supply

Abstract

The invention relates to the technical field of power supplies, and mainly provides an overcurrent dead-zone wave sealing circuit and an energy storage power supply, the circuit comprises a dead-zone detection module, a first logic module connected with the dead-zone detection module, and a second logic module connected with the first logic module, the first logic module is also used for connecting a current detection module, and the second logic module is also used for connecting a current detection module. The second logic module is used for connecting a bridge circuit. The dead zone detection module is used for outputting a first control signal to the first logic module when the received first driving signal and the second driving signal are both low-level signals, so that the first logic module outputs a wave sealing signal to the second logic module according to an overcurrent signal and the first control signal when receiving the overcurrent signal; therefore, the second logic module controls the bridge circuit to stop working based on the wave sealing signal and the two driving signals so as to control soft switching of a power tube in the bridge circuit in the dead zone of the driving signals, the situation that the power tube is turned off in the case of large current is avoided, and the reliability of the energy storage power supply is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of power supplies, and in particular to an overcurrent dead zone wave blocking circuit and an energy storage power supply. Background Art

[0002] With the rapid development of power electronics technology, power supply products are increasingly widely used in the field of modern science and technology, and their types and forms are becoming increasingly diverse. In terms of reliability, the extreme protection capabilities under various abnormal conditions, such as high reliability of overvoltage protection and overcurrent protection, have attracted much attention. In the design process of power supply products, the choice of power supply topology plays a decisive role in whether the product can meet the above requirements.

[0003] Among them, LLC resonant topology is widely used in various power supply design solutions because it can effectively achieve high efficiency. However, when the back stage of the LLC resonant topology circuit encounters an overcurrent anomaly, the current sampling circuit detects that the current exceeds the threshold and outputs a fault signal. If the PWM drive of the switch tube is directly shut down, especially when the overcurrent blocking wave occurs at the maximum current point in the upper tube conduction interval, the current will instantly turn to the lower tube diode loop because the current of inert components such as the resonant cavity inductor cannot change suddenly. In this process, due to the high current peak, the forced blocking wave of the upper tube will cause a large dV / dT, causing the lower tube diode to quickly change from reverse cutoff to forward conduction, and the reverse recovery time characteristics of the diode make it very easy for the upper tube to generate a large voltage spike. In addition, under normal circumstances of the LLC resonant topology, the switch tube can be selected based on a voltage value close to BAT+ to meet the design, but when the switch tube is forced to be blocked at the current peak point to turn off the switch tube, it cannot withstand the high voltage spike according to the conventional selection, and the switch tube faces the risk of burning. Summary of the invention

[0004] The embodiments of the present invention mainly provide an overcurrent dead zone wave blocking circuit and an energy storage power supply, aiming to solve the technical problems in the prior art that when an overcurrent fault occurs in a power supply circuit, a switch tube is easily burned out and the power supply reliability is low.

[0005] In order to solve the above technical problems, a technical solution adopted by the embodiment of the present invention is: providing an overcurrent dead zone wave blocking circuit, applied to a bridge circuit, the overcurrent dead zone wave blocking circuit comprising a dead zone detection module, a first logic module and a second logic module;

[0006] The dead zone detection module is connected to the first logic module, the first logic module is connected to the second logic module, the first logic module is further used to connect to the current detection module, and the second logic module is used to connect to the bridge circuit;

[0007] The dead zone detection module is used to receive a first drive signal and a second drive signal, and output a first control signal to the first logic module when the first drive signal and the second drive signal are both low level signals;

[0008] The first logic module is used to receive the detection signal output by the current detection module, and when the detection signal is an overcurrent signal and the dead zone detection module outputs the first control signal, output a wave-sealing signal to the second logic module;

[0009] The second logic module receives the first drive signal and the second drive signal respectively, and drives the bridge circuit to stop working when the wave-enclosing signal is received; and when the wave-enclosing signal is not received, drives the first power tube of the bridge circuit to work in response to the first drive signal, and drives the second power tube of the bridge circuit to work in response to the second drive signal.

[0010] Optionally, the overcurrent dead zone wave blocking circuit further includes a control module;

[0011] The control module is connected to the second logic module;

[0012] The control module is used for outputting a locking signal to the second logic module after the second logic module receives the envelope signal for a first preset time, so that the second logic module continuously drives the bridge circuit to stop working.

[0013] Optionally, the second logic module includes a logic driving unit and a delay unit;

[0014] The logic drive unit is connected to the first logic module, the logic drive unit is also connected to the control module, the delay unit is connected to the logic drive unit, and the logic drive unit is also used to receive the first drive signal and the second drive signal, wherein the first drive signal and the second drive signal are both pulse signals;

[0015] The logic driving unit is used for outputting a first voltage signal to drive the bridge circuit to stop working when the first driving signal and the second driving signal are both low-level signals and the envelope signal is received; and

[0016] When the wave-enclosing signal is not received and the first driving signal is a high-level signal, a second voltage signal is output to the first power tube to drive the first power tube to work; or when the wave-enclosing signal is not received and the second driving signal is a high-level signal, a second voltage signal is output to the second power tube to drive the second power tube to work;

[0017] The delay unit is used to delay the output of the first drive signal or the second drive signal to the logic drive unit for a second preset time after the bridge circuit stops working and when the first drive signal or the second drive signal is a high-level signal, so that the logic drive unit continues to drive the bridge circuit to stop working according to the locking signal, wherein the first preset time is less than the second preset time.

[0018] Optionally, the second logic module further includes a logic locking unit;

[0019] The logic locking unit is connected to the logic driving unit, and the logic locking unit is further used to receive the first driving signal and the second driving signal;

[0020] The logic locking unit is used for outputting a shutdown signal to the logic driving unit when the first driving signal and the second driving signal are both at high levels, so that the logic driving unit drives the bridge circuit to stop working according to the shutdown signal.

[0021] Optionally, the logic driving unit includes an AND gate U2A, an AND gate U2B and a diode D1;

[0022] The first input end of the AND gate U2A is used to receive the first drive signal, the second input end of the AND gate U2A is respectively connected to the anode of the diode D1 and the first power supply, the output end of the AND gate U2A is connected to the first power tube, the cathode of the diode D1 is connected to the first logic module, the first input end of the AND gate U2B is used to receive the second drive signal, the second input end of the AND gate U2B is connected to the second input end of the AND gate U2A, the second input end of the AND gate U2B is also connected to the control module, and the output end of the AND gate U2B is connected to the second power tube.

[0023] Optionally, the delay unit includes a capacitor C1;

[0024] The capacitor C1 is connected to the second input terminal of the AND gate U2A, and the capacitor C1 is also used for grounding.

[0025] Optionally, the overcurrent dead zone wave blocking circuit further includes a first interlocking module;

[0026] The first interlocking module is connected to the logic driving unit, and the first interlocking module is also connected to the first power tube in the bridge circuit and the second power tube in the bridge circuit;

[0027] The first interlocking module is used for controlling the bridge circuit to stop working according to the first voltage signal when the logic driving unit outputs the first voltage signal; and

[0028] When the logic driving unit outputs a second voltage signal, the first power tube or the second power tube is controlled to operate according to the second voltage signal.

[0029] Optionally, the first interlocking module includes a first interlocking unit and a second interlocking unit;

[0030] The first end of the first interlock unit is connected to the first output end of the logic drive unit, the second end of the first interlock unit is connected to the second output end of the logic drive unit, the output end of the first interlock unit is connected to the first power tube, the first end of the second interlock unit is connected to the second output end of the logic drive unit, the second end of the second interlock unit is connected to the first output end of the logic drive unit, and the output end of the second interlock unit is connected to the second power tube;

[0031] When the first output terminal of the logic driving unit and the second output terminal of the logic driving unit both output a first voltage signal, the first interlocking unit is configured to control the first power tube to stop working according to the first voltage signal, and the second interlocking unit is configured to control the second power tube to stop working according to the first voltage signal;

[0032] When the first output terminal of the logic driving unit outputs a second voltage signal and the second output terminal of the logic driving unit outputs a first voltage signal, the first interlocking unit is configured to control the first power tube to work according to the second voltage signal, and the second interlocking unit is configured to control the second power tube to stop working according to the first voltage signal;

[0033] When the first output end of the logic driving unit outputs a first voltage signal and the second output end of the logic driving unit outputs a second voltage signal, the first interlocking unit is configured to control the first power tube to stop working according to the first voltage signal, and the second interlocking unit is configured to control the second power tube to work according to the second voltage signal.

[0034] Optionally, the first interlocking unit includes an optical coupler U3, a resistor R2, a resistor R3 and a capacitor C2;

[0035] The first input end of the optocoupler U3 is connected to the first output end of the logic driving unit through the resistor R2, the second input end of the optocoupler U3 is connected to the second output end of the logic driving unit, the output end of the optocoupler U3 is connected to the first power tube, the capacitor C2 is respectively connected to the first input end of the optocoupler U3 and the second input end of the optocoupler U3, and the resistor R3 is connected in parallel with the capacitor C2.

[0036] In order to solve the above technical problems, another technical solution adopted in the embodiment of the present invention is: to provide an energy storage power supply, the energy storage power supply comprising:

[0037] Bridge circuit;

[0038] Batteries; and

[0039] The overcurrent dead-band wave-blocking circuit as described above, wherein the battery is connected to the bridge circuit, and the bridge circuit is connected to the overcurrent dead-band wave-blocking circuit.

[0040] Different from the related art, the present invention provides an overcurrent dead zone wave-sealing circuit and an energy storage power supply, which are applied to a bridge circuit. The overcurrent dead zone wave-sealing circuit includes a dead zone detection module, a first logic module and a second logic module; the dead zone detection module is connected to the first logic module, the first logic module is connected to the second logic module, the first logic module is also used to connect to the current detection module, and the second logic module is used to connect to the bridge circuit. The dead zone detection module is used to receive the first drive signal and the second drive signal, and when the first drive signal and the second drive signal are both low-level signals, output a first control signal to the first logic module; the first logic module is used to receive the detection signal output by the current detection module, and when the detection signal is an overcurrent signal and the dead zone detection module outputs the first control signal, output a wave-sealing signal to the second logic module, so that the second logic module controls the bridge circuit to stop working based on the wave-sealing signal, the first drive signal and the second drive signal, thereby controlling the soft switch of the power tube in the bridge circuit when the first drive signal and the second drive signal are in the dead zone, avoiding the situation where the power tube is shut down under high voltage and high current, thereby improving the reliability of the energy storage power supply. When the second logic module does not receive the wave-enclosing signal, it drives the first power tube of the bridge circuit to work in response to the first drive signal, and drives the second power tube of the bridge circuit to work in response to the second drive signal, so that the energy storage power supply outputs the power supply voltage normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0042] Figure 1 is a schematic diagram of an application scenario provided by an embodiment of the present invention;

[0043] Figure 2 is a circuit diagram of an energy storage power supply provided by an embodiment of the present invention;

[0044] Figure 3 is a waveform diagram between PWM drive and resonant current of a bridge circuit provided by an embodiment of the present invention;

[0045] Figure 4 It is a structural block diagram of an overcurrent dead zone wave blocking circuit provided by an embodiment of the present invention;

[0046] Figure 5 is a circuit diagram of an overcurrent dead zone wave-sealing circuit provided by an embodiment of the present invention;

[0047] Figure 6 It is a timing diagram of an overcurrent dead zone wave blocking circuit provided by an embodiment of the present invention;

[0048] Figure 7 is a circuit diagram of an overcurrent dead zone wave blocking circuit provided by another embodiment of the present invention;

[0049] Figure 8 is a circuit diagram of an interlocking module provided by an embodiment of the present invention;

[0050] Fig. 9 is a circuit diagram of an interlocking module provided in another embodiment of the present invention. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0052] It should be noted that, if there is no conflict, the various features in the embodiments of the present invention can be combined with each other, and all are within the protection scope of the present invention. In addition, although the functional modules are divided in the device schematic diagram and the logical order is shown in the flow chart, in some cases, the steps shown or described can be performed in a different order from the module division in the device schematic diagram or the order in the flow chart.

[0053] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0054] See also Figure 1 , Figure 1 is a schematic diagram of an application scenario provided by an embodiment of the present invention, such as Figure 1As shown, the application scenario 1 includes an energy storage power supply 100 and a load 200 , wherein the energy storage power supply 100 is connected to the load 200 , and the energy storage power supply 100 is used to output a supply voltage to the load 200 to supply power to the load 200 .

[0055] Among them, Figure 1 As shown, the energy storage power supply 100 includes a battery 10, a bridge circuit 20, an LLC resonant circuit 30 and a high-voltage side rectifier circuit 40; the bridge circuit 20 is connected to the battery 10 and the LLC resonant circuit 30 respectively, the LLC resonant circuit 30 is connected to the high-voltage side rectifier circuit 40, and the high-voltage side rectifier circuit 40 is also connected to the load 200. The LLC resonant circuit 30 is used to adjust the resonant frequency according to the opening condition of the power tube in the bridge circuit 20, so as to convert the output voltage of the battery 10 into a target voltage and output it to the load 200, thereby providing a suitable power supply voltage for the load 200.

[0056] It should be noted that, during the process of the energy storage power supply 100 being the load 200, if the load 200 has a short circuit or other faults, the current in the high-voltage side rectifier circuit 40 will increase abnormally. At this time, it is necessary to forcibly shut down the output of the LLC resonant circuit 30 according to the current, and if the power tube is turned off at the highest current point, the peak voltage of the power tube will be too high, damaging the power tube. Therefore, in order to extend the service life of the energy storage power supply 100, it is necessary to detect the output current of the bridge circuit 20 in real time when the energy storage power supply 100 is working, so that when an overcurrent fault occurs in the energy storage power supply 100, the bridge circuit 20 is turned off at zero current (i.e., dead time), so that the bridge circuit 20 stops working, thereby protecting the energy storage power supply 100.

[0057] In some embodiments, the energy storage power supply 100 further includes an overcurrent dead zone wave-enclosing circuit 50, and the LLC resonant circuit 30 further includes a current detection module 31, the current detection module 31 is connected to the bridge circuit 20, the current detection module 31 is also connected to the overcurrent dead zone wave-enclosing circuit 50, and the overcurrent dead zone wave-enclosing circuit 50 is also connected to the bridge circuit 20. The current detection module 31 is used to collect the output current of the bridge circuit 20, and judge whether an overcurrent fault occurs in the energy storage power supply 100 based on the output current. Specifically, when the current detection module 31 collects the output current of the bridge circuit 20, it will determine whether the output current exceeds the current threshold, and when the output current exceeds the current threshold, it will determine that the high-voltage side rectifier circuit 40 has an overcurrent fault, thereby outputting an overcurrent signal to the overcurrent dead-band wave-blocking circuit 50, so that the overcurrent dead-band wave-blocking circuit 50 controls the bridge circuit 20 to stop working according to the overcurrent signal, thereby stopping outputting the target voltage to the load 200, thereby protecting the energy storage power supply 100.

[0058] It should be noted that the bridge circuit 20 mainly controls the output voltage of the LLC resonant circuit 30 through the power tube. Figure 2 , Figure 2 is a circuit diagram of an energy storage power supply provided by an embodiment of the present invention, such as Figure 2 As shown, the bridge circuit 20 can also be a full-bridge circuit, that is, the bridge circuit 20 includes a first power tube Q1, a second power tube Q2, a third power tube Q3 and a fourth power tube Q4, the first power tube Q1 and the second power tube Q2 are connected in series, the third power tube Q3 and the fourth power tube Q4 are connected in series, and the first power tube Q1 and the second power tube Q2 after the series connection are also connected in parallel with the third power tube Q3 and the fourth power tube Q4 after the series connection; wherein, the first power tube Q1 and the second power tube Q2 work alternately, the third power tube Q3 and the fourth power tube Q4 work alternately, and the first power tube Q1 and the fourth power tube Q4 are in the same conduction state. In another embodiment, the bridge circuit 20 can be a half-bridge circuit, that is, the bridge circuit 20 includes a first power tube Q1 and a second power tube Q2, the first power tube Q1 and the second power tube Q2 are connected in series with each other, and the first power tube Q1 and the second power tube Q2 are alternately turned on, so as to control the LLC resonant circuit 30 to output the target voltage.

[0059] In some embodiments, Figure 2 As shown, the LLC resonant circuit 30 includes a resonant capacitor Cr, a resonant inductor Lr and a transformer T1, and the bridge circuit 20 is a full-bridge circuit. The bridge circuit 20 controls the voltage stored in the resonant capacitor Cr and the resonant inductor Lr by controlling the on and off of the power tube, thereby changing the output voltage.

[0060] See also Figure 3 , Figure 3 is a waveform diagram between the PWM drive and the resonant current of the bridge circuit provided by the embodiment of the present invention, combined with Figure 2 and Figure 3 It can be seen that the PWM drive also includes a dead time, and the resonant current in the LLC resonant circuit 30 will change continuously with the on and off of the first power tube Q1, the second power tube Q2, the third power tube Q3 and the fourth power tube Q4, but during the dead time of the drive signal, the resonant current is zero. Therefore, in order to reduce the turn-off voltage spike of the power tube, when the bridge circuit 20 needs to stop working, the on and off of the power tube is controlled within the dead time of the PWM drive, thereby realizing soft switching of the power tube, thereby improving the service life of the energy storage power supply 100.

[0061] In some embodiments, the energy storage power supply 100 also includes a controller (not shown), which is connected to the overcurrent dead-zone wave-sealing circuit 50, and the controller is used to output a first drive signal and a second drive signal to the overcurrent dead-zone wave-sealing circuit 50, so that the overcurrent dead-zone wave-sealing circuit 50 controls the working state of the bridge circuit 20 according to the first drive signal and the second drive signal.

[0062] In some embodiments, see Figure 4 , Figure 4 is a structural block diagram of an overcurrent dead zone wave blocking circuit provided by an embodiment of the present invention, such as Figure 4 As shown, the overcurrent dead zone wave blocking circuit 50 includes a dead zone detection module 51, a first logic module 52 and a second logic module 53;

[0063] The dead zone detection module 51 is connected to the first logic module 52, the first logic module 52 is connected to the second logic module 53, the first logic module 52 is also used to connect to the current detection module 31, and the second logic module 53 is used to connect to the bridge circuit 20;

[0064] The dead zone detection module 51 is used to receive a first drive signal and a second drive signal, and output a first control signal to the first logic module 52 when the first drive signal and the second drive signal are both low level signals;

[0065] The first logic module 52 is used to receive the detection signal output by the current detection module 31, and when the detection signal is an overcurrent signal and the dead zone detection module 51 outputs the first control signal, output a wave-sealing signal to the second logic module 53;

[0066] The second logic module 53 receives the first drive signal and the second drive signal respectively, and drives the bridge circuit 20 to stop working when receiving the wave-enclosing signal; and when not receiving the wave-enclosing signal, drives the first power tube Q1 of the bridge circuit 20 to work in response to the first drive signal, and drives the second power tube Q2 of the bridge circuit 20 to work in response to the second drive signal. It should be noted that the second logic module 53 can be connected to the bridge circuit 20 directly or indirectly, for example, the second logic module 53 is connected to the bridge circuit 20 through a drive circuit, and for example, the drive circuit can be an optocoupler drive circuit. The second logic module 53 in this embodiment is used to provide a drive signal to the bridge circuit 20 to drive the bridge circuit 20 to work.

[0067] Specifically, when the dead zone detection module 51 receives the first drive signal and the second drive signal output by the controller, it will determine the level of the first drive signal and the second drive signal. When the first drive signal and the second drive signal are both low-level signals, the dead zone detection module 51 will output a first control signal to the first logic module 52. When the first logic module 52 receives the first control signal, it will receive the detection signal output by the current detection module 31, and when the detection signal is an overcurrent signal, it will output a wave-enclosing signal to the second logic module 53. When the second logic module 53 receives the wave-enclosing signal, it will drive the bridge circuit 20 to stop working according to the wave-enclosing signal, the first drive signal and the second drive signal, thereby protecting the energy storage power supply 100. If the first drive signal or the second drive signal is a high-level signal, the dead zone detection module 51 will output a second control signal to the first logic module 52. When the first logic module 52 receives the second control signal, even if the overcurrent signal is received, the first logic module 52 will not output a wave-enclosing signal. That is, the first logic module 52 will output the wave blocking signal to the second logic module 53 only after receiving the first control signal and the overcurrent signal. Based on this, when an overcurrent fault occurs in the energy storage power supply 100, the power tube in the bridge circuit 20 can be turned off during the dead time, thereby protecting the power tube in the bridge circuit 20 and improving the reliability of the energy storage power supply 100.

[0068] When the second logic module 53 does not receive the enveloping signal, the second logic module 53 receives the first drive signal and the second drive signal. At this time, the first drive signal or the second drive signal is a high-level signal, thereby driving the first power tube Q1 or the second power tube Q2 to work based on the first drive signal or the second drive signal.

[0069] In some embodiments, see Figure 5 , Figure 5 is a circuit diagram of an overcurrent dead zone wave blocking circuit provided by an embodiment of the present invention, such as Figure 5 As shown, the dead zone detection module 51 includes an OR gate U1A; the first logic module 52 includes an OR gate U1B.

[0070] The input end of the OR gate U1A is used to receive the first driving signal and the second driving signal respectively, and the output end of the OR gate U1A is connected to the first logic module 52 .

[0071] The first input end of the OR gate U1B is connected to the dead zone detection module 51 , the second input end of the OR gate U1B is connected to the current detection module 31 , and the output end of the OR gate U1B is connected to the second logic module 53 .

[0072] Specifically, when both the first drive signal and the second drive signal are low-level signals, the OR gate U1A will output a first control signal (low-level signal) to the first input end of the OR gate U1B. At this time, if the second input end of the OR gate U1B receives an overcurrent signal, the OR gate U1B will output a wave-enclosing signal (low-level signal) to the second logic module 53, so that the second logic module 53 controls the bridge circuit 20 to stop working based on the wave-enclosing signal, the first drive signal and the second drive signal. If the first drive signal or the second drive signal is a high-level signal, the OR gate U1A will output a second control signal (high-level signal). At this time, regardless of whether the second input end of the OR gate U1B receives an overcurrent signal, the OR gate U1B will not output a wave-enclosing signal, so that the second logic module 53 drives the first power tube Q1 or the second power tube Q2 to work according to the first drive signal or the second drive signal.

[0073] It should be noted that, since the first driving signal and the second driving signal are periodic pulse signals, the first driving signal and the second driving signal change in real time. Figure 6 , Figure 6 is a timing diagram of an overcurrent dead zone wave blocking circuit provided by an embodiment of the present invention, such as Figure 6As shown, from time T1 to time T2, the first drive signal (PWM-H) is a low-level signal, and the second drive signal (PWM-L) is a high-level signal. At this time, even if the detection signal (LLC-OCP) output by the current detection module 31 is an overcurrent signal (LLC-OCP is low), the first logic module 52 will not output a wave-blocking signal (PWM-EN1 is high), and the second logic module 53 will still drive the second power tube Q2 to work according to the second drive signal (that is, the lower tube PWMG-L is a high-level signal, and the upper tube PWMG-H is a low-level signal). From time T2 to time T3, both the first drive signal and the second drive signal are low-level signals, that is, the dead time of the pulse signal is reached. At this time, the first logic module 52 will output a wave-blocking signal (PWM-EN is low) to the second logic module 53 according to the first control signal and the overcurrent signal, so that the second logic module 53 controls the bridge circuit 20 to stop working according to the wave-blocking signal. At time T3-T4, the pulse signal enters the next cycle. At this time, the first drive signal is converted from a low level to a high level, which causes the first power tube Q1 in the bridge circuit 20 to work. However, at this time, the energy storage power supply 100 has an overcurrent fault. Therefore, in order to prevent the bridge circuit 20 from re-entering the working state, Figure 4 As shown, the overcurrent dead-band wave blocking circuit 50 further includes a control module 54 .

[0074] The control module 54 is connected to the second logic module 53 , and is used to output a locking signal to the second logic module 53 after the second logic module 53 receives the envelope signal for a first preset time, so that the second logic module 53 continues to drive the bridge circuit 20 to stop working.

[0075] Specifically, when the second logic module 53 controls the bridge circuit 20 to stop working based on the wave envelope signal and the first drive signal and the second drive signal, the control module 54 will also output a locking signal to the second logic module 53 after the second logic module 53 receives the wave envelope signal for a first preset time, so that the second logic module 53 locks the current working state of the bridge circuit 20 based on the locking signal, thereby protecting the energy storage power supply 100.

[0076] In yet another embodiment, Figure 4 As shown, the second logic module 53 includes a logic driving unit 531 and a delay unit 532;

[0077] The logic driving unit 531 is connected to the first logic module 52, and the logic driving unit 531 is also connected to the control module 54. The delay unit 532 is connected to the logic driving unit 531, and the logic driving unit 531 is also used to receive the first driving signal and the second driving signal, wherein the first driving signal and the second driving signal are both pulse signals;

[0078] The logic driving unit 531 is used for outputting a first voltage signal to drive the bridge circuit 20 to stop working when the first driving signal and the second driving signal are both low-level signals and the envelope signal is received; and

[0079] When the wave-enclosing signal is not received and the first driving signal is a high-level signal, a second voltage signal is output to the first power tube Q1 to drive the first power tube Q1 to work; or when the wave-enclosing signal is not received and the second driving signal is a high-level signal, a second voltage signal is output to the second power tube Q2 to drive the second power tube Q2 to work;

[0080] The delay unit 532 is used to delay the output of the first drive signal or the second drive signal to the logic drive unit 531 for a second preset time after the bridge circuit 20 stops working and when the first drive signal or the second drive signal is a high-level signal, so that the logic drive unit 531 continues to drive the bridge circuit 20 to stop working according to the locking signal, wherein the first preset time is less than the second preset time.

[0081] Specifically, when the first drive signal and the second drive signal are both at a low level, the logic drive unit 531 will receive the wave envelope signal, and output a first voltage signal to the bridge circuit 20 according to the wave envelope signal and the low level signal, so that the bridge circuit 20 stops working based on the first voltage signal. If the first drive signal or the second drive signal is at a high level, the logic drive unit 531 will not receive the wave envelope signal. At this time, the logic drive unit 531 will output a second voltage signal based on the first drive signal to drive the first power tube Q1 in the bridge circuit 20 to work, or output a second voltage signal based on the second drive signal to drive the second power tube Q2 in the bridge circuit 20 to work. Among them, when the bridge circuit 20 stops working, since the first drive signal and the second drive signal are periodic pulse signals, the first power tube Q1 or the second power tube Q2 will be turned on again based on the high level signal in the next cycle of the pulse signal. In order to avoid this situation, in the next cycle of the pulse signal, the delay unit 532 will receive the high level signal, thereby delaying the time for the logic drive unit 531 to receive the first drive signal or the second drive signal. Since the second preset time is greater than the first preset time, before the logic drive unit 531 receives the first drive signal or the second drive signal, the logic drive unit 531 will first receive the locking signal output by the control module 54, and maintain the bridge circuit 20 to stop working according to the locking signal. At this time, if the delay unit 532 inputs the first drive signal or the second drive signal to the logic drive unit 531, the logic drive unit 531 will not control the first power tube Q1 or the second power tube Q2 to work. Based on this, when an overcurrent fault occurs in the energy storage power supply 100, the energy storage power supply 100 can be controlled to stop working, thereby improving the reliability of the energy storage power supply 100.

[0082] In some embodiments, Figure 5 As shown, the logic driving unit 531 includes an AND gate U2A, an AND gate U2B and a diode D1; the delay unit 532 includes a capacitor C1;

[0083] The first input end of the AND gate U2A is used to receive the first drive signal, the second input end of the AND gate U2A is respectively connected to the anode of the diode D1 and the first power supply (VCC-MCU), the output end of the AND gate U2A is connected to the first power tube Q1, the cathode of the diode D1 is connected to the first logic module 52, the first input end of the AND gate U2B is used to receive the second drive signal, the second input end of the AND gate U2B is connected to the second input end of the AND gate U2A, the second input end of the AND gate U2B is also connected to the control module 54, and the output end of the AND gate U2B is connected to the second power tube Q2.

[0084] The capacitor C1 is connected to the second input terminal of the AND gate U2A, and the capacitor C1 is also used for grounding.

[0085] Specifically, after the OR gate U1B outputs the wave-sealing signal, the diode D1 is turned on, and the voltages of the second input terminal of the AND gate U2A and the second input terminal of the AND gate U2B are both pulled down. At this time, since the first drive signal and the second drive signal are also low-level signals, the AND gate U2A and the AND gate U2B both output the first voltage signal to the bridge circuit 20, thereby controlling the bridge circuit 20 to stop working. If the OR gate U1A does not output the wave-sealing signal and the first drive signal is a high-level signal, the first input terminal and the second input terminal of the AND gate U2A both receive high-level signals, thereby outputting the second voltage signal to the first power tube Q1 in the bridge circuit 20; and since the second drive signal is a low-level signal at this time, the AND gate U2B outputs the first voltage signal, thereby causing the first power tube Q1 to work and the second power tube Q2 to stop working. When the OR gate U1B does not output the wave blocking signal and the second driving signal is a high level signal, the AND gate U2A outputs the second voltage signal, and the AND gate U2B outputs the first voltage signal, thereby stopping the first power tube Q1 and starting the second power tube Q2.

[0086] Further, combined with Figure 5 and Figure 6It can be seen that at the time T2-T3, the first drive signal and the second drive signal are both low-level signals (that is, the dead time of the pulse signal), and the bridge circuit 20 will stop working; and at the time T3-T4, the first drive signal will jump to a high-level signal again. At this time, the OR gate U1B does not output the sealing signal, the diode D1 is cut off, and the first power supply will start to charge the capacitor C1. During the second preset time of charging the capacitor C1, the voltage at the second input end of the AND gate U2A will slowly rise, and before the second input end of the AND gate U2A receives the high-level signal, the locking signal (MCU-OCP) output by the control module 54 will be directly input to the second input end of the AND gate U2B and the AND gate U2A to pull down the voltage of the second input end of the AND gate U2A and the AND gate U2B, so that the AND gate U2A and the AND gate U2B continue to output the first voltage signal, thereby locking the bridge circuit 20 into a stopped working state.

[0087] In another embodiment, when the first drive signal and the second drive signal output by the controller are both at a high level, even if the energy storage power supply 100 has an overcurrent, LLC_OCP is at a low level, but PWM_EN1 is still at a high level, thereby causing the logic drive unit 531 to drive the first power tube Q1 and the second power tube Q2 to work simultaneously according to the first drive signal and the second drive signal. Therefore, in order to avoid the situation where the first power tube Q1 and the second power tube Q2 work at the same time, the second logic module 53 also includes a logic locking unit 533; the logic locking unit 533 is connected to the logic drive unit 531, and the logic locking unit 533 is also used to receive the first drive signal and the second drive signal.

[0088] The logic locking unit 533 is used to output a shutdown signal to the logic driving unit 531 when the first driving signal and the second driving signal are both at high levels, so that the logic driving unit 531 drives the bridge circuit 20 to stop working according to the shutdown signal.

[0089] For details, please refer to Figure 7 , Figure 7 is a circuit diagram of an overcurrent dead zone wave blocking circuit provided by another embodiment of the present invention, such as Figure 7 As shown, the logic locking unit 533 includes a NAND gate U2C;

[0090] The two input terminals of the NAND gate U2C are respectively used to receive the first driving signal and the second driving signal, and the output terminal of the NAND gate U2C is connected to the AND gate U2B.

[0091] When the first drive signal and the second drive signal are both high-level signals, the NAND gate U2C will output a shutdown signal (low-level signal) to the second input end of the AND gate U2B and the second input end of the AND gate U2A, so that the AND gate U2B and the AND gate U2A both output the first voltage signal, thereby stopping the first power tube Q1 and the second power tube Q2 from working. It should be noted that the first drive signal and the second drive signal are both high-level signals, which are abnormal drive signals, and are often waveforms output when the MCU is uncontrollably damaged.

[0092] In another embodiment, in order to prevent the logic driving unit 531 from driving the first power tube Q1 and the second power tube Q2 to work at the same time, as shown in FIG. Figure 4 As shown, the overcurrent dead zone wave blocking circuit 50 further includes a first interlocking module 55; the first interlocking module 55 is connected to the logic driving unit 531, and the first interlocking module 55 is also connected to the first power tube Q1 in the bridge circuit 20 and the second power tube Q2 in the bridge circuit 20;

[0093] The first interlocking module 55 is used to control the bridge circuit 20 to stop working according to the first voltage signal when the logic driving unit 531 outputs the first voltage signal; and

[0094] When the logic driving unit 531 outputs the second voltage signal, the first power tube Q1 or the second power tube Q2 is controlled to operate according to the second voltage signal.

[0095] Further, such as Figure 5 As shown, the first interlocking module 55 includes a first interlocking unit 551 and a second interlocking unit 552;

[0096] The first end of the first interlocking unit 551 is connected to the first output end of the logic driving unit 531, the second end of the first interlocking unit 551 is connected to the second output end of the logic driving unit 531, the output end of the first interlocking unit 551 is connected to the first power tube Q1, the first end of the second interlocking unit 552 is connected to the second output end of the logic driving unit 531, the second end of the second interlocking unit 552 is connected to the first output end of the logic driving unit 531, and the output end of the second interlocking unit 552 is connected to the second power tube Q2;

[0097] When the first output terminal of the logic driving unit 531 and the second output terminal of the logic driving unit 531 both output the first voltage signal, the first interlocking unit 551 is configured to control the first power tube Q1 to stop working according to the first voltage signal, and the second interlocking unit 552 is configured to control the second power tube Q2 to stop working according to the first voltage signal;

[0098] When the first output terminal of the logic driving unit 531 outputs a second voltage signal, and the second output terminal of the logic driving unit 531 outputs a first voltage signal, the first interlocking unit 551 is configured to control the first power tube Q1 to work according to the second voltage signal, and the second interlocking unit 552 is configured to control the second power tube Q2 to stop working according to the first voltage signal;

[0099] When the first output end of the logic driving unit 531 outputs a first voltage signal and the second output end of the logic driving unit 531 outputs a second voltage signal, the first interlocking unit 551 is configured to control the first power tube Q1 to stop working according to the first voltage signal, and the second interlocking unit 552 is configured to control the second power tube Q2 to work according to the second voltage signal.

[0100] Specifically, when both output ends of the logic driving unit 531 output the first voltage signal, the first interlocking unit 551 and the second interlocking unit 552 will both receive the first voltage signal and stop the bridge circuit 20 according to the first voltage signal. If the first output end of the logic driving unit 531 outputs the second voltage signal and the second output end still outputs the first voltage signal, the first interlocking unit 551 will drive the first power tube Q1 to close, while the second power tube Q2 remains in the disconnected state. When the second input end of the logic driving unit 531 outputs the second voltage signal and the first output end outputs the first voltage signal, the second interlocking unit 552 will drive the second power tube Q2 to close based on the second voltage signal, and the first power tube Q1 will switch to the disconnected state. Based on this, the alternating conduction of the first power tube Q1 and the second power tube Q2 can be achieved based on the first drive signal and the second drive signal.

[0101] In yet another embodiment, see Figure 8 , Figure 8 is a circuit diagram of an interlocking module provided by an embodiment of the present invention, such as Figure 8 As shown, the first interlocking unit 551 includes an optical coupler U3, a resistor R2, a resistor R3 and a capacitor C2; the second interlocking unit 552 includes an optical coupler U4, a resistor R5, a resistor R6 and a capacitor C4.

[0102] The first input end of the optocoupler U3 is connected to the first output end of the logic driving unit 531 through the resistor R2, the second input end of the optocoupler U3 is connected to the second output end of the logic driving unit 531, the output end of the optocoupler U3 is connected to the first power tube Q1, the capacitor C2 is respectively connected to the first input end of the optocoupler U3 and the second input end of the optocoupler U3, and the resistor R3 is connected in parallel with the capacitor C2.

[0103] The first input end of the optocoupler U4 is connected to the second output end of the logic driving unit 531 through the resistor R5, the second input end of the optocoupler U4 is connected to the first output end of the logic driving unit 531, the output end of the optocoupler U4 is connected to the second power tube Q2, the capacitor C4 is respectively connected to the first input end of the optocoupler U4 and the second input end of the optocoupler U4, and the resistor R6 is connected in parallel with the capacitor C4.

[0104] Specifically, when the AND gate U2A and the AND gate U2B both output the first voltage signal, the optical coupler U3 and the optical coupler U4 both do not work, so that the first power tube Q1 and the second power tube Q2 stop working; and when the AND gate U2A outputs the second voltage signal and the AND gate U2B outputs the first voltage signal, the optical coupler U3 is turned on, so as to control the first power tube Q1 to work, and the optical coupler U4 is turned off, so that the second power tube Q2 does not work. When the AND gate U2A outputs the first voltage signal and the AND gate U2B outputs the second voltage signal, the optical coupler U3 is turned off, so that the first power tube Q1 does not work, and the optical coupler U4 is turned on, so that the second power tube Q2 starts to work.

[0105] In yet another embodiment, when the bridge circuit 20 is a full-bridge circuit, the overcurrent dead-band wave-enclosing circuit 50 further includes a second interlocking module 56;

[0106] The second interlocking module 56 is connected to the logic driving unit 531, and the second interlocking module 56 is also connected to the third power tube Q3 in the bridge circuit 20 and the fourth power tube Q4 in the bridge circuit 20;

[0107] The second interlocking module 56 is used for controlling the bridge circuit 20 to stop working according to the first voltage signal when the logic driving unit 531 outputs the first voltage signal; and

[0108] When the logic driving unit 531 outputs the second voltage signal, the third power tube Q3 or the fourth power tube Q4 is controlled to operate according to the second voltage signal.

[0109] It can be understood that the structure and working principle of the second interlocking module 56 are the same as those of the first interlocking module 55 , and will not be described in detail in this embodiment.

[0110] In some embodiments, please combine Figure 2 , Figure 5 and Fig. 9 , after the controller outputs the first drive signal and the second drive signal, if the first drive signal and the second drive signal are both low-level signals, the U1A will output a low-level signal. At this time, if the energy storage power supply 100 has an overcurrent fault, the U1B will also output a low-level signal, thereby turning on the diode D1. When the diode D1 is turned on, the voltages at the second input terminals of the AND gates U2A and U2B are pulled low, and the first drive signal and the second drive signal are also low-level. Therefore, the optocouplers U3, U4, U5 and U6 will all receive low-level signals, thereby controlling the first power tube Q1, the second power tube Q2, the third power tube Q3 and the fourth power tube Q4 to not work, thereby protecting the energy storage power supply 100.

[0111] When the first drive signal is a high level signal and the second drive signal is a low level signal, the OR gate U1A will output a high level signal. At this time, regardless of whether the current detection module 31 outputs an overcurrent signal, the OR gate U1B will output a high level signal, so that the diode D1 is cut off. At this time, the second input terminals of the AND gates U2A and U2B are both pulled high, so that the AND gates U2A output a high level signal and the AND gates U2B output a low level signal. As a result, the optical coupler U3 and the optical coupler U6 work, and the optical coupler U4 and the optical coupler U5 do not work, so that the first power tube Q1 and the fourth power tube Q4 work, so that the LLC resonant circuit 30 processes the battery voltage and then outputs the target voltage to the load 200. It should be noted that the working principles of the second power tube Q2 and the third power tube Q3 are similar to those of the first power tube Q1 and the fourth power tube Q4, which will not be repeated here.

[0112] The present invention provides an overcurrent dead zone wave-sealing circuit and an energy storage power supply, which are applied to a bridge circuit. The overcurrent dead zone wave-sealing circuit includes a dead zone detection module, a first logic module and a second logic module; the dead zone detection module is connected to the first logic module, the first logic module is connected to the second logic module, the first logic module is also used to connect to a current detection module, and the second logic module is used to connect to the bridge circuit. The dead zone detection module is used to receive a first drive signal and a second drive signal, and when the first drive signal and the second drive signal are both low-level signals, output a first control signal to the first logic module; the first logic module is used to receive a detection signal output by the current detection module, and when the detection signal is an overcurrent signal and the dead zone detection module outputs the first control signal, output a wave-sealing signal to the second logic module, so that the second logic module controls the bridge circuit to stop working based on the wave-sealing signal, the first drive signal and the second drive signal, thereby controlling the soft switch of the power tube in the bridge circuit when the first drive signal and the second drive signal are in the dead zone, avoiding the situation where the power tube is shut down under high voltage and high current, thereby improving the reliability of the energy storage power supply. When the second logic module does not receive the wave-enclosing signal, it drives the first power tube of the bridge circuit to work in response to the first drive signal, and drives the second power tube of the bridge circuit to work in response to the second drive signal, so that the energy storage power supply outputs the power supply voltage normally.

[0113] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them. Under the concept of the present invention, the technical features in the above embodiments or different embodiments may also be combined, the steps may be implemented in any order, and there are many other changes in different aspects of the present invention as described above, which are not provided in detail for the sake of simplicity. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they may still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An overcurrent dead zone wave blocking circuit, characterized in that: Applied to a bridge circuit, the overcurrent dead zone wave blocking circuit comprises a dead zone detection module, a first logic module and a second logic module; The dead zone detection module is connected to the first logic module, the first logic module is connected to the second logic module, the first logic module is further used to connect to the current detection module, and the second logic module is used to connect to the bridge circuit; The dead zone detection module is used to receive a first drive signal and a second drive signal, and output a first control signal to the first logic module when the first drive signal and the second drive signal are both low level signals; The first logic module is used to receive the detection signal output by the current detection module, and when the detection signal is an overcurrent signal and the dead zone detection module outputs the first control signal, output a wave-sealing signal to the second logic module; The second logic module receives the first drive signal and the second drive signal respectively, and drives the bridge circuit to stop working when the wave-enclosing signal is received; and when the wave-enclosing signal is not received, drives the first power tube of the bridge circuit to work in response to the first drive signal, and drives the second power tube of the bridge circuit to work in response to the second drive signal.

2. The overcurrent dead zone wave blocking circuit according to claim 1, characterized in that: The overcurrent dead zone wave blocking circuit also includes a control module; The control module is connected to the second logic module; The control module is used for outputting a locking signal to the second logic module after the second logic module receives the envelope signal for a first preset time, so that the second logic module continuously drives the bridge circuit to stop working.

3. The overcurrent dead zone wave blocking circuit according to claim 2, characterized in that: The second logic module includes a logic driving unit and a delay unit; The logic drive unit is connected to the first logic module, the logic drive unit is also connected to the control module, the delay unit is connected to the logic drive unit, and the logic drive unit is also used to receive the first drive signal and the second drive signal, wherein the first drive signal and the second drive signal are both pulse signals; The logic driving unit is used for outputting a first voltage signal to drive the bridge circuit to stop working when the first driving signal and the second driving signal are both low-level signals and the envelope signal is received; and When the wave-enclosing signal is not received and the first driving signal is a high-level signal, a second voltage signal is output to the first power tube to drive the first power tube to work; or when the wave-enclosing signal is not received and the second driving signal is a high-level signal, a second voltage signal is output to the second power tube to drive the second power tube to work; The delay unit is used to delay the output of the first drive signal or the second drive signal to the logic drive unit for a second preset time after the bridge circuit stops working and when the first drive signal or the second drive signal is a high-level signal, so that the logic drive unit continues to drive the bridge circuit to stop working according to the locking signal, wherein the first preset time is less than the second preset time.

4. The overcurrent dead zone wave blocking circuit according to claim 3, characterized in that: The second logic module also includes a logic locking unit; The logic locking unit is connected to the logic driving unit, and the logic locking unit is further used to receive the first driving signal and the second driving signal; The logic locking unit is used for outputting a shutdown signal to the logic driving unit when the first driving signal and the second driving signal are both at high levels, so that the logic driving unit drives the bridge circuit to stop working according to the shutdown signal.

5. The overcurrent dead zone wave blocking circuit according to claim 3, characterized in that: The logic driving unit includes an AND gate U2A, an AND gate U2B and a diode D1; The first input end of the AND gate U2A is used to receive the first drive signal, the second input end of the AND gate U2A is respectively connected to the anode of the diode D1 and the first power supply, the output end of the AND gate U2A is connected to the first power tube, the cathode of the diode D1 is connected to the first logic module, the first input end of the AND gate U2B is used to receive the second drive signal, the second input end of the AND gate U2B is connected to the second input end of the AND gate U2A, the second input end of the AND gate U2B is also connected to the control module, and the output end of the AND gate U2B is connected to the second power tube.

6. The overcurrent dead zone wave blocking circuit according to claim 5, characterized in that: The delay unit includes a capacitor C1; The capacitor C1 is connected to the second input terminal of the AND gate U2A, and the capacitor C1 is also used for grounding.

7. The overcurrent dead zone wave blocking circuit according to any one of claims 3 to 6, characterized in that: The overcurrent dead zone wave blocking circuit also includes a first interlocking module; The first interlocking module is connected to the logic driving unit, and the first interlocking module is also connected to the first power tube in the bridge circuit and the second power tube in the bridge circuit; The first interlocking module is used for controlling the bridge circuit to stop working according to the first voltage signal when the logic driving unit outputs the first voltage signal; as well as When the logic driving unit outputs a second voltage signal, the first power tube or the second power tube is controlled to operate according to the second voltage signal.

8. The overcurrent dead zone wave blocking circuit according to claim 7, characterized in that: The first interlocking module includes a first interlocking unit and a second interlocking unit; The first end of the first interlock unit is connected to the first output end of the logic drive unit, the second end of the first interlock unit is connected to the second output end of the logic drive unit, the output end of the first interlock unit is connected to the first power tube, the first end of the second interlock unit is connected to the second output end of the logic drive unit, the second end of the second interlock unit is connected to the first output end of the logic drive unit, and the output end of the second interlock unit is connected to the second power tube; When the first output terminal of the logic driving unit and the second output terminal of the logic driving unit both output a first voltage signal, the first interlocking unit is configured to control the first power tube to stop working according to the first voltage signal, and the second interlocking unit is configured to control the second power tube to stop working according to the first voltage signal; When the first output terminal of the logic driving unit outputs a second voltage signal and the second output terminal of the logic driving unit outputs a first voltage signal, the first interlocking unit is configured to control the first power tube to work according to the second voltage signal, and the second interlocking unit is configured to control the second power tube to stop working according to the first voltage signal; When the first output end of the logic driving unit outputs a first voltage signal and the second output end of the logic driving unit outputs a second voltage signal, the first interlocking unit is configured to control the first power tube to stop working according to the first voltage signal, and the second interlocking unit is configured to control the second power tube to work according to the second voltage signal.

9. The overcurrent dead zone wave blocking circuit according to claim 8, characterized in that: The first interlocking unit includes an optical coupler U3, a resistor R2, a resistor R3 and a capacitor C2; The first input end of the optocoupler U3 is connected to the first output end of the logic driving unit through the resistor R2, the second input end of the optocoupler U3 is connected to the second output end of the logic driving unit, the output end of the optocoupler U3 is connected to the first power tube, the capacitor C2 is respectively connected to the first input end of the optocoupler U3 and the second input end of the optocoupler U3, and the resistor R3 is connected in parallel with the capacitor C2.

10. An energy storage power supply, characterized in that: The energy storage power supply comprises: Bridge circuit; Batteries; and The overcurrent dead-band wave-sealing circuit according to any one of claims 1 to 9, wherein the battery is connected to the bridge circuit, and the bridge circuit is connected to the overcurrent dead-band wave-sealing circuit.

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