Semiconductor device

Abstract

A semiconductor device is disclosed, the semiconductor device including: a substrate including a device isolation pattern and an active region; a bit line extending in a first direction on the substrate; the semiconductor pattern is positioned on the bit line; a growth mask layer on the bit line and having a sidewall in contact with the semiconductor pattern; a word line on the bit line and extending in a second direction crossing the first direction; and a gate dielectric pattern between the word line and the semiconductor pattern. A top surface of the growth mask layer is at a height higher than a height of a bottom surface of the semiconductor pattern.

Description

Technical Field

[0001] The inventive concept relates to a semiconductor device, and more particularly, to a semiconductor device including a vertical channel transistor and a method of manufacturing the semiconductor device. Background Art

[0002] The reduction of design rules of semiconductor devices leads to the development of manufacturing technology to improve the integration, operation speed and manufacturing yield of semiconductor devices. Therefore, transistors with vertical channels have been proposed to increase their integration, resistance, current driving capability, etc. Summary of the invention

[0003] Some embodiments of the inventive concept provide semiconductor devices having improved electrical characteristics and increased reliability.

[0004] The objects of the inventive concept are not limited to the above-mentioned contents, and other objects not mentioned above will be clearly understood by those skilled in the art from the following description.

[0005] According to some embodiments of the present inventive concept, a semiconductor device may include: a substrate including a device isolation pattern and an active region; a bit line extending in a first direction on the substrate; a semiconductor pattern located on the bit line; a growth mask layer located on the bit line, a sidewall of the growth mask layer contacting the semiconductor pattern; a word line located on the bit line, the word line extending in a second direction intersecting the first direction; and a gate dielectric pattern located between the word line and the semiconductor pattern. A top surface of the growth mask layer may be at a height higher than a height of a bottom surface of the semiconductor pattern.

[0006] According to some embodiments of the present inventive concept, a semiconductor device may include: a substrate including a device isolation pattern and an active region; a bit line extending in a first direction on the substrate; a semiconductor pattern located on the bit line; a growth mask layer located on the bit line; a word line located on the bit line, the word line extending in a second direction intersecting the first direction; and a gate dielectric pattern located between the word line and the semiconductor pattern. A sidewall of the semiconductor pattern may contact a sidewall of the gate dielectric pattern and a sidewall of the growth mask layer.

[0007] According to some embodiments of the present invention, a semiconductor device may include: a substrate, the substrate including a device isolation pattern and an active area; a cell array structure, the cell array structure being located on the substrate; a peripheral circuit structure, the peripheral circuit structure being located on the substrate and adjacent to the cell array structure in a first direction parallel to an extension direction of the substrate, the peripheral circuit structure including a peripheral gate structure and a peripheral contact pad; a bit line, the bit line being located in the cell array structure, the bit line extending in the first direction; a semiconductor pattern, the semiconductor pattern being located on the bit line; a growth mask layer, the growth mask layer being located on the bit line, the sidewall of the growth mask layer being in contact with the semiconductor pattern; a first word line and a second word line, the first word line and the second word line being located on the bit line, the first word line and the second word line extending in a second direction intersecting the first direction; a gate dielectric pattern, the gate dielectric pattern being located between the first word line and the semiconductor pattern; a contact pattern, the contact pattern being located on the semiconductor pattern; and a landing pad, the landing pad being located on the contact pattern. A top surface of the landing pad may be at the same height as a top surface of the peripheral contact pad. A bottom surface of the peripheral gate structure may be at the same height as a bottom surface of the bit line. A top surface of the growth mask layer may be at a height higher than a bottom surface of the semiconductor pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A block diagram illustrating a semiconductor device according to example embodiments of the inventive concepts is shown.

[0009] Figure 2 A simplified perspective view illustrating a semiconductor device according to an example embodiment of the inventive concepts is shown.

[0010] Figure 3 A top view illustrating a semiconductor device according to example embodiments of the inventive concepts is shown.

[0011] Figure 4 and Figure 5 Shown along Figure 3 A cross-sectional view taken along lines AA' and BB'.

[0012] Figure 6 Cross-sectional views illustrating a semiconductor device according to example embodiments of the inventive concepts are illustrated.

[0013] Figure 7 Shown along Figure 3 A cross-sectional view taken along line BB′ of FIG. 1 illustrates a semiconductor device according to an example embodiment of the inventive concept.

[0014] Figure 8 Shown along Figure 3 A cross-sectional view taken along line BB′ of FIG. 1 illustrates a semiconductor device according to an example embodiment of the inventive concept.

[0015] 9A to 13A A top view illustrating a method of fabricating a semiconductor device according to an example embodiment of the inventive concepts is shown.

[0016] FIG. 9B to FIG. 13B Shown along Figure 3 A cross-sectional view taken along line AA′ of FIG. 1 illustrates a method of fabricating a semiconductor device according to an example embodiment of the inventive concept.

[0017] FIG. 9C to FIG. 13C Shown along Figure 3 A cross-sectional view taken along line BB′ of FIG. 1 illustrates a method of fabricating a semiconductor device according to an example embodiment of the inventive concept.

[0018] FIG. 14A to FIG. 14C Shown according to Figure 8 A cross-sectional view of a method of fabricating a semiconductor device according to an example embodiment of the present invention. DETAILED DESCRIPTION

[0019] Semiconductor devices and methods for fabricating semiconductor devices according to some embodiments of the inventive concept will be discussed below in conjunction with the accompanying drawings. The same reference numerals refer to the same elements throughout the text.

[0020] It should be understood that when an element is referred to as being "connected" or "coupled" to another element or "on another element", it can be directly connected or coupled to another element or on another element, or there may be intervening elements. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or as being "in contact with" another element or "in contact with another element" (or any form of the word "contacting"), there are no intervening elements at the point of contact.

[0021] Figure 1 A block diagram illustrating a semiconductor device according to example embodiments of the inventive concepts is shown.

[0022] refer to Figure 1 , the semiconductor device may include a memory cell array 1 , a row decoder 2 , a sense amplifier 3 , a column decoder 4 and a control logic 5 .

[0023] The memory cell array 1 may include a plurality of memory cells MC arranged two-dimensionally or three-dimensionally. Each memory cell MC may be connected between a word line WL and a bit line BL crossing each other.

[0024] Each memory cell MC may include a selection element SE and a data storage element DS, and the selection element SE and the data storage element DS may be electrically connected in series. The selection element SE may be connected between the data storage element DS and the word line WL, and the data storage element DS may be connected to the bit line BL through the selection element SE. The selection element SE may be a field effect transistor (FET), and the data storage element DS may be a capacitor, a magnetic tunnel junction pattern, or a variable resistor. For example, the selection element SE may include a transistor whose gate electrode is connected to the word line WL and whose source / drain terminal is connected to the bit line BL and the data storage element DS.

[0025] The row decoder 2 may decode an address input from the outside and select one word line WL of the memory cell array 1. The address decoded in the row decoder 2 may be provided to a row driver (not shown), and in response to a control operation of a control circuit, the row driver may provide a specific voltage to the selected word line WL and each unselected word line WL.

[0026] In response to an address decoded from the column decoder 4 , the sense amplifier 3 may detect and amplify a voltage difference between a selected bit line BL and a reference bit line, and may then output the amplified voltage difference.

[0027] The column decoder 4 may provide a data transfer path between the sense amplifier 3 and an external device (eg, a memory controller). The column decoder 4 may decode an address input from the outside and select a bit line.

[0028] The control logic 5 may generate a control signal for controlling an operation for writing data to the memory cell array 1 and / or reading data from the memory cell array 1 .

[0029] Figure 2 A simplified perspective view illustrating a semiconductor device according to an example embodiment of the inventive concepts is shown.

[0030] refer to Figure 2 , a semiconductor device according to some embodiments of the present inventive concept may include a peripheral circuit structure PS located on a substrate 100, and may also include a cell array structure CS located on the substrate 100, such that the cell array structure CS is adjacent to the peripheral circuit structure PS in a direction parallel to the substrate 100.

[0031] The peripheral circuit structure PS may include core / peripheral circuits formed on the substrate 100. The core / peripheral circuits may include a row decoder and a column decoder (eg, see Figure 1 The row decoder 2 and column decoder 4 of FIG. 1 ), the sense amplifier (see, for example, Figure 1 sense amplifier 3) and control logic (see, for example, Figure 1The peripheral circuit structure PS may be disposed on the substrate 100 in a third direction D3 perpendicular to the top surface of the substrate 100 .

[0032] The cell array structure CS may include bit lines BL, word lines WL, and memory cells located between the bit lines BL and the word lines WL (eg, see Figure 1 Memory cell MC). Memory cell (for example, see Figure 1 The memory cells MC) may be arranged two-dimensionally or three-dimensionally on planes extending in first and second directions D1 and D2 that intersect each other and are parallel to the top surface of the substrate 100. As discussed above, each memory cell (e.g., see Figure 1 The memory cell MC) may include a selection element SE and a data storage element DS.

[0033] According to some embodiments, a vertical channel transistor (VCT) TR may be included as each memory cell (eg, see Figure 1 The vertical channel transistor TR may indicate a structure in which the channel length thereof extends in a direction (eg, a third direction D3) perpendicular to the top surface of the substrate 100. In addition, each memory cell (eg, see Figure 1 The memory cell MC) may include a capacitor as a data storage element DS.

[0034] Figure 3 A top view illustrating a semiconductor device according to example embodiments of the inventive concepts is shown. Figure 4 and Figure 5 Shown along Figure 3 A cross-sectional view taken along lines AA' and BB'. Figure 6 Cross-sectional views illustrating a semiconductor device according to example embodiments of the inventive concepts are illustrated.

[0035] refer to Figures 3 to 6 , a semiconductor device according to some embodiments of the inventive concept may include a substrate 100 , a peripheral circuit structure PS on the substrate 100 , and a cell array structure CS adjacent to the peripheral circuit structure PS in a first direction D1 .

[0036] The substrate 100 may be a semiconductor substrate, such as a silicon substrate, a germanium substrate, or a silicon germanium substrate.

[0037] The peripheral circuit structure PS may include: a peripheral gate structure PC, which is integrated on the substrate 100; a peripheral contact pad CP; a peripheral contact plug CPLG; and a peripheral interlayer dielectric layer 102, which covers the peripheral gate structure PC, the peripheral contact pad CP and the peripheral contact plug CPLG. The peripheral gate structure PC may contact the substrate 100. The peripheral contact plug CPLG may contact the upper surface of the substrate 100, and the peripheral contact pad CP may contact the upper surface of the peripheral contact plug CPLG. The peripheral gate structure PC may include Figure 1 The sense amplifier 3.

[0038] The cell array structure CS may include a memory cell including a vertical channel transistor. The cell array structure CS may include: a bit line BL; a growth mask layer 111, which is located on the bit line BL; a semiconductor pattern SP, which is located on the bit line BL; a plurality of lower gate capping patterns 112, which are located on the growth mask layer 111; a first word line WL1 and a second word line WL2, which are located on the lower gate capping pattern 112; an upper gate capping pattern 113, which is located on the first word line WL1 and the second word line WL2; a first dielectric pattern 140 and a second dielectric pattern 120, which are located on the growth mask layer 111; a gate dielectric pattern Gox, which is in contact with the semiconductor pattern SP; a contact pattern BC, which is located on the semiconductor pattern SP; a landing pad LP, which is located on the contact pattern BC; and a data storage pattern DSP, which is located on the landing pad LP. In example embodiments, the growth mask layer 111 and the semiconductor pattern SP may contact an upper surface of the bit line BL, the plurality of lower gate capping patterns 112 may contact an upper surface of the growth mask layer 111, the first word line WL1 and the second word line WL2 may contact an upper surface of the lower gate capping pattern 112, the upper gate capping pattern 113 may contact an upper surface of the first word line WL1 and the second word line WL2, the first dielectric pattern 140 and the second dielectric pattern 120 may contact an upper surface of the growth mask layer 111, the contact pattern BC may contact upper surfaces of the semiconductor pattern SP, the upper gate capping pattern 113, and the gate dielectric pattern Gox, the landing pad LP may contact an upper surface of the contact pattern BC, and the data storage pattern DSP may contact an upper surface of the landing pad LP. Upper surfaces of the first dielectric pattern 140, the upper gate capping pattern 113, the gate dielectric pattern Gox, and the semiconductor pattern SP may be coplanar with each other.

[0039] The peripheral gate structure PC of the peripheral circuit structure PS can be electrically connected to the cell array structure CS through the peripheral contact plug CPLG and the peripheral contact pad CP. The peripheral interlayer dielectric layer 102 may include a plurality of stacked dielectric layers, including at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and low-k dielectrics.

[0040] The bit line BL may be disposed on the substrate 100 while longitudinally extending in the first direction D1. The bit line BL may be disposed in plurality, and the plurality of bit lines BL may be spaced apart from each other in the second direction D2.

[0041] The bit line BL may include, for example, doped polysilicon. The bit line BL may include phosphorus (P). The bit line BL may include phosphasilene. The bit line BL may include at least one selected from a conductive metal silicide and a metal such as Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, and Co.

[0042] The substrate 100 may include an active area ACT and a device isolation pattern STI. The active area ACT and the device isolation pattern STI may be disposed in the substrate 100. The device isolation pattern STI may define the active area ACT. The active area ACT may extend longitudinally in the first direction D1. The active area ACT may be defined as an upper portion of the substrate 100 protruding in the third direction D3. The active areas ACT may be spaced apart from each other. The device isolation pattern STI may be disposed between the active areas ACT. The device isolation pattern STI may include a dielectric material. For example, the device isolation pattern STI may include an oxide. The device isolation pattern STI may separate the bit lines BL from each other in the second direction D2.

[0043] A top surface of the device isolation pattern STI may be coplanar with a top surface BL_T of the bit line BL. A top surface of the device isolation pattern STI may be located at the same height as that of the top surface BL_T of the bit line BL.

[0044] The growth mask layer 111 and the semiconductor pattern SP may be disposed on the bit line BL. The semiconductor pattern SP may be disposed on the top surface BL_T of the bit line BL on which the growth mask layer 111 is not disposed. The growth mask layer 111 may be disposed on the device isolation pattern STI. The top surface of the device isolation pattern STI may be in contact with the growth mask layer 111. The device isolation pattern STI and the growth mask layer 111 may overlap each other. The device isolation pattern STI and the semiconductor pattern SP may not overlap each other. The growth mask layer 111 and the semiconductor pattern SP may not overlap each other.

[0045] The semiconductor pattern SP may be provided in plurality. The plurality of semiconductor patterns SP may be spaced apart from each other in the first direction D1 and the second direction D2.

[0046] The bottom surface SP_BS of the semiconductor pattern SP may be in contact with the top surface BL_T of the bit line BL. The semiconductor pattern SP may extend from the bit line BL in the third direction D3. The sidewall 111_SW of the growth mask layer 111 may be in contact with the sidewall SP_SW of the semiconductor pattern SP. The top surface 111_TS of the growth mask layer 111 may be located at a height higher than that of the bottom surface SP_BS of the semiconductor pattern SP.

[0047] The semiconductor pattern SP may include silicon. The semiconductor pattern SP may include a crystalline material. The semiconductor pattern SP may include doped silicon. For example, the semiconductor pattern SP may include silicon doped with boron (B).

[0048] The semiconductor pattern SP may be formed by epitaxially growing silicon from the bit line BL serving as a seed pattern. As the semiconductor pattern SP is epitaxially grown from the bit line BL, a lattice direction of the bit line BL may be the same as that of the semiconductor pattern SP.

[0049] The word line WL may be disposed on the substrate 100. The word line WL may overlap the growth mask layer 111 in the third direction D3. The word line WL may extend longitudinally in the second direction D2 intersecting the first direction D1. The lower gate capping pattern 112 may be interposed between the word line WL and the growth mask layer 111. The lower gate capping pattern 112 may be spaced apart from the bit line BL. The growth mask layer 111 may be interposed between the lower gate capping pattern 112 and the bit line BL.

[0050] The word line WL may include, for example, doped polysilicon, metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), conductive metal silicide, and conductive metal oxide (e.g., PtO, RuO 2 、IrO 2 、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 )、CRO(CaRuO 3 ) or LSCo), but the inventive concept is not limited thereto. The word line WL may include a single layer or multiple layers of the above-mentioned materials. In some embodiments, the word line WL may include a two-dimensional semiconductor material such as graphene, carbon nanotubes, or any combination thereof.

[0051] The upper gate capping pattern 113 may be disposed on the word line WL. The upper gate capping pattern 113 may be disposed between the word line WL and the contact pattern BC. The word line WL may be spaced apart from the contact pattern BC. The upper gate capping pattern 113 and the lower gate capping pattern 112 may include one or more of a silicon oxide layer, a silicon oxynitride layer, and a silicon nitride layer.

[0052] The gate dielectric pattern Gox may be disposed on the growth mask layer 111. The gate dielectric pattern Gox may be between the word line WL and the semiconductor pattern SP. The sidewall SP_SW of the semiconductor pattern SP may contact the sidewall of the gate dielectric pattern Gox and the sidewall 111_SW of the growth mask layer 111. The gate dielectric pattern Gox may surround the semiconductor pattern SP. The gate dielectric pattern Gox may separate the word line WL from the semiconductor pattern SP. The gate dielectric pattern Gox may have a uniform thickness to cover the semiconductor pattern SP. The gate dielectric pattern Gox may be between the second dielectric pattern 120 and the semiconductor pattern SP.

[0053] A sidewall of the gate dielectric pattern Gox may be in contact with the lower gate capping pattern 112, the word line WL, and the upper gate capping pattern 113. A bottom surface of the gate dielectric pattern Gox may be in contact with the top surface 111_TS of the growth mask layer 111.

[0054] The gate dielectric pattern Gox may include at least one selected from silicon oxide, silicon oxynitride, and a high-k dielectric whose dielectric constant is greater than that of silicon oxide. The high-k dielectric may include a metal oxide or a metal oxynitride. For example, the high-k dielectric that may be used as the gate dielectric pattern Gox may include a dielectric selected from HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO 2 、Al 2 O 3 and at least one selected from any combination thereof, but the inventive concept is not limited thereto.

[0055] The first dielectric pattern 140 may be interposed between word lines WL adjacent to each other in the first direction D1. The first dielectric pattern 140 may be interposed between the first word line WL1 and the second word line WL2. The sidewall of the first dielectric pattern 140 may contact the lower gate capping pattern 112, the word line WL, and the upper gate capping pattern 113.

[0056] The second dielectric pattern 120 may be between semiconductor patterns SP adjacent to each other in the second direction D2. The second dielectric pattern 120 may be in contact with the gate dielectric pattern Gox. The second dielectric pattern 120 may be provided in plurality. A plurality of second dielectric patterns 120 may extend longitudinally in the first direction D1 and may be spaced apart from each other in the second direction D2. The second dielectric pattern 120 may cover the top surface 111_TS of the growth mask layer 111. For example, the second dielectric pattern 120 may include at least one selected from silicon oxide, silicon nitride, silicon oxynitride, and a low-k dielectric. For example, the second dielectric pattern 120 may be formed by a single layer or a plurality of layers.

[0057] The contact pattern BC may be disposed on the semiconductor pattern SP. The contact pattern BC may be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx, or any combination thereof, but the inventive concept is not limited thereto. When viewed in a top view, the contact pattern BC has a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape, or any other suitable shape.

[0058] The landing pad LP may be disposed on the contact pattern BC. The landing pad LP may be in direct contact with the contact pattern BC and electrically connected to the contact pattern BC. When viewed in a top view, a plurality of contact patterns BC may be spaced apart from each other in the first direction D1 and the second direction D2, and may be arranged in a matrix shape, a zigzag shape, a honeycomb shape, or any other suitable shape. When viewed in a top view, a plurality of landing pads LP may each have a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, a hexagonal shape, or any other suitable shape.

[0059] The landing pad LP can be formed of doped polysilicon, Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, Co, TiN, TaN, WN, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, RuOx or any combination thereof, but the inventive concept is not limited thereto.

[0060] The separation dielectric pattern IL may be interposed between the contact patterns BC and between the landing pads LP. The separation dielectric pattern IL may contact the sidewalls of the contact patterns BC and the sidewalls of the landing pads LP. Upper surfaces of the separation dielectric pattern IL and the landing pads LP may be coplanar with each other.

[0061] The data storage pattern DSP may be correspondingly disposed on the landing pad LP. The data storage pattern DSP may be correspondingly electrically connected to the active area ACT. The data storage pattern DSP may be arranged in a matrix shape along the first direction D1 and the second direction D2. The data storage pattern DSP may completely or partially overlap the landing pad LP. The data storage pattern DSP may completely or partially contact the top surface of the landing pad LP.

[0062] According to an embodiment, the data storage pattern DSP may be a capacitor and may include a bottom electrode and a top electrode and a capacitor dielectric layer between the bottom electrode and the top electrode. Alternatively, the data storage pattern DSP may each be a variable resistance pattern that switches from one of its two resistance states to another resistance state by an applied electric pulse. For example, the data storage pattern DSP may include a phase change material, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material whose crystalline state changes based on the amount of current.

[0063] Figure 7 Shown along Figure 3 A cross-sectional view taken along line BB' of FIG. 1 shows a semiconductor device according to an exemplary embodiment of the inventive concept. For the sake of brevity of explanation, the same description of repeated components will not be repeated.

[0064] refer to Figure 7 In an embodiment, the width SPW of the semiconductor pattern SP may be different from the width SLW of the top surface BL_T of the bit line BL. The width SPW of the semiconductor pattern SP may be greater than the width SLW of the top surface BL_T of the bit line BL. Although the semiconductor pattern SP is silicon epitaxially grown from the bit line BL, the silicon orientation may be adjusted to achieve epitaxial growth in the third direction D3 as well as in the first direction D1 or the second direction D2.

[0065] The bottom surface SP_BS of the semiconductor pattern SP may be in contact with the top surface BL_T of the bit line BL and the top surface of the device isolation pattern STI In this case, the device isolation pattern STI may overlap the growth mask layer 111 and the semiconductor pattern SP.

[0066] Figure 8 Shown along Figure 3 A cross-sectional view taken along line BB' of FIG. 1 illustrates a semiconductor device according to an example embodiment of the inventive concept. For the sake of brevity of explanation, the same description of repeated parts will be omitted.

[0067] refer to Figure 8 The sensing capping layer 222 may be disposed on the semiconductor pattern SP. The sensing capping layer 222 may overlap the bit line BL and may not overlap the growth mask layer 111.

[0068] The top surface of the semiconductor pattern SP may be located at a height different from that of the top surface Gox_TS of the gate dielectric pattern Gox. The top surface of the semiconductor pattern SP may be lower than that of the top surface Gox_TS of the gate dielectric pattern Gox. The bottom surface 222_BS of the sensing cover layer 222 may be located at a height lower than that of the top surface Gox_TS of the gate dielectric pattern Gox, and the top surface of the sensing cover layer 222 may be coplanar with the top surface Gox_TS of the gate dielectric pattern Gox.

[0069] The sensing cap layer 222 may include transition metal silicide. The sensing cap layer 222 may include one or more of Au, Ni, Pt, and Al.

[0070] 9A to 13A A top view illustrating a method of fabricating a semiconductor device according to an example embodiment of the inventive concepts is shown. FIG. 9B to FIG. 13B Shown along Figure 3 A cross-sectional view taken along line AA′ of FIG. 1 illustrates a method of fabricating a semiconductor device according to an example embodiment of the inventive concept. FIG. 9C to FIG. 13C Shown along Figure 3 A cross-sectional view taken along line BB′ of FIG. 1 illustrates a method of fabricating a semiconductor device according to an example embodiment of the inventive concept.

[0071] refer to Figure 3 , Fig.9A , Fig. 9B and Fig. 9C , a seed line SL may be formed on the substrate 100 . The formation of the seed line SL may include, for example, depositing a phosphorus silicene-containing material on the substrate 100 .

[0072] refer to Figure 3 , Fig. 10A , Fig. 10B and Fig. 10C , a bit line BL may be formed on the substrate 100. A plurality of bit lines BL may be formed. The bit lines BL may be formed to extend longitudinally in the first direction D1 and to be spaced apart from each other in the second direction D2. The bit lines BL may be formed to be electrically connected to the underlying lines. The formation of the bit lines BL may include epitaxially growing phosphosilicate from a seed line SL serving as a seed pattern, and patterning the epitaxially grown phosphosilicate layer. For example, the formation of the bit lines BL may include epitaxially growing p-doped silicon using a chemical vapor deposition method. In this case, the bit lines BL may be formed at a temperature of approximately 1E20 / cm 3 Up to about 6E21 / cm 3 The concentration of p-doping is .

[0073] Afterwards, a device isolation pattern STI may be formed. The formation of the device isolation pattern STI may include removing an upper portion of the substrate 100 and a portion of an upper portion of the bit line BL using a patterning process and filling an empty region with the device isolation pattern STI.

[0074] The active area ACT may be defined to refer to a region of the substrate 100 surrounded by the device isolation pattern STI (eg, an upper portion that is not removed).

[0075] refer to Figure 3 , Fig.11A , Fig. 11B and Fig. 11C , a growth mask layer 111 may be formed on the bit line BL. The formation of the growth mask layer 111 may include forming a preliminary growth mask layer on the device isolation pattern STI and the bit line BL, and patterning the preliminary growth mask layer to form the growth mask layer 111 only on a section in which a channel will not be formed. The preliminary growth mask layer may be patterned by photolithography and etching processes.

[0076] The growth mask layer 111 may include an oxide. For example, the growth mask layer 111 may include SiO 2 Or Si(OC)N.

[0077] refer to Figure 3 , Fig. 12A , Fig. 12B and Fig. 12C , a semiconductor pattern SP may be formed on the bit line BL. The formation of the semiconductor pattern SP may include epitaxially growing the semiconductor pattern SP from the top surface BL_T of the bit line BL that is exposed without overlapping the growth mask layer 111. In this case, the semiconductor pattern SP may overlap the bit line BL but may not overlap the growth mask layer 111. As the semiconductor pattern SP is epitaxially grown from the bit line BL, the semiconductor pattern SP and the bit line BL may have the same lattice direction.

[0078] For example, a metal catalyst may be used to form the semiconductor pattern SP. The semiconductor pattern SP may be formed by using a transition metal such as Au, Ni, Pt, or Al as a catalyst. The formation of the semiconductor pattern SP may include introducing a precursor gas containing silicon onto the bit line BL. The precursor gas may include, for example, SiH 4 .

[0079] In an embodiment, the precursor gas and the doping gas (eg, boron) may be introduced together. In this case, the semiconductor pattern SP may include doped silicon.

[0080] refer to Figure 3 , Fig.13A , Fig. 13B and Fig. 13C, a gate dielectric pattern Gox, a lower gate capping pattern 112 , word lines WL1 and WL2 , an upper gate capping pattern 113 may be formed on the growth mask layer 111 , and a first dielectric pattern 140 and a second dielectric pattern 120 may be formed.

[0081] Thereafter, a contact pattern BC may be formed on the semiconductor pattern SP, and a landing pad LP may be formed on the contact pattern BC. A separation dielectric pattern IL may be formed to cover the contact pattern BC and the landing pad LP. A data storage pattern DSP may be formed on the landing pad LP. Figures 3 to 5 A semiconductor device is fabricated as shown.

[0082] FIG. 14A to FIG. 14C Shown according to Figure 8 For the sake of brevity of explanation, the same description of repeated parts will not be repeated.

[0083] refer to Figure 8 and Fig.14A , a bit line BL, a device isolation pattern STI, and a growth mask layer 111 may be formed on the substrate 100, and then a sensing cap layer 222 may be formed on the exposed bit line BL. The sensing cap layer 222 may include a transition metal silicide. The sensing cap layer 222 may include, for example, AuSi, NiSi, PtSi, or AlSi.

[0084] refer to Fig. 14B , the semiconductor pattern SP may be formed on the bit line BL and under the sensing cap layer 222. The formation of the semiconductor pattern SP may include allowing a precursor gas including silicon to be introduced to epitaxially grow silicon under the sensing cap layer 222. When the precursor gas is introduced, a doping gas may also be introduced. In this case, the semiconductor pattern SP may include doped silicon.

[0085] refer to Fig. 14C , a gate dielectric pattern Gox may be formed to cover side surfaces of the semiconductor pattern SP and the sensing cover layer 222 .

[0086] Thereafter, as discussed above, the lower gate capping pattern 112, the word lines WL1 and WL2, the upper gate capping pattern 113, the first dielectric pattern 140, the second dielectric pattern 120, the contact pattern BC, the landing pad LP, the separation dielectric pattern IL, and the data storage pattern DSP may be formed. Figure 8 A semiconductor device is fabricated as shown.

[0087] According to the inventive concept, a semiconductor channel can be formed by a bit line used as a seed line while a growth mask layer is disposed on a device isolation pattern. Since the semiconductor channel is formed by epitaxial growth, a semiconductor device can be simply manufactured.

[0088] Although the present invention has been described in conjunction with some embodiments of the present invention shown in the accompanying drawings, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the technical spirit and essential features of the present invention. It will be apparent to those skilled in the art that various substitutions, modifications and changes may be made without departing from the scope and spirit of the present invention.

Claims

1. A semiconductor device, comprising: a substrate comprising a device isolation pattern and an active region; a bit line extending in a first direction on the substrate; a semiconductor pattern, the semiconductor pattern being located on the bit line; a growth mask layer, the growth mask layer being located on the bit line, and a sidewall of the growth mask layer being in contact with the semiconductor pattern; a word line, the word line being located on the bit line, the word line extending in a second direction intersecting the first direction; as well as a gate dielectric pattern, the gate dielectric pattern being located between the word line and the semiconductor pattern, Wherein, a top surface of the growth mask layer is at a height higher than a height of a bottom surface of the semiconductor pattern.

2. The semiconductor device according to claim 1, wherein A lattice direction of the bit line is the same as a lattice direction of the semiconductor pattern.

3. The semiconductor device according to claim 1, wherein A width of the semiconductor pattern in the second direction is greater than a width of a top surface of the bit line in the second direction.

4. The semiconductor device according to claim 1, in, A top surface of the device isolation pattern contacts the growth mask layer, and Wherein, the bottom surface of the semiconductor pattern contacts the bit line.

5. The semiconductor device according to claim 1, wherein The bit line includes phosphosilicate. 6 . The semiconductor device according to claim 1 , further comprising a sensing cover layer, wherein the sensing cover layer is located on the semiconductor pattern.

7. The semiconductor device according to claim 6, wherein: The sensing cover layer includes one or more of Au, Ni, Pt and Al.

8. The semiconductor device according to claim 1, wherein The word line overlaps the growth mask layer.

9. A semiconductor device, comprising: a substrate comprising a device isolation pattern and an active region; a bit line extending in a first direction on the substrate; a semiconductor pattern, the semiconductor pattern being located on the bit line; a growth mask layer, the growth mask layer being located on the bit line; a word line, the word line being located on the bit line, the word line extending in a second direction intersecting the first direction; as well as a gate dielectric pattern, the gate dielectric pattern being located between the word line and the semiconductor pattern, Wherein, a sidewall of the semiconductor pattern contacts a sidewall of the gate dielectric pattern and a sidewall of the growth mask layer.

10. The semiconductor device according to claim 9, wherein The bit line includes phosphosilicate.

11. The semiconductor device according to claim 9, wherein: The growth mask layer overlaps the word line and the gate dielectric pattern.

12. The semiconductor device according to claim 9, wherein The growth mask layer is located between the gate dielectric pattern and the bit line.

13. The semiconductor device according to claim 9, wherein: A width of the semiconductor pattern in the second direction is different from a width of a top surface of the bit line in the second direction.

14. The semiconductor device according to claim 9, wherein: A top surface of the growth mask layer and a bottom surface of the gate dielectric pattern are at substantially the same height.

15. The semiconductor device according to claim 9, further comprising a sensing cover layer, wherein the sensing cover layer is located on the semiconductor pattern. in, A bottom surface of the sensing cover layer is at a height lower than that of a top surface of the gate dielectric pattern.

16. The semiconductor device according to claim 15, wherein: The sensing cover layer includes transition metal silicide.

17. A semiconductor device, comprising: a substrate comprising a device isolation pattern and an active region; a cell array structure, wherein the cell array structure is located on the substrate; a peripheral circuit structure, the peripheral circuit structure being located on the substrate and adjacent to the cell array structure in a first direction parallel to an extension direction of the substrate, the peripheral circuit structure comprising a peripheral gate structure and a peripheral contact pad; A bit line, the bit line is located in the cell array structure, and the bit line extends in the first direction; a semiconductor pattern, the semiconductor pattern being located on the bit line; a growth mask layer, the growth mask layer being located on the bit line, and a sidewall of the growth mask layer being in contact with the semiconductor pattern; a first word line and a second word line, the first word line and the second word line are located on the bit line, and the first word line and the second word line extend in a second direction intersecting the first direction; a gate dielectric pattern, the gate dielectric pattern being located between the first word line and the semiconductor pattern; a contact pattern, the contact pattern being located on the semiconductor pattern; as well as a landing pad, the landing pad being located on the contact pattern, wherein the top surface of the landing pad is at the same height as the top surface of the peripheral contact pad, wherein the bottom surface of the peripheral gate structure is at the same height as the bottom surface of the bit line, and Wherein, a top surface of the growth mask layer is at a height higher than a height of a bottom surface of the semiconductor pattern.

18. The semiconductor device according to claim 17, further comprising: a sensing cover layer, the sensing cover layer being located on the semiconductor pattern, Wherein, a bottom surface of the sensing cover layer is at a height lower than a height of a top surface of the gate dielectric pattern.

19. The semiconductor device according to claim 18, wherein: The sensing cover layer includes transition metal silicide.

Images