A high-heat-dissipation double-layer back barrier transistor, its fabrication method and application

Abstract

This invention discloses a high-heat-dissipation double-layer back barrier transistor, its fabrication method, and its applications, relating to the field of microelectronics technology. It includes a substrate, and multiple layers of h-BN layers, a site-controlled B-diffusion double-layer back barrier layer, a channel layer, a barrier layer, a cap layer, a passivation layer, and a metal gate layer sequentially stacked on the substrate. The multiple h-BN layers are multi-layer h-BN layers implanted with high-energy aluminum ions. The site-controlled B-diffusion double-layer back barrier layer includes AlN and GaN layers sequentially deposited on the multiple h-BN layers. This invention utilizes site-controlled ion implantation technology to achieve the effect of a site-controlled B-diffusion-assisted epitaxial barrier layer. Furthermore, a double-layer back barrier is formed between the upper GaN layer and the lower AlN layer using a two-step B-diffusion Gaussian distribution method. Due to the B interface state modulation within the back barrier, the lattice mismatch and thermal mismatch between the upper and lower layers are optimized, significantly improving heat dissipation. Simultaneously, the double-layer back barrier can effectively reduce leakage current and improve the transistor breakdown voltage.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, specifically to a high heat dissipation double-layer back barrier transistor, its fabrication method, and its application. Background Technology

[0002] AlGaN / GaN transistors occupy an important position in radio frequency (RF) technology due to their excellent electron mobility, breakdown voltage, and power density. These characteristics enable AlGaN / GaN transistors to perform exceptionally well in high-frequency and high-power applications, and they are widely used in radar, communication systems, and power amplifiers. Despite the many advantages of AlGaN / GaN transistors, high-frequency signals are prone to delay and distortion during transmission under high-frequency operating conditions, affecting device performance. To improve device performance, a back barrier layer is often introduced into the device structure.

[0003] However, traditional back barrier processes have several drawbacks that can affect device performance and reliability. The back barrier layer is typically composed of a different material than the channel layer. For example, using AlN as the back barrier layer in AlGaN / GaN transistors, without a GaN buffer layer, can lead to lattice mismatch, resulting in strain and impacting device performance. Roughness or defects at the interface between the back barrier layer (AlN, AlGaN, and InGaN) and the channel layer can increase carrier scattering, thereby reducing device mobility and current density.

[0004] Existing technologies employ AlGaN / GaN transistors with a graded Al composition AlGaN back barrier structure. However, the growth process of this graded Al composition is inherently difficult to control, and the constantly changing composition easily introduces more interface defects. Existing technologies also utilize InGaN back barriers; however, due to the lower growth temperature of InGaN, it is difficult to form a high-quality epitaxial layer, and controlling the In composition is also very challenging. Those skilled in the art have attempted to fabricate AlGaN / GaN transistors by optimizing the AlN back barrier, but the significant lattice mismatch between AlN and GaN can lead to stress accumulation, ultimately affecting the device's reliability and lifespan. Summary of the Invention

[0005] To address the shortcomings of the aforementioned background technology, this invention provides a high-heat-dissipation double-layer back barrier transistor, its fabrication method, and its applications. This invention proposes a site-controlled B-diffused double-layer back barrier scheme, increasing the back barrier height, effectively reducing leakage current, and thus improving the device's breakdown voltage. Through site-controlled B-interface state modulation within the back barrier, the lattice mismatch and thermal mismatch issues between the upper and lower layers are significantly optimized. Simultaneously, the site-controlled B-diffused double-layer back barrier and the GaN channel interface achieve homoepitaxial growth, effectively solving the impact of internal lattice stress and electron scattering on the transistor channel.

[0006] The first objective of this invention is to provide a high heat dissipation double-layer back barrier transistor, comprising a substrate, and multiple layers of h-BN layer, control position B diffusion double-layer back barrier layer, channel layer, barrier layer, cap layer, passivation layer and metal gate layer sequentially stacked on the substrate.

[0007] The multilayer h-BN layer is a multilayer h-BN layer implanted with high-energy aluminum ions at specific points;

[0008] The controlled-site B-diffusion bilayer back barrier layer comprises AlN and GaN layers deposited sequentially on multiple h-BN layers.

[0009] Preferably, the number of the multilayer h-BN layers is 2 to 10; the thickness of the AlN layer is 200-300 nm; and the thickness of the GaN layer is 100-200 nm.

[0010] Preferably, the channel layer is a GaN channel layer with a thickness of 120-160 nm; the barrier layer is Al. 0.25 Ga 0.75 The N-type barrier layer has a thickness of 20-30 nm; the cap layer is a GaN cap layer with a thickness of 3-5 nm; and the passivation layer is a SiN passivation layer with a thickness of 120-160 nm.

[0011] Preferably, the metal gate layer is Ni / Au as the gate metal.

[0012] The second objective of this invention is to provide a method for fabricating a high-heat-dissipation double-layer back barrier transistor, characterized by comprising the following steps:

[0013] Multilayer h-BN is transferred onto a substrate using PDMS-assisted wet transfer, i.e., multilayer h-BN layers are fabricated on the substrate.

[0014] High-energy aluminum ions are implanted at specific points on the multilayer h-BN layer to form a multi-B quasi-van der Waals epitaxial region on the multilayer h-BN layer;

[0015] An AlN layer was deposited on a multi-B quasi-van der Waals epitaxial region, followed by annealing, and then a GaN layer was deposited. After annealing, a site-controlled B diffusion bilayer back barrier layer was obtained.

[0016] GaN channel layer and Al were sequentially deposited on a B-diffusion-controlled bilayer back barrier layer. 0.25 Ga 0.75 N-barrier layer and GaN cap layer;

[0017] A SiN passivation layer is deposited on the GaN cap layer, and then the gate region is defined by electron beam lithography. The gate metal layer is obtained by evaporating the metal, thus obtaining a high heat dissipation double-layer back barrier transistor.

[0018] Preferably, a multilayer h-BN layer is formed on the substrate, comprising:

[0019] Multilayer h-BN layers are grown on one side of a copper foil, and PMMA is coated on the other side of the copper foil. After curing, the PMMA is adsorbed onto PDMS, and the PDMS is immersed in ammonium persulfate solution for 6-12 hours. The copper foil is then removed, and the multilayer h-BN layers are transferred to the substrate through PDMS. Subsequently, the substrate is immersed in acetone solution to remove PDMS and PMMA, thus forming multilayer h-BN layers on the substrate.

[0020] Preferably, high-energy aluminum ions are implanted at specific points onto the multilayer h-BN layer to form a multi-B quasi-van der Waals epitaxial region on the multilayer h-BN layer, including:

[0021] The multilayer h-BN layer and the substrate are placed in a reaction chamber at room temperature and a pressure of 10 Torr. A high-energy aluminum ion beam is then accelerated and enters the reaction chamber, and is directed at the surface of the multilayer h-BN layer at an angle of 5-15°, thus forming a multi-B quasi-van der Waals epitaxial region on the multilayer h-BN layer.

[0022] Preferably, the controlled-site B-diffusion double-layer back barrier layer is prepared according to the following steps:

[0023] In a chamber at 1200–1300 °C and 35–45 Torr, with H2 flow rate set to 800–1000 sccm, NH3 flow rate set to 1000–2000 sccm, and trimethylaluminum flow rate set to 80–100 μmol / L, an AlN layer was deposited on the multi-B quasi-van der Waals epitaxial region. While maintaining a constant chamber temperature, the pressure was increased to 650–750 Torr for annealing for 2–4 minutes to allow B diffusion to modulate the AlN interface state. The chamber temperature was then reduced to 1050–1150 °C and the pressure to 150–250 Torr, with N2 flow rate set to 2000 sccm, H2 flow rate set to 800–1000 sccm, and NH3 flow rate set to 1000–2000 μmol / L. GaN layers were deposited using sccm and trimethylgallium flow rate of 150-200 μmol / L, and then annealed for 10-20 min at 650-750 °C and 750-850 Torr to obtain a patterned controlled-site B-diffused bilayer back barrier layer.

[0024] Preferably, after depositing the GaN cap layer, the process further includes:

[0025] After RCA cleaning and ICP etching, a 1 μm linewidth ohmic contact region was defined using a double-layer adhesion technique. Subsequently, metallization and stabilization were performed by annealing in nitrogen at 800-900°C for 30-40 seconds. The metals used were Ti / Al / Ni / Au.

[0026] The third objective of this invention is to provide an application of a high-heat-dissipation double-layer back barrier transistor in a communication system.

[0027] Compared with the prior art, the beneficial effects of the present invention are:

[0028] This invention provides a high-heat-dissipation double-layer back barrier transistor, its fabrication method, and its applications. By employing a controlled-site B-diffusion double-layer back barrier structure, this invention not only possesses the functions of other back barrier layers but also increases the back barrier height, effectively reducing leakage current and thus improving the device's breakdown voltage. Point-to-point high-energy aluminum ion implantation modulates the interface states of multilayer h-BN thin films, disrupting the BN bonds in the multilayer h-BN and generating B-Al and N-Al dangling bonds, as well as free-state B atoms, forming patterned multi-B, quasi-van der Waals epitaxial regions on the multilayer h-BN. The lower layer of the controlled-site B-diffusion double-layer back barrier grows through the h-BN quasi-van der Waals epitaxy mode. High-energy aluminum ion implantation not only increases the nucleation sites of h-BN through dangling bonds and improves interlayer stress to obtain free-state B atoms, but also allows for rapid growth of nuclei in the ion-implanted region, forming fused regions that are annihilated by the slowly growing nuclei, significantly reducing dislocations. The upper layer of the site-controlled B-diffused double-layer back barrier is a B-diffused GaN epitaxial layer. This layer achieves homoepitaxial growth with the GaN channel, effectively solving the impact of internal lattice mismatch and stress problems on the transistor channel. The upper GaN layer and the lower AlN layer of the back barrier form a double-layer back barrier through a two-step B-diffusion Gaussian distribution method. The B interface states inside the back barrier are controlled, which greatly optimizes the lattice mismatch and thermal mismatch problems between the upper and lower layers.

[0029] This invention regulates the interface state of h-BN by targeted implantation of high-energy aluminum ions, and grows subsequent structures in a quasi-van der Waals epitaxy mode. This regulation method can not only increase the nucleation sites of the h-BN layer, improve interlayer stress, and significantly reduce dislocations through dangling bonds, but also allow free B atoms to diffuse into the back barrier layer through annealing to assist subsequent epitaxy.

[0030] This invention proposes a site-controlled B-diffused double-layer back barrier scheme, which increases the back barrier height, effectively reduces leakage current, and thus improves the device's breakdown voltage. Through B-interface state modulation within the back barrier, the lattice and thermal mismatch issues between the upper and lower layers are significantly optimized. Simultaneously, it enables homoepitaxial development of the site-controlled B-diffused double-layer back barrier and the GaN channel interface, effectively addressing the impact of internal lattice stress and electron scattering on the transistor channel. Attached Figure Description

[0031] Figure 1 A schematic diagram of a high-heat-dissipation double-layer back barrier transistor structure;

[0032] Figure 2 Flowchart for fabrication of a high-heat-dissipation double-layer back barrier transistor;

[0033] Figure 3 A schematic diagram of a high-heat-dissipating double-layer back barrier for boron nitride-assisted epitaxy with ion-site implantation regulation. Detailed Implementation

[0034] To enable those skilled in the art to better understand and implement the technical solutions of the present invention, the present invention will be further described below in conjunction with specific embodiments and accompanying drawings. However, the embodiments described are not intended to limit the present invention.

[0035] This invention provides a high-heat-dissipation double-layer back barrier transistor, see [link to relevant documentation]. Figure 1 As shown, it includes a substrate 1, and multiple layers of h-BN layer 2, control site B diffusion double layer back barrier layer 3, channel layer, barrier layer, cap layer 4, passivation layer and metal gate layer 5 are stacked sequentially on the substrate 1.

[0036] The multilayer h-BN layer is a multilayer h-BN layer implanted with high-energy aluminum ions at specific points;

[0037] The controlled-site B-diffusion bilayer back barrier layer comprises AlN and GaN layers deposited sequentially on multiple h-BN layers.

[0038] The controlled-site B-diffusion double-layer back barrier employed in this invention not only possesses the functions of other back barrier layers but also enhances the back barrier height, effectively reducing leakage current and thus improving the device's breakdown voltage. High-energy aluminum ion implantation modulates the interface states of the multilayer h-BN thin film, disrupting the BN bonds in the multilayer h-BN and generating B-Al and N-Al dangling bonds, as well as free B atoms, forming patterned multi-B quasi-van der Waals epitaxial regions on the multilayer h-BN. The lower layer of the controlled-site B-diffusion double-layer back barrier is grown using the h-BN quasi-van der Waals epitaxial mode. High-energy aluminum ion implantation not only increases the nucleation sites of h-BN and improves interlayer stress through controlled dangling bonds but also facilitates the diffusion of free B atoms. The upper layer of the controlled-site B-diffusion double-layer back barrier is a B-diffused GaN epitaxial layer. This layer achieves homoepitaxialization with the GaN channel, effectively solving the impact of internal lattice mismatch and stress problems on the transistor channel. The upper GaN and lower AlN layers of the back barrier are formed into a double-layer back barrier through a two-step B-diffusion Gaussian distribution method. The B interface states inside the back barrier are controlled, which greatly optimizes the lattice mismatch and thermal mismatch problems between the upper and lower layers.

[0039] The number of h-BN layers is 2 to 10; the thickness of the AlN layer is 200-300 nm; and the thickness of the GaN layer is 100-200 nm.

[0040] The channel layer is a GaN channel layer with a thickness of 120~160nm;

[0041] The barrier layer is Al. 0.25 Ga 0.75 The N-barrier layer has a thickness of 20~30 nm;

[0042] The capping layer is a GaN capping layer with a thickness of 3~5 nm;

[0043] The passivation layer is a SiN passivation layer with a thickness of 120~160 nm.

[0044] The metal gate layer uses pure metal Ni / Au as the gate metal. Ni / Au refers to pure metals nickel and gold.

[0045] This invention provides a high heat dissipation double-layer back barrier transistor, its fabrication method, and its application, comprising the following steps:

[0046] Multilayer h-BN is transferred onto a substrate using PDMS-assisted wet transfer, i.e., multilayer h-BN layers are fabricated on the substrate.

[0047] High-energy aluminum ions are implanted at specific points on the multilayer h-BN layer to form a multi-B quasi-van der Waals epitaxial region on the multilayer h-BN layer;

[0048] An AlN layer was deposited on a multi-B quasi-van der Waals epitaxial region, followed by annealing, and then a GaN layer was deposited. After annealing, a site-controlled B diffusion bilayer back barrier layer was obtained.

[0049] GaN channel layer and Al were sequentially deposited on a B-diffusion-controlled bilayer back barrier layer. 0.25 Ga 0.75 N-barrier layer and GaN cap layer;

[0050] A SiN passivation layer is deposited on the GaN cap layer, and then the gate region is defined by electron beam lithography. The gate metal layer is obtained by evaporating the metal, thus obtaining a high heat dissipation double-layer back barrier transistor.

[0051] This invention proposes a high-heat-dissipation double-layer back barrier transistor, its fabrication method, and its applications. First, by controlling the interface states of h-BN through high-energy aluminum ion implantation, subsequent structures are grown in a quasi-van der Waals epitaxial mode. This control method not only increases the nucleation sites of the h-BN layer through dangling bonds, improves interlayer stress, and significantly reduces dislocations, but also allows free-state B atoms to diffuse into the back barrier layer through annealing to assist in subsequent epitaxy. Second, a site-controlled B-diffusion double-layer back barrier scheme is proposed, increasing the back barrier height and effectively reducing leakage current, thereby improving the device's breakdown voltage. The B interface states within the back barrier are controlled, greatly optimizing the lattice and thermal mismatch problems between the upper and lower layers. Simultaneously, the site-controlled B-diffusion double-layer back barrier and the GaN channel interface achieve homogeneous epitaxy, effectively solving the impact of internal lattice stress and electron scattering on the transistor channel.

[0052] Among them, multiple h-BN layers are fabricated on the substrate, including:

[0053] Multilayer h-BN layers are grown on one side of a copper foil, and PMMA is coated on the other side of the copper foil. After curing, the PMMA is adsorbed onto PDMS, and the PDMS is immersed in ammonium persulfate solution for 6-12 hours. The copper foil is then removed, and the multilayer h-BN layers are transferred to the substrate through PDMS. Subsequently, the substrate is immersed in acetone solution to remove PDMS and PMMA, thus forming multilayer h-BN layers on the substrate.

[0054] Specifically, high-energy aluminum ions are implanted at specific points on multilayer h-BN layers to form multi-B quasi-van der Waals epitaxial regions on the multilayer h-BN layers, including:

[0055] The multilayer h-BN layer and the substrate are placed in a reaction chamber at room temperature and a pressure of 10 Torr. A high-energy aluminum ion beam is then accelerated and enters the reaction chamber, and is directed at the surface of the multilayer h-BN layer at an angle of 5-15°, thus forming a multi-B quasi-van der Waals epitaxial region on the multilayer h-BN layer.

[0056] The controlled-position B-diffused double-layer back barrier layer is prepared according to the following steps:

[0057] In a chamber at 1200–1300 °C and 35–45 Torr, with H2 flow rate set to 800–1000 sccm, NH3 flow rate set to 1000–2000 sccm, and trimethylaluminum flow rate set to 80–100 μmol / L, an AlN layer was deposited on the multi-B quasi-van der Waals epitaxial region. While maintaining a constant chamber temperature, the pressure was increased to 650–750 Torr for annealing for 2–4 minutes to allow B diffusion to modulate the AlN interface state. The chamber temperature was then reduced to 1050–1150 °C and the pressure to 150–250 Torr, with N2 flow rate set to 2000 sccm, H2 flow rate set to 800–1000 sccm, and NH3 flow rate set to 1000–2000 μmol / L. GaN layers were deposited using sccm and trimethylgallium flow rate of 150-200 μmol / L, and then annealed for 10-20 min at 650-750 °C and 750-850 Torr to obtain a site-controlled B-diffused bilayer back barrier layer.

[0058] According to the present invention, after depositing the GaN cap layer, the method further includes:

[0059] After RCA cleaning and ICP etching, a 1 μm linewidth ohmic contact region was defined using a double-layer adhesion technique. Subsequently, metallization and stabilization were performed by annealing in nitrogen at 800-900°C for 30-40 seconds. The metals used were Ti / Al / Ni / Au.

[0060] For example, see Figure 2As shown, a method for fabricating a high heat dissipation double-layer back barrier transistor includes: Step 1: transferring multilayer h-BN onto a sapphire substrate by PDMS-assisted wet transfer;

[0061] Step 2: High-energy aluminum ion targeted implantation is used to regulate the interface states of the h-BN layer to prepare multi-B quasi-van der Waals epitaxial regions;

[0062] Step 3: Use a composite h-BN layer as a B source and perform staged annealing to prepare a controlled-site B diffusion bilayer back barrier;

[0063] Step 4: Fabricate AlGaN / GaN transistors with controlled-site B-diffused double-layer back barrier;

[0064] In one embodiment of the present invention, step 1 includes: transferring multilayer h-BN onto a sapphire substrate by PMMA / PDMS-assisted wet transfer.

[0065] (1a) Polish the front side of the copper foil and grow a multilayer h-BN film on the copper foil by CVD or other methods;

[0066] (1b) Spin-coat a layer of PMMA onto the surface of a copper foil with multiple h-BN layers. The initial rotation speed is 1000 rpm for 6 s, and then the rotation speed is 3000 rpm for 60 s. Place the spin-coated copper foil on a drying rack and dry it at 55°C for 20 min to allow the PMMA film to cure.

[0067] (1c) After spin coating, the PMMA surface is adsorbed onto PDMS;

[0068] (1d) PDMS was immersed in a 64 g / L ammonium persulfate solution for 6-12 hours, and the metal substrate was removed to obtain a multilayer h-BN film with PDMS / PMMA.

[0069] (1e) The multilayer h-BN film was transferred onto the sapphire substrate by PDMS and immersed in acetone solution for 12-24h to remove the PDMS / PMMA layer;

[0070] (1f) The multilayer h-BN / sapphire substrate was transferred from the acetone solution to the ethanol solution and left to stand for 30 min to remove the residual acetone solution. Then the substrate was taken out and dried quickly with a nitrogen gun to complete the transfer of the multilayer h-BN film.

[0071] In one experimental example of the present invention, see Figure 3 As shown, step 2 includes: high-energy aluminum ion targeted implantation to regulate the interface states of the h-BN layer and prepare multi-B quasi-van der Waals epitaxial regions.

[0072] (2a) The ion accelerator uses a 5-10kV high-voltage electric field to accelerate the ion, forming an energy of 30keV and a dose of 10.12 -10 14 High-energy aluminum ion beam;

[0073] (2b) The multilayer h-BN / sapphire substrate is placed in the reaction chamber. The temperature of the reaction chamber is room temperature and the pressure is 10 Torr. The high-energy aluminum ion beam is accelerated and enters the reaction chamber, and is directed at the surface of the multilayer h-BN / sapphire substrate at a 5-15° angle.

[0074] (2c) After ions penetrate into the material surface, they collide and break the BN bonds of the multilayer h-BN, generating B-Al, N-Al dangling bonds, and free B atoms, forming patterned multi-B, quasi-van der Waals epitaxial regions on the multilayer h-BN.

[0075] In one embodiment of the present invention, step 3 includes: using a composite h-BN layer as a B source, and preparing a controlled-site B diffusion bilayer back barrier by staged annealing.

[0076] (3a) MOCVD was used at 1250 °C and 40 Torr, with H2 flow rate set to 800-1000 sccm, NH3 flow rate set to 1000-2000 sccm, and trimethylaluminum flow rate set to 80-100 μmol / L. A 200 nm thick B-diffused AlN layer was deposited on the multi-B quasi-van der Waals epitaxial h-BN film.

[0077] (3b) Annealing was performed at 1250℃ and 700 Torr for 3 minutes to induce B diffusion and regulate the AlN interface state;

[0078] (3c) Using MOCVD, at 1100℃ and 100 Torr, the N2 flow rate was set to 2000 sccm, the H2 flow rate to 800-1000 sccm, the NH3 flow rate to 1000-2000 sccm, and the trimethylgallium flow rate to 150-200 μmol / L. A 100 nm thick boron-diffused GaN layer was deposited.

[0079] (3d) The B-diffused bilayer back barrier layer was obtained by annealing at 700℃ and 800 Torr for 15 minutes.

[0080] In one experimental example of the present invention, step 4 includes: fabricating a high heat dissipation double-layer back barrier transistor.

[0081] (4a) Using MOCVD, at 1050 °C and 200 Torr, the N2 flow rate was set to 2000 sccm, the H2 flow rate to 1500 sccm, the NH3 flow rate to 500 sccm, and the trimethylgallium flow rate to 100 μmol / L. A 120 nm GaN channel layer was deposited on the B-diffused bilayer back barrier layer;

[0082] (4b) MOCVD was used at 1000 °C and 200 Torr, with N2 flow rate set to 2000 sccm, H2 flow rate set to 1500 sccm, NH3 flow rate set to 500 sccm, trimethylaluminum flow rate set to 60 μmol / L, and trimethylgallium flow rate set to 10 μmol / L. A 20 nm layer of Al was deposited on the channel layer. 0.25 Ga 0.75 N-barrier layer;

[0083] (4c) MOCVD was used at 950℃ and 200 Torr, with N2 flow rate set to 2000 sccm, H2 flow rate to 1500 sccm, NH3 flow rate to 500 sccm, and trimethylgallium flow rate to 10 μmol / L. In Al... 0.25 Ga 0.75 A 3nm GaN cap layer is deposited on the N-barrier layer;

[0084] (4d) After RCA cleaning and ICP etching, an ohmic contact region with a linewidth of 1 μm was defined using a double-layer adhesion technique. Subsequently, metallization and stabilization were performed by annealing at 850°C for 35 seconds in nitrogen. The metal used was Ti / Al / Ni / Au.

[0085] (4e) A 120 nm thick SiN layer was deposited by PECVD, the gate region was defined by electron beam lithography, and the aperture was opened by ICP-RIE. Finally, Ni / Au was evaporated as the gate metal to obtain a high heat dissipation double-layer back barrier transistor.

[0086] See Figure 1 As shown, the high-heat-dissipation double-layer back barrier transistor fabricated by the above method of the present invention consists of, from top to bottom, a sapphire substrate 1, a high-energy aluminum ion implanted multilayer h-BN layer 2, a site-controlled B-diffusion double-layer back barrier AlN / GaN layer 3, a GaN channel layer, and an AlN / Ga ... 0.25 Ga 0.75 4. N-barrier layer, GaN cap layer, SiN passivation layer / gate metal layer.

[0087] The present invention will be further described below by changing the number of h-BN layers to obtain a high heat dissipation double-layer back barrier transistor.

[0088] This invention provides an application of a high heat dissipation double-layer back barrier transistor in a communication system.

[0089] It should be noted that, unless otherwise specified, the experimental methods used in this invention are all conventional methods; and the reagents and materials used, unless otherwise specified, are all commercially available.

[0090] Example 1

[0091] High heat dissipation bilayer back barrier transistor based on bilayer h-BN.

[0092] Step 1, PMMA / PDMS-assisted wet transfer of multilayer h-BN:

[0093] The front side of a polished copper foil was then used to grow two h-BN thin films via CVD or similar methods. A layer of PMMA was spin-coated onto the copper foil with the double h-BN layers, initially at 1000 rpm for 6 seconds, then at 3000 rpm for 60 seconds. The spin-coated copper foil was then dried at 55°C for 20 minutes to allow the PMMA film to cure. After spin-coating, the PMMA surface was adsorbed onto PDMS. The PDMS was then immersed in a 64 g / L ammonium persulfate solution for 6 hours to remove the copper foil substrate. The double h-BN film was transferred to a sapphire substrate using PDMS and immersed in acetone for 12 hours to remove the PDMS / PMMA layer. Subsequently, the double h-BN / sapphire substrate was transferred from the acetone solution to an ethanol solution and allowed to stand for 30 minutes to remove residual acetone. The substrate was then removed and rapidly air-dried using a nitrogen gun to complete the transfer of the multilayer h-BN film.

[0094] Step 2: High-energy aluminum ion targeted implantation to regulate the interface states of the h-BN layer, preparing multi-B quasi-van der Waals epitaxial regions:

[0095] The ion accelerator uses a 5kV high-voltage electric field to accelerate the ion, resulting in an energy of 30keV and a dose of 10. 12 A high-energy aluminum ion beam was used. A multilayer h-BN / sapphire substrate was placed in a reaction chamber at room temperature and a pressure of 10 Torr. The high-energy aluminum ion beam, after acceleration, entered the reaction chamber and was directed at a fixed point at a 5° angle onto the surface of the multilayer h-BN / sapphire substrate. The ions penetrated the material surface, colliding and breaking the BN bonds in the multilayer h-BN, generating B-Al and N-Al dangling bonds, as well as free B atoms, forming a Gaussian-distributed multi-B quasi-van der Waals epitaxial region on the multilayer h-BN.

[0096] Step 3: Using the composite h-BN layer as a B source, staged annealing is performed to prepare a controlled-site B diffusion bilayer back barrier.

[0097] MOCVD was used to deposit a 200 nm thick B-diffused AlN layer on a multi-B quasi-van der Waals epitaxial h-BN film in a chamber at 1250 °C and 40 Torr, with H2 flow rates of 800 sccm, NH3 flow rates of 1000 sccm, and trimethylaluminum flow rates of 80 μmol / L. The chamber temperature was kept constant, but the pressure was increased to 700 Torr for 3 minutes of annealing to modulate the AlN interface states through B diffusion. The chamber temperature was then decreased to 1100 °C, the pressure to 200 Torr, and the N2 flow rates to 2000 sccm, H2 flow rates to 800 sccm, NH3 flow rates to 1000 sccm, and trimethylgallium flow rates to 150 μmol / L. A 100 nm thick B-diffused GaN layer was deposited; annealing at 700 °C and 800 Torr for 15 minutes yielded a B-diffused bilayer back barrier layer.

[0098] Step 4: Fabricate a high-heat-dissipation double-layer back barrier transistor:

[0099] MOCVD was used at 1050 °C and 200 Torr, with N2 flow rates set to 2000 sccm, H2 flow rates to 1500 sccm, NH3 flow rates to 500 sccm, and trimethylgallium flow rates to 100 μmol / L. A 120 nm GaN channel layer was deposited on a boron-diffused bilayer back barrier layer. The chamber temperature was then reduced to 1000 °C, while the pressure remained constant, with N2 flow rates set to 2000 sccm, H2 flow rates to 1500 sccm, NH3 flow rates to 500 sccm, trimethylaluminum flow rates to 60 μmol / L, and trimethylgallium flow rates to 10 μmol / L. A 20 nm Al layer was then deposited on the channel layer. 0.25 Ga 0.75 N-barrier layer. The chamber temperature was reduced to 950℃, pressure remained constant, and the N2 flow rate was set to 2000 sccm, H2 flow rate to 1500 sccm, NH3 flow rate to 500 sccm, and trimethylgallium flow rate to 10 μmol / L. In Al... 0.25 Ga 0.75 A 3 nm GaN cap layer was deposited on the N-type barrier layer. After RCA cleaning and ICP etching, a 1 μm linewidth ohmic contact region was defined using a bilayer adhesion technique. Subsequently, metallization and stabilization were performed by annealing at 850°C for 35 seconds in nitrogen (metal evaporation was performed in this region using Ti / Al / Ni / Au metals, and a stable ohmic contact was formed with the aid of a nitrogen environment). A 120 nm thick SiN layer was deposited by PECVD, the gate region was defined using electron beam lithography, and vias were opened using ICP-RIE. Finally, Ni / Au was evaporated as the gate metal to obtain a high-heat-dissipating bilayer back barrier transistor.

[0100] Example 2

[0101] High heat dissipation double-layer back barrier transistor based on few-layer h-BN

[0102] Step 1, PMMA / PDMS-assisted wet transfer of multilayer h-BN:

[0103] The front side of a polished copper foil was then used to grow five layers of h-BN film via CVD or other methods. A layer of PMMA was spin-coated onto the copper foil surface with a few h-BN layers, initially at 1000 rpm for 6 seconds, then at 3000 rpm for 60 seconds. The spin-coated copper foil was then dried at 55°C for 20 minutes to allow the PMMA film to cure. After spin-coating, the PMMA surface was adsorbed onto PDMS. The PDMS was then immersed in a 64 g / L ammonium persulfate solution for 9 hours to remove the copper foil substrate. The few h-BN layers were transferred to a sapphire substrate using PDMS and immersed in acetone for 18 hours to remove the PDMS / PMMA layer. Subsequently, the multilayer h-BN / sapphire substrate was transferred from the acetone solution to an ethanol solution and allowed to stand for 30 minutes to remove residual acetone. The substrate was then removed and rapidly air-dried using a nitrogen gun to complete the transfer of the few h-BN layers.

[0104] Step 2: High-energy aluminum ion targeted implantation to regulate the interface states of the h-BN layer, preparing multi-B quasi-van der Waals epitaxial regions:

[0105] The ion accelerator uses an 8kV high-voltage electric field to accelerate the ion, resulting in an energy of 30keV and a dose of 10. 13 A high-energy aluminum ion beam was used. A multilayer h-BN / sapphire substrate was placed in a reaction chamber at room temperature and a pressure of 10 Torr. The high-energy aluminum ion beam, after acceleration, entered the reaction chamber and was directed at a fixed point at a 10° angle onto the surface of the multilayer h-BN / sapphire substrate. The ions penetrated the material surface, colliding and breaking the BN bonds in the multilayer h-BN, generating B-Al and N-Al dangling bonds, as well as free B atoms, forming a Gaussian-distributed multi-B quasi-van der Waals epitaxial region on the multilayer h-BN.

[0106] Step 3: Using the composite h-BN layer as a B source, staged annealing is performed to prepare a controlled-site B diffusion bilayer back barrier.

[0107] MOCVD was used to deposit a 200 nm thick B-diffused AlN layer on a multi-B quasi-van der Waals epitaxial h-BN film in a chamber at 1250 °C and 40 Torr, with H2 flow rates of 900 sccm, NH3 flow rates of 1500 sccm, and trimethylaluminum flow rates of 90 μmol / L. The chamber temperature was kept constant, but the pressure was increased to 700 Torr for 3 minutes of annealing to modulate the AlN interface states through B diffusion. The chamber temperature was then decreased to 1100 °C, the pressure to 200 Torr, and the N2 flow rates to 2000 sccm, H2 flow rates to 900 sccm, NH3 flow rates to 1500 sccm, and trimethylgallium flow rates to 200 μmol / L. A 100 nm thick B-diffused GaN layer was deposited; annealing at 700 °C and 800 Torr for 15 minutes yielded a B-diffused bilayer back barrier layer.

[0108] Step 4: Fabricate a high-heat-dissipation double-layer back barrier transistor:

[0109] MOCVD was used at 1050 °C and 200 Torr, with N2 flow rates set to 2000 sccm, H2 flow rates to 1500 sccm, NH3 flow rates to 500 sccm, and trimethylgallium flow rates to 100 μmol / L. A 120 nm GaN channel layer was deposited on a boron-diffused bilayer back barrier layer. The chamber temperature was then reduced to 1000 °C, while the pressure remained constant, with N2 flow rates set to 2000 sccm, H2 flow rates to 1500 sccm, NH3 flow rates to 500 sccm, trimethylaluminum flow rates to 60 μmol / L, and trimethylgallium flow rates to 10 μmol / L. A 20 nm Al layer was then deposited on the channel layer. 0.25 Ga 0.75 N-barrier layer. The chamber temperature was reduced to 950℃, pressure remained constant, and the N2 flow rate was set to 2000 sccm, H2 flow rate to 1500 sccm, NH3 flow rate to 500 sccm, and trimethylgallium flow rate to 10 μmol / L. In Al... 0.25 Ga 0.75 A 3 nm GaN cap layer was deposited on the N-type barrier layer. After RCA cleaning and ICP etching, a 1 μm linewidth ohmic contact region was defined using a bilayer adhesion technique. Subsequently, metallization and stabilization were performed by annealing at 850°C for 35 seconds in nitrogen (metal evaporation was performed in this region using Ti / Al / Ni / Au metals, and a stable ohmic contact was formed with the aid of a nitrogen environment). A 120 nm thick SiN layer was deposited by PECVD, the gate region was defined using electron beam lithography, and vias were opened using ICP-RIE. Finally, Ni / Au was evaporated as the gate metal to obtain a high-heat-dissipating bilayer back barrier transistor.

[0110] Example 3

[0111] High heat dissipation double-layer back barrier transistor based on multilayer h-BN

[0112] Step 1, PMMA / PDMS-assisted wet transfer of multilayer h-BN:

[0113] The front side of a polished copper foil was then used to grow ten layers of h-BN film via CVD or other methods. A layer of PMMA was spin-coated onto the surface of the copper foil with multiple h-BN layers, initially at 1000 rpm for 6 seconds, then at 3000 rpm for 60 seconds. The spin-coated copper foil was then dried at 55°C for 20 minutes to allow the PMMA film to cure. After spin-coating, the PMMA layer was adsorbed onto PDMS. The PDMS was then immersed in a 64 g / L ammonium persulfate solution for 12 hours to remove the copper foil substrate. The multilayer h-BN film was transferred to a sapphire substrate using PDMS and immersed in acetone for 24 hours to remove the PDMS / PMMA layer. Subsequently, the multilayer h-BN / sapphire substrate was transferred from the acetone solution to an ethanol solution and allowed to stand for 30 minutes to remove residual acetone. The substrate was then removed and rapidly air-dried using a nitrogen gun to complete the transfer of the multilayer h-BN film.

[0114] Step 2: High-energy aluminum ion targeted implantation to regulate the interface states of the h-BN layer, preparing multi-B quasi-van der Waals epitaxial regions:

[0115] The ion accelerator uses a 10kV high-voltage electric field to accelerate the ion, resulting in an energy of 30keV and a dose of 10. 14 A high-energy aluminum ion beam was used. A multilayer h-BN / sapphire substrate was placed in a reaction chamber at room temperature and a pressure of 10 Torr. The high-energy aluminum ion beam, after acceleration, entered the reaction chamber and was directed at a fixed point at a 15° angle onto the surface of the multilayer h-BN / sapphire substrate. The ions penetrated the material surface, colliding and breaking the BN bonds in the multilayer h-BN, generating B-Al and N-Al dangling bonds, as well as free B atoms, forming a Gaussian-distributed multi-B quasi-van der Waals epitaxial region on the multilayer h-BN.

[0116] Step 3: Using the composite h-BN layer as a B source, staged annealing is performed to prepare a controlled-site B diffusion bilayer back barrier.

[0117] MOCVD was used to deposit a 200 nm thick B-diffused AlN layer on a multi-B quasi-van der Waals epitaxial h-BN film at 1250 °C and 40 Torr, with H2 flow rates of 100 sccm, NH3 flow rates of 1500 sccm, and trimethylaluminum flow rates of 100 μmol / L. The chamber temperature was kept constant, but the pressure was increased to 700 Torr for 3 minutes of annealing to modulate the AlN interface states through B diffusion. The chamber temperature was then decreased to 1100 °C, the pressure to 200 Torr, and the N2 flow rates to 2000 sccm, H2 flow rates to 1000 sccm, NH3 flow rates to 2000 sccm, and trimethylgallium flow rates to 200 μmol / L. A 100 nm thick B-diffused GaN layer was deposited; annealing at 700 °C and 800 Torr for 15 minutes yielded a B-diffused bilayer back barrier layer.

[0118] Step 4: Fabricate a high-heat-dissipation double-layer back barrier transistor:

[0119] MOCVD was used at 1050 °C and 200 Torr, with N2 flow rates set to 2000 sccm, H2 flow rates to 1500 sccm, NH3 flow rates to 500 sccm, and trimethylgallium flow rates to 100 μmol / L. A 120 nm GaN channel layer was deposited on a boron-diffused bilayer back barrier layer. The chamber temperature was then reduced to 1000 °C, while the pressure remained constant, with N2 flow rates set to 2000 sccm, H2 flow rates to 1500 sccm, NH3 flow rates to 500 sccm, trimethylaluminum flow rates to 60 μmol / L, and trimethylgallium flow rates to 10 μmol / L. A 20 nm Al layer was then deposited on the channel layer. 0.25 Ga 0.75 N-barrier layer. The chamber temperature was reduced to 950℃, pressure remained constant, and the N2 flow rate was set to 2000 sccm, H2 flow rate to 1500 sccm, NH3 flow rate to 500 sccm, and trimethylgallium flow rate to 10 μmol / L. In Al... 0.25 Ga 0.75A 3 nm GaN cap layer was deposited on the N-type barrier layer. After RCA cleaning and ICP etching, a 1 μm ohmic contact region was defined using a double-layer adhesion technique. Subsequently, metallization and stabilization were performed by annealing at 850°C for 35 seconds in nitrogen (metal evaporation was performed in this region using Ti / Al / Ni / Au metals, and a stable ohmic contact was formed with the aid of a nitrogen environment). A 120 nm thick SiN layer was deposited by PECVD, the gate region was defined using electron beam lithography, and vias were opened using ICP-RIE. Finally, Ni / Au was evaporated as the gate metal, resulting in a high-heat-dissipating AlGaN / GaN transistor with a controlled B-diffused double-layer back barrier, i.e., a high-heat-dissipating double-layer back barrier transistor.

[0120] This invention describes preferred embodiments and their effects. However, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to include both the preferred embodiments and all changes and modifications falling within the scope of this invention.

[0121] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-heat-dissipation double-layer back barrier transistor, characterized in that, It includes a substrate, and multiple layers of h-BN layer, control site B diffusion double layer back barrier layer, channel layer, barrier layer, cap layer, passivation layer and metal gate layer stacked sequentially on the substrate; The multilayer h-BN layer is a multilayer h-BN layer implanted with high-energy aluminum ions at specific points; The controlled-site B-diffusion bilayer back barrier layer comprises AlN and GaN layers deposited sequentially on multiple h-BN layers.

2. The high heat dissipation double-layer back barrier transistor according to claim 1, characterized in that, The number of h-BN layers is 2 to 10; the thickness of the AlN layer is 200-300 nm; and the thickness of the GaN layer is 100-200 nm.

3. The high heat dissipation double-layer back barrier transistor according to claim 1, characterized in that, The channel layer is a GaN channel layer with a thickness of 120~160nm; the barrier layer is Al. 0.25 Ga 0.75 The N-type barrier layer has a thickness of 20-30 nm; the cap layer is a GaN cap layer with a thickness of 3-5 nm; and the passivation layer is a SiN passivation layer with a thickness of 120-160 nm.

4. The high heat dissipation double-layer back barrier transistor according to claim 1, characterized in that, The metal gate layer uses Ni / Au as the gate metal.

5. A method for fabricating a high heat dissipation double-layer back barrier transistor as described in claim 3, characterized in that, Includes the following steps: Multilayer h-BN is transferred onto a substrate using PDMS-assisted wet transfer, i.e., multilayer h-BN layers are fabricated on the substrate. High-energy aluminum ions are injected at specific points into the multilayer h-BN layer to form patterned multi-B quasi-van der Waals epitaxial regions on the multilayer h-BN layer. An AlN layer was deposited on a multi-B quasi-van der Waals epitaxial region, followed by annealing, and then a GaN layer was deposited. After annealing, a site-controlled B diffusion bilayer back barrier layer was obtained. GaN channel layer and Al were sequentially deposited on a B-diffusion-controlled bilayer back barrier layer. 0.25 Ga 0.75 N-barrier layer and GaN cap layer; A SiN passivation layer is deposited on the GaN cap layer, and then the gate region is defined by electron beam lithography. The gate metal layer is obtained by evaporating the metal, thus obtaining a high heat dissipation double-layer back barrier transistor.

6. The method for fabricating a high heat dissipation double-layer back barrier transistor according to claim 5, characterized in that, Multiple h-BN layers are fabricated on the substrate, including: Multilayer h-BN layers are grown on one side of a copper foil, and PMMA is coated on the other side of the copper foil. After curing, the PMMA is adsorbed onto PDMS, and the PDMS is immersed in ammonium persulfate solution for 6-12 hours. The copper foil is then removed, and the multilayer h-BN layers are transferred to the substrate through PDMS. Subsequently, the substrate is immersed in acetone solution to remove PDMS and PMMA, thus forming multilayer h-BN layers on the substrate.

7. The method for fabricating a high heat dissipation double-layer back barrier transistor according to claim 5, characterized in that, High-energy aluminum ions are implanted at specific points onto multilayer h-BN layers to form multi-B quasi-van der Waals epitaxial regions, including: The multilayer h-BN layer and the substrate are placed in a reaction chamber at room temperature and a pressure of 10 Torr. A high-energy aluminum ion beam is then accelerated and enters the reaction chamber, and is directed at the surface of the multilayer h-BN layer at an angle of 5-15°, thus forming a multi-B quasi-van der Waals epitaxial region on the multilayer h-BN layer.

8. The method for fabricating a high-heat-dissipation double-layer back barrier transistor according to claim 5, characterized in that, The controlled-position B-diffused double-layer back barrier layer is prepared according to the following steps: In a chamber at 1200–1300 °C and 35–45 Torr, with H2 flow rate set to 800–1000 sccm, NH3 flow rate set to 1000–2000 sccm, and trimethylaluminum flow rate set to 80–100 μmol / L, an AlN layer was deposited on the multi-B quasi-van der Waals epitaxial region. While maintaining a constant chamber temperature, the pressure was increased to 650–750 Torr for annealing for 2–4 min to allow B diffusion to modulate the AlN interface states. The chamber temperature was then reduced to 1050–1150 °C and the pressure to 150–250 Torr, with N2 flow rate set to 2000 sccm, H2 flow rate set to 800–1000 sccm, and NH3 flow rate set to 1000–2000 μmol / L. A GaN layer was deposited by setting the sccm and trimethylgallium flow rate to 150-200 μmol / L, and then annealed for 10-20 min at 650-750 °C and 750-850 Torr to obtain a patterned controlled-site B-diffused bilayer back barrier layer.

9. The method for fabricating a high heat dissipation double-layer back barrier transistor according to claim 5, characterized in that, After depositing the GaN cap layer, the process also includes: After RCA cleaning and ICP etching, a 1 μm linewidth ohmic contact region was defined using a double-layer adhesion technique. Subsequently, metallization and stabilization were performed by annealing in nitrogen at 800-900°C for 30-40 seconds. The metals used were Ti / Al / Ni / Au.

10. The application of a high heat dissipation double-layer back barrier transistor according to any one of claims 1 to 4 in a communication system.

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