Display panel, manufacturing method thereof, and display device

Abstract

This application discloses a display panel, its fabrication method, and a display device. An interlayer dielectric layer covers the side of the first active portion and the first gate electrode away from the substrate. The interlayer dielectric layer has a first contact hole and a second contact hole. The depth of the first contact hole is less than the depth of the second contact hole. The first contact hole exposes the first active portion, and the second contact hole exposes a light-shielding portion. The first contact hole includes a first upper hole and a first lower hole; the second contact hole includes a second upper hole and a second lower hole. The depth of the second upper hole is equal to the depth of the first upper hole, and the depth of the second lower hole is greater than the depth of the first lower hole. This application uses the same photomask to etch the interlayer dielectric layer to form the first contact hole exposing the first active portion and the second contact hole exposing the light-shielding portion, thus saving on the photomask. Furthermore, the first lower hole of the first contact hole penetrates a portion of the first active portion, reducing the degree of etching of the first active portion.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel, its manufacturing method, and a display device. Background Technology

[0002] In the driving backplane of a conventional top-gate thin-film transistor architecture, shallow and deep vias are typically required for connection. Deep vias need to penetrate a buffer layer, while shallow vias do not. For example, shallow vias expose the active layer, while deep vias expose a light-shielding layer. To avoid excessive over-etching of the active layer at the shallow vias, the art uses two photomasks to form the shallow and deep vias respectively. However, using two photomasks increases the fabrication cost. Summary of the Invention

[0003] This application provides a display panel, a method for manufacturing the same, and a display device, which can reduce the risk of severe over-etching of the active layer while saving the photomask used for forming shallow and deep holes.

[0004] This application provides a display panel, which includes:

[0005] substrate;

[0006] A light-shielding portion is disposed on the substrate;

[0007] A buffer layer is disposed on the side of the light-shielding portion away from the substrate;

[0008] The first active part is disposed on the side of the buffer layer away from the substrate;

[0009] The first gate is disposed on a different layer from the first active portion;

[0010] An interlayer dielectric layer covers the side of the first active portion and the first gate away from the substrate. The interlayer dielectric layer has a first contact hole and a second contact hole. The depth of the first contact hole is less than the depth of the second contact hole. The first contact hole penetrates the interlayer dielectric layer and exposes the first active portion. The second contact hole penetrates the interlayer dielectric layer and the buffer layer and exposes the light-shielding portion.

[0011] In the thickness direction of the display panel, the first contact hole includes a first upper hole and a first lower hole. The first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active portion. The first upper hole is connected to the side of the first lower hole away from the substrate. The opening width of the first lower hole is smaller than the opening width of the first upper hole.

[0012] In the thickness direction of the display panel, the second contact hole includes a second upper hole and a second lower hole. The second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer. The second upper hole communicates with the side of the second lower hole away from the substrate. The opening width of the second lower hole is smaller than the opening width of the second upper hole. The depth of the second upper hole is equal to the depth of the first upper hole. The depth of the second lower hole is greater than the depth of the first lower hole.

[0013] Optionally, in some embodiments of this application, in the thickness direction of the display panel, the distance from the opening end face of the first lower hole to the first active portion is a first distance, and the first distance is between 1 nanometer and 60 nanometers.

[0014] Optionally, in some embodiments of this application, the depth of the first lower hole penetrating the first active portion in the thickness direction of the display panel is between 1 nanometer and 30 nanometers.

[0015] Optionally, in some embodiments of this application, the distance from the opening of the first lower hole to the wall of the first upper hole is a second distance, the second distance being between 0.1 micrometers and 2 micrometers.

[0016] Optionally, in some embodiments of this application, the distance from the opening of the second lower hole to the wall of the second upper hole is a third distance, and the second distance is equal to the third distance.

[0017] Optionally, in some embodiments of this application, the first lower hole includes a first sub-hole and a second sub-hole, the first sub-hole is connected to the first upper hole, the second sub-hole is connected to the side of the first sub-hole near the substrate, the second sub-hole is disposed in the first active portion, and the opening width of the second sub-hole is smaller than the opening width of the first sub-hole.

[0018] Optionally, in some embodiments of this application, the inclination angle of the wall of the first upper hole is greater than the inclination angle of the wall of the first sub-hole, and the inclination angle of the wall of the first sub-hole is greater than the inclination angle of the wall of the second sub-hole.

[0019] Optionally, in some embodiments of this application, the display panel further includes a second active portion, a second gate, a first insulating portion, a second insulating portion, and a first metal layer. The first insulating portion is disposed on the side of the first active portion away from the substrate. The second active portion, the second insulating portion, and the second gate are stacked sequentially on the side of the buffer layer away from the substrate. The interlayer dielectric layer covers the first gate, the second gate, and the buffer layer.

[0020] The first metal layer is disposed on the side of the interlayer dielectric layer away from the substrate. The first metal layer includes a first electrode, a second electrode, a third electrode, and a fourth electrode. The first electrode is connected to one side of the first active portion through a first contact hole, and the second electrode is connected to the other side of the first active portion through a first contact hole. The other end of the second electrode is connected to the light-shielding portion through a second contact hole. The third electrode is connected to one side of the second active portion through a first contact hole, and the fourth electrode is connected to the other side of the second active portion through a first contact hole.

[0021] Optionally, in some embodiments of this application, the first metal layer further includes a first peripheral trace, and the interlayer dielectric layer further has a third contact hole that exposes the second gate. The depth of the third contact hole is less than the depth of the first contact hole, and the first peripheral trace is connected to the second gate through the third contact hole.

[0022] The third contact hole includes a third upper hole and a third lower hole. The third lower hole is connected to the side of the third upper hole near the substrate. The opening width of the third lower hole is smaller than the opening width of the third upper hole. The third lower hole penetrates the portion of the second gate. The depth of the third lower hole is greater than the depth of the first lower hole penetrating the first active portion.

[0023] Optionally, in some embodiments of this application, the display panel further includes a second insulating layer, a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate is disposed on the same layer as the light-shielding portion, the second electrode plate is disposed on the same layer as the first active portion and overlaps with the first electrode plate to form a capacitor, the second insulating layer covers the first gate, the second gate, the second electrode plate, and the buffer layer, the third electrode plate is disposed on the side of the second insulating layer away from the substrate and forms a capacitor with the second electrode plate, and the interlayer dielectric layer covers the second insulating layer and the third electrode plate.

[0024] The first metal layer further includes a connecting wire, and the interlayer dielectric layer is further provided with a fourth contact hole exposing the third electrode plate and another second contact hole exposing the first electrode plate. The first contact hole and the second contact hole also penetrate the second insulating layer. One end of the connecting wire is connected to the third electrode plate through the fourth contact hole, and the other end of the connecting wire is connected to the first electrode plate through the other second contact hole.

[0025] The fourth contact hole includes a fourth upper hole and a fourth lower hole. The fourth lower hole is connected to the side of the fourth upper hole near the substrate. The opening width of the fourth lower hole is smaller than the opening width of the fourth upper hole. The fourth lower hole penetrates the portion of the third electrode plate. The depth of the fourth lower hole is greater than the depth of the first lower hole penetrating the first active portion.

[0026] Accordingly, this application also provides a method for manufacturing a display panel, which includes the following steps:

[0027] A light-shielding portion, a buffer layer, a first active portion, a first insulating portion, a first gate, and an interlayer dielectric layer are sequentially formed on the substrate.

[0028] The interlayer dielectric layer is dry-etched twice using the same photomask to form a first contact hole and a second contact hole. The depth of the first contact hole is less than the depth of the second contact hole. The first contact hole penetrates the interlayer dielectric layer and exposes the first active portion. The second contact hole penetrates the interlayer dielectric layer and the buffer layer and exposes the light-shielding portion. The first contact hole includes a first upper hole and a first lower hole. The first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active portion. The first upper hole is connected to the side of the first lower hole away from the substrate. The opening width of the first lower hole is less than the opening width of the first upper hole. The second contact hole includes a second upper hole and a second lower hole. The second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer. The second upper hole is connected to the side of the second lower hole away from the substrate. The opening width of the second lower hole is less than the opening width of the second upper hole. The depth of the second upper hole is equal to the depth of the first upper hole, and the depth of the second lower hole is greater than the depth of the first lower hole.

[0029] Optionally, in some embodiments of this application, the step of performing two dry etching operations on the interlayer dielectric layer using the same photomask to form the first contact hole and the second contact hole includes:

[0030] The interlayer dielectric layer is subjected to a first dry etching based on a photomask to form a first blind hole corresponding to the first active part and a second blind hole corresponding to the light-shielding part. The first blind hole and the second blind hole have the same depth. The distance from the bottom of the first blind hole to the first active part is a set distance, which is between 10 nanometers and 80 nanometers.

[0031] A second dry etching is performed on the interlayer dielectric layer based on the same photomask to form a first contact hole and a second contact hole. The distance from the opening end face of the first lower hole to the first active part is a first distance, which is between 1 nanometer and 60 nanometers. The etching rate of the second dry etching on the interlayer dielectric layer is greater than the etching rate of the second dry etching on the first active part.

[0032] Accordingly, this application also provides a display device, which includes a display panel as described in any of the above embodiments.

[0033] The display panel and display device of this application embodiment use the same photomask to etch the interlayer dielectric layer to form a first contact hole exposing the first active part and a second contact hole exposing the light-shielding part, so as to save photomask; secondly, the depth of the first upper hole of the first contact hole and the second upper hole of the second contact hole are equal, the depth of the first lower hole of the first contact hole is less than the depth of the second lower hole of the second contact hole, and the first lower hole of the first contact hole penetrates the portion of the first active part, so as to reduce the degree of etching of the first active part. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of the display panel provided in an embodiment of this application;

[0035] Figure 2 This is a partial structural schematic diagram of the display panel provided in an embodiment of this application;

[0036] Figure 3 yes Figure 2 Enlarged schematic diagram of section M1;

[0037] Figure 4 yes Figure 2 An enlarged schematic diagram of section M2 in the middle;

[0038] Figure 5 This is another structural schematic diagram of the display panel provided in the embodiments of this application;

[0039] Figure 6 This is a schematic diagram of another partial structure of the display panel provided in an embodiment of this application;

[0040] Figure 7 yes Figure 6 An enlarged schematic diagram of section M3;

[0041] Figure 8 yes Figure 6 An enlarged schematic diagram of section M4;

[0042] Figure 9 This is a schematic diagram of step B01 in the method for preparing a display panel provided in this application embodiment;

[0043] Figure 10 This is a schematic diagram of step B021 in the method for preparing a display panel provided in this application embodiment;

[0044] Figure 11 This is a schematic diagram of step B022 in the method for preparing a display panel provided in this application embodiment;

[0045] Figure 12 This is a schematic diagram of step B03 in the method for preparing a display panel provided in this application embodiment;

[0046] Figure 13 This is a schematic diagram of the structure of the display device provided in the embodiments of this application. Detailed Implementation

[0047] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific implementation methods described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, the embodiments can be combined with each other but will not be described in detail one by one. Unless otherwise stated, the directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device; the terms "first," "second," "third," etc. are only used as markings and do not impose numerical requirements or establish a sequence.

[0048] This application provides a display panel, a method for manufacturing the same, and a display device, which will be described in detail below. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0049] Please refer to Figures 1 to 4 This application provides a display panel 100, which includes a substrate 11, a light-shielding portion 121, a buffer layer 13, a first active portion 141, a first gate 161, and an interlayer dielectric layer 17.

[0050] A light-shielding portion 121 is disposed on the substrate 11. A buffer layer 13 is disposed on the side of the light-shielding portion 121 away from the substrate 11. A first active portion 141 is disposed on the side of the buffer layer 13 away from the substrate 11. A first gate 161 is disposed on a different layer from the first active portion 141. An interlayer dielectric layer 17 covers the side of the first active portion 141 and the first gate 161 away from the substrate 11.

[0051] The interlayer dielectric layer 17 has a first contact hole 171 and a second contact hole 172. The depth of the first contact hole 171 is less than the depth of the second contact hole 172. The first contact hole 171 penetrates the interlayer dielectric layer 17 and exposes the first active part 141. The second contact hole 172 penetrates the interlayer dielectric layer 17 and the buffer layer 13 and exposes the light-shielding part 121.

[0052] The first contact hole 171 includes a first upper hole 1a and a first lower hole 1b. The first lower hole 1b penetrates a portion of the interlayer dielectric layer 17 and a portion of the first active portion 141. The first upper hole 1a communicates with the side of the first lower hole 1b away from the substrate 11. The opening width k1 of the first lower hole 1b is smaller than the opening width k2 of the first upper hole 1a.

[0053] The second contact hole 172 includes a second upper hole 2a and a second lower hole 2b. The second lower hole 2b penetrates a portion of the interlayer dielectric layer 17 and the buffer layer 13. The second upper hole 2a connects to the side of the second lower hole 2b away from the substrate 11. The opening width k3 of the second lower hole 2b is smaller than the opening width k4 of the second upper hole 2a. The depth of the second upper hole 2a is equal to the depth of the first upper hole 1a, and the depth of the second lower hole 2b is greater than the depth of the first lower hole 1b.

[0054] The display panel 100 of this application embodiment uses the same photomask to etch the interlayer dielectric layer 17 to form a first contact hole 171 exposing the first active portion 141 and a second contact hole 172 exposing the light-shielding portion 121, so as to save photomask; secondly, the depths of the first upper hole 1a of the first contact hole 171 and the second upper hole 2a of the second contact hole 172 are equal, the depth of the first lower hole 1b of the first contact hole 171 is less than the depth of the second lower hole 2b of the second contact hole 172, and the first lower hole 1b of the first contact hole 171 penetrates a portion of the first active portion 141, so as to reduce the degree of etching of the first active portion 141.

[0055] It is understandable that the deeper the first lower hole 1b is over-etched into the first active part 141, the larger the opening width k1 of the first lower hole 1b will be, which will reduce the stability and lifespan of the thin film transistor. Furthermore, when the first contact hole 171 is an output electrode via, it will also increase the risk of leakage current in the thin film transistor device. Therefore, based on the considerations of leakage current, stability and lifespan of the thin film transistor, it is necessary to reduce the risk of the first lower hole 1b being over-etched into the first active part 141.

[0056] Therefore, in some embodiments of this application, in the thickness direction of the display panel 100, the depth of the first lower hole 1b penetrating the first active portion 141 is less than or equal to 3 / 5 of the thickness of the first active portion 141, so as to reduce the degree of etching of the first active portion 141, thereby reducing the risk of leakage current and the risk of device instability and short service life. In addition, the penetration depth of the first lower hole 1b being less than or equal to 3 / 5 of the thickness of the first active portion 141 can also increase the contact area between the source and drain and the first active portion 141, improve the current control capability of the device and reduce poor contact; it can also reduce the resistance of the source and drain regions of the first active portion 141 and improve the response speed of the device.

[0057] Optionally, the penetration depth of the first lower hole 1b is equal to 3 / 5, 2 / 5, 1 / 5, 1 / 6, 1 / 7, 1 / 8, 1 / 9 or 1 / 10 of the thickness of the first active part 141.

[0058] Optionally, in some embodiments of this application, the depth of the first lower hole 1b penetrating the first active portion 141 in the thickness direction of the display panel 100 is between 1 nanometer and 30 nanometers. Such a configuration can further reduce the risks of leakage current, device instability, and short lifespan, as well as improve the current control capability and response speed of the device and reduce the risk of poor contact.

[0059] Optionally, the depth of the first lower hole 1b penetrating the first active part 141 can be 1 nanometer, 2 nanometer, 3 nanometer, 4 nanometer, 5 nanometer, 6 nanometer, 7 nanometer, 8 nanometer, 9 nanometer, 10 nanometer, 11 nanometer, 12 nanometer, 13 nanometer, 14 nanometer, 15 nanometer, 16 nanometer, 17 nanometer, 18 nanometer, 19 nanometer, 20 nanometer, 21 nanometer, 22 nanometer, 23 nanometer, 24 nanometer, 25 nanometer, 26 nanometer, 27 nanometer, 28 nanometer, 29 nanometer or 30 nanometer, etc.

[0060] Please refer to Figure 2 and Figure 3 Optionally, in some embodiments of this application, in the thickness direction of the display panel 100, the distance from the opening end face of the first lower hole 1b to the first active portion 141 is a first distance D1, and the first distance D1 is between 1 nanometer and 60 nanometers.

[0061] It is important to understand that during the first etching of the first contact hole 171 and the second contact hole 172, a high etching rate gas is selected to etch the interlayer dielectric layer 17 to shorten the preparation time. Also, since the second lower hole 2b is relatively deep and the etching time and etching gas of the first lower hole 1b and the second lower hole 2b are the same, the larger the first distance D1 is, the larger the distance between the blind hole and the first active part 141 after the first etching is. This allows the first lower hole 1b formed in the second etching to have a larger distance to buffer the over-etching of the first active part 141, which can reduce the degree of over-etching of the first active part 141. However, the etching rate of the interlayer dielectric layer 17 is slower in the second etching, which will prolong the time for forming the first contact hole 171 and the second contact hole 172.

[0062] Therefore, based on the consideration of reducing the degree of over-etching of the first active part 141 and the time for preparing the contact hole, the first distance D1 can be selected to be between 1 nanometer and 60 nanometers, for example, it can be 1 nanometer, 2 nanometer, 3 nanometer, 4 nanometer, 5 nanometer, 6 nanometer, 7 nanometer, 8 nanometer, 9 nanometer, 10 nanometer, 11 nanometer, 12 nanometer, 13 nanometer, 14 nanometer, 15 nanometer, 16 nanometer, 17 nanometer, 18 nanometer, 19 nanometer, 20 nanometer, 21 nanometer, 22 nanometer, 23 nanometer, 24 nanometer, 25 nanometer, 26 nanometer, 27 nanometer, 28 nanometer, 29 nanometer, 30 nanometer, 32 nanometer, 34 nanometer, 36 nanometer, 38 nanometer, 40 nanometer, 42 nanometer, 44 nanometer, 46 nanometer, 48 nanometer, 50 nanometer, 52 nanometer, 54 nanometer, 56 nanometer, 58 nanometer or 60 nanometer, etc.

[0063] Optionally, in some embodiments of this application, the distance from the opening of the first lower hole 1b to the wall of the first upper hole 1a is a second distance D2, and the second distance D2 is between 0.1 micrometers and 2 micrometers.

[0064] Understandably, the larger the second distance D2, the smaller the opening width k1 of the first lower hole 1b, which also means that the degree to which the first active part 141 is over-etched in the first lower hole 1b is shallower; and the larger the second distance D2, the larger the buffer area between the first upper hole 1a and the first lower hole 1b, which can reduce the risk of subsequent film layer breakage covering the first contact hole 171. Secondly, the larger the second distance D2, the larger the layout area of ​​the first contact hole 171, while the aperture ratio decreases.

[0065] Therefore, considering the need to reduce the degree of etching of the first active part 141, the risk of subsequent film breakage, and the aperture ratio, the second distance D2 is selected to be between 0.1 micrometers and 2 micrometers, such as 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, 1 micrometer, 1.1 micrometers, 1.2 micrometers, 1.3 micrometers, 1.4 micrometers, 1.5 micrometers, 1.6 micrometers, 1.7 micrometers, 1.8 micrometers, 1.9 micrometers, or 2 micrometers.

[0066] Optionally, in some embodiments of this application, the distance from the opening of the second lower hole 2b to the wall of the second upper hole 2a is a third distance D3, and the second distance D2 is equal to the third distance D3.

[0067] Since the first lower hole 1b and the second lower hole 2b are etched under the same etching conditions, the third distance D3 is equal to the second distance D2.

[0068] Optionally, in some embodiments of this application, based on the consideration of reducing the risk of subsequent film breakage and the aperture ratio, the third distance D3 is selected to be between 0.1 micrometers and 2 micrometers, such as 0.1 micrometers, 0.2 micrometers, 0.3 micrometers, 0.4 micrometers, 0.5 micrometers, 0.6 micrometers, 0.7 micrometers, 0.8 micrometers, 0.9 micrometers, 1 micrometer, 1.1 micrometers, 1.2 micrometers, 1.3 micrometers, 1.4 micrometers, 1.5 micrometers, 1.6 micrometers, 1.7 micrometers, 1.8 micrometers, 1.9 micrometers or 2 micrometers.

[0069] Optionally, in some embodiments of this application, the first lower hole 1b includes a first sub-hole b01 and a second sub-hole b02. The first sub-hole b01 is connected to the first upper hole 1a, and the second sub-hole b02 is connected to the side of the first sub-hole b01 near the substrate 11. The second sub-hole b02 is disposed within the first active portion 141, and the opening width of the second sub-hole b02 is smaller than the opening width of the first sub-hole b01.

[0070] It is understandable that during the etching process of the interlayer dielectric layer 17 and the first active part 141, a gas with a relatively high etching selectivity is selected for etching to reduce the etching of the first active part 141 and accelerate the etching of the interlayer dielectric layer 17. This results in the etching rate of the etching gas etching the interlayer dielectric layer 17 and the buffer layer 13 being greater than the etching rate of the first active part 141. Consequently, the opening width of the second sub-hole b02 is smaller than the opening width of the first sub-hole b01, where the opening width of the first sub-hole b01 is the opening width k1 of the first lower hole 1b.

[0071] In other words, the opening width of the second sub-hole b02 is smaller than the opening width of the first sub-hole b01, so as to reduce the over-etching degree of the first lower hole 1b on the first active part 141 and improve the stability and service life of the thin film transistor device.

[0072] Optionally, in some embodiments of this application, the inclination angle of the wall of the first upper hole 1a is greater than the inclination angle v1 of the wall of the first sub-hole b01, and the inclination angle v2 of the wall of the first sub-hole b01 is greater than the inclination angle v3 of the wall of the second sub-hole b02.

[0073] Understandably, in the thickness direction of the display panel 100, from the first upper hole 1a to the second sub-hole b02, the slope of the hole wall gradually decreases, so as to reduce the risk of subsequent film layer (second electrode) breaking when covering the first contact hole 171.

[0074] Optionally, in some embodiments of this application, the depth of the first upper hole 1a is greater than the depth of the first sub-hole b01, and the depth of the first sub-hole b01 is greater than the depth of the second sub-hole b02.

[0075] It is understandable that in the three segments of the first upper hole 1a, the first sub-hole b01, and the second sub-hole b02 in the first contact hole 171, the first upper hole 1a is in the upper segment, the first sub-hole b01 is in the middle segment, and the second sub-hole b02 is in the lower segment. That is, the second sub-hole b02 is located in the deepest segment of the first contact hole 171, and the first upper hole 1a is located in the shallowest segment of the first contact hole 171. Therefore, the decreasing depth of the first upper hole 1a, the first sub-hole b01, and the second sub-hole b02 can reduce the proportion of the deep segment hole area, thereby reducing the risk of the second electrode breaking.

[0076] Optionally, in some embodiments of this application, the display panel 100 further includes a second active portion 142, a second gate 162, a first insulating portion 151, a second insulating portion 152, and a first metal layer 18. The first insulating portion 151 is disposed on the side of the first active portion 141 away from the substrate 11. The second active portion 142, the second insulating portion 152, and the second gate 162 are sequentially stacked and disposed on the side of the buffer layer 13 away from the substrate 11. The interlayer dielectric layer 17 covers the first gate 161, the second gate 162, and the buffer layer 13.

[0077] A first metal layer 18 is disposed on the side of the interlayer dielectric layer 17 away from the substrate 11. The first metal layer 18 includes a first electrode 181, a second electrode 182, a third electrode 183, and a fourth electrode 184. The first electrode 181 is connected to one side of the first active portion 141 through a first contact hole 171. One end of the second electrode 182 is connected to the other side of the first active portion 141 through a first contact hole 171, and the other end of the second electrode 182 is connected to the light-shielding portion 121 through a second contact hole 172. The third electrode 183 is connected to one side of the second active portion 142 through a first contact hole 171, and the fourth electrode 184 is connected to the other side of the second active portion 142 through a first contact hole 171.

[0078] The first active portion 141, the first gate 161, the first electrode 181, and the second electrode 182 constitute a first thin-film transistor, which is located in the display area of ​​the display panel 100. The second active portion 142, the second gate 162, the third electrode 183, and the fourth electrode 184 constitute a second thin-film transistor, which is located in the gate drive circuit area of ​​the display panel 100.

[0079] Please refer to Figure 1 and Figure 4 Optionally, in some embodiments of this application, the first metal layer 18 further includes a first peripheral trace 185, and the interlayer dielectric layer 17 further has a third contact hole 173 exposing the second gate 162. The depth of the third contact hole 173 is less than the depth of the first contact hole 171. The first peripheral trace 185 is connected to the second gate 162 through the third contact hole 173.

[0080] The third contact hole 173 includes a third upper hole 3a and a third lower hole 3b. The third lower hole 3b is connected to the side of the third upper hole 3a near the substrate 11. The opening width k5 of the third lower hole 3b is smaller than the opening width k6 of the third upper hole 3a. The third lower hole 3b penetrates a portion of the second gate 162, and the depth of the third lower hole 3b is greater than the depth of the first lower hole 1b penetrating the first active portion 141.

[0081] It is understandable that the third lower hole 3b penetrates part of the second gate 162, and the depth of the third lower hole 3b is greater than the depth of the first lower hole 1b, which increases the contact area of ​​the first outer peripheral trace 185 and the second gate 162, improves the contact yield of the two, and reduces the contact impedance of the two, thereby improving the response speed of the second thin film transistor.

[0082] Optionally, in some embodiments, the display panel 100 further includes a first electrode 122 and a second electrode 143, and the first metal layer 18 further includes a third electrode 186. The first electrode 122 and the third electrode 186 form a capacitor with the second electrode 143, respectively.

[0083] The first electrode 122 and the light-shielding part 121 are disposed in the same layer and are made of the same material. The second electrode 143, the first active part 141 and the second active part 142 are disposed in the same layer, and all three include semiconductor materials.

[0084] Optionally, in some embodiments of this application, the thickness of the light-shielding portion 121 and the first electrode plate 122 may each be between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, or 800 nanometers. The thicknesses of the two may be equal.

[0085] The materials of the light-shielding part 121 and the first electrode plate 122 can each be at least one of molybdenum, molybdenum-titanium alloy, copper, aluminum, and titanium. The light-shielding part 121 and the first electrode plate 122 can also be a single film layer or a multi-film layer stacked structure.

[0086] The thickness of the buffer layer 13 can be between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, or 800 nanometers. The material of the buffer layer 13 can be at least one of silicon nitride and silicon oxide, and the buffer layer 13 can be a single film layer or a multi-film layer stacked structure.

[0087] The thicknesses of the first active portion 141, the second active portion 142, and the second electrode 143 are each between 10 nanometers and 50 nanometers, such as 10 nanometers, 20 nanometers, 30 nanometers, 40 nanometers, or 50 nanometers. Optionally, the thicknesses of the first active portion 141, the second active portion 142, and the second electrode 143 are equal.

[0088] The first active part 141, the second active part 142, and the second electrode plate 143 are semiconductor materials, and each of them is made of at least two of indium oxide, gallium oxide, zinc oxide, and titanium niobium oxide.

[0089] The thickness of each of the first insulating portion 151 and the second insulating portion 152 is between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, or 800 nanometers. The material of each of the first insulating portion 151 and the second insulating portion 152 can be at least one of silicon nitride and silicon oxide. Each of the first insulating portion 151 and the second insulating portion 152 is a single film layer or a multi-film layer stacked structure. Optionally, the thickness, material, and film layer structure of the first insulating portion 151 and the second insulating portion 152 are the same.

[0090] The thicknesses of the first gate 161 and the second gate 162 can each be between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, or 800 nanometers. Their thicknesses can be equal. However, the thicknesses of both the first gate 161 and the second gate 162 are greater than the thickness of the first active portion 141.

[0091] The materials of the first gate 161 and the second gate 162 may each be at least one of molybdenum, molybdenum-titanium alloy, copper, aluminum, and titanium. The first gate 161 and the second gate 162 are single-layer or multi-layer stacked structures. The materials and film structures of the first gate 161 and the second gate 162 are the same.

[0092] The thickness of the interlayer dielectric layer 17 can be between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, or 800 nanometers. The material of the interlayer dielectric layer 17 can be at least one of silicon nitride and silicon oxide, and the interlayer dielectric layer 17 can be a single film layer or a multi-film layer stacked structure. Optionally, the material of the interlayer dielectric layer 17 can be the same as the material of the buffer layer 13.

[0093] The thickness of the first metal layer 18 is between 10 nanometers and 800 nanometers, such as 10 nanometers, 100 nanometers, 200 nanometers, 300 nanometers, 400 nanometers, 500 nanometers, 600 nanometers, 700 nanometers, or 800 nanometers. The material of the first metal layer 18 may be at least one of molybdenum, molybdenum-titanium alloy, copper, aluminum, and titanium. The first metal layer 18 may be a single film layer or a multi-film layer stacked structure.

[0094] Please refer to Figures 5 to 8 , Figure 5 The diagram shown is a schematic representation of another structure of the display panel 100 according to an embodiment of this application. Figure 6 for Figure 5 Partial diagram in the image, Figure 7 yes Figure 6 An enlarged schematic diagram of section M3. Figure 8 yes Figure 6 An enlarged schematic diagram of section M4.

[0095] exist Figures 5 to 8 In this section, we will describe the parts that differ from the embodiments described above in order to avoid redundancy.

[0096] Please refer to Figures 5 to 8 Compared to the above embodiments, in some embodiments of this application, the display panel 100 further includes a second insulating layer 19.

[0097] The second insulating layer 19 covers the first gate 161, the second gate 162, the second electrode 143 and the buffer layer 13. The third electrode 186 is disposed on the side of the second insulating layer 19 away from the substrate 11 and forms a capacitor with the second electrode 143. The interlayer dielectric layer 17 covers the second insulating layer 19 and the third electrode 186.

[0098] The first metal layer 18 also includes a connecting wire 187. The interlayer dielectric layer 17 is further provided with a fourth contact hole 174 exposing the third electrode plate 186 and another second contact hole 172 exposing the first electrode plate 122. The first contact hole 171 and the second contact hole 172 also penetrate the second insulating layer 19. One end of the connecting wire 187 is connected to the third electrode plate 186 through the fourth contact hole 174, and the other end of the connecting wire 187 is connected to the first electrode plate 122 through the other second contact hole 172.

[0099] The fourth contact hole 174 includes a fourth upper hole 4a and a fourth lower hole 4b. The fourth lower hole 4b connects to the side of the fourth upper hole 4a closest to the substrate 11. The opening width k7 of the fourth lower hole 4b is smaller than the opening width k8 of the fourth upper hole 4a. The fourth lower hole 4b penetrates a portion of the third electrode plate 186, and the depth of the fourth lower hole 4b is greater than the depth of the first lower hole 1b penetrating the first active portion 141.

[0100] It is understandable that the fourth lower hole 4b penetrates part of the third electrode plate 186, and the depth of the fourth lower hole 4b is greater than the depth of the first lower hole 1b, which increases the contact area between the connecting line 187 and the third electrode plate 186, improves the contact yield of the two, and reduces the contact impedance of the two, thereby improving the response speed of the capacitor.

[0101] In some embodiments, the display panel 100 further includes a passivation layer 191, a first planarization layer 192, a second metal layer 20, a second planarization layer 193, a pixel definition layer 21, and an anode 22, which are sequentially disposed on the side of the first metal layer 18 away from the substrate 11.

[0102] Optionally, the second metal layer 20 includes a second peripheral trace 201 and a third peripheral trace 202, wherein the second peripheral trace 201 is connected to the first peripheral trace 185 and the third peripheral trace 202 is connected to the fourth electrode 184.

[0103] The first outer peripheral trace 185, the second outer peripheral trace 201, and the third outer peripheral trace 202 are all located within the gate drive circuit area to reduce the border width.

[0104] Optionally, the second metal layer 20 further includes an adapter 203 and a bonding pad 204. The anode 22 is connected to the adapter 203, and the adapter 203 is connected to the second electrode 182. The bonding pad 204 is located in the bonding area of ​​the display panel 100 and is configured to bond to a chip or circuit board.

[0105] Accordingly, this application also provides a method for manufacturing a display panel, the method being configured to manufacture a display panel 100 as described above.

[0106] The preparation method includes the following steps:

[0107] Step B01: A light-shielding portion 121, a buffer layer 13, a first active portion 141, a first insulating portion 151, a first gate 161, and an interlayer dielectric layer 17 are sequentially formed on the substrate 11.

[0108] Step B02: The interlayer dielectric layer 17 is dry-etched twice using the same photomask to form a first contact hole 171 and a second contact hole 172. The depth of the first contact hole 171 is less than the depth of the second contact hole 172. The first contact hole 171 penetrates the interlayer dielectric layer 17 and exposes the first active portion 141, while the second contact hole 172 penetrates the interlayer dielectric layer 17 and the buffer layer 13 and exposes the light-shielding portion 121. The first contact hole 171 includes a first upper hole 1a and a first lower hole 1b. The first lower hole 1b penetrates a portion of the interlayer dielectric layer 17 and a portion of the first active portion 141, and the first upper hole 1a connects to the side of the first lower hole 1b away from the substrate 11. The opening width k1 of the first lower hole 1b is less than the opening width k2 of the first upper hole 1a. The second contact hole 172 includes a second upper hole 2a and a second lower hole 2b. The second lower hole 2b penetrates a portion of the interlayer dielectric layer 17 and the buffer layer 13, and the second upper hole 2a connects to the side of the second lower hole 2b away from the substrate 11. The opening width k3 of the second lower hole 2b is less than the opening width k4 of the second upper hole 2a. The depth of the second upper hole 2a is equal to the depth of the first upper hole 1a, and the depth of the second lower hole 2b is greater than the depth of the first lower hole 1b.

[0109] The method for fabricating the display panel 100 in this embodiment uses the same photomask to etch the interlayer dielectric layer 17 to form a first contact hole 171 exposing the first active portion 141 and a second contact hole 172 exposing the light-shielding portion 121, thereby saving photomask space. Furthermore, the depth of the first lower hole 1b of the first contact hole 171 is less than the depth of the second lower hole 2b of the second contact hole 172, and the first lower hole 1b of the first contact hole 171 penetrates a portion of the first active portion 141, thereby reducing the degree of etching of the first active portion 141.

[0110] The following text is incomplete and cannot be translated. Figure 1 The manufacturing method of the display panel 100 will be described using the display panel 100 of the corresponding embodiment as an example.

[0111] Please refer to Figure 9 In step B01, a light-shielding portion 121, a buffer layer 13, a first active portion 141, a first insulating portion 151, a first gate 161, and an interlayer dielectric layer 17 are sequentially formed on the substrate 11.

[0112] The material of the buffer layer 13 is the same as or has similar chemical properties as the interlayer dielectric layer 17, which facilitates the second dry etching.

[0113] Then proceed to step B02.

[0114] Step B02: The interlayer dielectric layer 17 is dry etched twice using the same photomask to form the first contact hole 171 and the second contact hole 172.

[0115] Optionally, step B02 includes:

[0116] Please refer to Figure 10 In step B021, the interlayer dielectric layer 17 is subjected to a first dry etching based on a photomask to form a first blind hole m1 corresponding to the first active portion 141 and a second blind hole m2 corresponding to the light-shielding portion 121. The first blind hole m1 and the second blind hole m2 have the same depth, and the distance from the bottom of the first blind hole m1 to the first active portion 141 is a set distance Ds, which is between 10 nanometers and 80 nanometers.

[0117] Optionally, the first dry etching may include SF6 and Cl2, or O2 or other etching gases may be added to SF6 and Cl2.

[0118] It should be noted that the etching selectivity of the etching gas is the ratio of the etching rate of the interlayer dielectric layer 17 to the etching rate of the first active part 141. Since the first dry etching only etches the interlayer dielectric layer 17, the etching selectivity of the first dry etching is set to be less than 4 / 1 to improve the etching rate and uniformity of the interlayer dielectric layer 17 and shorten the etching time of the interlayer dielectric layer 17.

[0119] It is important to understand that the set distance Ds is the condition for switching to the second dry etching. As long as the distance from the first blind hole m1 formed by the first dry etching to the first active part 141 meets the set distance Ds, the second dry etching will be switched to.

[0120] The distance Ds is set between 10 nanometers and 80 nanometers to avoid the first blind hole m1 being too close to the first active part 141, which would cause the subsequent second etching to over-etch the first active part 141, and to avoid the preparation time being too long.

[0121] Optionally, the distance Ds can be set to 10 nanometers, 15 nanometers, 20 nanometers, 25 nanometers, 30 nanometers, 35 nanometers, 40 nanometers, 45 nanometers, 50 nanometers, 55 nanometers, 60 nanometers, 65 nanometers, 70 nanometers, 75 nanometers, or 80 nanometers.

[0122] Then proceed to step B022.

[0123] Please refer to Figure 11 In step B022, a second dry etching is performed on the interlayer dielectric layer 17 based on the same photomask to form a first contact hole 171 and a second contact hole 172. The distance from the opening end face of the first lower hole 1b to the first active portion 141 is a first distance D1, which is between 1 nanometer and 60 nanometers. The etching rate of the second dry etching on the interlayer dielectric layer 17 is greater than the etching rate of the second dry etching on the first active portion 141.

[0124] Optionally, the second dry etching may include CF4 and O2, or other etching gases.

[0125] The purpose of the second dry etching is to accelerate the etching rate of the interlayer dielectric layer 17 and the buffer layer 13, while slowing down the etching rate of the first active part 141, so as to achieve penetration of the buffer layer 13 while reducing the over-etching degree of the first active part 141. Therefore, the etching selectivity of the second dry etching is set to be greater than 4 / 1.

[0126] Secondly, in the second dry etching, the etching rate of the etching gas etches the second gate 162 is greater than the etching rate of the first active portion 141, so that the etching depth of the second gate 162 is greater than the etching depth of the first active portion 141.

[0127] Optionally, the thickness of the second gate 162 is greater than the thickness of the first active portion 141 to prevent the second gate 162 from being etched through.

[0128] Furthermore, in some embodiments, the etching rate of the interlayer dielectric layer 17 during the first dry etching is greater than that during the second dry etching, and the etching rate of the interlayer dielectric layer 17 during the second dry etching is greater than that during the etching rate of the first active portion 141. Therefore, in the process corresponding to the first upper hole 1a and the second upper hole 2a, the first blind hole m1 and the second blind hole m2 are formed with relatively steep slopes after the first rapid etching. The slower second etching can smooth the hole walls of the first blind hole m1 and the second blind hole m2, making the hole walls smoother and having a weaker impact on the overall slope. At the same time, because the etching rate is slower in the second etching, the slopes of the first lower hole 1b and the second lower hole 2b formed are gentler, thereby reducing the risk of breakage of the second electrode 182.

[0129] Then proceed to step B03.

[0130] Please refer to Figure 12 Step B03: A patterned first metal layer 18 is formed on the interlayer dielectric layer 17.

[0131] It should be noted that, Figure 12 The display panel 100 in the corresponding embodiment and Figure 1The structure of the display panel 100 in the corresponding embodiment is the same, and can be referred to in detail. Figures 1 to 2 Therefore, the relevant explanations will not be repeated here.

[0132] Please refer to Figure 13 Accordingly, this application also provides a display device 1000, which includes a display panel 100 as described in any of the above embodiments.

[0133] Optionally, the display panel 100 may be an electroluminescent panel, such as an organic light-emitting display panel.

[0134] It should be noted that the display panel 100 of the display device 1000 in this application embodiment has a similar or identical structure to the display panel 100 of any of the above embodiments. For details, please refer to... Figures 1 to 12 The explanation is already given, so it will not be repeated here.

[0135] The display device 1000 of this application embodiment uses the same photomask to etch the interlayer dielectric layer 17 to form a first contact hole 171 exposing the first active portion 141 and a second contact hole 172 exposing the light-shielding portion 121, so as to save photomask; secondly, the depths of the first upper hole 1a of the first contact hole 171 and the second upper hole 2a of the second contact hole 172 are equal, the depth of the first lower hole 1b of the first contact hole 171 is less than the depth of the second lower hole 2b of the second contact hole 172, and the first lower hole 1b of the first contact hole 171 penetrates a portion of the first active portion 141, so as to reduce the degree of etching of the first active portion 141.

[0136] Display device 1000 can be applied to and used in a variety of products, including, for example, televisions, laptops, monitors, billboards, Internet of Things (IoT) devices, and portable electronic devices including mobile phones, smartphones, tablet computers, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs).

[0137] Furthermore, the display device 1000 according to some embodiments can be applied to and used within wearable devices, including smartwatches, watch phones, glasses-type displays, and head-mounted displays (HMDs). Additionally, according to some embodiments, the display device 1000 can be applied to instrument panels for automobiles, displays in central dashboards or central information displays (CIDs) arranged on instrument panels, interior mirror displays replacing side mirrors, and displays for entertainment systems arranged on the back of the front seats for rear-seat passengers in automobiles.

[0138] The above provides a detailed description of a display panel, its preparation method, and the display device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A display panel, characterized in that, include: substrate; A light-shielding portion is disposed on the substrate; A buffer layer is disposed on the side of the light-shielding portion away from the substrate; The first active part is disposed on the side of the buffer layer away from the substrate; The first gate is disposed on a different layer from the first active portion; An interlayer dielectric layer covers the side of the first active portion and the first gate away from the substrate. The interlayer dielectric layer has a first contact hole and a second contact hole. The depth of the first contact hole is less than the depth of the second contact hole. The first contact hole penetrates the interlayer dielectric layer and exposes the first active portion. The second contact hole penetrates the interlayer dielectric layer and the buffer layer and exposes the light-shielding portion. as well as The first contact hole includes a first upper hole and a first lower hole. The first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active portion. The first upper hole is connected to the side of the first lower hole away from the substrate. The opening width of the first lower hole is smaller than the opening width of the first upper hole. The second contact hole includes a second upper hole and a second lower hole. The second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer. The second upper hole is connected to the side of the second lower hole away from the substrate. The opening width of the second lower hole is smaller than the opening width of the second upper hole. The depth of the second upper hole is equal to the depth of the first upper hole. The depth of the second lower hole is greater than the depth of the first lower hole.

2. The display panel according to claim 1, characterized in that, In the thickness direction of the display panel, the distance from the opening end face of the first lower hole to the first active part is a first distance, which is between 1 nanometer and 60 nanometers.

3. The display panel according to claim 2, characterized in that, In the thickness direction of the display panel, the depth of the first lower hole penetrating the first active portion is between 1 nanometer and 30 nanometers.

4. The display panel according to claim 3, characterized in that, The distance from the opening of the first lower hole to the wall of the first upper hole is the second distance, which is between 0.1 micrometers and 2 micrometers.

5. The display panel according to claim 4, characterized in that, The distance from the opening of the second lower hole to the wall of the second upper hole is the third distance, and the second distance is equal to the third distance.

6. The display panel according to any one of claims 1-5, characterized in that, The first lower hole includes a first sub-hole and a second sub-hole. The first sub-hole is connected to the first upper hole, and the second sub-hole is connected to the side of the first sub-hole near the substrate. The second sub-hole is disposed in the first active portion, and the opening width of the second sub-hole is smaller than the opening width of the first sub-hole.

7. The display panel according to claim 6, characterized in that, The inclination angle of the first upper hole is greater than the inclination angle of the first sub-hole, and the inclination angle of the first sub-hole is greater than the inclination angle of the second sub-hole.

8. The display panel according to any one of claims 1-5, characterized in that, The display panel further includes a second active portion, a second gate, a first insulating portion, a second insulating portion, and a first metal layer. The first insulating portion is disposed on the side of the first active portion away from the substrate. The second active portion, the second insulating portion, and the second gate are stacked sequentially on the side of the buffer layer away from the substrate. The interlayer dielectric layer covers the first gate, the second gate, and the buffer layer. The first metal layer is disposed on the side of the interlayer dielectric layer away from the substrate. The first metal layer includes a first electrode, a second electrode, a third electrode, and a fourth electrode. The first electrode is connected to one side of the first active portion through a first contact hole, and the second electrode is connected to the other side of the first active portion through a first contact hole. The other end of the second electrode is connected to the light-shielding portion through a second contact hole. The third electrode is connected to one side of the second active portion through a first contact hole, and the fourth electrode is connected to the other side of the second active portion through a first contact hole.

9. The display panel according to claim 8, characterized in that, The first metal layer further includes a first peripheral trace, and the interlayer dielectric layer further has a third contact hole that exposes the second gate. The depth of the third contact hole is less than the depth of the first contact hole, and the first peripheral trace is connected to the second gate through the third contact hole. The third contact hole includes a third upper hole and a third lower hole. The third lower hole is connected to the side of the third upper hole near the substrate. The opening width of the third lower hole is smaller than the opening width of the third upper hole. The third lower hole penetrates the portion of the second gate. The depth of the third lower hole is greater than the depth of the first lower hole penetrating the first active portion.

10. The display panel according to claim 9, characterized in that, The display panel further includes a second insulating layer, a first electrode plate, a second electrode plate, and a third electrode plate. The first electrode plate is disposed on the same layer as the light-shielding portion. The second electrode plate is disposed on the same layer as the first active portion and overlaps with the first electrode plate to form a capacitor. The second insulating layer covers the first gate, the second gate, the second electrode plate, and the buffer layer. The third electrode plate is disposed on the side of the second insulating layer away from the substrate and forms a capacitor with the second electrode plate. The interlayer dielectric layer covers the second insulating layer and the third electrode plate. The first metal layer further includes a connecting wire, and the interlayer dielectric layer is further provided with a fourth contact hole exposing the third electrode plate and another second contact hole exposing the first electrode plate. The first contact hole and the second contact hole also penetrate the second insulating layer. One end of the connecting wire is connected to the third electrode plate through the fourth contact hole, and the other end of the connecting wire is connected to the first electrode plate through the other second contact hole. The fourth contact hole includes a fourth upper hole and a fourth lower hole. The fourth lower hole is connected to the side of the fourth upper hole near the substrate. The opening width of the fourth lower hole is smaller than the opening width of the fourth upper hole. The fourth lower hole penetrates the portion of the third electrode plate. The depth of the fourth lower hole is greater than the depth of the first lower hole penetrating the first active portion.

11. A method for manufacturing a display panel, characterized in that, Includes the following steps: A light-shielding portion, a buffer layer, a first active portion, a first insulating portion, a first gate, and an interlayer dielectric layer are sequentially formed on the substrate. The interlayer dielectric layer is dry etched twice using the same photomask to form a first contact hole and a second contact hole. The depth of the first contact hole is less than the depth of the second contact hole. The first contact hole penetrates the interlayer dielectric layer and exposes the first active part. The second contact hole penetrates the interlayer dielectric layer and the buffer layer and exposes the light-shielding part. The first contact hole includes a first upper hole and a first lower hole. The first lower hole penetrates a portion of the interlayer dielectric layer and a portion of the first active part. The first upper hole is connected to the side of the first lower hole away from the substrate. The opening width of the first lower hole is less than the opening width of the first upper hole. The second contact hole includes a second upper hole and a second lower hole. The second lower hole penetrates a portion of the interlayer dielectric layer and the buffer layer. The second upper hole is connected to the side of the second lower hole away from the substrate. The opening width of the second lower hole is smaller than the opening width of the second upper hole. The depth of the second upper hole is equal to the depth of the first upper hole. The depth of the second lower hole is greater than the depth of the first lower hole.

12. The method for manufacturing a display panel according to claim 11, characterized in that, The steps of performing two dry etching operations on the interlayer dielectric layer using the same photomask to form the first contact hole and the second contact hole include: The interlayer dielectric layer is subjected to a first dry etching based on a photomask to form a first blind hole corresponding to the first active part and a second blind hole corresponding to the light-shielding part. The first blind hole and the second blind hole have the same depth. The distance from the bottom of the first blind hole to the first active part is a set distance, which is between 10 nanometers and 80 nanometers. A second dry etching is performed on the interlayer dielectric layer based on the same photomask to form a first contact hole and a second contact hole. The distance from the opening end face of the first lower hole to the first active part is a first distance, which is between 1 nanometer and 60 nanometers. The etching rate of the second dry etching on the interlayer dielectric layer is greater than the etching rate of the second dry etching on the first active part.

13. A display device, characterized in that, Includes the display panel as described in any one of claims 1-10.

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