Display module and display device
By designing an isolation structure between the redundant sub-pixel unit and the sub-pixel unit in the display module, and controlling the leakage of the redundant switching transistors in high temperature and high humidity environments, the display cloud pattern (mura) problem is solved, and the reliability and quality of the display screen are improved.
Patent Information
- Application Number
- CN202311444024.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-01
- Publication Date
- 2025-05-06
AI Technical Summary
In high temperature and high humidity environments, display products carrying vias are prone to display cloud patterns (mura), which affects the quality of the display screen.
A display module is designed, including a display area, a redundant sub-pixel unit and an opening area. The redundant sub-pixel unit is isolated from the sub-pixel unit by the redundant pixel driving circuit, and when the control pole is loaded with the working level, the data voltage signal cannot be written, thereby avoiding leakage of the redundant switching transistor.
Effectively improve the mura problem of display products in reliability testing, greatly improving the reliability and quality of display products.
Smart Images
Figure CN119947433A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display module and a display device. Background Art
[0002] With the continuous iteration and upgrading of display technology, organic light-emitting diode (OLED) has gradually replaced liquid crystal display (LCD) and become the preferred choice for various screens. However, a high-quality display screen must not only meet the requirements of daily use, but also pass the reliability test in extreme environments.
[0003] The inventors found that: Figure 1 As shown, display products with vias in the active area (AA) are prone to display mura during reliability testing in high temperature and high humidity environments, thereby affecting the quality of the display screen. Summary of the invention
[0004] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides a display module and a display device.
[0005] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is a display module, which has a display area and an opening area; the display area includes a first display area and a second display area, the second display area is located between the first display area and the opening area, and surrounds the opening area; the display module includes a base substrate, and a plurality of sub-pixel units arranged on the base substrate and located in the first display area, a plurality of redundant sub-pixel units located in the second display area, and a via hole located in the opening area; the redundant sub-pixel unit isolates the sub-pixel unit from the via hole;
[0006] The redundant sub-pixel unit includes redundant sub-pixels and redundant pixel driving circuits corresponding to the redundant sub-pixels; when the redundant switching transistors in at least part of the redundant pixel driving circuits are loaded with working levels at their control electrodes, data voltage signals cannot be written.
[0007] In some embodiments, active layers of redundant switch transistors in at least some of the redundant pixel driving circuits are disconnected.
[0008] In some embodiments, for the redundant sub-pixel unit whose shortest distance from the center to the edge of the opening area is less than or equal to a first preset value, the active layer of the redundant switch transistor therein is disconnected.
[0009] In some embodiments, the redundant sub-pixel unit includes a first side and a second side disposed opposite to each other along a second direction, and the first side is closer to the redundant switch transistor than the second side;
[0010] For the redundant sub-pixel unit whose orthographic projection of the first side on the base substrate is located at the boundary between the opening area and the second display area, the active layer of the redundant switch transistor therein is disconnected.
[0011] In some embodiments, the display module also includes a plurality of gate lines and a plurality of data lines, and the plurality of gate lines and the plurality of data lines are cross-arranged and define a plurality of sub-pixel units and a plurality of redundant sub-pixel units; the second direction is an extension direction of the data lines; or, the second direction is an extension direction of the gate lines.
[0012] In some embodiments, for a redundant switch transistor whose distance to the edge of the opening area is less than or equal to a second preset value, its active layer is disconnected.
[0013] In some embodiments, the active layer of the redundant switch transistor includes a source contact region, a drain contact region, and a channel region sandwiched between the source contact region and the drain contact region;
[0014] The channel region of the active layer of the redundant switch transistor is disconnected.
[0015] In some embodiments, the active layer of the redundant switch transistor includes a source contact region, a drain contact region, and a channel region sandwiched between the source contact region and the drain contact region;
[0016] The source contact region and / or the drain contact region of the active layer of the redundant switch transistor are disconnected.
[0017] In some embodiments, the data line is disconnected from a source contact region of an active layer of the switch transistor.
[0018] In some embodiments, the display module includes a base substrate, a semiconductor layer, a first conductive layer, and a second conductive layer sequentially disposed on the base substrate;
[0019] The active layer of the redundant switch transistor is located in the semiconductor layer;
[0020] The control electrode of the redundant switch transistor is located in the first conductive layer;
[0021] The data line is located in the second conductive layer;
[0022] At least one insulating layer is disposed between the first conductive layer and the second conductive layer, and the at least one insulating layer disconnects the data line from the source contact region of the active layer of the redundant switch transistor.
[0023] In some embodiments, the sub-pixel unit includes a sub-pixel and a pixel driving circuit arranged corresponding to the sub-pixel;
[0024] The pixel driving circuit and the redundant pixel driving circuit have the same structure, and the arrangement of the transistors in the pixel driving circuit is the same as the arrangement of the transistors in the redundant pixel driving circuit.
[0025] In some embodiments, the redundant sub-pixel unit includes a first side and a second side that are arranged opposite to each other along the second direction;
[0026] The redundant pixel driving circuit at least includes a redundant switch transistor, a redundant driving transistor, a redundant first light emission control transistor, a redundant second light emission control transistor, a redundant first reset transistor, a redundant second reset transistor, a redundant third reset transistor and a storage capacitor;
[0027] An orthographic projection of a channel region of the redundant third reset transistor on the substrate is closer to an orthographic projection of the first side on the substrate than an orthographic projection of a channel region of other transistors in the redundant pixel driving circuit except the redundant third reset transistor on the substrate;
[0028] The orthographic projection of the channel region of the redundant switch transistor on the substrate is located on a side of the orthographic projection of the channel region of the redundant third reset transistor on the substrate away from the orthographic projection of the first side on the substrate;
[0029] The orthographic projections of the channel regions of the redundant first light-emitting control transistor and the redundant second light-emitting control transistor on the substrate are both located on a side of the orthographic projection of the channel region of the redundant switch transistor on the substrate away from the orthographic projection of the first side on the substrate;
[0030] The orthographic projections of the channel regions of the redundant first reset transistor and the redundant second reset transistor on the substrate are both located on a side of the orthographic projections of the channel regions of the redundant first light-emitting control transistor and the redundant second light-emitting control transistor on the substrate away from the orthographic projections of the first side on the substrate.
[0031] In some embodiments, the source contact areas of the active layers of at least some transistors in the redundant pixel driving circuit are reused as the sources of the corresponding transistors, and the drain contact areas are reused as the drains of the corresponding transistors.
[0032] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising a display module as described in any one of the above-mentioned first aspects. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 This is a picture showing the effect of display mura in the existing reliability test in high temperature and high humidity environment;
[0034] Figure 2a A schematic diagram of the area division of the display module in an embodiment of the present disclosure;
[0035] Figure 2b It is a structural schematic diagram of a display module in an embodiment of the present disclosure;
[0036] Figure 3 Example 1 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected;
[0037] Figure 4 Example 2 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected;
[0038] Figure 5 A schematic diagram of an exemplary distribution of redundant switch transistors provided in an embodiment of the present disclosure;
[0039] Figure 6 Example 3 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected;
[0040] Figure 7a A schematic diagram of an exemplary gate line and a data line crossing to define a sub-pixel unit provided in an embodiment of the present disclosure;
[0041] Figure 7b A schematic diagram of another exemplary gate line and data line crossing to define a sub-pixel unit provided in an embodiment of the present disclosure;
[0042] Figure 8a Example 4 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected;
[0043] Figure 8b Example 5 provided for an embodiment of the present disclosure, a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected;
[0044] Figure 8c Example 6 provided in the embodiment of the present disclosure, a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected;
[0045] Fig. 9 A schematic diagram of disconnecting a channel region of an active layer of a redundant switch transistor provided in an embodiment of the present disclosure;
[0046] Fig.10 A schematic diagram of disconnecting a source contact region of an active layer of a redundant switch transistor provided in an embodiment of the present disclosure;
[0047] Fig.11 A schematic diagram of disconnecting the drain contact region of the active layer of the redundant switch transistor provided in an embodiment of the present disclosure;
[0048] Fig.12 A circuit diagram of an exemplary redundant pixel driving circuit provided in an embodiment of the present disclosure;
[0049] Fig.13a A plan view of an exemplary semiconductor layer, a first conductive layer, and a second conductive layer stacked in accordance with an embodiment of the present disclosure;
[0050] Fig.13b for Fig.13a Schematic cross-section of the structure in the AA' direction.
[0051] The reference numerals are as follows: AA, display area; PP, opening area; AA1, first display area; AA2, second display area; 1, substrate; 10, sub-pixel unit; 101, pixel driving circuit; 102, sub-pixel; 20, redundant sub-pixel unit; 201, redundant pixel driving circuit; 202, redundant sub-pixel; V, via; T4, redundant switch transistor; T3, redundant driving transistor; T5, redundant first light-emitting control transistor; T6, redundant second light-emitting control transistor; T1, redundant first reset transistor; T8, redundant second reset transistor; T7, redundant third reset transistor; T 2. Redundant threshold compensation transistor; Cst, storage capacitor; X, first direction; Y, second direction; 21, first side; 22, second side; 23, third side; 24, fourth side; Gate, gate line; Data, data line; 31, semiconductor layer; 32, first conductive layer; 33, second conductive layer; 34, insulating layer; VDD, first power supply voltage terminal; VSS, second power supply voltage terminal; EM1, first light-emitting control signal line; EM2, first light-emitting control signal line; Reset1(n), first reset control signal line; Reset2(n), second reset control signal line. DETAILED DESCRIPTION
[0052] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the present disclosure for protection, but merely represents the selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present disclosure.
[0053] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0054] The "multiple or several" mentioned in this disclosure refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects before and after are in an "or" relationship.
[0055] In the related art, some OLED display products, such as mobile phones, etc., are usually equipped with camera devices and sensing devices, such as cameras, infrared sensors, etc. These devices are often installed in vias located in the effective display AA area. Figure 1 As shown, the camera is installed in the via hole above the AA area of the mobile phone screen. However, such display products with via holes inside the AA area are prone to display mura in reliability tests in high temperature and high humidity environments (e.g., 85°C, 85% humidity), thus affecting the quality of the display screen.
[0056] In view of this, an embodiment of the present disclosure provides a display module, which improves the mura problem of a display product in a reliability test by designing a redundant pixel driving circuit located near a via hole, thereby significantly improving the reliability quality of the display product.
[0057] The specific structure of the display module in the embodiment of the present disclosure is described in detail below.
[0058] Figure 2a FIG. 1 is a schematic diagram of the area division of the display module in the embodiment of the present disclosure, such as Figure 2a As shown, the display module has a display area AA and an opening area PP, wherein the display area AA includes a first display area AA1 and a second display area AA2, and the second display area AA2 is located between the first display area AA1 and the opening area PP and surrounds the opening area PP.
[0059] The first display area AA1 is mainly provided with sub-pixel units 10 ; the second display area AA2 is mainly provided with redundant sub-pixel units 20 ; the opening area PP is mainly provided with via holes V for accommodating shooting devices such as cameras.
[0060] For example, Figure 2a As shown, the opening area PP is located inside the display area AA and is surrounded by the display area AA. Specifically, the first display area AA1 surrounds the second display area AA2, and the second display area AA2 surrounds the opening area PP.
[0061] Figure 2b is a schematic diagram of the structure of the display module in the embodiment of the present disclosure, such as Figure 2b As shown, the display module includes a base substrate 1, and a plurality of sub-pixel units 10 arranged on the base substrate 1 and located in the first display area AA1, a plurality of redundant sub-pixel units 20 located in the second display area AA2, and a via V located in the opening area PP; the redundant sub-pixel unit 20 isolates the sub-pixel unit 10 from the via V; the redundant sub-pixel unit 20 includes a redundant sub-pixel 202 and a redundant pixel driving circuit 201 arranged corresponding to the redundant sub-pixel 202; the redundant switching transistor T4 (not shown in the figure) in at least part of the redundant pixel driving circuit 201 cannot write a data voltage signal when the working level is loaded on its control electrode.
[0062] Exemplarily, the sub-pixel unit 10 and the redundant sub-pixel unit 20 have the same size and / or the same arrangement.
[0063] Exemplarily, the sub-pixel unit 10 includes a sub-pixel 102 and a pixel driving circuit 101 arranged corresponding to the sub-pixel 102; the pixel driving circuit 101 in the sub-pixel unit 10 and the redundant pixel driving circuit 201 in the redundant sub-pixel unit 20 have the same structure.
[0064] Exemplarily, the arrangement of the transistors in the pixel driving circuit 101 is the same as the arrangement of the transistors in the redundant pixel driving circuit 201 .
[0065] The present disclosure sets a redundant sub-pixel unit 20 outside the opening area PP to isolate the via hole V from the sub-pixel unit 10. The redundant sub-pixel unit 20 protects the sub-pixel unit 10 to ensure the stability of the sub-pixel unit 10.
[0066] Exemplarily, the display module further includes a plurality of gate lines Gate and a plurality of data lines Data. Each gate line Gate is configured to provide a scan signal to a sub-pixel unit 10 and a redundant sub-pixel unit 20 electrically connected thereto. Each data line Data is configured to provide a data voltage signal to a sub-pixel unit 10 and a redundant sub-pixel unit 20 connected thereto.
[0067] Exemplarily, the redundant pixel driving circuit 201 includes at least a plurality of redundant transistors, wherein the plurality of redundant transistors includes at least a redundant switch transistor T4.
[0068] It should be noted that, on the one hand, since the redundant sub-pixel unit 20 is close to the via hole V, the characteristics of the redundant switch transistor T4 in the redundant sub-pixel unit 20 are not very stable, and the threshold voltage Vth is very likely to drift when used in a high temperature and high humidity environment. On the other hand, during the reliability test, the data voltage signal provided by the data line Data is often a high-voltage signal that displays a black state, and the threshold voltage Vth drifts, which eventually leads to leakage of the redundant switch transistor T4, resulting in display mura, which affects the quality of the display screen.
[0069] When the redundant switch transistor T4 in at least part of the redundant pixel driving circuit 201 in the present disclosure is loaded with the working level at its control electrode, that is, when the redundant switch transistor T4 responds to the scanning signal, the data voltage signal provided by the data line Data cannot be written, thus avoiding the redundant switch transistor T4 from leaking electricity. Therefore, even if the redundant switch transistor T4 is affected by its own characteristics and the threshold voltage Vth drifts, the redundant switch transistor T4 will not leak electricity, and will not affect the redundant sub-pixel unit 20 and the sub-pixel unit 10 located in the first display area AA1, thereby improving the mura problem in the reliability test and greatly improving the reliability quality of the product.
[0070] In some embodiments, a solution for preventing the data voltage signal from being written into the redundant switch transistor T4 may be: the active layer of the redundant switch transistor T4 in at least part of the redundant pixel driving circuit 201 is disconnected.
[0071] For example, Figure 3Example 1 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units in which the active layer of the redundant switch transistor is disconnected, such as Figure 3 As shown, for each redundant sub-pixel unit 20 (ie Figure 3 The middle gray filled portion), wherein the active layer of the redundant switching transistor T4 in the redundant pixel driving circuit 201 is disconnected.
[0072] Exemplarily, the active layer of the redundant switch transistor T4 includes a source contact region, a drain contact region, and a channel region sandwiched between the source contact region and the drain contact region. The active layer disconnection setting of the redundant switch transistor T4 can be a disconnection setting of at least one of the source contact region, the drain contact region and the channel region.
[0073] In some embodiments, Figure 4 Example 2 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units in which the active layer of the redundant switch transistor is disconnected, such as Figure 4 As shown, for the redundant sub-pixel unit 20 (ie, Figure 4 The middle grey filled part), in which the active layer of the redundant switching transistor T4 is disconnected.
[0074] Here, the center of the redundant sub-pixel unit 20 can be understood as the center of the pattern of the orthographic projection of the redundant sub-pixel unit 20 on the base substrate 1 .
[0075] It should be noted that the probability of leakage of the redundant switch transistor T4 is related to the distance of the redundant switch transistor T4 from the via hole V. The closer the redundant switch transistor T4 is to the via hole V, the higher the possibility of leakage in extreme environments. Based on this, the data of the first preset value is defined, for example, as 1 / 2 of the length of the redundant sub-pixel unit 20. The present disclosure does not specifically limit the specific data. In this way, it is not necessary to disconnect the active layers of the redundant switch transistors T4 located in the second display area AA2. As long as the active layer of the redundant switch transistors T4 in the redundant sub-pixel unit 20 whose center distance from the edge of the opening area PP is less than or equal to the first preset value, it is sufficient to ensure the stability of the sub-pixel unit 10 and avoid the display mura problem caused by leakage of the redundant switch transistor T4.
[0076] In some embodiments, Figure 5 A schematic diagram of an exemplary distribution of redundant switch transistors provided in an embodiment of the present disclosure is shown in FIG. Figure 5 As shown, the redundant sub-pixel unit 20 includes a first side 21 and a second side 22 that are oppositely arranged along the second direction Y, and the first side 21 is closer to the redundant switch transistor T4 than the second side 22 .
[0077] Figure 6 Example 3 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected, such as Figure 6 As shown, for the redundant sub-pixel unit 20 (ie, Figure 6 The middle grey filled part), in which the active layer of the redundant switching transistor T4 is disconnected.
[0078] Since the closer the redundant switch transistor T4 is to the via V, the higher the possibility of leakage in extreme environments. Also, because the first side 21 in the redundant sub-pixel unit 20 is closer to the redundant switch transistor T4 than the second side 22, the possibility of leakage of the redundant switch transistor T4 in the redundant sub-pixel unit 20 whose orthographic projection of the first side 21 on the base substrate 1 is located at the intersection of the opening area PP and the second display area AA2 is higher than the possibility of leakage of other redundant switch transistors T4 in the second display area AA2. Based on this, for the redundant sub-pixel unit 20 whose first side 21 is exposed to the opening area PP, the active layer disconnection setting of the redundant switch transistor T4 therein can not only ensure the stability of the sub-pixel unit 10, but also largely avoid leakage of the redundant switch transistor T4.
[0079] In some embodiments, Figure 7a A schematic diagram of an exemplary gate line and a data line crossing to define a sub-pixel unit provided in an embodiment of the present disclosure, Figure 7b Another exemplary schematic diagram of a sub-pixel unit defined by the intersection of a gate line and a data line provided in an embodiment of the present disclosure.
[0080] like Figure 7a and Figure 7b As shown, the display module further includes a plurality of gate lines Gate and a plurality of data lines Data, and the plurality of gate lines Gate and the plurality of data lines Data are cross-arranged to define a plurality of sub-pixel units 10 and a plurality of redundant sub-pixel units 20 .
[0081] For example, Figure 7a As shown, the second direction Y is the extending direction of the data line Data.
[0082] For example, Figure 7b As shown, the second direction Y is the extension direction of the gate line Gate.
[0083] In some embodiments, Figure 5As shown, the redundant sub-pixel unit 20 includes a first side 21 and a second side 22 that are oppositely arranged along the second direction Y; a third side 23 and a fourth side 24 that are oppositely arranged along the first direction X; and the first side 21 is closer to the redundant switch transistor T4 than the second side 22. The following description is made by taking the second direction Y as the extension direction of the gate line Gate and the second direction Y as the extension direction of the data line Data as an example.
[0084] like Figure 5 As shown, it shows a structure in which the semiconductor layer 31 of each transistor in the redundant pixel driving circuit 201 and the first conductive layer 32 where the gate is located are stacked. The redundant pixel driving circuit 201 at least includes a redundant switch transistor T4, a redundant drive transistor T3, a redundant first light-emitting control transistor T5, a redundant second light-emitting control transistor T6, a redundant first reset transistor T1, a redundant second reset transistor T8, a redundant third reset transistor T7 and a storage capacitor Cst; the orthographic projection of the channel region of the redundant third reset transistor T7 on the substrate substrate 1 is closer to the orthographic projection of the first side 21 on the substrate substrate 1 than the orthographic projection of the channel region of the other transistors in the redundant pixel driving circuit 201 except the redundant third reset transistor T7 on the substrate substrate 1; the orthographic projection of the channel region of the redundant switch transistor T4 on the substrate substrate 1 is located at the redundant third reset transistor T7. The orthographic projection of the channel region of the redundant transistor T7 on the substrate substrate 1 is away from the orthographic projection of the first side 21 on the substrate substrate 1; the orthographic projections of the channel regions of the redundant first light-emitting control transistor T5 and the redundant second light-emitting control transistor T6 on the substrate substrate 1 are both located on the side where the orthographic projection of the channel region of the redundant switch transistor T4 on the substrate substrate 1 is away from the orthographic projection of the first side 21 on the substrate substrate 1; the orthographic projections of the channel regions of the redundant first reset transistor T1 and the redundant second reset transistor T8 on the substrate substrate 1 are both located on the side where the orthographic projections of the channel regions of the redundant first light-emitting control transistor T5 and the redundant second light-emitting control transistor T6 on the substrate substrate 1 are away from the orthographic projection of the first side 21 on the substrate substrate 1.
[0085] With the transistor distribution in this embodiment, the redundant switch transistor T4 is located at the upper left corner or the upper right corner of the redundant sub-pixel unit 20 close to the first side 21 .
[0086] In some embodiments, Figure 8a Example 4 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected, Figure 8b Example 5 provided in the embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layer of the redundant switch transistor disconnected, Figure 8c Example 6 provided for an embodiment of the present disclosure is a schematic diagram of the distribution of redundant sub-pixel units with the active layers of redundant switch transistors disconnected.
[0087] like Figure 8a As shown, when the redundant switch transistor T4 is located at the upper right corner of the virtual quadrilateral surrounded by the first side 21, the second side 22, the third side 23 and the fourth side 24, for the redundant switch transistor T4 (i.e. Figure 8a The medium grey filled part) has its active layer disconnected setting.
[0088] Exemplarily, the second preset value is, for example, 1 / 2 of the width of the redundant sub-pixel unit 20 .
[0089] like Figure 8b As shown, when the redundant switch transistor T4 is located at the upper left corner of the virtual quadrilateral surrounded by the first side 21, the second side 22, the third side 23 and the fourth side 24, for the redundant switch transistor T4 (i.e. Figure 8b The medium grey filled part) has its active layer disconnected setting.
[0090] like Figure 8c As shown, a reference line extending along the second direction Y and passing through the center of the via hole V divides the opening area PP into a first sub-area PP-1 and a second sub-area PP-2; for the redundant sub-pixel unit 20 closer to the second sub-area PP-1 in the first sub-area PP-1 and the second sub-area PP-2, the redundant switch transistor T4 is located at the upper left corner of the virtual quadrilateral surrounded by the first side 21, the second side 22, the third side 23 and the fourth side 24; for the redundant sub-pixel unit 20 closer to the first sub-area PP-1 in the first sub-area PP-1 and the second sub-area PP-2, the redundant switch transistor T4 is located at the upper right corner of the virtual quadrilateral surrounded by the first side 21, the second side 22, the third side 23 and the fourth side 24. For the redundant switch transistor T4 (i.e., the redundant switch transistor T4) whose distance to the edge of the opening area PP is less than or equal to the second preset value, the redundant switch transistor T4 is located at the upper right corner of the virtual quadrilateral surrounded by the first side 21, the second side 22, the third side 23 and the fourth side 24. Figure 8c The medium grey filled part) has its active layer disconnected setting.
[0091] Here, the distance from the redundant switching transistor T4 to the edge of the opening area PP can be understood as the shortest distance from the center of the redundant switching transistor T4 to the edge of the opening area PP; or, it can also be understood as the shortest distance from the edge of the redundant switching transistor T4 to the edge of the opening area PP; or, it can also be understood as the shortest distance from the center of the orthographic projection of the channel region of the redundant switching transistor T4 on the substrate 1 to the edge of the opening area PP.
[0092] Exemplarily, the second preset value is smaller than the distance between the first side 21 and the second side 22. The second preset value is smaller than the distance between the third side 23 and the fourth side 24.
[0093] It should be noted that the probability of leakage of the redundant switch transistor T4 is related to the distance of the redundant switch transistor T4 from the via V. The closer the redundant switch transistor T4 is to the via V, the higher the possibility of leakage in extreme environments. Based on this, the data defining the second preset value is not specifically limited in this disclosure.
[0094] In some embodiments, Fig. 9 A schematic diagram of disconnecting the channel region of the active layer of the redundant switch transistor provided in the embodiment of the present disclosure, as shown in FIG. Fig. 9 As shown, the active layer of the redundant switch transistor T4 includes a source contact region, a drain contact region and a channel region sandwiched between the source contact region and the drain contact region; the channel region of the active layer of the redundant switch transistor T4 is disconnected.
[0095] In this embodiment, the channel region of the active layer of the redundant switch transistor T4 is disconnected so that the data voltage signal cannot be written into the redundant switch transistor T4 .
[0096] In some embodiments, Fig.10 A schematic diagram of disconnecting a source contact region of an active layer of a redundant switch transistor provided in an embodiment of the present disclosure, Fig.11 A schematic diagram of disconnecting the drain contact region of the active layer of the redundant switch transistor provided in an embodiment of the present disclosure, as shown in FIG. Fig.10 or Fig.11 As shown, the active layer of the redundant switch transistor T4 includes a source contact region, a drain contact region, and a channel region sandwiched between the source contact region and the drain contact region.
[0097] For example, Fig.10 As shown, the source contact region of the active layer of the redundant switching transistor T4 is disconnected.
[0098] For example, Fig.11 As shown, the drain contact region of the active layer of the redundant switching transistor T4 is disconnected.
[0099] In this embodiment, the source contact region and / or the drain contact region of the active layer of the redundant switch transistor T4 is disconnected so that the data voltage signal cannot be written into the redundant switch transistor T4 .
[0100] In some embodiments, another solution for preventing the data voltage signal from being written into the redundant switch transistor T4 may be: disconnecting the data line Data from the source contact region of the active layer of the switch transistor.
[0101] In some embodiments, Fig.12 A circuit diagram of an exemplary redundant pixel driving circuit provided in an embodiment of the present disclosure is shown in FIG. Fig.12As shown, the redundant pixel driving circuit 201 adopts an 8T1C (i.e., 8 transistors and 1 capacitor) circuit structure, specifically including a redundant switching transistor T4, a redundant driving transistor T3, a redundant first light-emitting control transistor T5, a redundant second light-emitting control transistor T6, a redundant first reset transistor T1, a redundant second reset transistor T8, a redundant third reset transistor T7, a redundant threshold compensation transistor T2 and a storage capacitor Cst.
[0102] It should be noted that the transistor used in the embodiment of the present disclosure may be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between the source and drain. In the embodiment of the present disclosure and the subsequent description, in order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode, the other electrode is called the second electrode, and the gate is called the control electrode. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. When a P-type transistor is used, the first electrode is the source of the P-type transistor, the second electrode is the drain of the P-type transistor, and when a low-level signal is input to the gate, the source and drain are turned on; when an N-type transistor is used, the first electrode is the source of the N-type transistor, the second electrode is the drain of the N-type transistor, and when a high-level signal is input to the gate, the source and drain are turned on. In the embodiment of the present disclosure, the redundant switch transistor T4, the redundant driving transistor T3, the redundant first light-emitting control transistor T5, the redundant second light-emitting control transistor T6, the redundant first reset transistor T1, the redundant second reset transistor T8, the redundant third reset transistor T7 and the redundant threshold compensation transistor T2 are all specifically described by taking P-type transistors as examples.
[0103] like Fig.12 As shown, the first electrode of the redundant switch transistor T4 is electrically connected to the data line Data to receive the data voltage signal, the second electrode of the redundant switch transistor T4 is electrically connected to the first electrode of the redundant drive transistor T3, and the control electrode of the redundant switch transistor T4 is electrically connected to the gate line Gate(n) of this level (or the gate line Gate(n) of this row) to receive the scan signal.
[0104] like Fig.12 As shown, the second electrode of the redundant driving transistor T3 is electrically connected to the first electrode of the redundant threshold compensation transistor T2, and the control electrode of the redundant driving transistor T3 is electrically connected to the second electrode of the redundant threshold compensation transistor T2 and the second electrode plate of the storage capacitor Cst.
[0105] like Fig.12 As shown, the first electrode of the redundant first light-emitting control transistor T5 is electrically connected to the first power supply voltage terminal VDD, the second electrode of the redundant first light-emitting control transistor T5 is electrically connected to the first electrode of the redundant driving transistor T3, and the control electrode of the redundant first light-emitting control transistor T5 is electrically connected to the first light-emitting control signal line EM1.
[0106] like Fig.12 As shown, the first electrode of the redundant second light emitting control transistor T6 is electrically connected to the second electrode of the redundant driving transistor T3, the second electrode of the redundant second light emitting control transistor T6 is electrically connected to the first electrode of the light emitting device, and the control electrode of the redundant second light emitting control transistor T6 is electrically connected to the second light emitting control signal line EM2.
[0107] Exemplarily, the first light emitting control signal line EM1 and the second light emitting control signal line EM2 may be the same.
[0108] like Fig.12 As shown, the first electrode of the redundant first reset transistor T1 is electrically connected to the first reset power supply terminal Vinit1, the second electrode of the redundant first reset transistor T1 is electrically connected to the second electrode of the redundant driving transistor T3, and the control electrode of the redundant first reset transistor T1 is electrically connected to the first reset control signal line Reset1(n) to receive the first sub-reset control signal.
[0109] like Fig.12 As shown, the first electrode of the redundant second reset transistor T8 is electrically connected to the second reset power supply terminal Vinit2, the second electrode of the redundant second reset transistor T8 is electrically connected to the first electrode of the redundant driving transistor T3, and the control electrode of the redundant second reset transistor T8 is electrically connected to the second reset control signal line Reset2(n) to receive the second sub-reset control signal.
[0110] Exemplarily, the first reset control signal line Reset1 (n) and the second reset control signal line Reset2 (n) may be the same.
[0111] Exemplarily, the first reset power terminal Vinit1 and the second reset power terminal Vinit2 may be the same or different.
[0112] like Fig.12 As shown, the first electrode of the redundant third reset transistor T7 is electrically connected to the third reset power supply terminal Vinit3, the second electrode of the redundant third reset transistor T7 is electrically connected to the first electrode of the light-emitting device, and the control electrode of the redundant third reset transistor T7 is electrically connected to the previous level gate line Gate (n-1) (or the previous row of gate lines Gate (n-1)) to receive the scanning signal provided by the previous level gate line Gate (n-1).
[0113] Exemplarily, the third reset power terminal Vinit3 and the first power reset terminal Vinit1 may be the same or different.
[0114] like Fig.12 As shown, the first plate of the storage capacitor Cst is electrically connected to the first power supply voltage terminal VDD.
[0115] like Fig.12 As shown, the second electrode of the light emitting device is electrically connected to the second power supply voltage terminal VSS.
[0116] Exemplarily, one of the first electrode and the second electrode of the light-emitting device is an anode, and the other is a cathode.
[0117] Exemplarily, the redundant pixel driving circuit 201 and the pixel driving circuit 101 have the same circuit structure, and both adopt an 8T1C circuit structure.
[0118] For example, Figure 5 As shown, the pixel driving circuit 101 and the redundant pixel driving circuit 201 have the same structure, and the arrangement of the transistors in the pixel driving circuit 101 is the same as the arrangement of the transistors in the redundant pixel driving circuit 201 .
[0119] Of course, in the embodiment of the present disclosure, the redundant pixel driving circuit 201 and the pixel driving circuit 101 may also adopt other circuit structures, such as 7T1C structure, 7T2C structure, 6T1C structure, 6T2C structure or 9T2C structure, etc., which is not limited in the embodiment of the present disclosure.
[0120] In some embodiments, Fig.13a A plan view of an exemplary semiconductor layer, a first conductive layer, and a second conductive layer stacked in accordance with an embodiment of the present disclosure, Fig.13b for Fig.13a The cross-sectional diagram of the structure in the AA' direction is as follows: Fig.13a and Fig.13b As shown, the display module includes a base substrate 1, a semiconductor layer 31, a first conductive layer 32 and a second conductive layer 33 arranged on the base substrate 1 in sequence; the active layer of the redundant switch transistor T4 is located in the semiconductor layer 31; the control electrode of the redundant switch transistor T4 is located in the first conductive layer 32; the data line Data is located in the second conductive layer 33; at least one insulating layer 34 is arranged between the first conductive layer 32 and the second conductive layer 33, and the at least one insulating layer 34 disconnects the data line Data from the source contact area T41 of the active layer of the redundant switch transistor T4.
[0121] In this embodiment, a transfer hole connecting the data line Data and the source contact area T41 of the switch transistor is not provided on the insulating layer 34, so that the data voltage signal cannot be written into the redundant switch transistor T4.
[0122] In some embodiments, the source contact regions of the active layers of at least some transistors in the redundant pixel driving circuit 201 are reused as the sources of the corresponding transistors, and the drain contact regions are reused as the drains of the corresponding transistors.
[0123] For example, Fig. 9 , Fig.10 or Fig.11 As shown, the source contact areas of the redundant switch transistor T4, the redundant driving transistor T3, the redundant first light-emitting control transistor T5, the redundant second light-emitting control transistor T6, the redundant first reset transistor T1, the redundant second reset transistor T8 and the redundant third reset transistor T7 are all reused as sources, and the drain contact areas are all reused as drains.
[0124] In some embodiments, the display module may be an active-matrix organic light-emitting diode (AMOLED) display module.
[0125] In addition, the embodiment of the present disclosure further provides a display device, which includes the display module described in any one of the above embodiments. The display device can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a vehicle-mounted device, or any other product with a display function. Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as limitations to the present disclosure.
[0126] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.
Claims
1. A display module, comprising a display area and an opening area; characterized in that: The display area includes a first display area and a second display area, the second display area is located between the first display area and the opening area, and surrounds the opening area; the display module includes a base substrate, and a plurality of sub-pixel units arranged on the base substrate and located in the first display area, a plurality of redundant sub-pixel units located in the second display area, and a via hole located in the opening area; the redundant sub-pixel unit isolates the sub-pixel unit from the via hole; The redundant sub-pixel unit includes redundant sub-pixels and redundant pixel driving circuits corresponding to the redundant sub-pixels; when the redundant switching transistors in at least part of the redundant pixel driving circuits are loaded with working levels at their control electrodes, data voltage signals cannot be written.
2. The display module according to claim 1, characterized in that: Active layers of redundant switch transistors in at least part of the redundant pixel driving circuits are disconnected.
3. The display module according to claim 1, characterized in that: For the redundant sub-pixel unit whose shortest distance from the center to the edge of the opening area is less than or equal to the first preset value, the active layer of the redundant switch transistor therein is disconnected.
4. The display module according to claim 1, characterized in that: The redundant sub-pixel unit comprises a first side and a second side arranged opposite to each other along a second direction, wherein the first side is closer to the redundant switch transistor than the second side; For the redundant sub-pixel unit whose orthographic projection of the first side on the base substrate is located at the boundary between the opening area and the second display area, the active layer of the redundant switch transistor therein is disconnected.
5. The display module according to claim 4, characterized in that: The display module also includes a plurality of gate lines and a plurality of data lines, which are cross-arranged and define a plurality of sub-pixel units and a plurality of redundant sub-pixel units; the second direction is an extension direction of the data lines; or, the second direction is an extension direction of the gate lines.
6. The display module according to claim 1, characterized in that: For the redundant switch transistor whose distance to the edge of the opening area is less than or equal to the second preset value, its active layer is disconnected.
7. The display module according to any one of claims 2 to 6, characterized in that: The active layer of the redundant switch transistor includes a source contact region, a drain contact region, and a channel region sandwiched between the source contact region and the drain contact region; The channel region of the active layer of the redundant switch transistor is disconnected.
8. The display module according to any one of claims 2 to 5, characterized in that: The active layer of the redundant switch transistor includes a source contact region, a drain contact region, and a channel region sandwiched between the source contact region and the drain contact region; The source contact region and / or the drain contact region of the active layer of the redundant switch transistor are disconnected.
9. The display module according to claim 1, characterized in that: The data line is disconnected from the source contact region of the active layer of the switch transistor.
10. The display module according to claim 1, characterized in that: The display module comprises a base substrate, a semiconductor layer, a first conductive layer and a second conductive layer sequentially arranged on the base substrate; The active layer of the redundant switch transistor is located in the semiconductor layer; The control electrode of the redundant switch transistor is located in the first conductive layer; The data line is located in the second conductive layer; At least one insulating layer is disposed between the first conductive layer and the second conductive layer, and the at least one insulating layer disconnects the data line from the source contact region of the active layer of the redundant switch transistor.
11. The display module according to claim 1, characterized in that: The sub-pixel unit includes a sub-pixel and a pixel driving circuit arranged corresponding to the sub-pixel; The pixel driving circuit and the redundant pixel driving circuit have the same structure, and the arrangement of the transistors in the pixel driving circuit is the same as the arrangement of the transistors in the redundant pixel driving circuit.
12. The display module according to claim 1, characterized in that: The redundant sub-pixel unit comprises a first side edge and a second side edge which are arranged opposite to each other along a second direction; The redundant pixel driving circuit at least includes a redundant switch transistor, a redundant driving transistor, a redundant first light emission control transistor, a redundant second light emission control transistor, a redundant first reset transistor, a redundant second reset transistor, a redundant third reset transistor and a storage capacitor; An orthographic projection of a channel region of the redundant third reset transistor on the substrate is closer to an orthographic projection of the first side on the substrate than an orthographic projection of a channel region of other transistors in the redundant pixel driving circuit except the redundant third reset transistor on the substrate; The orthographic projection of the channel region of the redundant switch transistor on the substrate is located on a side of the orthographic projection of the channel region of the redundant third reset transistor on the substrate away from the orthographic projection of the first side on the substrate; The orthographic projections of the channel regions of the redundant first light-emitting control transistor and the redundant second light-emitting control transistor on the substrate are both located on a side of the orthographic projection of the channel region of the redundant switch transistor on the substrate away from the orthographic projection of the first side on the substrate; The orthographic projections of the channel regions of the redundant first reset transistor and the redundant second reset transistor on the substrate are both located on a side of the orthographic projections of the channel regions of the redundant first light-emitting control transistor and the redundant second light-emitting control transistor on the substrate away from the orthographic projections of the first side on the substrate.
13. The display module according to claim 1, characterized in that: The source contact area of the active layer of at least part of the transistors in the redundant pixel driving circuit is reused as the source of the corresponding transistor, and the drain contact area is reused as the drain of the corresponding transistor.
14. A display device, characterized in that: It comprises the display module as claimed in any one of claims 1 to 13.