Pixel driving circuit, driving method thereof and display device

Abstract

The invention provides a pixel driving circuit, a driving method thereof and a display device, and relates to the technical field of display, the pixel driving circuit can separate an anode of a light emitting device from a source electrode of a driving transistor through setting a transistor, a capacitor and a time sequence signal, so that the anode of the light emitting device is separated from the source electrode of the driving transistor before a light emitting stage; the light-emitting device does not influence the potential change of the source electrode of the driving transistor, and meanwhile, the accurate adjustment of the driving current can be realized through the setting of the capacitance value, so that richer gray scale display is realized; besides, the pixel driving circuit can utilize grid driving signals provided by grid lines in different rows, so that the number of required external signal lines is small, the types and the number of shifting registers (or driving chips) externally connected with the pixel driving circuit are remarkably reduced, and preparation of a narrow-frame display device is facilitated.

Description

Pixel driving circuit and driving method thereof, and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to a patent application filed with the Patent Office of China on August 30, 2023, with application number PCT / CN2023 / 115648 and titled “Pixel driving circuit, driving method thereof, and display device,” the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, and a display device. Background Art

[0004] With the continuous development of the display industry, research on display pixel driving circuits has gradually become an important hotspot.

[0005] Light-emitting diodes (LEDs) are an important type of display device. However, as they are current-driven devices, their brightness and duration are affected by the current magnitude and driving time. In practical applications, negative factors such as coupling capacitance in the pixel drive circuit, leakage in each transistor, threshold voltage (Vth) shift of transistors due to non-uniform transistor manufacturing processes within the display panel, threshold voltage drift caused by long-term unidirectional voltage bias of the LED, and IR drop caused by wire resistance in the circuit all affect the stability of the pixel drive circuit, resulting in uneven brightness of the LED and reduced display quality.

[0006] Summary of the Invention

[0007] The embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, an embodiment of the present application provides a pixel driving circuit, wherein the pixel driving circuit in the nth row includes:

[0009] a reset subcircuit electrically connected to the first reset signal line, the first scan signal line, the first node, the second reset signal line, the control signal line, and the second node, and configured to reset the voltage of the first node under the control of the first scan signal and reset the second node under the control of the first control signal;

[0010] a data writing sub-circuit, electrically connected to the data line, the third scanning signal line and the second node, and configured to write a data signal transmitted by the data line into the second node;

[0011] a driving transistor, wherein a gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to the third node, a second electrode of the driving transistor is electrically connected to the first node, and the driving transistor is configured to generate a driving current under control of a voltage at the second node;

[0012] a light emitting control subcircuit electrically connected to the light emitting control signal line, the first power line, the third node, the first node, and the anode of the light emitting device, and configured to conduct a path between the first power line and the cathode of the light emitting device when the driving transistor is turned on;

[0013] a compensation sub-circuit, electrically connected to the fourth scan signal line, the first power line and the third node, and configured to complete reading of the threshold voltage of the driving transistor in cooperation with the reset sub-circuit;

[0014] a storage sub-circuit, electrically connected to the first node, the second node, and the first power line, and configured to store the voltage of the second node and adjust the voltage of the first node;

[0015] a reset subcircuit, electrically connected to the anode, the fifth scan signal line, and the second power line, and configured to reset the anode under the control of the fifth scan signal;

[0016] Wherein, n is a positive integer, and the first scanning signal line, the third scanning signal line, the fourth scanning signal line, and the fifth scanning signal line are gate lines in different rows.

[0017] In at least one embodiment of the present application, the control signal line includes the first scan signal line or the second scan signal line.

[0018] In at least one embodiment of the present application, pulse widths of the scan signals loaded on the first scan signal line, the third scan signal line, the fourth scan signal line, and the fifth scan signal line are the same.

[0019] In at least one embodiment of the present application, the first scanning signal line is the gate line in the n-4th row, the third scanning signal line is the gate line in the nth row, the fourth scanning signal line is the gate line in the n-2th row, and the fifth scanning signal line is the gate line in the n+2th row; wherein n is greater than 4;

[0020] The pixel driving circuit in the mth row is a dummy pixel driving circuit, where m is a positive integer, greater than or equal to 1 and less than or equal to 4, and equal to n+1 or n+2; the pixel driving circuit in the mth row is electrically connected to the shift register in the mth row.

[0021] In at least one embodiment of the present application, the first reset signal line includes a reference signal line, the second reset signal line includes an initialization signal line, and the absolute value of the difference between the voltage of the reference signal transmitted by the reference signal line and the voltage of the initialization signal transmitted by the initialization signal line is greater than the threshold voltage of the driving transistor.

[0022] In at least one embodiment of the present application, the first reset signal line includes the first power line, and the second reset signal line includes the second power line.

[0023] In at least one embodiment of the present application, the data writing sub-circuit includes a first transistor, a gate of the first transistor is electrically connected to the third scanning signal line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the second node.

[0024] In at least one embodiment of the present application, when the control signal line includes the second scan signal line, the data writing sub-circuit includes a first transistor and a ninth transistor;

[0025] The gate of the first transistor is electrically connected to the third scan signal line, the first electrode of the first transistor is electrically connected to the data line, the second electrode of the first transistor is electrically connected to the first electrode of the ninth transistor, the gate of the ninth transistor is electrically connected to the second scan signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

[0026] In at least one embodiment of the present application, the third scanning signal and the second scanning signal overlap in time.

[0027] In at least one embodiment of the present application, when the control signal line includes the second scan signal line, the data writing sub-circuit includes a first transistor, a ninth transistor, and a tenth transistor;

[0028] The gate of the first transistor is electrically connected to the third scan signal line, the first electrode of the first transistor is electrically connected to the data line, the second electrode of the first transistor is electrically connected to the first electrode of the ninth transistor, the gate of the ninth transistor is electrically connected to the second scan signal line, the second electrode of the ninth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the data line, the second electrode of the tenth transistor is electrically connected to the first electrode of the ninth transistor, and the gate of the tenth transistor is electrically connected to the sixth scan signal line.

[0029] In at least one embodiment of the present application, the sixth scanning signal and the second scanning signal overlap in time.

[0030] In at least one embodiment of the present application, when the control signal line includes the first scan signal line, the data writing sub-circuit includes a first transistor, a ninth transistor, and a tenth transistor;

[0031] The gate of the first transistor is electrically connected to the third scan signal line, the first electrode of the first transistor is electrically connected to the data line, the second electrode of the first transistor is electrically connected to the first electrode of the ninth transistor, the gate of the ninth transistor is electrically connected to the sixth scan signal line, the second electrode of the ninth transistor is electrically connected to the second node, the gate of the tenth transistor is electrically connected to the sixth scan signal line, the first electrode of the tenth transistor is electrically connected to the data line, and the second electrode of the tenth transistor is electrically connected to the first electrode of the ninth transistor.

[0032] In at least one embodiment of the present application, the sixth scan signal line is the gate line in the (n-1)th row, and a pulse width of the scan signal loaded on the sixth scan signal line is the same as a pulse width of the scan signal loaded on the first scan signal line.

[0033] In at least one embodiment of the present application, when the control signal line includes the second scan signal line, the reset sub-circuit includes a fourth transistor of the second transistor,

[0034] The gate of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the second reset signal line, the second electrode of the second transistor is electrically connected to the second node, the gate of the fourth transistor is electrically connected to the first scan signal line, the first electrode of the fourth transistor is electrically connected to the first reset signal line, and the second electrode of the fourth transistor is electrically connected to the first node.

[0035] In at least one embodiment of the present application, when the control signal line includes the first scan signal line, the reset sub-circuit includes a second transistor, a fourth transistor, and an eighth transistor.

[0036] The gate of the second transistor and the gate of the fourth transistor are both electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the second reset signal line, the second electrode of the second transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first reset signal line, the second electrode of the fourth transistor is electrically connected to the first node, the gate of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the second reset signal line, and the second electrode of the eighth transistor is electrically connected to the second node.

[0037] In at least one embodiment of the present application, the light emitting control subcircuit includes a third transistor and a fifth transistor.

[0038] The gate of the third transistor and the gate of the fifth transistor are both electrically connected to the light-emitting control signal line, the first electrode of the third transistor is electrically connected to the first power line, and the second electrode of the third transistor is electrically connected to the third node; the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the anode.

[0039] In at least one embodiment of the present application, the compensation sub-circuit includes a seventh transistor, a gate of the seventh transistor is electrically connected to the fourth scan signal line, a first electrode of the seventh transistor is electrically connected to the first power line, and a second electrode of the seventh transistor is electrically connected to the third node.

[0040] In at least one embodiment of the present application, the storage subcircuit includes a first capacitor and a second capacitor;

[0041] The first electrode of the first capacitor is electrically connected to the second node, and the second electrode of the first capacitor is electrically connected to the first node; the first electrode of the second capacitor is electrically connected to the first power line, and the second electrode of the second capacitor is electrically connected to the second electrode of the first capacitor through the first node.

[0042] In at least one embodiment of the present application, the reset subcircuit includes a sixth transistor, the gate of the sixth transistor is electrically connected to the fifth scan signal line, the first electrode of the sixth transistor is electrically connected to the anode, and the second electrode of the sixth transistor is electrically connected to the second power signal line.

[0043] In at least one embodiment of the present application, when the data writing sub-circuit includes a ninth transistor, the ninth transistor is of an opposite type to the other transistors.

[0044] In at least one embodiment of the present application, the ninth transistor is a P-type transistor.

[0045] In at least one embodiment of the present application, when the driving transistor is an N-type transistor, the voltage of the reference signal is greater than the voltage of the initialization signal, and the absolute value range of the difference between the voltage of the reference signal and the voltage of the initialization signal is 2V to 4V.

[0046] In at least one embodiment of the present application, the capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor.

[0047] In at least one embodiment of the present application, the driving transistor is a dual-gate transistor, and one gate of the driving transistor is electrically connected to the second node, and the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, and the constant voltage is less than the threshold voltage of the driving transistor.

[0048] In at least one embodiment of the present application, the light-emitting device includes an organic light-emitting diode, a micro light-emitting diode, or a sub-millimeter light-emitting diode.

[0049] In at least one embodiment of the present application, the third transistor, the fifth transistor, and the seventh transistor are all dual-gate transistors; two gates of the same transistor are electrically connected together;

[0050] Alternatively, the third transistor, the fifth transistor and the seventh transistor are all metal oxide transistors.

[0051] In a second aspect, an embodiment of the present application provides a display device, comprising a pixel driving circuit as described in any one of the first aspects.

[0052] In a third aspect, an embodiment of the present application provides a driving method for driving the pixel driving circuit according to any one of the first aspects, the method comprising:

[0053] In the first stage, a low-level light-emitting control signal is input to the light-emitting control signal line, a high-level first scanning signal is input to the first scanning signal line, a low-level fourth scanning signal is input to the fourth scanning signal line, a low-level third scanning signal is input to the third scanning signal line, and a low-level fifth scanning signal is input to the fifth scanning signal line;

[0054] In the second stage, a low-level light emission control signal is input to the light emission control signal line, a low-level first scan signal is input to the first scan signal line, a high-level fourth scan signal is input to the fourth scan signal line, a low-level third scan signal is input to the third scan signal line, and a low-level fifth scan signal is input to the fifth scan signal line;

[0055] In the third stage, a low-level light emission control signal is input to the light emission control signal line, a low-level first scan signal is input to the first scan signal line, a low-level fourth scan signal is input to the fourth scan signal line, a high-level third scan signal is input to the third scan signal line, and a low-level fifth scan signal is input to the fifth scan signal line;

[0056] In the fourth stage, a low-level light emission control signal is input to the light emission control signal line, a low-level first scan signal is input to the first scan signal line, a low-level fourth scan signal is input to the fourth scan signal line, a low-level third scan signal is input to the third scan signal line, and a high-level fifth scan signal is input to the fifth scan signal line;

[0057] In the fifth stage, a high-level light-emitting control signal is input to the light-emitting control signal line, a low-level first scanning signal is input to the first scanning signal line, a low-level fourth scanning signal is input to the fourth scanning signal line, a low-level third scanning signal is input to the third scanning signal line, and a low-level fifth scanning signal is input to the fifth scanning signal line.

[0058] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0060] FIG1 , FIG4 , FIG5 , FIG7 and FIG9 are schematic structural diagrams of five pixel driving circuits provided in embodiments of the present application;

[0061] FIG2 is a timing diagram corresponding to the pixel driving circuit shown in FIG1 ;

[0062] FIG3 is a timing diagram corresponding to the pixel driving circuit shown in FIG4 ;

[0063] FIG6 is a timing diagram corresponding to the pixel driving circuit shown in FIG5 ;

[0064] FIG8 is a timing diagram corresponding to the pixel driving circuit shown in FIG7 ;

[0065] FIG10 is a timing diagram corresponding to the pixel driving circuit shown in FIG9 ;

[0066] 11 to 15 are diagrams illustrating device states at different stages of the pixel driving circuit shown in FIG. 1 in the case of the timing diagram shown in FIG. 2 , provided by an embodiment of the present application;

[0067] 16 to 20 are diagrams illustrating device states at different stages of the pixel driving circuit shown in FIG. 7 in the case of the timing diagram shown in FIG. 8 , provided by an embodiment of the present application;

[0068] 21 to 24 are schematic diagrams of electrical connections of pixel driving circuits in four different rows;

[0069] FIG25 is a circuit connection diagram of a display device provided in an embodiment of the present application;

[0070] FIG26 is a circuit connection diagram of another display device provided in an embodiment of the present application. Specific embodiments

[0071] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0072] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0073] In the embodiments of the present application, the terms "upper" and "lower" indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0074] Throughout the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of the present application. Schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any one or more embodiments or examples in any suitable manner.

[0075] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0076] The features "parallel," "perpendicular," and "identical" used in the embodiments of the present application include features such as "parallel," "perpendicular," and "identical" in the strict sense, as well as "approximately parallel," "approximately perpendicular," and "approximately identical" that include certain tolerances, taking into account the measurement and tolerances associated with the measurement of a particular quantity (e.g., limitations of the measurement system), and represent within an acceptable range of deviation for a particular value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 10% or 5% of the stated value.

[0077] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, that is, meaning "including, but not limited to."

[0078] In the embodiments of this application, "same layer" refers to the relationship between multiple film layers formed from the same material after the same step (e.g., a one-step patterning process). "Same layer" here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same. Polygons in this specification are not strictly defined and can be approximate triangles, parallelograms, trapezoids, pentagons, or hexagons, etc., and some small deformations due to tolerances may exist.

[0079] In the embodiment of the present application, since the source and drain of the transistor are symmetrical, the source and drain can be interchanged. In the embodiment of the present application, one of the source and drain of the transistor is referred to as the first electrode, and the other of the source and drain is referred to as the second electrode.

[0080] In the embodiments of the present application, the term “electrically connected” may refer to a direct electrical connection between two components, or may refer to an electrical connection between two components via one or more other components.

[0081] This application improves upon the traditional 5T1C (five transistors, one capacitor) source-follower internal compensation pixel driver circuit. In a source-follower compensation pixel circuit, the threshold voltage (Vth) of the driver transistor is written into the source of the driver transistor through compensation, so the stability of the source potential of the driver transistor is very important. Although the traditional 5T1C pixel drive circuit can achieve compensation for the threshold voltage (Vth) of the driving transistor, it still has the following problems: 1. During the driving process, the source of the driving transistor is always directly connected to the anode of the light-emitting diode. This is affected by the unstable anode potential caused by uneven diode manufacturing process and the threshold voltage drift caused by the diode being biased by a unidirectional voltage for a long time. 2. Since the light-emitting diode itself has a capacitance, its size is comparable to the parasitic capacitance of the transistor, it is very easy to form a capacitive coupling circuit. As the potential of some scanning signals in the pixel circuit changes, it interferes with the potential of key nodes in the circuit (such as the gate and source of the driving transistor). 3. After the compensation stage, the transistors and light-emitting diodes in the circuit will inevitably leak, which will have a negative impact on the compensation effect of the threshold voltage of the driving transistor. 4. The brightness change of the light-emitting diode is greatly affected by the change of the operating current. That is, a small change in the operating current will cause a large change in the display brightness. When the pixel driving circuit in the prior art is used in a Micro LED (Micro light emitting diode) or Mini LED (Mini light emitting diode) display device, it is unable to adjust the fineness of the change in the operating current of the light-emitting diode, resulting in low adjustment accuracy of the display grayscale.

[0082] Based on this, the embodiments of the present application provide a pixel driving circuit, a driving method thereof, and a display device. The pixel driving circuit can improve the above-mentioned problems by setting transistors, capacitors, and timing signals. In addition, the pixel driving circuit can utilize gate driving signals provided by gate lines in different rows, so that the number of external signal lines required is small, which significantly reduces the types and number of shift registers external to the pixel driving circuit, and is conducive to the preparation of a narrow-frame display device.

[0083] The pixel driving circuit and its driving method, and the display device provided in the embodiments of the present application are introduced and explained below with reference to the accompanying drawings.

[0084] The display device includes a display area and a peripheral area located around the display area. The display area includes a plurality of sub-pixels. Each sub-pixel is provided with a light-emitting device and a pixel driving circuit for providing a driving signal to the light-emitting device.

[0085] An embodiment of the present application provides a pixel driving circuit, wherein, as shown in FIG1 , FIG4 , FIG5 , FIG7 and FIG9 , the pixel driving circuit of the nth row includes:

[0086] The reset sub-circuit 1 is electrically connected to a first reset signal line (e.g., a Ref line), a first scan signal line (e.g., the n-4th gate line), a first node NS, a second reset signal line (e.g., a Vinit line), a control signal line (e.g., a second scan signal line VR or the first scan signal line), and a second node NG. The reset sub-circuit 1 resets the voltage of the first node NS under the control of VG(n-4), and resets the voltage of the second node NG under the control of the first control signal.

[0087] The data writing sub-circuit 2 is electrically connected to the data line Data, the third scanning signal line (eg, the nth gate line) and the second node NG, and is configured to write the data signal Vdata transmitted by the data line Data into the second node NG;

[0088] a driving transistor MD, wherein a gate of the driving transistor MD is electrically connected to a second node NG, a first electrode of the driving transistor MD is electrically connected to a third node A, a second electrode of the driving transistor MD is electrically connected to a first node NS, and the driving transistor MD is configured to generate a driving current under control of a voltage at the second node NG;

[0089] The light emitting control sub-circuit 4 is electrically connected to the light emitting control signal line EM(n), the first power line VDD, the third node A, the first node NS, and the anode of the light emitting device 8 (at the position marked N1), and is configured to connect the path between the first power line VDD and the cathode of the light emitting device 8 when the driving transistor MD is turned on;

[0090] The compensation sub-circuit 5 is electrically connected to the fourth scanning signal line (e.g., the n-2th gate line), the first power line VDD line, and the third node A, and is configured to complete the reading of the threshold voltage of the driving transistor MD in cooperation with the reset sub-circuit 1;

[0091] The storage sub-circuit 6 is electrically connected to the first node NS, the second node NG and the first power line VDD, and is configured to store the voltage of the second node NG and adjust the voltage of the first node NS;

[0092] The reset sub-circuit 7 is electrically connected to the anode N1, the fifth scanning signal line (e.g., the n+2th gate line), and the second power line VDD, and is configured to reset the anode N1 under the control of the fifth scanning signal;

[0093] Wherein, n is a positive integer, and the first scanning signal line, the third scanning signal line, the fourth scanning signal line and the fifth scanning signal line are gate lines in different rows.

[0094] There is no limitation here on the specific circuit structures included in the above-mentioned reset sub-circuit 1, data writing sub-circuit 2, light-emitting control sub-circuit 4, compensation sub-circuit 5, storage sub-circuit 6 and reset sub-circuit 7. As long as the corresponding functions are met, they are within the scope of the pixel driving circuit protection provided in the embodiments of the present application.

[0095] The first node NS, the second node NG and the third node A are not actual circuit structures, but are concepts defined for the convenience of describing the circuit structure, and are hereby explained.

[0096] It should be noted that the above “nth gate line” refers to the gate line corresponding to the nth row of sub-pixels, that is, the gate line of the nth row, where one gate line connects one row of sub-pixels. Other similar descriptions have similar meanings and will not be repeated here.

[0097] In an exemplary embodiment, the light-emitting device 8 may be a light-emitting diode (LED), an organic light-emitting diode (OLED), a Micro LED (Micro light Emitting Diode) or a Mini LED (Mini light Emitting Diode, sub-millimeter light-emitting diode).

[0098] When the light-emitting device 8 is an organic light-emitting diode (OLED), the display device can be a silicon-based display device or a glass-based display device. A silicon-based display device means that the drive circuit of the display device is provided on a silicon-based substrate and the drive circuit is manufactured using a MOS process. A glass-based display device means that the drive circuit of the display device is provided on a glass-based substrate and the drive circuit is manufactured using a TFT process.

[0099] In an exemplary embodiment, the above-mentioned reset sub-circuit 1 can be used to reset the voltage of key nodes in the pixel driving circuit (for example, the first node NS electrically connected to the driving transistor MD, and the second node NG electrically connected to the gate of the driving transistor MD) before refreshing (rewriting new signals) each pixel driving circuit in a row of sub-pixels, so as to eliminate the residual signal in the previous frame of the picture and avoid the appearance of afterimages in the next frame of the display picture. When the pixel driving circuit is applied to a display device, the display effect of the display device can be improved.

[0100] In some embodiments, as shown in FIG. 1 or FIG. 7 , the data writing sub-circuit 2 is electrically connected to the data line Data line, the third scan signal line (eg, the nth gate line), and the second node NG, respectively.

[0101] In other embodiments, as shown in Figure 4, the data writing sub-circuit 2 is electrically connected to the data line Data line, the third scanning signal line (for example, the nth gate line) and the second node NG, respectively, and the data writing sub-circuit 2 is also electrically connected to the second scanning signal line (for example, the VR line).

[0102] In some other embodiments, as shown in Figure 5, the data writing sub-circuit 2 is electrically connected to the data line Data line, the third scanning signal line (for example, the nth gate line) and the second node NG, respectively, and the data writing sub-circuit 2 is also electrically connected to the second scanning signal line (for example, the VR line) and the sixth scanning signal line (for example, the n-1th gate line).

[0103] In some further embodiments, as shown in Figure 9, the data writing sub-circuit 2 is electrically connected to the data line Data line, the third scanning signal line (for example, the nth gate line) and the second node NG, respectively, and the data writing sub-circuit 2 is also electrically connected to the sixth scanning signal line (for example, the n-1th gate line).

[0104] The type of the driving transistor MD is not limited here, and transistors can be divided into N-type transistors and P-type transistors.

[0105] Exemplarily, the driving transistor MD may be an N-type transistor or a P-type transistor.

[0106] In addition, the reset sub-circuit 1 , the data writing sub-circuit 2 , the light emitting control sub-circuit 4 , the compensation sub-circuit 5 and the reset sub-circuit 7 also include at least one transistor respectively.

[0107] There is no limitation on the types of transistors in the reset sub-circuit 1 , the data writing sub-circuit 2 , the first light emitting control sub-circuit 4 , the compensation sub-circuit 5 and the reset sub-circuit 7 .

[0108] Each transistor in the present application can be independently selected from an N-type transistor or a P-type transistor; wherein, for an N-type transistor, an operating level state is a high level state, and a non-operating level state is a low level state; for a P-type transistor, an operating level state is a low level state, and a non-operating level state is a high level state. The operating level state refers to a level state that can turn on the first and second electrodes of the transistor, and the non-operating level state refers to a level state that can turn off the first and second electrodes of the transistor.

[0109] In some examples, the driving transistor MD may include one gate, ie, the gate is electrically connected to the second node NG.

[0110] In some other examples, the driving transistor MD may include two gates, which are electrically connected together and then electrically connected to the second node NG.

[0111] In some other examples, the driving transistor MD may include two gates, which are connected to different nodes and have different potentials. For example, one gate of the driving transistor MD is electrically connected to the second node NG, and is used to control the on and off states of the driving transistor MD; the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, and is used to stabilize the threshold voltage of the driving transistor MD and improve the driving stability of the driving transistor MD, wherein the voltage provided by the signal input terminal with a constant voltage cannot interfere with the on and off states of the driving transistor MD, and therefore the absolute value of the constant voltage is set to be smaller than the absolute value of the threshold voltage of the driving transistor MD.

[0112] In an exemplary embodiment, the first power line VDD line is a positive power signal line, and the second power line VSS line is a negative power signal line. Both the first power line VDD line and the second power line VSS line can continuously provide signals with constant voltages. The voltage of the first power signal VDD provided by the first power line VDD line is greater than the voltage of the second power signal VSS provided by the second power line VSS line.

[0113] In some embodiments, the second power signal line VSS may be electrically connected to the ground line GND.

[0114] In an exemplary embodiment, the light-emission control subcircuit 4 is configured to electrically connect the first power line VDD to the first electrode of the drive transistor MD, and to electrically connect the second electrode of the drive transistor MD to the anode of the light-emitting device 8, and to electrically connect the cathode of the light-emitting device 8 to the second power line VSS. When the light-emission control subcircuit 4 and the drive transistor MD are simultaneously turned on, a path is formed between the positive power signal line, the drive transistor MD, the light-emitting device 8, and the negative power signal line, enabling the light-emitting device 8 to emit light.

[0115] In an exemplary embodiment, the emission control signal EM(n) transmitted on the emission control signal line EM(n) may be provided by an EOA (also known as an EM GOA) or a driver chip. The EOA refers to an emission control shift register on array (ECR), which is used to provide emission control signals to the pixel driver circuits of the sub-pixels in display area AA to control the emission of the sub-pixels in display area AA.

[0116] In an exemplary embodiment, as shown in FIG. 21 , FIG. 22 , FIG. 23 or FIG. 24 , each row of sub-pixels corresponds to one emission control signal line EM line, that is, sub-pixels in the same row are electrically connected to the same emission control signal line EM line.

[0117] In an exemplary embodiment, as shown in Figures 21, 22, 23 or 24, the first scanning signal line, the third scanning signal line, the fourth scanning signal line and the fifth scanning signal line are gate lines of different rows, that is, for the pixel driving circuit of the nth row, it is not only electrically connected to the nth row (nth line) gate line, but also can be electrically connected to other gate lines except the nth row gate line, so that the gate lines of different rows provide it with scanning signals with different timings, avoiding the arrangement of other types of signal lines in areas outside the display area (the pixel driving circuit is arranged in the display area) to provide driving signals to the pixel driving circuit, thereby reducing the number of required external signal lines, significantly reducing the types and number of shift registers external to the pixel driving circuit (or, when the external signal is provided by a driver chip IC, the number of ICs used external to the pixel driving circuit can be significantly reduced), greatly reducing the power consumption of the display device, and facilitating the preparation of a display device with a narrow frame.

[0118] In at least one embodiment of the present application, the control signal line includes a first scan signal line or a second scan signal line.

[0119] In an exemplary embodiment, as shown in FIG. 1 , FIG. 4 , and FIG. 5 , the control signal line includes a second scan signal line VR line.

[0120] The second scanning signal VR can be generated by a driver chip and transmitted to the pixel driving circuits of each row, or can be generated by a shift register (EOA) and transmitted to the pixel driving circuits of each row.

[0121] In an exemplary embodiment, as shown in FIG. 7 and FIG. 9 , the control signal line includes a first scan signal line (eg, a gate line in the (n-4)th row).

[0122] In at least one embodiment of the present application, pulse widths of the scan signals loaded on the first scan signal line, the third scan signal line, the fourth scan signal line, and the fifth scan signal line are the same.

[0123] It should be noted that the pulse widths of the first scanning signal VG(n-4), the third scanning signal VG(n), the fourth scanning signal VG(n-2) and the fifth scanning signal VG(n+2) drawn in Figures 2, 3, 6 and 8 are only schematic illustrations and do not represent actual pulse widths. In actual applications, the pulse widths of the scanning signals on the first scanning signal VG(n-4), the third scanning signal VG(n), the fourth scanning signal VG(n-2) and the fifth scanning signal VG(n+2) are the same.

[0124] 21 , 22 , 23 or 24 , the first scan signal VG(n-4), the third scan signal VG(n), the fourth scan signal VG(n-2) and the fifth scan signal VG(n+2) are all generated by a shift register (GOA).

[0125] In at least one embodiment of the present application, as shown in Figures 21, 22, 23 or 24, the first scan signal line is the gate line of the n-4th row, the gate line of the n-4th row is electrically connected to the n-4th stage shift register GOA(n-4), and is used to transmit the VG(n-4) signal; the third scan signal line is the gate line of the nth row, the gate line of the nth row is electrically connected to the n-4th stage shift register GOA(n), and is used to transmit the VG(n) signal; the fourth scan signal line is the gate line of the n-2th row, the gate line of the n-2th row is electrically connected to the n-2th stage shift register GOA(n-2), and is used to transmit the VG(n-2) signal; the fifth scan signal line is the gate line of the n+2th row, the gate line of the n+2th row is electrically connected to the n+2th stage shift register GOA(n+2), and is used to transmit the VG(n+2) signal; wherein n is greater than 4;

[0126] The gate line of the nth row is electrically connected to the pixel driving circuit of the nth row (in Figure 21, Figure 22, Figure 23 or Figure 24, Pixel(n) is used to represent the sub-pixel of the nth row), and the second scanning signal line VR line of the nth row is electrically connected to the pixel driving circuit of the nth row.

[0127] In at least one embodiment of the present application, the pixel driving circuit in the mth row is a dummy pixel driving circuit (a pixel driving circuit set in the Dummy pixel row), m is a positive integer, m is greater than or equal to 1 and less than or equal to 4, and is equal to n+1 or n+2; the pixel driving circuit in the mth row is electrically connected to the shift register in the mth row.

[0128] It should be noted that the Dummy pixel row (virtual pixel row) can transmit scanning signals but does not actually display light.

[0129] In an embodiment of the present application, for the pixel driving circuit in the nth row, when n=5, the first scanning signal line is the gate line in the 1st row, the third scanning signal line is the gate line in the 5th row, and the fourth scanning signal line is the gate line in the 3rd row; the fifth scanning signal line is the gate line in the 7th row; in order to enable the pixel driving circuit in the 5th row to be driven normally, it is necessary to set four rows of dummy pixel driving rows and four rows of shift registers before the pixel driving circuit in this row to normally provide scanning signals to the pixel driving circuits after the 5th row. In addition, for the pixel driving circuit in the last row (i.e., the nth row) actually used for display, since the fifth scanning signal provided by the gate line in the n+2th row is required, at least two rows of dummy pixel driving rows and at least two rows of shift registers are required after the nth row of pixels to provide scanning signals to the pixel driving circuits before the nth row.

[0130] In an embodiment of the present application, the pixel driving circuit can utilize gate driving signals provided by gate lines of different rows, so that the number of external signal lines required by the pixel driving circuit is smaller, significantly reducing the types and number of shift registers external to the pixel driving circuit (or, when the external signal is provided by a driver chip IC, the number of ICs used external to the pixel driving circuit can be significantly reduced), greatly reducing the power consumption of the display device, and facilitating the preparation of a display device with a narrow bezel.

[0131] In at least one embodiment of the present application, the first reset signal line includes a reference signal line Ref line, the second reset signal line includes an initialization signal line Vinit line, and the absolute value of the difference between the voltage Vref of the reference signal transmitted by the reference signal line Ref line and the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line is greater than the threshold voltage (Vth) of the driving transistor.

[0132] In an embodiment of the present application, in the signal reset stage, the reset sub-circuit 1 resets the voltage of the first node NS under the control of the first scan signal VG(n-4), and also resets the voltage of the second node NG under the control of the control signal (for example, the first scan signal VG(n-4) or the second scan signal VR). By setting the absolute value of the difference between the voltage Vref of the reference signal transmitted by the reference signal line Ref line and the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line to be greater than the threshold voltage (Vth) of the driving transistor, it is possible to ensure that the driving transistor MD is in the on state, as shown in Figures 1, 4, 5, 7 or 9. It is also possible to pre-charge the electrodes electrically connected to the first capacitor C1 and the second capacitor C2 in the storage sub-circuit 6 to prevent the threshold compensation from being unable to be completed due to the large capacitance to be charged in the compensation stage of the pixel driving circuit, thereby improving the subsequent compensation effect of the threshold voltage of the driving transistor in the compensation stage.

[0133] In an exemplary embodiment, when the driving transistor MD is an N-type transistor, the voltage Vref of the reference signal transmitted by the reference signal line Ref line is greater than the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line.

[0134] In an exemplary embodiment, when the driving transistor MD is a P-type transistor, the voltage Vref of the reference signal transmitted by the reference signal line Ref line is lower than the voltage Vinit of the initialization signal transmitted by the initialization signal line Vinit line.

[0135] In an exemplary embodiment, the reference signal transmitted by the reference signal line Ref line is a signal with a constant voltage, and the initialization signal transmitted by the initialization signal line Vinit line is another signal with a constant voltage.

[0136] In at least one embodiment of the present application, the first reset signal line includes a first power line VDD line (i.e., the first electrode of the second transistor M2 is electrically connected to the first power line VDD line), and the second reset signal line includes a second power line VSS line (the first electrode of the fourth transistor M4 is electrically connected to the second power line VSS line).

[0137] In an embodiment of the present application, by setting the first reset signal line to include a first power line VDD line and the second reset signal line to include a second power line VSS line, the number of external signal lines of the pixel driving circuit can be further reduced, the circuit and wiring design in the display device can be simplified, the design space can be saved, the difficulty of the manufacturing process can be reduced, and it is conducive to application in display devices with narrow bezels.

[0138] In at least one embodiment of the present application, as shown in Figure 1 or Figure 7, the data writing sub-circuit 2 includes a first transistor M1, the gate of the first transistor M1 is electrically connected to the third scanning signal line (the n-th row gate line), the first electrode of the first transistor M1 is electrically connected to the data line Data, the second electrode of the first transistor M1 is electrically connected to the gate of the driving transistor MD through the second node NG, and the first transistor M1 is used to respond to the third scanning signal VG(n) and transmit and write the data signal to the gate of the driving transistor MD.

[0139] In at least one embodiment of the present application, a switching transistor SW is further arranged in series between the data line Data line and the first transistor M1 of the pixel driving circuit (the black rectangle in Figure 25 or Figure 26 represents the pixel driving circuit), and the switching transistor SW is configured to write the data signal Vdata into the data line Data line before the first transistor M1 is turned on.

[0140] For example, as shown in FIG25 , in order to improve the aperture ratio, the switching transistor SW is arranged at the junction of the display area and the binding area of ​​the display device, wherein a Source driver IC is arranged in the binding area, and all data lines Data are electrically connected to the Source driver IC through the switching transistor SW. The Source driver IC is used to provide data signals to the display area of ​​the display device.

[0141] For example, as shown in FIG26 , for a column of pixel driving circuits, a switching transistor SW can be shared between the first transistors M1 of multiple pixel driving circuits and the data line Data. Taking the connection structure shown in FIG26 as an example, four pixel driving circuits can be electrically connected to the data line Data through the same switching transistor SW. Before the first transistors M1 of each of the four pixel driving circuits are turned on, the switching transistor SW can be controlled so that the data signal Vdata is pre-written to the position of the first electrode (or second electrode) of the switching transistor SW, thereby shortening the transmission path and transmission time of the data signal.

[0142] It should be noted that, here, there is no limitation on the number of switch transistors SW electrically connected to the same data line Data, and the number can be specifically designed according to the design space and the transmission time requirement of the data signal.

[0143] As shown in FIG. 26 , when the same data line Data is connected to a plurality of switching transistors SW, at least some of the switching transistors SW may be disposed in the display area AA, for example, in a non-opening area of ​​the display area AA.

[0144] The opening area refers to the area in the display area AA that actually displays light; the non-opening area refers to the area in the display area AA other than the opening area, which is usually used for wiring and setting circuit structures.

[0145] In an embodiment of the present application, a switching transistor SW is further provided in series between the data line Data line and the first transistor M1 of the pixel driving circuit (the black rectangle in FIG18 represents the pixel driving circuit). Therefore, before the first transistor M1 is turned on, the data signal Vdata can be written into the data line Data line in advance by turning on the switching transistor SW. After the first transistor M1 is turned on, the data signal Vdata can be quickly written into the gate of the driving transistor MD, thereby shortening the time for the data signal Vdata to be transmitted to the pixel driving circuit, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0146] In at least one embodiment of the present application, as shown in FIG4 , when the control signal line includes a second scan signal line (eg, a VR line), the data writing sub-circuit 2 includes a first transistor M1 and a ninth transistor M9 ;

[0147] The gate of the first transistor M1 is electrically connected to the third scanning signal line (the gate line of the nth row), the first electrode of the first transistor M1 is electrically connected to the data line Data line, the second electrode of the first transistor M1 is electrically connected to the first electrode of the ninth transistor M9, the gate of the ninth transistor M9 is electrically connected to the second scanning signal line VR line, and the second electrode of the ninth transistor M9 is electrically connected to the second node NG (the second electrode of the ninth transistor M9 is electrically connected to the gate of the driving transistor MD through the second node NG).

[0148] In an exemplary embodiment, the first transistor M1 and the ninth transistor M9 are of opposite types. For example, the first transistor M1 is an N-type transistor and the ninth transistor M9 is a P-type transistor. For another example, the first transistor M1 is a P-type transistor and the ninth transistor M9 is an N-type transistor. The timing diagrams provided in the embodiments of the present application (such as the timing diagram shown in FIG3 ) and the subsequent description are all described based on the example that the first transistor M1 is an N-type transistor and the ninth transistor M9 is a P-type transistor.

[0149] In an exemplary embodiment, the first transistor M1 and the ninth transistor M9 are not turned on at the same time in a partial time period, and the first transistor M1 and the ninth transistor M9 are turned on at the same time in a partial time period.

[0150] In at least one embodiment of the present application, as shown in FIG. 3 , the third scan signal VG(n) and the second scan signal VR overlap in time.

[0151] 3 and 4 , in a time period in which the third scan signal VG(n) and the second scan signal VR overlap, the first transistor M1 is turned on and the ninth transistor M9 is turned off.

[0152] In an exemplary embodiment, the first transistor M1 can be controlled to be turned on and the ninth transistor M9 can be turned off, so that the data signal Vdata transmitted in the data line Data is written in advance to the position between the first transistor M1 and the ninth transistor M9 as shown in Figure 4; when the first transistor M1 and the ninth transistor M9 are turned on at the same time, the data signal Vdata can be quickly written into the gate of the driving transistor MD through the ninth transistor M9, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0153] In at least one embodiment of the present application, as shown in FIG5 , when the control signal line includes the second scanning signal line VR line, the data writing sub-circuit 2 includes a first transistor M1 , a ninth transistor M9 , and a tenth transistor M10 ;

[0154] The gate of the first transistor M1 is electrically connected to the third scan signal line (the nth row gate line), the first electrode of the first transistor M1 is electrically connected to the data line Data line, the second electrode of the first transistor M1 is electrically connected to the first electrode of the ninth transistor M9, the gate of the ninth transistor M9 is electrically connected to the second scan signal line VR line, the second electrode of the ninth transistor M9 is electrically connected to the second node NG, the first electrode of the tenth transistor M10 is electrically connected to the data line Data line, the second electrode of the tenth transistor M10 is electrically connected to the first electrode of the ninth transistor M9, and the gate of the tenth transistor M10 is electrically connected to the sixth scan signal line (the n-1th row gate line).

[0155] In an exemplary embodiment, the first transistor M1 and the ninth transistor M9 are of opposite types, and the first transistor M1 and the tenth transistor M10 are of the same type.

[0156] For example, the first transistor M1 is an N-type transistor, the ninth transistor M9 is a P-type transistor, and the tenth transistor M10 is an N-type transistor; for another example, the first transistor M1 is a P-type transistor, the ninth transistor M9 is an N-type transistor, and the tenth transistor M10 is a P-type transistor. The timing diagrams provided in the embodiments of the present application (such as the timing diagram shown in FIG6 ) and the subsequent descriptions are all based on the example that the first transistor M1 is an N-type transistor, the ninth transistor M9 is a P-type transistor, and the tenth transistor M10 is an N-type transistor.

[0157] In an exemplary embodiment, the first transistor M1 and the ninth transistor M9 are turned on at the same time, and the tenth transistor M10 and the ninth transistor M9 are not turned on at the same time.

[0158] In at least one embodiment of the present application, as shown in FIG. 6 , the sixth scan signal VG(n−1) and the second scan signal VR have a temporal overlap.

[0159] 5 and 6 , during the time period when the sixth scan signal VG(n−1) and the second scan signal VR overlap, the tenth transistor M10 is turned on and the ninth transistor M9 is turned off.

[0160] In an exemplary embodiment, the tenth transistor M10 can be controlled to be turned on and the ninth transistor M9 can be turned off, so that the data signal Vdata transmitted in the data line Data is written in advance to the position between the tenth transistor M10 and the ninth transistor M9 as shown in Figure 5; when the first transistor M1 and the ninth transistor M9 are turned on at the same time, the data signal Vdata can be quickly written into the gate of the driving transistor MD through the ninth transistor M9, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0161] In at least one embodiment of the present application, as shown in FIG9 , when the control signal line includes the first scanning signal line VG(n−4), the data writing sub-circuit 2 includes a first transistor M1 , a ninth transistor M9 , and a tenth transistor M10 ;

[0162] The gate of the first transistor M1 is electrically connected to the third scan signal line VG(n), the first electrode of the first transistor M1 is electrically connected to the data line Data line, the second electrode of the first transistor M1 is electrically connected to the first electrode of the ninth transistor M9, the gate of the ninth transistor M9 is electrically connected to the sixth scan signal line (the gate line of the n-1th row), the second electrode of the ninth transistor M9 is electrically connected to the second node NG, the gate of the tenth transistor M10 is electrically connected to the sixth scan signal line (the gate line of the n-1th row), the first electrode of the tenth transistor M10 is electrically connected to the data line Data line, and the second electrode of the tenth transistor M10 is electrically connected to the first electrode of the ninth transistor M9.

[0163] In an exemplary embodiment, the first transistor M1 and the ninth transistor M9 are of opposite types, and the first transistor M1 and the tenth transistor M10 are of the same type.

[0164] The timing diagrams provided in the embodiments of the present application (such as the timing diagram shown in FIG10 ) and the subsequent descriptions are all described by taking the first transistor M1 as an N-type transistor, the ninth transistor M9 as a P-type transistor, and the tenth transistor M10 as an N-type transistor as an example.

[0165] As shown in Figures 9 and 10, when the tenth transistor M10 is turned on, the ninth transistor M9 is turned off, so that the data signal Vdata transmitted in the data line Data is written in advance to the position between the tenth transistor M10 and the ninth transistor M9 as shown in Figure 9; when the first transistor M1 and the ninth transistor M9 are turned on at the same time, the data signal Vdata can be quickly written into the gate of the driving transistor MD through the ninth transistor M9, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0166] In at least one embodiment of the present application, the sixth scanning signal line is the gate line of the n-1th row. As shown in Figure 10, the pulse width of the scanning signal loaded on the sixth scanning signal line is the same as the pulse width of the scanning signal loaded on the first scanning signal line (the gate line of the n-4th row).

[0167] It should be noted that the pulse widths of the first scanning signal VG(n-4), the third scanning signal VG(n), the fourth scanning signal VG(n-2), the fifth scanning signal VG(n+2) and the sixth scanning signal VG(n-1) drawn in Figure 10 are only schematic illustrations and do not represent actual pulse widths. In actual applications, the pulse widths of the scanning signals on the first scanning signal VG(n-4), the third scanning signal VG(n), the fourth scanning signal VG(n-2), the fifth scanning signal VG(n+2) and the sixth scanning signal VG(n-1) are the same.

[0168] 21 , 22 , 23 or 24 , the first scan signal VG(n-4), the third scan signal VG(n), the fourth scan signal VG(n-2), the fifth scan signal VG(n+2) and the sixth scan signal VG(n-1) are all generated by a shift register (GOA).

[0169] In at least one embodiment of the present application, as shown in FIG1 , FIG3 , FIG4 and FIG5 , when the control signal line includes the second scan signal line VR line, the reset sub-circuit 1 includes the second transistor M2 and the fourth transistor M4.

[0170] The gate of the second transistor M2 is electrically connected to the second scan signal line VR line, the first electrode of the second transistor M2 is electrically connected to the second reset signal line (for example, the Vref line), the second electrode of the second transistor M2 is electrically connected to the second node NG, the gate of the fourth transistor M4 is electrically connected to the first scan signal line (for example, the n-4th gate line), the first electrode of the fourth transistor M4 is electrically connected to the first reset signal line (for example, the Vinit line), and the second electrode of the fourth transistor M4 is electrically connected to the first node NS.

[0171] In an exemplary embodiment, as shown in Figures 1, 3, 4 and 5, the second transistor M2 is controlled by the second scan signal VR transmitted by the second scan signal line (e.g., VR line), and in response to the second scan signal VR, the voltage of the second node NG electrically connected to the gate of the driving transistor MD is reset by a reset signal (e.g., reference signal Vref) transmitted by the second reset signal line (e.g., Ref line).

[0172] In an exemplary embodiment, the fourth transistor M4 is controlled by a first scan signal (e.g., a VG(n-4) signal) transmitted by a first scan signal line (e.g., an n-4th gate line), and responds to the first scan signal to reset the first node NS electrically connected to the second electrode of the driving transistor MD via a first reset signal (e.g., a Vinit signal) transmitted by a first reset signal line (e.g., a Vinit line).

[0173] In at least one embodiment of the present application, as shown in FIG7 and FIG9 , when the control signal line includes the first scan signal line (for example, the n-4th gate line), the reset sub-circuit 1 includes a second transistor M2, a fourth transistor M4, and an eighth transistor M8.

[0174] The gate of the second transistor M2 and the gate of the fourth transistor M4 are both electrically connected to the first scan signal line (for example, the n-4th gate line), the first electrode of the second transistor M2 is electrically connected to the second reset signal line (for example, the Vref line), the second electrode of the second transistor M2 is electrically connected to the second node NG, the first electrode of the fourth transistor M4 is electrically connected to the first reset signal line (for example, the Vinit line), the second electrode of the fourth transistor M4 is electrically connected to the first node NS, the gate of the eighth transistor M8 is electrically connected to the fourth scan signal line (for example, the n-2th gate line), the first electrode of the eighth transistor M8 is electrically connected to the second reset signal line (for example, the Vref line), and the second electrode of the eighth transistor M8 is electrically connected to the second node NG.

[0175] In an exemplary embodiment, as shown in Figures 7 and 9, the above-mentioned second transistor M2 is controlled by the first scan signal VG(n-4) transmitted by the first scan signal line (e.g., the n-4th gate line), and responds to the first scan signal VG(n-4) to reset the voltage of the second node NG electrically connected to the gate of the driving transistor MD through the reset signal (e.g., the reference signal Vref) transmitted by the second reset signal line (e.g., the Ref line).

[0176] In an exemplary embodiment, the fourth transistor M4 is controlled by a first scan signal VG(n-4) transmitted by a first scan signal line (e.g., the n-4th gate line), and responds to the first scan signal to reset the first node NS electrically connected to the second electrode of the driving transistor MD via a first reset signal (e.g., Vinit signal) transmitted by a first reset signal line (e.g., Vinit line).

[0177] In an embodiment of the present application, before refreshing (rewriting new signals) each pixel driving circuit in a row of sub-pixels, the voltage of key nodes in the pixel driving circuit (for example, the first node NS electrically connected to the source of the driving transistor MD and the second node NG electrically connected to the gate of the driving transistor MD) can be reset through the second transistor M2 and the fourth transistor M4 to eliminate the residual signal in the previous frame of the picture and avoid the appearance of afterimages in the next frame of the display picture. When the pixel driving circuit is applied to a display device, the display effect of the display device can be improved.

[0178] In at least one embodiment of the present application, as shown in FIG. 1 , FIG. 4 , FIG. 5 , FIG. 7 and FIG. 9 , the light emitting control subcircuit 4 includes a third transistor M3 and a fifth transistor M5 .

[0179] The gate of the third transistor M3 and the gate of the fifth transistor M5 are both connected to the light-emitting control signal line EM(n), the first electrode of the third transistor M3 is electrically connected to the first power line VDD, and the second electrode of the third transistor M3 is electrically connected to the third node A; the first electrode of the fifth transistor M5 is electrically connected to the first node NS, and the second electrode of the fifth transistor M5 is electrically connected to the anode N1.

[0180] In an exemplary embodiment, the third transistor M3 is used to transmit the first power signal VDD of the first power line VDD line to the first electrode (for example, the source) of the driving transistor MD through the third node A under the control of the light-emitting control signal EM(n) transmitted by the light-emitting control signal line EM(n); the fifth transistor M5 is used to transmit the driving current generated by the driving transistor MD to the anode N1 of the light-emitting device 8 under the control of the light-emitting control signal EM(n) transmitted by the light-emitting control signal line EM(n).

[0181] In at least one embodiment of the present application, as shown in Figures 1, 4, 5, 7 and 9, the compensation sub-circuit 5 includes a seventh transistor M7, a gate of the seventh transistor M7 is electrically connected to the fourth scan signal line (for example, the n-2th gate line), a first electrode of the seventh transistor M7 is electrically connected to the first power line VDD line, and a second electrode of the seventh transistor M7 is electrically connected to the third node A.

[0182] With the cooperation of the eighth transistor M8, that is, when the seventh transistor M7 and the eighth transistor M8 are turned on at the same time, the first capacitor C1 can keep the potential of the second node NG still at Vref, the driving transistor MD remains in the on state, and a path is formed between the first power line VDD line and the first node NS. The first power line VDD line charges the first node NS. When the potential of the first node NS becomes Vref-Vth, the driving transistor MD is turned off. Since this process changes slowly and the potential of the second node NG is always pulled by Vref, the potential of the second node NG remains at Vref. At this time, Vgs=Vref-(Vref-Vth)=Vth, thereby completing the extraction of the threshold voltage Vth of the driving transistor MD.

[0183] In at least one embodiment of the present application, as shown in FIG1 , FIG4 , FIG5 , FIG7 and FIG9 , the storage sub-circuit 6 includes a first capacitor C1 and a second capacitor C2 ;

[0184] The first electrode of the first capacitor C1 is electrically connected to the second node NG, and the second electrode of the first capacitor C1 is electrically connected to the first node NS; the first electrode of the second capacitor C2 is electrically connected to the first power line VDD line, and the second electrode of the second capacitor C2 is electrically connected to the second electrode of the first capacitor C1 through the first node NS.

[0185] There is no limitation on the capacitance values ​​of the first capacitor C1 and the second capacitor C2 .

[0186] In some embodiments, the driving current of the driving transistor MD may be adjusted by adjusting the capacitance ratio of the first capacitor C1 to the second capacitor C2 .

[0187] In other embodiments, in order to have a smaller impact on the voltage of the gate of the driving transistor MD when the voltage value of the data signal Vdata changes greatly, thereby having a smaller impact on the driving current of the driving transistor MD (that is, the change amplitude of the driving current of the driving transistor MD is smaller), the capacitance value of the first capacitor C1 can be set to be greater than the capacitance value of the second capacitor C2.

[0188] In an embodiment of the present application, the voltage of the second node NG can be stabilized by setting the first capacitor C1, and the voltage of the first node NS can be stabilized by setting the second capacitor C2. By adjusting the size ratio of the capacitance values ​​of the first capacitor C1 and the second capacitor C2, a data signal Vdata with a large change can be brought about a driving current with a small change, thereby achieving more precise control of the driving current, achieving more precise adjustment and display of the grayscale of the display device, and improving the display effect of the display device.

[0189] In at least one embodiment of the present application, as shown in Figures 1, 4, 5, 7 and 9, the reset sub-circuit 7 includes a sixth transistor M6, a gate of the sixth transistor M6 is electrically connected to the fifth scan signal line (for example, the n+2th gate line), a first electrode of the sixth transistor M6 is electrically connected to the anode N1, and a second electrode of the sixth transistor M6 is electrically connected to the second power line VSS line and the cathode of the light-emitting device 8, respectively.

[0190] In an exemplary embodiment, the sixth transistor M6 is used to transfer the second power signal VSS transmitted by the second power line VSS line to the anode of the light-emitting device 8 under the control of the fifth scan signal transmitted by the fifth scan signal line (for example, the n+2th gate line), thereby resetting the anode of the light-emitting device 8 through the second power line VSS line before the light-emitting device 8 emits light.

[0191] Exemplarily, the second power line VSS line may be electrically connected to the ground terminal GND.

[0192] In at least one embodiment of the present application, when the data writing sub-circuit 2 includes the ninth transistor M9 , the ninth transistor M9 and the other transistors are of opposite types.

[0193] In at least one embodiment of the present application, as shown in FIG. 1 , FIG. 4 , FIG. 5 , FIG. 7 and FIG. 9 , the ninth transistor is a P-type transistor, and the other transistors are all P-type transistors.

[0194] In at least one embodiment of the present application, when the driving transistor is an N-type transistor, the voltage Vref of the reference signal is greater than the voltage Vinit of the initialization signal; the absolute value range of the difference between the voltage Vref of the reference signal and the voltage Vinit of the initialization signal is 2V to 4V.

[0195] Exemplarily, the absolute value of the difference between the voltage Vref of the reference signal and the voltage Vinit of the initialization signal is 2.3V, 2.5V, 2.8V, 3V, 3.3V, 3.5V or 3.8V.

[0196] In an embodiment of the present application, in the signal reset stage, by setting the absolute value range of the difference between the voltage Vref of the reference signal and the voltage Vinit of the initialization signal to 2V~4V, it is possible to ensure that the driving transistor MD is in the on state, and it is also possible to pre-charge the electrodes electrically connected to the first capacitor C1 and the second capacitor C2 in the storage sub-circuit 6, so as to prevent the threshold compensation from being unable to be completed due to the large capacitance to be charged during the compensation stage of the pixel driving circuit, thereby improving the subsequent compensation effect on the threshold voltage of the driving transistor in the compensation stage.

[0197] In at least one embodiment of the present application, the capacitance of the second capacitor C2 is smaller than the capacitance of the first capacitor C1 .

[0198] In the embodiment of the present application, by setting the capacitance value of the second capacitor C2 to be smaller than the capacitance value of the first capacitor C1, it is possible to achieve a small change in the driving current caused by a large change in the data signal Vdata. When using a low-resolution Source IC in the prior art, more precise control of the driving current can be achieved, and more precise adjustment and display of the grayscale displayed by the display device can be achieved, thereby improving the display effect of the display device.

[0199] In at least one embodiment of the present application, for the pixel driving circuit shown in Figure 1, the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be set to be dual-gate transistors; the two gates of the same transistor are electrically connected together; or the first transistor M1, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be metal oxide transistors.

[0200] In at least one embodiment of the present application, for the pixel driving circuit shown in Figures 4 and 5, the ninth transistor M9, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be set to be dual-gate transistors; the two gates of the same transistor are electrically connected together; or, the ninth transistor M9, the second transistor M2, the fourth transistor M4, and the fifth transistor M5 can be set to be metal oxide transistors.

[0201] In at least one embodiment of the present application, for the pixel driving circuit shown in Figure 7, the first transistor M1, the second transistor M2, the eighth transistor M8, the fourth transistor M4 and the fifth transistor M5 can be set to be dual-gate transistors; the two gates of the same transistor are electrically connected together; or, the first transistor M1, the second transistor M2, the eighth transistor M8, the fourth transistor M4 and the fifth transistor M5 can be set to be metal oxide transistors.

[0202] In at least one embodiment of the present application, for the pixel driving circuit shown in Figure 9, the ninth transistor M9, the second transistor M2, the eighth transistor M8, the fourth transistor M4, and the fifth transistor M5 can be set to be dual-gate transistors; the two gates of the same transistor are electrically connected together; or, the ninth transistor M9, the second transistor M2, the eighth transistor M8, the fourth transistor M4, and the fifth transistor M5 can be metal oxide transistors.

[0203] In the embodiments of the present application, during the operation of the pixel circuit, leakage of transistors and light-emitting devices is inevitable, thereby affecting the compensation and light-emitting effects. Therefore, the transistors around the key nodes (such as transistors around the NS and NG nodes) can be designed with a dual gate, or set as metal oxide transistors, which can significantly reduce the leakage of transistors around the key nodes, thereby improving the display effect of the display device.

[0204] In at least one embodiment of the present application, the driving transistor MD is a dual-gate transistor, and one gate of the driving transistor MD is electrically connected to the second node NG, and the other gate of the driving transistor MD is electrically connected to the signal input terminal with a constant voltage, and the constant voltage is less than the threshold voltage of the driving transistor MD.

[0205] In an embodiment of the present application, one gate of the driving transistor MD is electrically connected to the second node NG, for controlling the on and off states of the driving transistor MD; the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, for stabilizing the threshold voltage of the driving transistor MD and improving the driving stability of the driving transistor MD, wherein the voltage provided by the signal input terminal with a constant voltage cannot interfere with the on and off states of the driving transistor MD, and therefore the absolute value of the constant voltage is set to be smaller than the absolute value of the threshold voltage of the driving transistor MD.

[0206] In at least one embodiment of the present application, the light-emitting device 8 includes an organic light-emitting diode (OLED), a Micro LED (Micro light Emitting Diode) or a Mini LED (Mini light Emitting Diode, sub-millimeter light-emitting diode).

[0207] An embodiment of the present application provides a display device, which includes a pixel driving circuit as described in any one of the above.

[0208] The above-mentioned display device can be an organic light-emitting diode (OLED) display device, a Micro LED (Micro light Emitting Diode) display device or a Mini LED (Mini light Emitting Diode) display device.

[0209] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0210] The display device provided by the embodiment of the present application includes the pixel driving circuit described above. Due to the setting of transistors, capacitors and timing signals in the pixel driving circuit, the anode of the light-emitting device 8 and the second electrode (e.g., source) of the driving transistor MD can be separated. Therefore, before the light-emitting stage, the light-emitting device 8 itself (threshold voltage drift, self-capacitance coupling in the circuit) does not affect the potential change of the source level of the driving transistor MD. At the same time, the second capacitor C2 is set to ensure the stability of the NS node potential and the compensation effect. In addition, by setting the size of the capacitance ratio of C2 and C1, the pixel driving circuit can achieve a richer grayscale display when driving Micro LED and Mini LED type light-emitting devices; finally, the pixel driving circuit can use the gate drive signal provided by the gate lines of different rows, so that the number of external signal lines required is small, significantly reducing the type and number of shift registers external to the pixel driving circuit (or, when the external signal is provided by the driver chip IC, significantly reducing the number of ICs used external to the pixel driving circuit), greatly reducing the power consumption of the display device, and facilitating the preparation of a narrow-frame display device.

[0211] Exemplarily, in combination with Figures 1 and 21, the pixel driving circuit can utilize four gate lines in different rows (the nth row gate line, the n-2th row gate line, the n-4th row gate line and the n+2th row gate line), thereby reducing the number of external signal lines to 6 (including the Data line, the VR line, the Vref line, the Vinit line, the VDD line and the VSS line). When the VDD line is used instead of the Vref line and the VSS line is used instead of the Vinit line, the number of external signal lines is reduced to 4.

[0212] Exemplarily, the pixel driving circuits shown in FIG. 4 and FIG. 1 can utilize the same gate lines and external signal lines.

[0213] Exemplarily, in combination with Figures 5 and 23, the pixel driving circuit can utilize five gate lines of different rows (the nth row gate line, the n-1th row gate line, the n-2th row gate line, the n-4th row gate line and the n+2th row gate line), thereby reducing the number of external signal lines to 6 (including the Data line, the VR line, the Vref line, the Vinit line, the VDD line and the VSS line). When the VDD line is used instead of the Vref line and the VSS line is used instead of the Vinit line, the number of external signal lines is reduced to 4.

[0214] Exemplarily, in combination with Figures 7 and 22, the pixel driving circuit can utilize four gate lines in different rows (the nth row gate line, the n-2th row gate line, the n-4th row gate line and the n+2th row gate line), thereby reducing the number of external signal lines to 5 (including the Data line, the Vref line, the Vinit line, the VDD line and the VSS line). When the VDD line is used instead of the Vref line and the VSS line is used instead of the Vinit line, the number of external signal lines is reduced to 3.

[0215] Exemplarily, in combination with Figures 9 and 24, the pixel driving circuit can utilize five gate lines of different rows (the nth row gate line, the n-1th row gate line, the n-2th row gate line, the n-4th row gate line and the n+2th row gate line), thereby reducing the number of external signal lines to 5 (including the Data line, the Vref line, the Vinit line, the VDD line and the VSS line). When the VDD line is used instead of the Vref line and the VSS line is used instead of the Vinit line, the number of external signal lines is reduced to 3.

[0216] In this way, signal crosstalk during the operation of the pixel driving circuit is reduced and the operating reliability is optimized; at the same time, the reduction in the number of external signals also saves power consumption and wiring space, making the pixel driving circuit more suitable for display devices with narrow bezels.

[0217] An embodiment of the present application provides a driving method for driving a pixel driving circuit as described above, the method comprising:

[0218] S801. In a first stage, such as stage T1 shown in FIG. 2 , FIG. 3 , FIG. 6 , or FIG. 8 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a high-level first scan signal VG(n−4) is input to the first scan signal line, a low-level fourth scan signal VG(n−2) is input to the fourth scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, and a low-level fifth scan signal VG(n+2) is input to the fifth scan signal line.

[0219] S802. In the second stage, for example, stage T2 shown in FIG. 2 , FIG. 3 , FIG. 6 , or FIG. 8 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scan signal VG(n−4) is input to the first scan signal line, a high-level fourth scan signal VG(n−2) is input to the fourth scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, and a low-level fifth scan signal VG(n+2) is input to the fifth scan signal line.

[0220] S803. In the third stage, for example, stage T3 shown in FIG. 2 , FIG. 3 , FIG. 6 or FIG. 8 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a low-level fourth scan signal VG(n-2) is input to the fourth scan signal line, a high-level third scan signal VG(n) is input to the third scan signal line, and a low-level fifth scan signal VG(n+2) is input to the fifth scan signal line.

[0221] S804. In the fourth stage, for example, stage T4 shown in FIG. 2 , FIG. 3 , FIG. 6 or FIG. 8 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scan signal VG(n−4) is input to the first scan signal line, a low-level fourth scan signal VG(n−2) is input to the fourth scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, and a high-level fifth scan signal VG(n+2) is input to the fifth scan signal line.

[0222] S805. In the fifth stage, for example, the T5 stage shown in FIG. 2 , FIG. 3 , FIG. 6 or FIG. 8 , a high-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scanning signal VG(n-4) is input to the first scanning signal line, a low-level fourth scanning signal VG(n-2) is input to the fourth scanning signal line, a low-level third scanning signal VG(n) is input to the third scanning signal line, and a low-level fifth scanning signal VG(n+2) is input to the fifth scanning signal line.

[0223] The driving method of the pixel driving circuit provided in the embodiment of the present application can improve the threshold voltage drift problem of the driving transistor during the driving process of the circuit. Since the anode of the light-emitting device 8 and the second electrode (e.g., source electrode) of the driving transistor MD in the pixel driving circuit are separated (not directly electrically connected), the light-emitting device 8 itself (threshold voltage drift, coupling of its own capacitance in the circuit) will not affect the potential change of the source level of the driving transistor MD before the light-emitting stage. At the same time, a second capacitor C2 is provided to ensure the stability of the NS node potential and the compensation effect. In addition, by setting the size of the capacitance ratio of C2 and C1, the pixel driving circuit can achieve a richer grayscale display when driving Micro LED and Mini LED type light-emitting devices. Finally, the pixel driving circuit can use the gate drive signals provided by the gate lines of different rows, so that the number of external signal lines required is small, significantly reducing the types and number of shift registers external to the pixel driving circuit, which is conducive to the preparation of narrow-frame display devices.

[0224] Taking the circuit diagram shown in FIG1 as an example, and taking all transistors as N-type transistors as an example, the driving principle and driving process of the driving circuit are specifically explained; FIG2 provides the timing corresponding to the circuit diagram in FIG1; FIG11 to FIG15 respectively provide the circuit states of the circuit diagram in FIG1 at different stages of the timing shown in FIG2. In FIG11 to FIG15, the transistor cut-off is marked with “×”.

[0225] In the first stage (reset stage), for example, stage T1 shown in FIG2 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a high-level first scanning signal VG(n-4) is input to the first scanning signal line, a low-level fourth scanning signal VG(n-2) is input to the fourth scanning signal line, a low-level third scanning signal VG(n) is input to the third scanning signal line, a low-level fifth scanning signal VG(n+2) is input to the fifth scanning signal line, and a high-level second scanning signal VR is input to the second scanning signal line;

[0226] At this time, in combination with Figures 2 and 11, the second transistor M2 and the fourth transistor M4 are turned on, the potential of the first node NS is Vinit, and the potential of the second node NG is Vref. Since Vref and Vinit are both high-level potentials with constant voltage, the driving transistor MD is turned on. In this way, the potential of the first node NS and the second node NG is reset. In addition, the electrodes (plates) connected to the first capacitor C1 and the second capacitor C2 are pre-charged to prevent the inability to complete the extraction and compensation of the threshold voltage in the subsequent threshold voltage extraction stage due to the large capacitance to be charged.

[0227] In the second stage (threshold voltage extraction stage), for example, stage T2 shown in FIG2 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scanning signal VG(n-4) is input to the first scanning signal line, a high-level fourth scanning signal VG(n-2) is input to the fourth scanning signal line, a low-level third scanning signal VG(n) is input to the third scanning signal line, a low-level fifth scanning signal VG(n+2) is input to the fifth scanning signal line, and a high-level second scanning signal VR is input to the second scanning signal line;

[0228] At this time, in combination with Figures 2 and 12, the second transistor M2 and the seventh transistor M7 are turned on, the first capacitor C1 can keep the potential of the second node NG still at Vref, the driving transistor MD remains on, and a path is formed between the first power line VDD line and the first node NS. The first power line VDD line charges the first node NS. When the potential of the first node NS becomes Vref-Vth, the driving transistor MD is turned off. Since this process changes slowly and the potential of the second node NG is always pulled by Vref, the potential of the second node NG remains at Vref. At this time, Vgs=Vref-(Vref-Vth)=Vth, thereby completing the extraction of the threshold voltage Vth of the driving transistor MD.

[0229] In the third stage (data writing and compensation stage), for example, stage T3 shown in FIG2 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a low-level fourth scan signal VG(n-2) is input to the fourth scan signal line, a high-level third scan signal VG(n) is input to the third scan signal line, a low-level fifth scan signal VG(n+2) is input to the fifth scan signal line, and a low-level second scan signal VR is input to the second scan signal line;

[0230] At this time, as shown in Figures 2 and 13 , the first transistor M1 is turned on, the potential of the second node NG is Vdata, and the driving transistor MD is turned on. Since the potential of the second node NG changes from Vref in the previous stage to Vdata, due to the coupling effect of capacitance, the potential of the first node NS changes to (Vdata-Vref)*C1 / (C1+C2)+Vref-Vth, where C1 and C2 represent the capacitance values ​​of the first capacitor and the second capacitor. In addition, since the fifth transistor M5 is turned off at this time, the potential of the first node NS is not affected by the potential of the anode of the light-emitting device 8 and the IR Rise of VSS in the second and third stages.

[0231] In the fourth stage (reset stage), for example, stage T4 shown in FIG2 , a low-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a low-level fourth scan signal VG(n-2) is input to the fourth scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, a high-level fifth scan signal VG(n+2) is input to the fifth scan signal line, and a low-level second scan signal VR is input to the second scan signal line;

[0232] At this time, as shown in FIG2 and FIG14 , the sixth transistor M6 is turned on. Furthermore, under the action of the first capacitor C1, the potential of the second node NG is maintained at Vdata, and the driving transistor MD is turned on. The potential of the second power line VSS is written to the anode N1 of the light-emitting device 8 via the sixth transistor M6, thereby resetting the potential of the anode N1. This prevents uneven potential of the anodes of the light-emitting devices due to factors such as the process from negatively impacting the operating current of the pixel during the light-emitting phase. Furthermore, since the fifth transistor M5 is turned off at this time, resetting the potential of the anode N1 of the light-emitting device does not affect the potential of the first node NS, which has already been compensated, thereby ensuring the compensation effect of the threshold voltage Vth of the driving transistor MD.

[0233] In the fifth stage (light-emitting stage), for example, stage T5 in FIG2 , a high-level light-emitting control signal EM(n) is input to the light-emitting control signal line, a low-level first scan signal VG(n-4) is input to the first scan signal line, a low-level fourth scan signal VG(n-2) is input to the fourth scan signal line, a low-level third scan signal VG(n) is input to the third scan signal line, a low-level fifth scan signal VG(n+2) is input to the fifth scan signal line, and a low-level second scan signal VR is input to the second scan signal line;

[0234] At this time, in combination with Figures 2 and 18, the third transistor M3 and the fifth transistor M5 are turned on. Due to the action of the first capacitor C1, the potential of the second node NG is maintained at Vdata, the driving transistor MD is turned on, and a path is formed between the first power line VDD line and the second power line VSS line, and the light-emitting device 8 (EL) emits light.

[0235] Since Vg = Vdata, Vs = [C1(Vdata-Vref) / (C1+C2)+Vref-Vth];

[0236] Vgs=Vdata-[C1(Vdata-Vref) / (C1+C2)+Vref-Vth];

[0237] Ids=k(Vgs-Vth) 2 =k[C2(Vdata-Vref) / (C1+C2)] 2 ;

[0238] Here, k is a device parameter, which is related to the carrier mobility, channel width-to-length ratio, and self-capacitance of the driving transistor. It can be seen that in the light-emitting stage, the magnitude of the driving current Ids is independent of the threshold voltage Vth, the voltage of the first power signal VDD, and the voltage of the second power signal VSS. Therefore, the pixel driving circuit can avoid different potential changes in different sub-pixels due to the uneven threshold voltage Vth of the driving transistor MD and the different resistance differences between the first power line VDD and the second power line VSS, thereby avoiding the problem of uneven display images in different areas of the display device and improving the display effect.

[0239] 4 as an example, taking the ninth transistor M9 as a P-type transistor and the other transistors as N-type transistors as an example, the driving principle and driving process of the driving circuit are specifically described; FIG3 provides the timing corresponding to the circuit diagram in FIG4;

[0240] It should be noted that in the first stage T1, the second stage T2, the fourth stage T4 and the fifth stage T5, the driving principle and driving process of the circuit diagram shown in Figure 4 are the same as the driving principle and driving process of the circuit diagram shown in Figure 1 in the previous text. Only the driving process of the third stage T3 is specifically introduced and explained below.

[0241] During the third phase (data writing and compensation phase), such as phase T3 shown in FIG4 , the first transistor M1 and the ninth transistor M9 are simultaneously turned on, the potential of the second node NG is Vdata, and the driving transistor MD is turned on. Since the potential of the second node NG changes from Vref in the previous phase to Vdata, due to capacitive coupling, the potential of the first node NS changes to (Vdata-Vref)*C1 / (C1+C2)+Vref-Vth, where C1 and C2 represent the capacitance values ​​of the first and second capacitors. Furthermore, since the fifth transistor M5 is turned off at this time, during the second and third phases, the potential of the first node NS is not affected by the potential of the anode of the light-emitting device 8 or the IR Rise of VSS.

[0242] It should be noted that, since a high-level third scan signal VG(n) is input to the third scan signal line in advance in the third stage, for example, before the T3 stage shown in Figure 4, the first transistor M1 is already turned on before the ninth transistor M9 is turned on, thereby writing the data signal Vdata transmitted by the data line Data line in advance to the position between the first transistor M1 and the ninth transistor M9. When the first transistor M1 and the ninth transistor M9 are turned on at the same time, the data signal Vdata can be quickly written into the gate of the driving transistor MD through the ninth transistor M9, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0243] 5 as an example, taking the ninth transistor M9 as a P-type transistor and the other transistors as N-type transistors as an example, the driving principle and driving process of the driving circuit are specifically described; FIG6 provides the timing corresponding to the circuit diagram in FIG5;

[0244] It should be noted that in the first stage T1, the second stage T2, the fourth stage T4 and the fifth stage T5, the driving principle and driving process of the circuit diagram shown in Figure 4 are the same as the driving principle and driving process of the circuit diagram shown in Figure 1 in the previous text. Only the driving process of the third stage T3 is specifically introduced and explained below.

[0245] As shown in conjunction with FIG5 and FIG6, after stage T2 and before stage T3, the second scan signal line inputs the second scan signal VR of a high level, the sixth scan signal line inputs the sixth scan signal VG(n-1) of a high level, the tenth transistor M10 is turned on, and the ninth transistor M9 is turned off, so that the data signal Vdata transmitted by the data line Data is written in advance to the position between the tenth transistor M10 and the ninth transistor M9;

[0246] In the T3 phase, a low-level second scan signal VR is input to the second scan signal line, and a high-level third scan signal VG(n) is input to the third scan signal line. The first transistor M1 and the ninth transistor M9 are turned on at the same time, and the data signal Vdata can be quickly written into the gate of the driving transistor MD through the ninth transistor M9, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0247] Taking the circuit diagram shown in FIG7 as an example, and taking each transistor as an N-type transistor as an example, the driving principle and driving process of the driving circuit are specifically explained; FIG8 provides the timing corresponding to the circuit diagram in FIG7; and FIG16 to FIG20 respectively provide the circuit states of the circuit diagram in FIG7 at different stages of the timing shown in FIG8. In FIG16 to FIG20, the transistor cut-off is marked with “×”.

[0248] It should be noted that in the third stage T3, the fourth stage T4 and the fifth stage T5, the driving principle and driving process of the circuit diagram shown in Figure 7 are the same as the driving principle and driving process of the circuit diagram shown in Figure 1 in the previous text. The following only specifically introduces and explains the driving process of the first stage T1 and the second stage T2.

[0249] In the first stage (reset stage), for example, stage T1 shown in FIG8 , the first scan signal line inputs a high-level first scan signal VG(n−4), the third scan signal line inputs a low-level third scan signal VG(n), the fourth scan signal line inputs a low-level fourth scan signal VG(n−2), the fifth scan signal line inputs a low-level fifth scan signal VG(n+2), and the light-emission control signal line inputs a low-level light-emission control signal EM(n);

[0250] At this time, as shown in Figure 16, the second transistor M2 and the fourth transistor M4 are turned on, the potential of the first node NS is Vinit, and the potential of the second node NG is Vref. Since Vref and Vinit are both high-level potentials with constant voltage, the driving transistor MD is turned on. In this way, the potential of the first node NS and the second node NG is reset. In addition, the electrodes (plates) connected to the first capacitor C1 and the second capacitor C2 are pre-charged to prevent the inability to complete the extraction and compensation of the threshold voltage due to the large capacitance to be charged in the subsequent threshold voltage extraction stage.

[0251] In the second stage (threshold voltage extraction stage), for example, stage T2 shown in FIG8 , the first scan signal line inputs the first scan signal VG(n−4) of a low level, the third scan signal line inputs the third scan signal VG(n) of a low level, the fourth scan signal line inputs the fourth scan signal VG(n−2) of a high level, the fifth scan signal line inputs the fifth scan signal VG(n+2) of a low level, and the light emission control signal line inputs the light emission control signal EM(n) of a low level;

[0252] At this time, as shown in Figure 17, the eighth transistor M8 and the seventh transistor M7 are turned on, the first capacitor C1 can keep the potential of the second node NG still at Vref, the driving transistor MD remains on, and a path is formed between the first power line VDD line and the first node NS. The first power line VDD line charges the first node NS. When the potential of the first node NS becomes Vref-Vth, the driving transistor MD is turned off. Since this process changes slowly and the potential of the second node NG is always pulled by Vref, the potential of the second node NG remains at Vref. At this time, Vgs=Vref-(Vref-Vth)=Vth, thereby completing the extraction of the threshold voltage Vth of the driving transistor MD.

[0253] 9 as an example, taking the ninth transistor M9 as a P-type transistor and the other transistors as N-type transistors as an example, the driving principle and driving process of the driving circuit are specifically described; FIG10 provides the timing corresponding to the circuit diagram in FIG9;

[0254] It should be noted that in the first stage T1, the second stage T2, the fourth stage T4 and the fifth stage T5, the driving principle and driving process of the circuit diagram shown in Figure 4 are the same as the driving principle and driving process of the circuit diagram shown in Figure 1 in the previous text. Only the driving process of the third stage T3 is specifically introduced and explained below.

[0255] As shown in conjunction with FIG9 and FIG10, after stage T2 and before stage T3, the sixth scan signal line inputs a high-level sixth scan signal VG(n-1), the tenth transistor M10 is turned on, and the ninth transistor M9 is turned off, so that the data signal Vdata transmitted by the data line Data is written in advance to a position between the tenth transistor M10 and the ninth transistor M9;

[0256] In the T3 stage (data writing and compensation stage), a high-level third scan signal VG(n) is input to the third scan signal line, and a low-level sixth scan signal VG(n-1) is input to the sixth scan signal line. The first transistor M1 and the ninth transistor M9 are turned on at the same time, and the data signal Vdata can be quickly written into the gate of the driving transistor MD through the ninth transistor M9, thereby shortening the transmission time of the data signal Vdata, improving the refresh speed and response speed of the pixel driving circuit, and improving the display effect of the display device.

[0257] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A pixel driving circuit, wherein: The pixel driving circuit in the nth row includes: a reset subcircuit, electrically connected to the first reset signal line, the first scan signal line, the first node, the second reset signal line, the control signal line and the second node, and configured to reset the voltage of the first node under the control of the first scan signal and reset the second node under the control of the first control signal; a data writing sub-circuit, electrically connected to the data line, the third scanning signal line and the second node, and configured to write the data signal transmitted by the data line into the second node; a driving transistor, wherein a gate of the driving transistor is electrically connected to the second node, a first electrode of the driving transistor is electrically connected to a third node, a second electrode of the driving transistor is electrically connected to the first node, and the driving transistor is configured to generate a driving current under the control of a voltage of the second node; a light emitting control subcircuit, electrically connected to the light emitting control signal line, the first power line, the third node, the first node and the anode of the light emitting device, and configured to conduct a path between the first power line and the cathode of the light emitting device when the driving transistor is turned on; a compensation subcircuit, electrically connected to the fourth scan signal line, the first power line and the third node, and configured to complete the reading of the threshold voltage of the driving transistor in cooperation with the reset subcircuit; a storage subcircuit, electrically connected to the first node, the second node and the first power line, and configured to store the voltage of the second node and adjust the voltage of the first node; a reset subcircuit, electrically connected to the anode, the fifth scan signal line and the second power supply line, and configured to reset the anode under the control of the fifth scan signal; Wherein, n is a positive integer, and the first scanning signal line, the third scanning signal line, the fourth scanning signal line and the fifth scanning signal line are gate lines of different rows.

2. The pixel driving circuit according to claim 1, wherein: The control signal line includes the first scan signal line or the second scan signal line.

3. The pixel driving circuit according to claim 2, wherein: The pulse widths of the scan signals loaded on the first scan signal line, the third scan signal line, the fourth scan signal line, and the fifth scan signal line are the same.

4. The pixel driving circuit according to claim 3, wherein: The first scanning signal line is the gate line in the n-4th row, the third scanning signal line is the gate line in the nth row, the fourth scanning signal line is the gate line in the n-2th row, and the fifth scanning signal line is the gate line in the n+2th row; wherein n is greater than 4; The pixel driving circuit in the mth row is a dummy pixel driving circuit, m is a positive integer, m is greater than or equal to 1 and less than or equal to 4, and equal to n+1 or n+2; the pixel driving circuit in the mth row is electrically connected to the shift register in the mth row.

5. The pixel driving circuit according to claim 1, wherein: The first reset signal line includes a reference signal line, the second reset signal line includes an initialization signal line, and an absolute value of a difference between a voltage of a reference signal transmitted by the reference signal line and a voltage of an initialization signal transmitted by the initialization signal line is greater than a threshold voltage of the driving transistor.

6. The pixel driving circuit according to claim 1, wherein: The first reset signal line includes the first power line, and the second reset signal line includes the second power line.

7. The pixel driving circuit according to claim 4, wherein: The data writing subcircuit includes a first transistor, a gate of the first transistor is electrically connected to the third scanning signal line, a first electrode of the first transistor is electrically connected to the data line, and a second electrode of the first transistor is electrically connected to the second node.

8. The pixel driving circuit according to claim 4, wherein: In the case where the control signal line includes the second scanning signal line, the data writing sub-circuit includes a first transistor and a ninth transistor; The gate of the first transistor is electrically connected to the third scan signal line, the first electrode of the first transistor is electrically connected to the data line, the second electrode of the first transistor is electrically connected to the first electrode of the ninth transistor, the gate of the ninth transistor is electrically connected to the second scan signal line, and the second electrode of the ninth transistor is electrically connected to the second node.

9. The pixel driving circuit according to claim 8, wherein: The third scanning signal and the second scanning signal overlap in time.

10. The pixel driving circuit according to claim 4, wherein: In the case where the control signal line includes the second scanning signal line, the data writing sub-circuit includes a first transistor, a ninth transistor and a tenth transistor; The gate of the first transistor is electrically connected to the third scan signal line, the first electrode of the first transistor is electrically connected to the data line, the second electrode of the first transistor is electrically connected to the first electrode of the ninth transistor, the gate of the ninth transistor is electrically connected to the second scan signal line, the second electrode of the ninth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the data line, the second electrode of the tenth transistor is electrically connected to the first electrode of the ninth transistor, and the gate of the tenth transistor is electrically connected to the sixth scan signal line.

11. The pixel driving circuit according to claim 10, wherein: The sixth scanning signal and the second scanning signal overlap in time.

12. The pixel driving circuit according to claim 4, wherein: In the case where the control signal line includes the first scanning signal line, the data writing sub-circuit includes a first transistor, a ninth transistor and a tenth transistor; The gate of the first transistor is electrically connected to the third scan signal line, the first electrode of the first transistor is electrically connected to the data line, the second electrode of the first transistor is electrically connected to the first electrode of the ninth transistor, the gate of the ninth transistor is electrically connected to the sixth scan signal line, the second electrode of the ninth transistor is electrically connected to the second node, the gate of the tenth transistor is electrically connected to the sixth scan signal line, the first electrode of the tenth transistor is electrically connected to the data line, and the second electrode of the tenth transistor is electrically connected to the first electrode of the ninth transistor.

13. The pixel driving circuit according to claim 11 or 12, wherein: The sixth scanning signal line is the gate line in the (n-1)th row, and a pulse width of a scanning signal loaded on the sixth scanning signal line is the same as a pulse width of a scanning signal loaded on the first scanning signal line.

14. The pixel driving circuit according to any one of claims 7 to 11, wherein: In the case where the control signal line includes the second scanning signal line, the reset sub-circuit includes a fourth transistor of the second transistor, The gate of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the second reset signal line, the second electrode of the second transistor is electrically connected to the second node, and the gate of the fourth transistor is electrically connected to the first scan signal line. The first electrode of the fourth transistor is electrically connected to the first reset signal line, and the second electrode of the fourth transistor is electrically connected to the first node.

15. The pixel driving circuit according to claim 7 or 12, wherein: In the case where the control signal line includes the first scanning signal line, the reset sub-circuit includes a second transistor, a fourth transistor and an eighth transistor, The gate of the second transistor and the gate of the fourth transistor are both electrically connected to the first scan signal line, the first electrode of the second transistor is electrically connected to the second reset signal line, the second electrode of the second transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first reset signal line, the second electrode of the fourth transistor is electrically connected to the first node, the gate of the eighth transistor is electrically connected to the fourth scan signal line, the first electrode of the eighth transistor is electrically connected to the second reset signal line, and the second electrode of the eighth transistor is electrically connected to the second node.

16. The pixel driving circuit according to claim 4, wherein: The light emitting control subcircuit includes a third transistor and a fifth transistor, The gate of the third transistor and the gate of the fifth transistor are both electrically connected to the light-emitting control signal line, the first electrode of the third transistor is electrically connected to the first power line, and the second electrode of the third transistor is electrically connected to the third node; the first electrode of the fifth transistor is electrically connected to the first node, and the second electrode of the fifth transistor is electrically connected to the anode.

17. The pixel driving circuit according to claim 16, wherein: The compensation subcircuit includes a seventh transistor, a gate of the seventh transistor is electrically connected to the fourth scan signal line, a first electrode of the seventh transistor is electrically connected to the first power line, and a second electrode of the seventh transistor is electrically connected to the third node.

18. The pixel driving circuit according to claim 17, wherein: The storage subcircuit includes a first capacitor and a second capacitor; A first electrode of the first capacitor is electrically connected to the second node, and a second electrode of the first capacitor is electrically connected to the first node; A first electrode of the second capacitor is electrically connected to the first power line, and a second electrode of the second capacitor is electrically connected to the second electrode of the first capacitor via the first node.

19. The pixel driving circuit according to claim 18, wherein: The reset subcircuit includes a sixth transistor, a gate of the sixth transistor is electrically connected to the fifth scanning signal line, a first electrode of the sixth transistor is electrically connected to the anode, and a second electrode of the sixth transistor is electrically connected to the second power signal line.

20. The pixel driving circuit according to claim 19, wherein: In the case where the data writing sub-circuit includes a ninth transistor, the ninth transistor is of an opposite type to the other transistors.

21. The pixel driving circuit according to claim 20, wherein: The ninth transistor is a P-type transistor.

22. The pixel driving circuit according to claim 5, wherein: In the case where the driving transistor is an N-type transistor, the voltage of the reference signal is greater than the voltage of the initialization signal, and the absolute value range of the difference between the voltage of the reference signal and the voltage of the initialization signal is 2V to 4V.

23. The pixel driving circuit according to claim 18, wherein: The capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor.

24. The pixel driving circuit according to claim 1, wherein: The driving transistor is a dual-gate transistor, one gate of the driving transistor is electrically connected to the second node, and the other gate of the driving transistor is electrically connected to a signal input terminal with a constant voltage, and the constant voltage is less than a threshold voltage of the driving transistor.

25. The pixel driving circuit according to claim 1, wherein: The light emitting device includes an organic light emitting diode, a micro light emitting diode or a sub-millimeter light emitting diode.

26. The pixel driving circuit according to claim 19, wherein: The third transistor, the fifth transistor and the seventh transistor are all dual-gate transistors; two gates of the same transistor are electrically connected together; Alternatively, the third transistor, the fifth transistor and the seventh transistor are all metal oxide transistors.

27. A display device, wherein: Comprising the pixel driving circuit as described in any one of claims 1-26.

28. A driving method, wherein: Applied to driving a pixel driving circuit as claimed in any one of claims 1 to 26, the method comprising: In the first stage, a low-level light-emitting control signal is input to the light-emitting control signal line, a high-level first scanning signal is input to the first scanning signal line, a low-level fourth scanning signal is input to the fourth scanning signal line, a low-level third scanning signal is input to the third scanning signal line, and a low-level fifth scanning signal is input to the fifth scanning signal line; In the second stage, a low-level light-emitting control signal is input to the light-emitting control signal line, a low-level first scanning signal is input to the first scanning signal line, a high-level fourth scanning signal is input to the fourth scanning signal line, a low-level third scanning signal is input to the third scanning signal line, and a low-level fifth scanning signal is input to the fifth scanning signal line; In the third stage, a low-level light-emitting control signal is input to the light-emitting control signal line, a low-level first scanning signal is input to the first scanning signal line, a low-level fourth scanning signal is input to the fourth scanning signal line, a high-level third scanning signal is input to the third scanning signal line, and a low-level fifth scanning signal is input to the fifth scanning signal line; In the fourth stage, a low-level light-emitting control signal is input to the light-emitting control signal line, a low-level first scanning signal is input to the first scanning signal line, a low-level fourth scanning signal is input to the fourth scanning signal line, a low-level third scanning signal is input to the third scanning signal line, and a high-level fifth scanning signal is input to the fifth scanning signal line; In the fifth stage, a high-level light-emitting control signal is input to the light-emitting control signal line, a low-level first scanning signal is input to the first scanning signal line, a low-level fourth scanning signal is input to the fourth scanning signal line, a low-level third scanning signal is input to the third scanning signal line, and a low-level fifth scanning signal is input to the fifth scanning signal line.

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