Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a pixel driving circuit (PDC) having a first reset transistor (T1) and a second reset transistor (T6). At least a portion of a gate electrode (G1) of a first reset transistor (T1) in the current row of pixel driving circuits (PDC) and at least a portion of a gate electrode (G6) of a second reset transistor (T6) in the previous row of pixel driving circuits (PDC) are a portion of an integral structure. A grid electrode (G1) of a first reset transistor (T1) in the current row of pixel driving circuits (PDC) and a grid electrode (G6) of a second reset transistor (T6) in the previous row of pixel driving circuits (PDC) are arranged in the direction not parallel to the extending direction of the reset control signal lines.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular to an array substrate and a display device. Background Art

[0002] Organic light emitting diode (OLED) display is one of the hot spots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal display (TFT-LCD) that uses a stable voltage to control brightness, OLED is driven by a driving current that needs to be kept constant to control brightness. The OLED display panel includes a plurality of pixel units, which are configured with pixel driving circuits arranged in multiple rows and columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to a gate line in each row and a drain terminal connected to a data line in each column. When the row in which the pixel unit is selected is turned on, the switching transistor connected to the driving transistor is turned on, and the data voltage is applied to the driving transistor from the data line via the switching transistor, so that the driving transistor outputs a current corresponding to the data voltage to the OLED device. The OLED device is driven to emit light of corresponding brightness. Summary of the invention

[0003] In one aspect, the present disclosure provides an array substrate, comprising a pixel driving circuit having a first reset transistor and a second reset transistor; wherein at least a portion of a gate of the first reset transistor in a current row of pixel driving circuits and at least a portion of a gate of the second reset transistor in a previous row of pixel driving circuits are part of an integral structure; and the gate of the first reset transistor in the current row of pixel driving circuits and the gate of the second reset transistor in the previous row of pixel driving circuits are arranged along a direction that is not parallel to an extension direction of a reset control signal line.

[0004] In some embodiments of the present disclosure, a channel direction of the first reset transistor is not parallel to a channel direction of the second reset transistor; and the channel direction of the first reset transistor and the channel direction of the second reset transistor intersect with each other to form a non-zero angle.

[0005] In some embodiments of the present disclosure, the array substrate also includes a plurality of first reset signal lines, a plurality of second reset control signal lines and a plurality of second reset signal lines; wherein the plurality of second reset control signal lines include a second reset control signal line of a current level; in the same row of pixel driving circuits, the orthographic projection of a corresponding first reset signal line among the plurality of first reset signal lines on the substrate substrate is located between the orthographic projection of the second reset control signal line of the current level on the substrate substrate and the orthographic projection of a corresponding second reset signal line among the plurality of second reset signal lines on the substrate substrate.

[0006] In some embodiments of the present disclosure, the pixel driving circuit also includes a data writing transistor, a compensation transistor and a driving transistor; the array substrate includes a semiconductor material layer; the semiconductor material layer includes: a continuous line, which includes an active layer and a second electrode of the compensation transistor and a second electrode of the first reset transistor; and a branch, which branches from the continuous line; wherein the branch is connected to the gate of the driving transistor; and the orthographic projection of the branch on the substrate substrate does not overlap with the orthographic projection of the electrode block including the gate of the data writing transistor and the gate of the compensation transistor on the substrate substrate.

[0007] In some embodiments of the present disclosure, the array substrate also includes a plurality of first reset control signal lines; wherein each of the plurality of first reset control signal lines includes a main line portion extending in a direction substantially parallel to a first direction, and a protrusion protruding in a direction away from the main line portion in a direction substantially parallel to a second direction, the second direction being different from the first direction; the protrusion includes at least a portion of the gate of the second reset transistor in the previous row of pixel driving circuits; and the main line portion includes at least a portion of the gate of the first reset transistor in the current row of pixel driving circuits.

[0008] In some embodiments of the present disclosure, the array substrate also includes a plurality of first reset control signal lines and a plurality of second reset control signal lines; wherein the gate of the first reset transistor includes a first portion from a corresponding first reset control signal line among the plurality of first reset control signal lines and a second portion from a corresponding second reset control signal line among the plurality of second reset control signal lines; and an orthographic projection of the first portion on the base substrate at least partially overlaps with an orthographic projection of the second portion on the base substrate.

[0009] In some embodiments of the present disclosure, the array substrate also includes a voltage supply network; wherein the voltage supply network includes a plurality of third voltage supply lines and a plurality of fourth voltage supply lines; each of the plurality of third voltage supply lines is connected to one or more fourth voltage supply lines among the plurality of fourth voltage supply lines; and each of the plurality of fourth voltage supply lines is connected to one or more third voltage supply lines among the plurality of third voltage supply lines; the plurality of third voltage supply lines are located in a first signal line layer; and the plurality of fourth voltage supply lines are located in a second signal line layer, and the second signal line layer is located on a side of the first signal line layer away from the substrate.

[0010] In some embodiments of the present disclosure, the array substrate also includes a plurality of light-emitting control signal lines and a plurality of second reset signal lines; wherein the orthographic projection of a corresponding third voltage supply line among the plurality of third voltage supply lines on the substrate is located between the orthographic projection of a corresponding light-emitting control signal line among the plurality of light-emitting control signal lines on the substrate and the orthographic projection of a corresponding second reset signal line among the plurality of second reset signal lines on the substrate.

[0011] In some embodiments of the present disclosure, the array substrate also includes a first reset signal network and a second reset signal network; wherein the first reset signal network includes multiple first reset signal lines and multiple third reset signal lines; the second reset signal network includes multiple second reset signal lines and multiple fourth reset signal lines; each first reset signal line among the multiple first reset signal lines is connected to one or more third reset signal lines among the multiple third reset signal lines; each third reset signal line among the multiple third reset signal lines is connected to one or more first reset signal lines among the multiple first reset signal lines; each second reset signal line among the multiple second reset signal lines is connected to one or more fourth reset signal lines among the multiple fourth reset signal lines; and each fourth reset signal line among the multiple fourth reset signal lines is connected to one or more second reset signal lines among the multiple second reset signal lines.

[0012] In some embodiments of the present disclosure, the array substrate further includes a plurality of data lines, a plurality of second voltage supply lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines, and a plurality of fourth voltage supply lines; wherein a corresponding fourth voltage supply line among the plurality of fourth voltage supply lines is located between two adjacent data lines among the plurality of data lines configured to provide data signals to two adjacent columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the plurality of second voltage supply lines configured to provide first reference voltage signals to two adjacent columns of pixel driving circuits; a corresponding third reset signal line among the plurality of third reset signal lines is located between the plurality of The fourth reset signal line is located between two adjacent data lines among the plurality of data lines that are configured to provide data signals to two adjacent columns of pixel driving circuits, and between two adjacent second voltage supply lines among the plurality of second voltage supply lines that are configured to provide first reference voltage signals to two adjacent columns of pixel driving circuits; and a corresponding fourth reset signal line among the plurality of fourth reset signal lines is located between two adjacent data lines among the plurality of data lines that are configured to provide data signals to two adjacent columns of pixel driving circuits, and between two adjacent second voltage supply lines among the plurality of second voltage supply lines that are configured to provide first reference voltage signals to two adjacent columns of pixel driving circuits.

[0013] In some embodiments of the present disclosure, the pixel driving circuit also includes a storage capacitor and a compensation transistor; wherein the storage capacitor includes a first capacitor electrode and a second capacitor electrode; the second capacitor electrode is configured to be provided with a first reference voltage signal; the positive projection of the overall structure including the second capacitor electrode on the substrate substrate at least partially overlaps with the positive projection of a portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate substrate.

[0014] In some embodiments of the present disclosure, the overall structure including the second capacitor electrode includes a main body and an extension portion extending in a direction away from the main body; the extension portion E includes a first part, a second part and a third part; the first part connects the main body and the second part; the second part connects the first part and the third part; the first part and the third part extend along directions substantially parallel to the second direction, respectively; and the second part extends along a direction substantially parallel to the first direction.

[0015] In some embodiments of the present disclosure, an orthographic projection of the third portion on the substrate at least partially overlaps with an orthographic projection of the portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

[0016] In some embodiments of the present disclosure, the array substrate also includes a node connection line and a plurality of gate lines; wherein the node connection line is connected to the second electrode of the compensation transistor at a position between a corresponding gate line among the plurality of gate lines and a capacitor electrode of the storage capacitor; the orthographic projection of the node connection line on the substrate does not overlap with the orthographic projection of the plurality of gate lines on the substrate; and the orthographic projection of the second electrode of the compensation transistor on the substrate partially overlaps with the orthographic projection of the corresponding gate line on the substrate.

[0017] In some embodiments of the present disclosure, the array substrate further includes a node connection line and a plurality of data lines; wherein the second capacitor electrode separates the node connection line from a corresponding data line among the plurality of data lines configured to provide a data signal to the pixel driving circuit.

[0018] In some embodiments of the present disclosure, the array substrate further includes a node connection line and a plurality of data lines; wherein the extension portion separates the node connection line from a corresponding data line among the plurality of data lines configured to provide a data signal to the pixel driving circuit.

[0019] In some embodiments of the present disclosure, the array substrate also includes a shielding block and a plurality of first reset signal lines; wherein the pixel driving circuit also includes a compensation transistor; the shielding block is connected to a corresponding first reset signal line among the plurality of first reset signal lines; and an orthographic projection of the shielding block on the substrate at least partially overlaps with an orthographic projection of a portion of the semiconductor material layer located between two channel portions of the compensation transistor on the substrate.

[0020] In some embodiments of the present disclosure, the pixel driving circuit also includes a compensation transistor and a data writing transistor; wherein at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data writing transistor in the previous column pixel driving circuit are part of the overall structure.

[0021] In some embodiments of the present disclosure, the array substrate also includes a plurality of gate lines; wherein the overall structure including at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data writing transistor in the previous column pixel driving circuit is connected to one of the plurality of gate lines.

[0022] In some embodiments of the present disclosure, the array substrate also includes an anti-interference block and a plurality of second reset signal lines; wherein the anti-interference block is connected to corresponding second reset signal lines among the plurality of second reset signal lines; and an orthographic projection of the anti-interference block on the substrate substrate at least partially overlaps with an orthographic projection of a portion of the semiconductor material layer located between two channel portions of the first reset transistor on the substrate substrate.

[0023] In some embodiments of the present disclosure, the array substrate also includes an anti-interference block and a plurality of constant voltage signal lines; wherein the anti-interference block is connected to corresponding constant voltage signal lines among the plurality of constant voltage signal lines; the plurality of constant voltage signal lines are configured to provide a constant voltage signal to the anti-interference block; and an orthographic projection of the anti-interference block on the substrate substrate at least partially overlaps with an orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the first reset transistor on the substrate substrate.

[0024] In some embodiments of the present disclosure, the array substrate also includes a voltage supply network, a first reset signal network, a second reset signal network and a pixel defining layer that defines multiple sub-pixel openings; wherein the voltage supply network includes multiple third voltage supply lines and multiple fourth voltage supply lines; the first reset signal network includes multiple first reset signal lines and multiple third reset signal lines; the second reset signal network includes multiple second reset signal lines and multiple fourth reset signal lines; the vias connecting the signal lines of the voltage supply network, the first reset signal network and the second reset signal network are basically located outside the area of ​​the multiple sub-pixel openings; and the orthographic projection of the pixel defining layer on the base substrate basically covers the orthographic projection of the conductive material in the vias connecting the signal lines of the voltage supply network, the first reset signal network and the second reset signal network on the base substrate.

[0025] In one aspect, the present disclosure provides a display device, including the array substrate and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] According to various disclosed embodiments, the following drawings are examples only for illustration purposes and are not intended to limit the scope of the present invention.

[0027] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0028] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0029] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments according to the present disclosure.

[0030] Figure 2C is a timing diagram illustrating the operation of a pixel driving circuit in some embodiments according to the present disclosure.

[0031] Figure 3A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0032] Figure 3B To show Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate shown in .

[0033] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the semiconductor material layer in the array substrate is shown in FIG.

[0034] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate is shown in FIG.

[0035] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate is shown in FIG.

[0036] Figure 3F It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is shown in FIG.

[0037] Figure 3G It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG.

[0038] Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG.

[0039] Fig. 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG.

[0040] Figure 3J It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG.

[0041] Figure 3K It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG.

[0042] Figure 3L It is shown Figure 3A A schematic diagram of the structure of a pixel defining layer in an array substrate is shown in FIG.

[0043] Figure 4A is along Figure 3A Cross-sectional view along line A-A'.

[0044] Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0045] Figure 5A is a schematic diagram showing the structure of a semiconductor material layer and a second conductive layer according to some embodiments of the present disclosure.

[0046] Figure 5B Schematic diagram showing the structure of a semiconductor material layer, a second conductive layer, and a first signal line layer in an array substrate according to some embodiments of the present disclosure.

[0047] Figure 5Cis a schematic diagram showing the structure of a semiconductor material layer and a first conductive layer according to some embodiments of the present disclosure.

[0048] Fig. 6A is a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure.

[0049] Figure 6B Schematic diagram showing the structure of a semiconductor material layer, a second conductive layer, and a first signal line layer in an array substrate according to some embodiments of the present disclosure.

[0050] Fig. 7A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0051] Figure 7B To show Fig. 7A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate shown in .

[0052] Figure 7C It is shown Fig. 7A A schematic diagram of the structure of the semiconductor material layer in the array substrate is shown in FIG.

[0053] Fig.7D It is shown Fig. 7A A schematic diagram of the structure of the first conductive layer in the array substrate is shown in FIG.

[0054] Fig. 7E It is shown Fig. 7A A schematic diagram of the structure of the second conductive layer in the array substrate is shown in FIG.

[0055] Figure 7F It is shown Fig. 7A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is shown in FIG.

[0056] Figure 7G It is shown Fig. 7A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG.

[0057] Figure 7H It is shown Fig. 7A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG.

[0058] Fig.7I It is shown Fig. 7A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG.

[0059] Figure 7J It is shown Fig. 7A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG.

[0060] Figure 7K It is shown Fig. 7A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG.

[0061] Figure 7L It is shown Fig. 7A A schematic diagram of the structure of a pixel defining layer in an array substrate is shown in FIG.

[0062] Fig. 8A is along Fig. 7A Cross-sectional view along line CC'.

[0063] Figure 8B is along Fig. 7A Cross-sectional view along line D-D'.

[0064] Fig.9A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure.

[0065] Fig. 9B To show Fig.9A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate shown in .

[0066] Fig. 9C It is shown Fig.9A A schematic diagram of the structure of the semiconductor material layer in the array substrate is shown in FIG.

[0067] Fig.9D It is shown Fig.9A A schematic diagram of the structure of the first conductive layer in the array substrate is shown in FIG.

[0068] Fig.9E It is shown Fig.9A A schematic diagram of the structure of the second conductive layer in the array substrate is shown in FIG.

[0069] Fig.9F It is shown Fig.9A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is shown in FIG.

[0070] Figure 9G It is shown Fig.9A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG.

[0071] Figure 9H It is shown Fig.9A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG.

[0072] Fig.9I It is shown Fig.9A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG.

[0073] Figure 9J It is shown Fig.9A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG.

[0074] Figure 9K It is shown Fig.9A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG.

[0075] Figure 9L It is shown Fig.9A A schematic diagram of the structure of a pixel defining layer in an array substrate is shown in FIG.

[0076] Fig.10 is a schematic diagram showing a voltage supply network in an array substrate according to some embodiments of the present disclosure.

[0077] Fig.11 is a schematic diagram showing a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure.

[0078] Fig.12 is a schematic diagram showing the connection between signal lines in a display area and signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure.

[0079] Fig.13 is a schematic diagram showing the connection between signal lines in a display area and signal lines in a peripheral area of ​​an array substrate according to some embodiments of the present disclosure.

[0080] Fig.14 is a schematic diagram showing a voltage supply network, a first reset signal network, a second reset signal network, and an anode layer in an array substrate according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0081] The present disclosure will now be described in more detail with reference to the following examples. It should be noted that the following description of some of the embodiments presented herein is for illustration and description purposes only. It is not intended to be exhaustive or limited to the precise form disclosed.

[0082] The present disclosure particularly provides an array substrate and a display device, which substantially overcome one or more problems caused by the limitations and shortcomings of the prior art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a pixel driving circuit having a first reset transistor and a second reset transistor. Optionally, at least a portion of the gate of the first reset transistor in the current row pixel driving circuit and at least a portion of the gate of the second reset transistor in the previous row pixel driving circuit are part of the overall structure. Optionally, the gate of the first reset transistor in the current row pixel driving circuit and the gate of the second reset transistor in the previous row pixel driving circuit are arranged along a direction that is not parallel to the extension direction of the reset control signal line.

[0083] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is a 7T1C driving circuit. Various suitable light-emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light-emitting elements include organic light-emitting diodes, quantum dot light-emitting diodes and micro light-emitting diodes. Optionally, the light-emitting element is a micro light-emitting diode. Optionally, the light-emitting element is an organic light-emitting diode including an organic light-emitting layer.

[0084] Figure 1 is a plan view of an array substrate in some embodiments of the present disclosure. Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes an electronic component, for example, a light-emitting element. In one example, the light-emitting element is driven by a corresponding pixel driving circuit PDC. The array substrate includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of first voltage supply lines Vdd, and a corresponding second voltage supply line (for example, a low voltage supply line). The light emission of each sub-pixel Sp is driven by a corresponding pixel driving circuit PDC. In one example, a high voltage signal (for example, a VDD signal) is input to a corresponding pixel driving circuit PDC connected to an anode of a light-emitting element through a corresponding first voltage supply line in a plurality of first voltage supply lines Vdd; a low voltage signal (for example, a VSS signal) is input to a cathode of the light-emitting element through a low voltage supply line. The voltage difference between the high voltage signal (for example, a VDD signal) and the low voltage signal (for example, a VSS signal) is a driving voltage ΔV, which drives the light emission of the light-emitting element.

[0085] Figure 2A is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2AIn some embodiments, the pixel driving circuit includes: a driving transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first transistor T1 having a gate connected to a corresponding reset control signal line rstN of a current stage, a source connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1, and a drain connected to the first capacitor electrode Ce1 of the storage capacitor Cst and the gate of the driving transistor Td; a second transistor T2 having a gate connected to a corresponding gate line among a plurality of gate lines GL, a source connected to a corresponding data line among a plurality of data lines DL, and a drain connected to the source of the driving transistor Td; a third transistor T3 having a gate connected to the corresponding gate line, a first capacitor electrode Ce1 connected to the storage capacitor Cst, and a drain connected to the source of the driving transistor Td. A source electrode connected to the gate of the transistor Td, and a drain electrode connected to the drain electrode of the driving transistor Td; a fourth transistor T4 having a gate connected to a corresponding light emitting control signal line among a plurality of light emitting control signal lines em, a source electrode connected to a corresponding voltage supply line among a plurality of voltage supply lines Vdd, and a drain electrode connected to the source electrode of the driving transistor Td and the drain electrode of the second transistor T2; a fifth transistor T5 having a gate connected to a corresponding light emitting control signal line, a source electrode connected to the drain electrode of the driving transistor Td and the third transistor T3, and a drain electrode connected to the anode electrode of the light emitting element LE; and a sixth transistor T6 having a gate connected to a reset control signal line rst(N+1) of the next stage, a source electrode connected to a second reset signal line among a plurality of second reset signal lines Vint2, and a drain electrode connected to the drain electrode of the fifth transistor and the anode electrode of the light emitting element LE. The second capacitor electrode Ce2 is connected to the corresponding voltage supply line and the source electrode of the fourth transistor T4.

[0086] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a second transistor T2), a compensation transistor (e.g., a third transistor T3), two light emitting control transistors (e.g., a fourth transistor T4 and a fifth transistor T5), and two reset transistors (e.g., a first transistor T1 and a sixth transistor T6).

[0087] Figure 2B is a circuit diagram showing the structure of a pixel driving circuit in some embodiments of the present disclosure. Figure 2BIn some embodiments, the third transistor T3 is a "dual-gate" transistor, and the first transistor T1 is a "dual-gate" transistor. Optionally, in the "dual-gate" first transistor, the active layer of the first transistor crosses the corresponding reset control signal line twice (or, the corresponding reset control signal line crosses the active layer of the first transistor T1 twice). Similarly, in the "dual-gate" third transistor, the active layer of the third transistor T3 crosses the corresponding first gate line among the plurality of first gate lines GL1 twice (or, the corresponding gate line crosses the active layer of the third transistor T3 twice).

[0088] The pixel driving circuit also includes a first node N1, a second node N2, a third node N3 and a fourth node N4. The first node N1 is connected to the gate of the driving transistor Td, the first capacitor electrode Ce1 and the first electrode of the third transistor T3. The second node N2 is connected to the second electrode of the fourth transistor T4, the second electrode of the second transistor T2, and the first electrode of the driving transistor Td. The third node N3 is connected to the second electrode of the driving transistor Td, the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5. The fourth node N4 is connected to the second electrode of the fifth transistor T5, the second electrode of the sixth transistor T6 and the anode of the light emitting element LE.

[0089] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, and the first terminal and the second terminal are connected to the active layer of the transistor. The direction of the current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Therefore, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive an input signal, and the first electrode is configured to output an output signal.

[0090] Figure 2C is a timing diagram showing the operation of the pixel driving circuit in some embodiments according to the present disclosure. FIG. 2A to FIG. 2C During one frame of image, the operation of the pixel driving circuit includes a reset sub-stage t1, a data writing sub-stage t2, and a light emitting sub-stage t3. In the initial sub-stage t0, a cut-off reset control signal is provided to the gate of the first transistor T1 through a corresponding reset control signal line among a plurality of reset control signal lines rst to cut off the first transistor T1. In the initial sub-stage t0, each of the plurality of gate lines GL is provided with a cut-off signal, so that the second transistor T2 and the third transistor T3 are cut off.

[0091] In the reset sub-phase t1, the on-reset control signal is provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst to turn on the first transistor T1; the initialization voltage signal from the corresponding first reset signal line in the plurality of first reset signal lines Vint1 is allowed to be transmitted from the first electrode of the first transistor T1 to the second electrode of the first transistor T1, and then to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding first voltage supply line in the plurality of first voltage supply lines Vdd. As the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 increases, the first capacitor electrode Ce1 is charged in the reset sub-phase t1. In the reset sub-phase t1, each of the plurality of gate lines GL is provided with a cut-off signal, so that the second transistor T2 and the third transistor T3 are cut off. Each of the plurality of light-emitting control signal lines em is provided with a high voltage signal to cut off the fourth transistor T4 and the fifth transistor T5.

[0092] In the data writing sub-phase t2, the gate of the first transistor T1 is again provided with a cut-off reset control signal through the corresponding reset control signal line in the plurality of reset control signal lines rst to cut off the first transistor T1. Each of the plurality of gate lines GL is provided with a turn-on signal, so that the second transistor T2 is turned on with the third transistor T3. The second electrode of the driving transistor Td is connected to the second electrode of the third transistor T3. The gate of the driving transistor Td is electrically connected to the first electrode of the third transistor T3. Since the third transistor T3 is turned on in the data writing sub-phase t2, the gate of the driving transistor Td is connected to the second electrode and short-circuited, and only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The second transistor T2 is turned on in the data writing sub-phase t2. The data voltage signal transmitted through each of the plurality of data lines DL is received by the first electrode of the second transistor T2, and then transmitted to the first electrode of the driving transistor Td, which is connected to the second electrode of the second transistor T2. The node N2 connected to the first electrode of the driving transistor Td has the voltage level of the data voltage signal. Since only the PN junction between the gate of the driving transistor Td and the first electrode is effective, in the data writing sub-phase t2, the voltage level of the N1 node gradually rises to (Vdata+Vth), where Vdata is the voltage level of the data voltage signal and Vth is the voltage level of the threshold voltage Th of the PN junction. Because the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 is reduced to a relatively small value, the storage capacitor Cst is discharged. Each of the plurality of light emitting control signal lines em is provided with a high voltage signal to turn off the fourth transistor T4 and the fifth transistor T5.

[0093] In the data writing sub-phase t2, the on-reset control signal is provided to the gate of the sixth transistor T6 through the corresponding reset control signal line among the multiple reset control signal lines rst of the next adjacent stage to turn on the sixth transistor T6; allowing the initialization voltage signal from the corresponding second reset signal line among the multiple second reset signal lines Vint2 to be transferred from the first electrode of the sixth transistor T6 to the second electrode of the sixth transistor T6; and then to the node N4. Initialize the anode of the light emitting element LE.

[0094] In the light-emitting sub-stage t3, a cut-off reset control signal is again provided to the gate of the first transistor T1 through the corresponding reset control signal line in the plurality of reset control signal lines rst to cut off the first transistor T1. Each of the plurality of gate lines GL is provided with a cut-off signal, and the second transistor T2 and the third transistor T3 are cut off. Each of the plurality of light-emitting control signal lines em is provided with a low voltage signal to turn on the fourth transistor T4 and the fifth transistor T5. In the light-emitting sub-stage t3, the voltage level of the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and operates in the saturation region. A path is formed through the fourth transistor T4, the driving transistor Td, and the fifth transistor T5 to the light-emitting element LE. The driving transistor Td generates a driving current for driving the light-emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light-emitting voltage of the light-emitting element LE.

[0095] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels include respective first sub-pixels, respective second sub-pixels, and respective third sub-pixels. Optionally, each pixel of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes a S1-S2-S3 format repeating array, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, and S3 represents the corresponding third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, and C3 represents the corresponding third sub-pixel of the third color. In another example, the C1-C2-C3 format is an RGB format, wherein the corresponding first sub-pixel is a red sub-pixel, the corresponding second sub-pixel is a green sub-pixel, and the corresponding third sub-pixel is a blue sub-pixel.

[0096] In another example, the array of multiple sub-pixels includes a repeating array of the S1-S2-S3-S4 format, wherein S1 represents the corresponding first sub-pixel, S2 represents the corresponding second sub-pixel, S3 represents the corresponding third sub-pixel, and S4 represents the corresponding fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C4 represents the corresponding fourth sub-pixel of the fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2' format, wherein C1 represents the corresponding first sub-pixel of the first color, C2 represents the corresponding second sub-pixel of the second color, C3 represents the corresponding third sub-pixel of the third color, and C2' represents the corresponding fourth sub-pixel of the second color. In another example, the C1-C2-C3-C2′ format is an RGBG format, wherein the corresponding first subpixel is a red subpixel, the corresponding second subpixel is a green subpixel, the corresponding third subpixel is a blue subpixel, and the corresponding fourth subpixel is a green subpixel.

[0097] In some embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, and a corresponding third sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, and the corresponding third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0098] In an alternative embodiment, the minimum repeating unit of the plurality of sub-pixels of the array substrate includes a corresponding first sub-pixel, a corresponding second sub-pixel, a corresponding third sub-pixel, and a corresponding fourth sub-pixel. Optionally, each of the corresponding first sub-pixel, the corresponding second sub-pixel, the corresponding third sub-pixel, and the corresponding fourth sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a driving transistor Td, and a storage capacitor Cst.

[0099] Figure 3A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 3B To show Figure 3A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate shown in . Figure 3A and Figure 3B Depicted is a portion of an array substrate having six pixel driving circuits including PDC1, PDC2, PDC3, PDC4, PDC5, and PDC6.

[0100] Figure 3C It is shown Figure 3A A schematic diagram of the structure of the semiconductor material layer in the array substrate is shown in FIG. Figure 3D It is shown Figure 3A A schematic diagram of the structure of the first conductive layer in the array substrate is shown in FIG. Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second conductive layer in the array substrate is shown in FIG. Figure 3F It is shown Figure 3A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is shown in FIG. Figure 3G It is shown Figure 3A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG. Figure 3H It is shown Figure 3A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG. Fig. 3I It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG. Figure 3J It is shown Figure 3A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG. Figure 3K It is shown Figure 3A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG. Figure 3L It is shown Figure 3A A schematic diagram of the structure of a pixel defining layer in an array substrate is shown in FIG. Figure 4A is along Figure 3A Cross-sectional view along line A-A'. Figure 4B is along Figure 3A Cross-sectional view along line BB'.

[0101] refer to FIG. 3A to FIG. 3L and FIG. 4A to FIG. 4BIn some embodiments, the array substrate includes a base substrate BS; a semiconductor material layer SML, which is located on the base substrate BS; a gate insulating layer GI, which is located on a side of the semiconductor material layer SML away from the base substrate BS; a first conductive layer CT1, which is located on a side of the gate insulating layer GI away from the semiconductor material layer SML; an insulating layer IN, which is located on a side of the first conductive layer CT1 away from the gate insulating layer GI; a second conductive layer CT2, which is located on a side of the insulating layer IN away from the first conductive layer CT1; an interlayer dielectric layer ILD, which is located on a side of the second conductive layer CT2 away from the insulating layer IN; and a first signal line layer SL1. , which is located on the side of the interlayer dielectric layer ILD away from the second conductive layer CT2; the first planarization layer PLN1, which is located on the side of the first signal line layer SL1 away from the interlayer dielectric layer ILD; the second signal line layer SL2, which is located on the side of the first planarization layer PLN1 away from the first signal line layer SL1; the second planarization layer PLN2, which is located on the side of the second signal line layer SL2 away from the first planarization layer PLN1; the anode layer ADL, which is located on the side of the second planarization layer PLN2 away from the second signal line layer SL2; and the pixel defining layer PDL, which is located on the side of the anode layer ADL away from the substrate BS.

[0102] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3C, each pixel driving circuit is marked with a number, and the number indicates the area corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also marked with a number, and the number indicates the component of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are located on the same layer.

[0103] As used herein, an active layer refers to a component of a transistor including at least a portion of a semiconductor material layer, the orthographic projection of which on the substrate substrate overlaps with the orthographic projection of the gate on the substrate substrate. A first electrode refers to a component of a transistor connected to one side of the active layer, and a second electrode refers to a component of a transistor connected to the other side of the active layer. In the context of a dual-gate transistor (e.g., a third transistor T3), an active layer refers to a component of a transistor including a first portion of a semiconductor material layer, a second portion of a semiconductor material layer, and a third portion between the first portion and the second portion, wherein the orthographic projection of the first portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the first gate on the substrate substrate, and the orthographic projection of the second portion of the semiconductor material layer on the substrate substrate overlaps with the orthographic projection of the second gate on the substrate substrate. In the context of a dual-gate transistor, a first electrode refers to a component of a transistor connected to a side of the first portion away from the third portion, and a second electrode refers to a component of a transistor connected to a side of the second portion away from the third portion.

[0104] In some embodiments, the channel direction of the first transistor T1 is not parallel to the channel direction of the sixth transistor T6. The channel direction of the first transistor T1 and the channel direction of the sixth transistor T6 intersect each other to form a non-zero angle. As used herein, the term "channel direction" refers to the direction from the first electrode to the second electrode of the transistor. In an example, the channel direction of the first transistor T1 is substantially parallel to the second direction DR2, and the channel direction of the sixth transistor T6 is substantially parallel to the first direction DR1.

[0105] refer to Figure 2A , Figure 2B , Figure 3A and Figure 3DIn some embodiments, the first conductive layer includes a plurality of first reset control signal lines rst1 (including a first reset signal line rst1N of the current stage and a first reset signal line rst1(N+1) of the next stage), a plurality of light emitting control signal lines em, an electrode block including one or more gates G3 of the third transistor T3 and a gate G2 of the second transistor T2, and a first capacitor electrode Ce1 of the storage capacitor Cst. Various suitable electrode materials and various suitable manufacturing methods can be used to manufacture the first conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, and the like. Optionally, the plurality of first reset control signal lines rst1, the plurality of light emitting control signal lines em, the electrode block including one or more gates G3 of the third transistor T3 and a gate G2 of the second transistor T2, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0106] As used herein, the term "same layer" refers to the relationship between layers formed simultaneously in the same step. In one example, when a plurality of light emitting control signal lines em and a first capacitor electrode Ce1 are formed due to one or more steps of the same patterning process performed in the same material layer, the plurality of light emitting control signal lines em and the first capacitor electrode Ce1 are located in the same layer. In another example, by simultaneously performing the step of forming a plurality of light emitting control signal lines em and the step of forming the first capacitor electrode Ce1, a plurality of light emitting control signal lines em and the first capacitor electrode Ce1 can be formed in the same layer. The term "same layer" does not always mean that the thickness of the layer or the height of the layer in the cross-sectional view is the same.

[0107] Reference Figure 2A , Figure 2B , Figure 3A as well as Figure 3E In some embodiments, the second conductive layer includes an anti-interference block IPB and a second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second conductive layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the second conductive layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the anti-interference block IPB and the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0108] Figure 3FA via extending through the interlayer dielectric layer ILD is described in FIG.

[0109] refer to Figure 2A , Figure 2B , Figure 3A and Figure 3G In some embodiments, the first signal line layer includes a node connection line Cln, a plurality of second reset control signal lines rst2 (including a second reset control signal line rst2N of the current stage and a second reset control signal line rst2(N+1) of the next stage), a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, a plurality of gate lines GL, a plurality of first voltage supply lines Vdd1, a relay electrode RE, and a data signal connection pad DCP. The node connection line Cln connects the first capacitor electrode Ce1 and the first electrode of the driving transistor Td in each pixel driving circuit together. The data signal connection pad DCP is configured to connect the corresponding data line of the plurality of data lines to the first electrode of the second transistor T2. The relay electrode RE connects the fourth node N4 to the anode contact pad. The relay electrode is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6. The anode contact pad is in the second signal line layer and is connected to the anode in each sub-pixel. The plurality of first voltage supply lines Vdd1 are interconnected with the plurality of second voltage supply lines to form an interconnected reset signal network. Each of the plurality of first voltage supply lines Vdd1 is connected to the first electrode of the fourth transistor T4 and to the second capacitor electrode Ce2 of the storage capacitor Cst. Optionally, the plurality of first voltage supply lines Vdd1 extend in a direction substantially parallel to the first direction DR1; and the plurality of second voltage supply lines extend in a direction substantially parallel to the second direction DR2. As used herein, the term "substantially parallel" means that the angle is in the range of 0 degrees to about 45 degrees, for example, 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0110] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer. For example, the conductive material can be deposited on the substrate and patterned by a plasma enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the node connection line Cln, a plurality of second reset control signal lines rst2 (including the second reset control signal line rst2N of the current level and the second reset control signal line rst2(N+1) of the next level), a plurality of first reset signal lines Vint1, a plurality of second reset signal lines Vint2, a plurality of gate lines GL, a plurality of first voltage supply lines Vdd1, a relay electrode RE and a data signal connection pad DCP are located in the same layer.

[0111] In some embodiments, in the same row of pixel driving circuits, the orthographic projection of a corresponding first reset signal line among multiple first reset signal lines Vint1 on the substrate substrate is located between the orthographic projection of a second reset control signal line rst2N of the current level among multiple second reset control signal lines rst2 on the substrate substrate and the orthographic projection of a corresponding second reset signal line among multiple second reset signal lines Vint2 on the substrate substrate.

[0112] Figure 3H Vias extending through the first planarization layer PLN1 are shown.

[0113] Reference Figure 2A , Figure 2B , Figure 3A and Fig. 3I In some embodiments, the second signal line layer includes a plurality of second voltage supply lines Vdd2, a plurality of data lines DL and an anode contact pad ACP. The anode contact pad ACP is electrically connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in each pixel driving circuit through a relay electrode. The anode contact pad ACP is electrically connected to the anode in each sub-pixel. The plurality of second voltage supply lines Vdd2 are interconnected with the plurality of first voltage supply lines to form an interconnected reset signal network. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 through a data signal connection pad.

[0114] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the second signal line layer. For example, the conductive material can be deposited on the substrate by a plasma enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the second signal line layer include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, a plurality of second voltage supply lines Vdd2, a plurality of data lines DL and an anode contact pad ACP are located on the same layer.

[0115] Figure 3J Vias extending through the second planarization layer PLN2 are described.

[0116] Reference Figure 2A , Figure 2B , Figure 3A as well as Figure 3K , the array substrate further includes an anode layer ADL. Figure 3K , a plurality of sub-pixel openings SA corresponding to the plurality of anodes, respectively, are shown. Figure 3J Vias extending through the second planarization layer PLN2 are depicted. Respective anodes are connected to respective anode contact pads through respective vias extending through the second planarization layer PLN2.

[0117] Reference Figure 2A , Figure 2B , Figure 3A and Figure 3L The array substrate further includes a pixel defining layer PDL defining a plurality of sub-pixel openings SA.

[0118] refer to Figure 2A , Figure 2B , Figure 3A , Figure 3D , Figure 3E , Figure 3G and Figure 4A In some embodiments, except for the hole region H in which a portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the substrate substrate BS completely covers and exceeds the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln, which is located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located in the same layer as at least one of the plurality of second reset control signal lines rst2, the plurality of first reset signal lines Vint1, the plurality of second reset signal lines Vint2, the plurality of gate lines GL, the plurality of first voltage supply lines Vdd1, the relay electrode RE, or the data signal connection pad DCP.

[0119] In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. Optionally, the array substrate further includes a first via hole v1 and a second via hole v2. The first via hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via hole v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via hole v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor, as shown in FIG. Figure 4A shown.

[0120] In some embodiments, the array substrate further includes a third via hole v3 and a fourth via hole v4. The third via hole v3 extends through the first planarization layer PLN1. The fourth via hole v4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding data line among the plurality of data lines DL is connected to the data signal connection pad DCP through the third via hole v3. The data signal connection pad DCP is connected to the first electrode S2 of the second transistor through the fourth via hole v4.

[0121] Reference Figure 2A , Figure 2B , FIG. 3A to FIG. 3I as well as Figure 4B , in some embodiments, the array substrate further includes a fifth via v5, a sixth via v6, a seventh via v7, and an eighth via v8. The fifth via v5 extends through the first planarization layer PLN1. The sixth via v6 and the seventh via v7 extend through the interlayer dielectric layer ILD, respectively. The eighth via v8 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding second voltage supply line in the plurality of second voltage supply lines Vdd2 is connected to a corresponding first voltage supply line in the plurality of first voltage supply lines Vdd1 through the fifth via v5. Optionally, a corresponding first voltage supply line in the plurality of first voltage supply lines Vdd1 is connected to the second capacitor electrode Ce2 of the storage capacitor Cst through one or more vias (e.g., the sixth via v6 and the seventh via v7). Optionally, a corresponding first voltage supply line in the plurality of first voltage supply lines Vdd1 is connected to the first electrode S4 of the fourth transistor T4 through the eighth via v8.

[0122] refer to Figure 3A , Figure 3E and Figure 4AIn some embodiments, the second capacitor electrode Ce2 includes a main body MB and an extension E extending in a direction away from the main body MB. In some embodiments, the extension E includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 connects the main body MB and the second portion P2, and the second portion P2 connects the first portion P1 and the third portion P3. Optionally, the first portion P1 and the third portion P3 extend in directions substantially parallel to the second direction DR2, respectively. Optionally, the second portion P2 extends in a direction substantially parallel to the first direction DR1.

[0123] Figure 5A is a schematic diagram showing the structure of a semiconductor material layer and a second conductive layer according to some embodiments of the present disclosure. Figure 5B Schematic diagram showing the structure of a semiconductor material layer, a second conductive layer, and a first signal line layer in an array substrate according to some embodiments of the present disclosure. Figure 3A , Figure 3E , Figure 4A , Figure 5A as well as Figure 5B In some embodiments, the orthographic projection of the third portion P3 on the substrate BS at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between two active layer portions (e.g., two channel portions) of the third transistor T3 on the substrate BS. The inventors of the present disclosure have discovered that this unique structure enhances the stability of the third transistor T3.

[0124] Figure 5C is a schematic diagram showing the structure of a semiconductor material layer and a first conductive layer according to some embodiments of the present disclosure. Figure 3C , Figure 3D , Figure 3G , in some embodiments, the semiconductor material layer includes: a branch Br, which branches out from a continuous line; the continuous line includes an active layer ACT3 and a second electrode D3 of a third transistor T3 and a second electrode D1 of a first transistor T2. The branch Br is connected to a node connection line Cln. Optionally, the orthographic projection of the branch Br on the substrate substrate does not overlap with the orthographic projection of an electrode block including a gate G2 of the second transistor T2 and a gate G3 of the third transistor T3 on the substrate substrate. The electrode block including the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3 is an integral structure. By setting the branch Br, the electrode blocks located in the first conductive layer (each electrode block includes the gate G2 of the second transistor T2 and the gate G3 of the third transistor T3) can be connected to the corresponding gate lines among the multiple gate lines GL located in the first signal line layer.

[0125] Various suitable alternative implementations may be implemented to enhance the stability of the third transistor T3. Fig. 6Ais a schematic diagram showing the structure of a second conductive layer in an array substrate according to some embodiments of the present disclosure. Figure 6B Schematic diagram showing the structure of a semiconductor material layer, a second conductive layer, and a first signal line layer in an array substrate according to some embodiments of the present disclosure. Fig. 6A and Figure 6B In some embodiments, the second conductive layer includes a shielding block SDB. Optionally, the shielding block SDB is connected to a corresponding first reset signal line among a plurality of first reset signal lines Vint1. Optionally, the shielding block SDB is configured to receive a reset signal. In some embodiments, an orthographic projection of the shielding block SDB on the substrate substrate BS at least partially overlaps an orthographic projection of a portion of the semiconductor material layer located between two active layer portions (e.g., two channel portions) of the third transistor T3 on the substrate substrate BS. The inventors of the present disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0126] Reference Figure 3A , Figure 3C , Figure 3E , Figure 3G , Figure 5B and Figure 6B , in some embodiments, the array substrate further includes an anti-interference block IPB. Optionally, the anti-interference block IPB is located in the second conductive layer. Optionally, the anti-interference block IPB is located in the same layer as the second capacitor electrode Ce2. Optionally, the anti-interference block IPB is connected to a corresponding second reset signal line in a plurality of second reset signal lines Vint2. Optionally, the anti-interference block IPB is configured to receive a reset signal. In some embodiments, the positive projection of the anti-interference block IPB on the substrate substrate overlaps at least partially with the positive projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate substrate BS. Optionally, the positive projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate substrate BS does not overlap with the positive projection of any reset signal line on the substrate substrate. The inventors of the present disclosure have found that this unique structure enhances the stability of the first transistor T1.

[0127] Reference Figure 3A , Figure 3C , Figure 3E , Figure 3G , Figure 4A , Figure 5B and Figure 6BIn some embodiments, the node connection line Cln is connected to the second electrode D3 of the third transistor T3 at a position between each gate line in a plurality of gate lines GL and the capacitor electrode of the storage capacitor. Optionally, the positive projection of the node connection line Cln on the substrate substrate BS does not overlap with the positive projection of the corresponding gate line GL in a plurality of gate lines GL on the substrate substrate BS. Optionally, the positive projection of the second electrode D3 of the third transistor T3 on the substrate substrate BS partially overlaps with the positive projection of the corresponding gate line in a plurality of gate lines GL on the substrate substrate BS. The inventors of the present disclosure have found that this unique structure reduces or prevents interference from the gate scan signal transmitted to the node connection line Cln (corresponding to the first node N1) in each gate line. In addition, the length of the node connection line Cln can be reduced, thereby reducing the potential interference of the data signal transmitted in each data line in a plurality of data lines SL to the node connection line Cln (corresponding to the first node N1).

[0128] Reference Figure 3A , Figure 3C , Figure 3E , Figure 3G and Fig. 3I In some embodiments, the second capacitor electrode Ce2 separates the first node N1 in each pixel driving circuit from each data line in a plurality of data lines DL, which are configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 separates the node connection line Cln from each data line in a plurality of data lines DL configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 includes an extension E; and the extension E separates the second electrode D3 of the third transistor T3 (connected to the node connection line Cln) from each data line in a plurality of data lines DL configured to provide data signals to each pixel driving circuit. The inventors of the present disclosure have found that this unique structure reduces interference from data signals transmitted to the node connection line Cln (corresponding to the first node N1) and the second electrode D3 of the third transistor T3 in each data line SL in the plurality of data lines SL.

[0129] See also Figure 3A , Figure 3C , Figure 3D and Figure 3G In some embodiments, the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are configured to receive the same reset control signal.

[0130] In some embodiments, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row of pixel driving circuits and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row of pixel driving circuits are part of an integral structure. Optionally, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row of pixel driving circuits and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row of pixel driving circuits are part of the same reset control signal line.

[0131] In some embodiments, a corresponding first reset control signal line among a plurality of first reset control signal lines (e.g., the first reset control signal line rst1N of the current stage) includes a main line portion extending in a direction substantially parallel to the first direction DR1, and a protrusion P protruding in a direction away from the main line portion MLP in a direction substantially parallel to the second direction DR2. The protrusion P protrudes away from the current row of pixel driving circuits toward the previous row of pixel driving circuits. Optionally, the protrusion P includes at least a portion of a gate (e.g., G6) of a second reset transistor (e.g., T6) in the previous row of pixel driving circuits. Optionally, the main line portion MLP includes at least a portion of a gate (e.g., G1) of a first reset transistor (e.g., T1) in the current row of pixel driving circuits.

[0132] In some embodiments, the gate of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction that is not parallel to the extension direction of the reset control signal line of the array substrate. Optionally, the gate of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction that is not parallel to the first direction DR1.

[0133] In some embodiments, a gate of a first reset transistor (eg, T1 ) includes a first portion from a corresponding first reset control signal line of a plurality of first reset control signal lines and a second portion from a corresponding second reset control signal line of a plurality of second reset control signal lines.

[0134] In some embodiments, an orthographic projection of a corresponding first reset control signal line among the plurality of first reset control signal lines on the substrate at least partially overlaps an orthographic projection of a corresponding second reset control signal line among the plurality of second reset control signal lines on the substrate.

[0135] In some embodiments, an orthographic projection of a first portion of the gate of the first reset transistor from a corresponding first reset control signal line among a plurality of first reset control signal lines on the substrate substrate at least partially overlaps with an orthographic projection of a second portion of the gate of the first reset transistor from a corresponding second reset control signal line among a plurality of second reset control signal lines on the substrate substrate.

[0136] The inventor of the present disclosure has found that by providing two reset control signal lines for providing a reset control signal, the resistance of the reset control signal line can be reduced, and the driving power of the reset control signal line can be ensured. By having such a unique structure, the first reset transistor and the second reset transistor can share the same reset control signal generated by the same reset control generation circuit. The total number of scanning circuits can be reduced, and the peripheral area of ​​the array substrate can be further reduced.

[0137] See also Figure 3A , Figure 3D , Figure 3G In some embodiments, along the second direction DR2, a first reset signal line configured to provide a reset signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits among the plurality of first reset signal lines Vint1, and a second reset signal line configured to provide a reset signal to a second reset transistor (e.g., T6) in a previous row of pixel driving circuits among the plurality of second reset signal lines Vint2 are located on both sides of a second reset control signal line configured to provide a reset control signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits among the plurality of second reset control signal lines. Optionally, a second reset control signal line configured to provide a reset control signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits among the plurality of second reset control signal lines separates a first reset signal line configured to provide a reset signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits among the plurality of first reset signal lines Vint1 from a second reset signal line configured to provide a reset signal to a second reset transistor (e.g., T6) in a previous row of pixel driving circuits among the plurality of second reset signal lines Vint2.

[0138] See also Figure 3A , Figure 3D , Figure 3GIn some embodiments, along the second direction DR2, a first reset signal line among the multiple first reset signal lines Vint1, which is configured to provide a reset signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits, and a second reset signal line among the multiple second reset signal lines Vint2, which is configured to provide a reset signal to a second reset transistor (e.g., T6) in a previous row of pixel driving circuits, are located on both sides of a main line portion of a first reset control signal line among the multiple first reset control signal lines, which is configured to provide a reset control signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits and a second reset transistor (e.g., T6) in a previous row of pixel driving circuits. Optionally, a main line portion of a first reset control signal line among a plurality of first reset control signal lines, which is configured to provide a reset control signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits and a second reset transistor (e.g., T6) in a previous row of pixel driving circuits, separates a first reset signal line among a plurality of first reset signal lines Vint1, which is configured to provide a reset signal to a first reset transistor (e.g., T1) in a current row of pixel driving circuits and a second reset signal line among a plurality of second reset signal lines Vint2, which is configured to provide a reset signal to a second reset transistor (e.g., T6) in a previous row of pixel driving circuits.

[0139] In some embodiments, the orthographic projection of the reset signal line in the array substrate on the base substrate does not overlap with the orthographic projection of any main line portion of any reset control signal line in the array substrate on the base substrate, thereby reducing interference of the reset control signal on the reset signal line.

[0140] See also Figure 3A , Figure 3C , Figure 3D and Figure 3G In some embodiments, the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and the gate (e.g., G2) of the data writing transistor (e.g., T2) in the previous column pixel driving circuit are configured to receive the same gate scanning signal generated by, for example, the same gate scanning circuit. By having this unique structure, the data writing transistor and the compensation transistor can share the same gate scanning signal generated by the same gate scanning circuit (e.g., the same array on-gate circuit). The total number of scanning circuits can be reduced, and the peripheral area of ​​the array substrate can be further reduced.

[0141] In some embodiments, at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit are part of an integral structure (e.g., an integral electrode block). Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is connected to a gate line in a plurality of gate lines GL. Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is in the first conductive layer, and the plurality of gate lines GL are in the first signal line layer.

[0142] Fig. 7A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Figure 7B To show Fig. 7A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate shown in . Figure 7C It is shown Fig. 7A A schematic diagram of the structure of the semiconductor material layer in the array substrate is shown in FIG. Fig.7D It is shown Fig. 7A A schematic diagram of the structure of the first conductive layer in the array substrate is shown in FIG. Fig. 7E It is shown Fig. 7A A schematic diagram of the structure of the second conductive layer in the array substrate is shown in FIG. Figure 7F It is shown Fig. 7A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is shown in FIG. Figure 7G It is shown Fig. 7A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG. Figure 7H It is shown Fig. 7A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG. Fig.7I It is shown Fig. 7A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG. Figure 7J It is shown Fig. 7A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG. Figure 7K It is shown Fig. 7A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG. Figure 7L It is shown Fig. 7A A schematic diagram of the structure of a pixel defining layer in an array substrate is shown in FIG. Fig. 8A is along Fig. 7A Cross-sectional view along line C-C'. Figure 8B is along Fig. 7A Cross-sectional view along line D-D'.

[0143] Reference Figure 2A , Figure 2B , Fig. 7A and Figure 7C , each pixel driving circuit is marked with a number, and the number indicates the area corresponding to the multiple transistors (including the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the driving transistor Td) in each pixel driving circuit. Each pixel driving circuit is also marked with a number, and the number indicates the component of each of the multiple transistors in the pixel driving circuit. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1 and a second electrode D1. The second transistor T2 includes an active layer ACT2, a first electrode S2 and a second electrode D2. The third transistor T3 includes an active layer ACT3, a first electrode S3 and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4 and a second electrode D4. The fifth transistor T5 includes an active layer ACT5, a first electrode S5 and a second electrode D5. The sixth transistor T6 includes an active layer ACT6, a first electrode S6 and a second electrode D6. The driving transistor Td includes an active layer ACTd, a first electrode Sd and a second electrode Dd. In one example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) in each pixel driving circuit, the first electrodes (S1, S2, S3, S4, S5, S6, and Sd), and the second electrodes (D1, D2, D3, D4, D5, D6, and Dd) are part of the overall structure. In another example, the active layers (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6, and ACTd) of the transistors (T1, T2, T3, T4, T5, T6, and Td) are located on the same layer. In another example, the active layer (ACT1, ACT2, ACT3, ACT4, ACT5, ACT6 and ACTd), the first electrodes (S1, S2, S3, S4, S5, S6 and Sd) and the second electrodes (D1, D2, D3, D4, D5, D6 and Dd) of the transistors (T1, T2, T3, T4, T5, T6 and Td) are located on the same layer.

[0144] refer to Figure 2A , Figure 2B , Fig. 7A and Fig.7D In some embodiments, the first conductive layer includes a plurality of first reset control signal lines rst1 (including a first reset signal line rst1N of a current stage and a first reset signal line rst1(N+1) of a next stage), a plurality of light emitting control signal lines em, an electrode block including one or more gates G3 of a third transistor T3 and a gate G2 of a second transistor T2, and a first capacitor electrode Ce1 of a storage capacitor Cst.

[0145] Reference Figure 2A , Figure 2B , Fig. 7A and Fig. 7E In some embodiments, the second conductive layer includes a plurality of first reset signal lines Vint1, an anti-interference block IPB, and a second capacitor electrode Ce2 of a storage capacitor Cst.

[0146] Figure 7F A via extending through the interlayer dielectric layer ILD is described in FIG.

[0147] refer to Figure 2A , Figure 2B , Fig. 7A and Figure 7G In some embodiments, the first signal line layer includes a node connection line Cln, a plurality of constant voltage signal lines X, a plurality of second reset control signal lines rst2 (including a second reset control signal line rst2N of the current stage and a second reset control signal line rst2(N+1) of the next stage), a plurality of gate lines GL, a plurality of first voltage supply lines Vdd1, a relay electrode RE, and a data signal connection pad DCP. The node connection line Cln connects the first capacitor electrode Ce1 and the first electrode of the driving transistor Td in each pixel driving circuit together. The data signal connection pad DCP is configured to connect the corresponding data line of the plurality of data lines to the first electrode of the second transistor T2. The relay electrode RE connects the fourth node N4 to the anode contact pad. The relay electrode is connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6. The anode contact pad is in the second signal line layer and is connected to the anode in each sub-pixel. The plurality of first voltage supply lines Vdd1 are interconnected with the plurality of second voltage supply lines to form an interconnected reset signal network. Each of the plurality of first voltage supply lines Vdd1 is connected to the first electrode of the fourth transistor T4 and to the second capacitor electrode Ce2 of the storage capacitor Cst. Optionally, the plurality of first voltage supply lines Vdd1 extend in a direction substantially parallel to the first direction DR1; and the plurality of second voltage supply lines extend in a direction substantially parallel to the second direction DR2.

[0148] In some embodiments, the plurality of constant voltage signal lines X may be configured to transmit any appropriate constant voltage signal, for example, a first reference voltage signal (a high reference voltage signal) or a second reference voltage signal (a low reference voltage signal). Optionally, the first reference voltage signal is a constant voltage signal, the second reference voltage signal is a constant voltage signal, and the voltage level of the first reference voltage signal is higher than the voltage level of the second reference voltage signal.

[0149] In some embodiments, a corresponding constant voltage signal line among the plurality of constant voltage signal lines X in the first signal line layer is connected to the anti-interference block IPB in the second conductive layer and is configured to provide a constant voltage signal to the anti-interference block IPB.

[0150] Figure 7H Vias extending through the first planarization layer PLN1 are shown.

[0151] Reference Figure 2A , Figure 2B , Fig. 7A and Fig.7I In some embodiments, the second signal line layer includes a plurality of second voltage supply lines Vdd2, a plurality of data lines DL and an anode contact pad ACP. The anode contact pad ACP is electrically connected to the second electrodes of the fifth transistor T5 and the sixth transistor T6 in each pixel driving circuit through a relay electrode. The anode contact pad ACP is electrically connected to the anode in each sub-pixel. The plurality of second voltage supply lines Vdd2 are interconnected with the plurality of first voltage supply lines to form an interconnected reset signal network. Each of the plurality of data lines is electrically connected to the first electrode of the second transistor T2 through a data signal connection pad.

[0152] Figure 7J Vias extending through the second planarization layer PLN2 are shown.

[0153] Reference Figure 2A , Figure 2B , Fig. 7A as well as Figure 7K , the array substrate further includes an anode layer ADL. Figure 7K , a plurality of sub-pixel openings SA corresponding to the plurality of anodes, respectively, are shown. Figure 7J Vias extending through the second planarization layer PLN2 are depicted. Respective anodes are connected to respective anode contact pads through respective vias extending through the second planarization layer PLN2.

[0154] Reference Figure 2A , Figure 2B , Fig. 7A and Figure 7L The array substrate further includes a pixel defining layer PDL, which defines a plurality of sub-pixel openings SA.

[0155] refer to Figure 2A , Figure 2B , Fig. 7A , Fig.7D , Fig. 7E , Figure 7G and Fig. 8A In some embodiments, except for the hole region H in which a portion of the second capacitor electrode Ce2 does not exist, the orthographic projection of the second capacitor electrode Ce2 on the substrate substrate BS completely covers and exceeds the orthographic projection of the first capacitor electrode Ce1 on the substrate substrate BS. In some embodiments, the first signal line layer includes a node connection line Cln, which is located on a side of the interlayer dielectric layer ILD away from the second capacitor electrode Ce2. The node connection line Cln is located in the same layer as at least one of the plurality of constant voltage signal lines X, the plurality of first reset control signal lines rst1, the plurality of second reset control signal lines rst2, the plurality of gate lines GL, the plurality of first voltage supply lines Vdd1, the relay electrode RE, and the data signal connection pad DCP.

[0156] In some embodiments, the first capacitor electrode Ce1 is located on a side of the gate insulating layer GI away from the base substrate BS. Optionally, the array substrate further includes a first via hole v1 and a second via hole v2. The first via hole v1 is located in the hole area H and extends through the interlayer dielectric layer ILD and the insulating layer IN. The second via hole v2 extends through the interlayer dielectric layer ILD, the insulating layer IN and the gate insulating layer GI. Optionally, the node connection line Cln is connected to the first capacitor electrode Ce1 through the first via hole v1, and the node connection line Cln is connected to the semiconductor material layer SML through the second via hole v2. Optionally, the node connection line Cln is connected to the second electrode D3 of the third transistor, as shown in FIG. Fig. 8A shown.

[0157] In some embodiments, the array substrate further includes a third via hole v3 and a fourth via hole v4. The third via hole v3 extends through the first planarization layer PLN1. The fourth via hole v4 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding data line among the plurality of data lines DL is connected to the data signal connection pad DCP through the third via hole v3. The data signal connection pad DCP is connected to the first electrode S2 of the second transistor through the fourth via hole v4.

[0158] Reference Figure 2A , Figure 2B , 7A to 7I as well as Figure 8B, in some embodiments, the array substrate further includes a fifth via v5, a sixth via v6, a seventh via v7, and an eighth via v8. The fifth via v5 extends through the first planarization layer PLN1. The sixth via v6 and the seventh via v7 extend through the interlayer dielectric layer ILD, respectively. The eighth via v8 extends through the interlayer dielectric layer ILD, the insulating layer IN, and the gate insulating layer GI. Optionally, a corresponding second voltage supply line in the plurality of second voltage supply lines Vdd2 is connected to a corresponding first voltage supply line in the plurality of first voltage supply lines Vdd1 through the fifth via v5. Optionally, a corresponding first voltage supply line in the plurality of first voltage supply lines Vdd1 is connected to the second capacitor electrode Ce2 of the storage capacitor Cst through one or more vias (e.g., the sixth via v6 and the seventh via v7). Optionally, a corresponding first voltage supply line in the plurality of first voltage supply lines Vdd1 is connected to the first electrode S4 of the fourth transistor T4 through the eighth via v8.

[0159] refer to Fig. 7A , Fig. 7E and Fig. 8A In some embodiments, the second capacitor electrode Ce2 includes a main body MB and an extension E extending in a direction away from the main body MB. In some embodiments, the extension E includes a first portion P1, a second portion P2, and a third portion P3. The first portion P1 connects the main body MB and the second portion P2, and the second portion P2 connects the first portion P1 and the third portion P3. Optionally, the first portion P1 and the third portion P3 extend in directions substantially parallel to the second direction DR2, respectively. Optionally, the second portion P2 extends in a direction substantially parallel to the first direction DR1. In some embodiments, the orthographic projection of the third portion P3 on the substrate substrate BS at least partially overlaps with the orthographic projection of a portion of the semiconductor material layer located between two active layer portions (e.g., two channel portions) of the third transistor T3 on the substrate substrate BS. The inventors of the present disclosure have found that this unique structure enhances the stability of the third transistor T3.

[0160] Reference Fig. 7A , Figure 7C , Fig. 7E and Figure 7G, in some embodiments, the array substrate further includes an anti-interference block IPB. Optionally, the anti-interference block IPB is located in the second conductive layer. Optionally, the anti-interference block IPB is located in the same layer as the second capacitor electrode Ce2. Optionally, the anti-interference block IPB is connected to a constant voltage signal line in a plurality of constant voltage signal lines X, and is configured to receive a constant voltage signal. In some embodiments, the positive projection of the anti-interference block IPB on the substrate substrate overlaps at least partially with the positive projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate substrate BS. Optionally, the positive projection of a portion of the semiconductor material layer located between the two active layer portions (e.g., two channel portions) of the first transistor T1 on the substrate substrate BS does not overlap with the positive projection of any reset signal line on the substrate substrate. The inventors of the present disclosure have found that this unique structure enhances the stability of the first transistor T1.

[0161] Reference Fig. 7A , Figure 7C , Fig. 7E , Figure 7G and Fig. 8A In some embodiments, the node connection line Cln is connected to the second electrode D3 of the third transistor T3 at a position between each gate line in a plurality of gate lines GL and the capacitor electrode of the storage capacitor. Optionally, the positive projection of the node connection line Cln on the substrate substrate BS does not overlap with the positive projection of the corresponding gate line GL in a plurality of gate lines GL on the substrate substrate BS. Optionally, the positive projection of the second electrode D3 of the third transistor T3 on the substrate substrate BS partially overlaps with the positive projection of the corresponding gate line in a plurality of gate lines GL on the substrate substrate BS. The inventors of the present disclosure have found that this unique structure reduces or prevents interference from the gate scan signal transmitted to the node connection line Cln (corresponding to the first node N1) in each gate line. In addition, the length of the node connection line Cln can be reduced, thereby reducing the potential interference of the data signal transmitted in each data line in a plurality of data lines SL to the node connection line Cln (corresponding to the first node N1).

[0162] Reference Fig. 7A , Figure 7C , Fig. 7E , Figure 7G and Fig.7IIn some embodiments, the second capacitor electrode Ce2 separates the first node N1 in each pixel driving circuit from each data line in a plurality of data lines DL, which are configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 separates the node connection line Cln from each data line in a plurality of data lines DL configured to provide data signals to each pixel driving circuit. In some embodiments, the second capacitor electrode Ce2 includes an extension E; and the extension E separates the second electrode D3 of the third transistor T3 (connected to the node connection line Cln) from each data line in a plurality of data lines DL configured to provide data signals to each pixel driving circuit. The inventors of the present disclosure have found that this unique structure reduces interference from data signals transmitted to the node connection line Cln (corresponding to the first node N1) and the second electrode D3 of the third transistor T3 in each data line SL in the plurality of data lines SL.

[0163] See also Fig. 7A , Figure 7C , Fig.7D and Figure 7G In some embodiments, the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are configured to receive the same reset control signal.

[0164] In some embodiments, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row of pixel driving circuits and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row of pixel driving circuits are part of an integral structure. Optionally, at least a portion of the gate (e.g., G1) of the first reset transistor (e.g., T1) in the current row of pixel driving circuits and at least a portion of the gate (e.g., G6) of the second reset transistor (e.g., T6) in the previous row of pixel driving circuits are part of the same reset control signal line.

[0165] In some embodiments, the gate of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction substantially parallel to the extension direction of the reset control signal line of the array substrate. Optionally, the gate of the first reset transistor (e.g., T1) in the current row pixel driving circuit and the gate of the second reset transistor (e.g., T6) in the previous row pixel driving circuit are arranged along a direction substantially parallel to the first direction DR1.

[0166] In some embodiments, a gate of a first reset transistor (eg, T1 ) includes a first portion from a corresponding first reset control signal line of a plurality of first reset control signal lines and a second portion from a corresponding second reset control signal line of a plurality of second reset control signal lines.

[0167] In some embodiments, an orthographic projection of a corresponding first reset control signal line among the plurality of first reset control signal lines on the substrate at least partially overlaps an orthographic projection of a corresponding second reset control signal line among the plurality of second reset control signal lines on the substrate.

[0168] In some embodiments, an orthographic projection of a first portion of the gate of the first reset transistor from a corresponding first reset control signal line among a plurality of first reset control signal lines on the substrate substrate at least partially overlaps with an orthographic projection of a second portion of the gate of the first reset transistor from a corresponding second reset control signal line among a plurality of second reset control signal lines on the substrate substrate.

[0169] The inventor of the present disclosure has found that by providing two reset control signal lines for providing a reset control signal, the resistance of the reset control signal line can be reduced, and the driving power of the reset control signal line can be ensured. By having such a unique structure, the first reset transistor and the second reset transistor can share the same reset control signal generated by the same reset control generation circuit. The total number of scanning circuits can be reduced, and the peripheral area of ​​the array substrate can be further reduced.

[0170] See also Fig. 7A , Figure 7C , Fig.7D and Figure 7G In some embodiments, the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and the gate (e.g., G2) of the data writing transistor (e.g., T2) in the previous column pixel driving circuit are configured to receive the same gate scanning signal generated by, for example, the same gate scanning circuit. By having this unique structure, the data writing transistor and the compensation transistor can share the same gate scanning signal generated by the same gate scanning circuit (e.g., the same array on-gate circuit). The total number of scanning circuits can be reduced, and the peripheral area of ​​the array substrate can be further reduced.

[0171] In some embodiments, at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit are part of an integral structure (e.g., an integral electrode block). Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is connected to a gate line in a plurality of gate lines GL. Optionally, the integral structure including at least a portion of the gate (e.g., G3) of the compensation transistor (e.g., T3) in the current column pixel driving circuit and at least a portion of the gate (e.g., G2) of the data write transistor (e.g., T2) in the previous column pixel driving circuit is in the first conductive layer, and the plurality of gate lines GL are in the first signal line layer.

[0172] Fig.9A is a schematic diagram showing the structure of an array substrate in some embodiments of the present disclosure. Fig. 9B To show Fig.9A Schematic diagram of the arrangement of multiple pixel driving circuits in the array substrate shown in . Fig. 9C It is shown Fig.9A A schematic diagram of the structure of the semiconductor material layer in the array substrate is shown in FIG. Fig.9D It is shown Fig.9A A schematic diagram of the structure of the first conductive layer in the array substrate is shown in FIG. Fig.9E It is shown Fig.9A A schematic diagram of the structure of the second conductive layer in the array substrate is shown in FIG. Fig.9F It is shown Fig.9A A schematic diagram of the structure of the interlayer dielectric layer in the array substrate is shown in FIG. Figure 9G It is shown Fig.9A A schematic diagram of the structure of the first signal line layer in the array substrate is shown in FIG. Figure 9H It is shown Fig.9A A schematic diagram of the structure of the first planarization layer in the array substrate is shown in FIG. Fig.9I It is shown Fig.9A A schematic diagram of the structure of the second signal line layer in the array substrate is shown in FIG. Figure 9J It is shown Fig.9A Schematic diagram of the structure of the second planarization layer in the array substrate shown in FIG. Figure 9K It is shown Fig.9A Schematic diagram of the structure of the anode layer in the array substrate shown in FIG. Figure 9L It is shown Fig.9A A schematic diagram of the structure of a pixel defining layer in an array substrate is shown in FIG.

[0173] like Fig. 9C , Fig.9D , Fig.9E and Figure 9K The structures of the semiconductor material layer, the first conductive layer, the second conductive layer and the anode layer are similar to those shown in FIG. Figure 3C , Figure 3D , Figure 3E and Figure 3K The structures shown are basically similar.

[0174] refer to Figure 2A , Figure 2B , Fig.9A and Figure 9G ,and Figure 3G Compared to the structure shown in , in some embodiments, the first signal line layer further includes a plurality of third voltage supply lines Vss1. Optionally, the plurality of third voltage supply lines Vss1 extend in a direction substantially parallel to the first direction DR1. In some embodiments, the plurality of first voltage supply lines Vdd1 and the plurality of second voltage supply lines Vdd2 are configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and the plurality of third voltage supply lines Vss1 are configured to provide a second reference voltage signal (e.g., a low reference voltage signal).

[0175] like Figure 9G As shown, in some embodiments, the first signal line layer includes a plurality of first reset signal lines Vint1 and a plurality of second reset signal lines Vint2. Optionally, the plurality of first reset signal lines Vint1 and the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1.

[0176] In some embodiments, the orthographic projection of a corresponding third voltage supply line among the plurality of third voltage supply lines Vss1 on the substrate substrate is located between the orthographic projection of a corresponding light emitting control signal line among the plurality of light emitting control signal lines em on the substrate substrate and the orthographic projection of a corresponding second reset signal line among the plurality of second reset signal lines Vint2 on the substrate substrate. The inventors of the present disclosure have discovered that this unique layout can minimize the interference of the second reference voltage signal from the plurality of third voltage supply lines Vss1 on nearby nodes.

[0177] refer to Figure 2A , Figure 2B , Fig.9A and Fig.9I ,and Fig. 3ICompared to the structure shown in , in some embodiments, the second signal line layer further includes a plurality of fourth voltage supply lines Vss2, a plurality of third reset signal lines Vint3, and a plurality of fourth reset signal lines Vint4. Optionally, the plurality of fourth voltage supply lines Vss2, the plurality of third reset signal lines Vint3, and the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. In some embodiments, the plurality of first voltage supply lines Vdd1 and the plurality of second voltage supply lines Vdd2 are configured to provide a first reference voltage signal (e.g., a high reference voltage signal); and the plurality of third voltage supply lines Vss1 and the plurality of fourth voltage supply lines Vss2 are configured to provide a second reference voltage signal (e.g., a low reference voltage signal).

[0178] Fig.10 is a schematic diagram showing a voltage supply network in an array substrate according to some embodiments of the present disclosure. Fig.10 In some embodiments, the voltage supply network includes a plurality of third voltage supply lines Vss1 and a plurality of fourth voltage supply lines Vss2 interconnected with each other. Optionally, the plurality of third voltage supply lines Vss1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth voltage supply lines Vss2 extend in a direction substantially parallel to the second direction DR2. Optionally, the plurality of third voltage supply lines Vss1 are in a first signal line layer. Optionally, the plurality of fourth voltage supply lines Vss2 are in a second signal line layer. Optionally, each of the plurality of third voltage supply lines Vss1 is connected to one or more fourth voltage supply lines in the plurality of fourth voltage supply lines Vss2. Optionally, each of the plurality of fourth voltage supply lines Vss2 is connected to one or more third voltage supply lines in the plurality of third voltage supply lines Vss1.

[0179] Fig.11 Schematic diagram showing a first reset signal network and a second reset signal network in an array substrate according to some embodiments of the present disclosure. Fig.11In some embodiments, the first reset signal network includes a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3 interconnected with each other. Optionally, the plurality of first reset signal lines Vint1 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of third reset signal lines Vint3 extend in a direction substantially parallel to the second direction DR2. Optionally, the plurality of first reset signal lines Vint1 are located in a first signal line layer. Optionally, the plurality of third reset signal lines Vint3 are located in a second signal line layer. Optionally, each of the plurality of first reset signal lines Vint1 is connected to one or more third reset signal lines in the plurality of third reset signal lines Vint3. Optionally, each of the plurality of third reset signal lines Vint3 is connected to one or more first reset signal lines in the plurality of first reset signal lines Vint1.

[0180] Reference Fig.11 In some embodiments, the second reset signal network includes a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4 interconnected with each other. Optionally, the plurality of second reset signal lines Vint2 extend in a direction substantially parallel to the first direction DR1. Optionally, the plurality of fourth reset signal lines Vint4 extend in a direction substantially parallel to the second direction DR2. Optionally, the plurality of second reset signal lines Vint2 are located in the first signal line layer. Optionally, the plurality of fourth reset signal lines Vint4 are located in the second signal line layer. Optionally, each of the plurality of second reset signal lines Vint2 is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines Vint4. Optionally, each of the plurality of fourth reset signal lines Vint4 is connected to one or more second reset signal lines in the plurality of second reset signal lines Vint2.

[0181] See also Fig.9I , Fig.10 and Fig.11 In some embodiments, the plurality of fourth voltage supply lines Vss2, the plurality of third reset signal lines Vint3, and the plurality of fourth reset signal lines Vint4 are alternately arranged along the first direction DR1. In one example, each of the plurality of fourth voltage supply lines Vss2, each of the plurality of third reset signal lines Vint3, and each of the plurality of fourth reset signal lines Vint4 are sequentially arranged along the first direction DR1. In another example, each of the plurality of third reset signal lines Vint3, each of the plurality of fourth voltage supply lines Vss2, and each of the plurality of fourth reset signal lines Vint4 are sequentially arranged along the first direction DR1.

[0182] In some embodiments, a corresponding fourth voltage supply line among the plurality of fourth voltage supply lines Vss2 is located between two adjacent data lines among the plurality of data lines DL configured to provide data signals to two adjacent columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the plurality of second voltage supply lines Vdd2 configured to provide a first reference voltage signal to two adjacent columns of pixel driving circuits. In some embodiments, a corresponding third reset signal line among the plurality of third reset signal lines Vint3 is located between two adjacent data lines among the plurality of data lines DL configured to provide data signals to two adjacent columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the plurality of second voltage supply lines Vdd2 configured to provide a first reference voltage signal to two adjacent columns of pixel driving circuits. In some embodiments, a corresponding fourth reset signal line among the plurality of fourth reset signal lines Vint4 is located between two adjacent data lines among the plurality of data lines DL configured to provide data signals to two adjacent columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the plurality of second voltage supply lines Vdd2 configured to provide a first reference voltage signal to two adjacent columns of pixel driving circuits.

[0183] Fig.12 Schematic diagram showing the connection between the signal lines in the display area and the signal lines in the peripheral area of ​​the array substrate according to some embodiments of the present disclosure. Fig.12 In some embodiments, the array substrate includes a display area DA and a peripheral area PA. As used herein, the term "display area" refers to the area of ​​the array substrate in the display panel that actually displays the image. Optionally, the display area may include a sub-pixel area and an inter-sub-pixel area. The sub-pixel area refers to the light-emitting area of ​​the sub-pixel, for example, the area corresponding to the pixel electrode in the liquid crystal display or the area corresponding to the light-emitting layer in the organic light-emitting diode display panel. The inter-sub-pixel area refers to the area between adjacent sub-pixel areas, for example, the area corresponding to the black matrix in the liquid crystal display or the area corresponding to the pixel defining layer in the organic light-emitting diode display panel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in the same pixel. Optionally, the inter-sub-pixel area is the area between adjacent sub-pixel areas in two adjacent pixels. As used herein, the term "peripheral area" refers to the area of ​​the array substrate in the display panel, in which various circuits and wires are provided to transmit signals to the display substrate. In order to increase the transparency of the display device, non-transparent or opaque components (e.g., batteries, printed circuit boards, metal frames) of the display device can be arranged in the peripheral area instead of in the display area.

[0184] In some embodiments, the array substrate includes a first peripheral voltage supply line PVdd located in the peripheral area PA. A plurality of second voltage supply lines Vdd2 located in the display area DA are respectively connected to the first peripheral voltage supply line PVdd located in the peripheral area PA. Optionally, the first peripheral voltage supply line PVdd includes a first sublayer in the first signal line layer and a second sublayer in the second signal line layer.

[0185] In some embodiments, the array substrate includes a second peripheral voltage supply line PVss located in the peripheral area PA. A plurality of fourth voltage supply lines Vss2 located in the display area DA are respectively connected to the second peripheral voltage supply line PVss located in the peripheral area PA. Optionally, the second peripheral voltage supply line PVss is located in the first signal line layer.

[0186] In some embodiments, the array substrate includes a first peripheral reset signal line PVint1 located in the peripheral area PA. A plurality of third reset signal lines Vint3 located in the display area DA are respectively connected to the first peripheral reset signal line PVint1 located in the peripheral area PA. Optionally, the first peripheral reset signal line PVint1 is located in the first signal line layer.

[0187] In some embodiments, the array substrate includes a second peripheral reset signal line PVint2 located in the peripheral area PA. A plurality of fourth reset signal lines Vint4 located in the display area DA are respectively connected to the second peripheral reset signal line PVint2 located in the peripheral area PA. Optionally, the second peripheral reset signal line PVint2 is located in the first signal line layer.

[0188] Fig.13 Schematic diagram showing the connection between the signal lines in the display area and the signal lines in the peripheral area of ​​the array substrate according to some embodiments of the present disclosure. Fig.13 , a plurality of first reset signal lines Vint1 located in the display area DA are respectively connected to a first peripheral reset signal line PVint1 located in the peripheral area PA. Optionally, a corresponding first reset signal line among the plurality of first reset signal lines Vint1 is connected to the first peripheral reset signal line PVint1 through a first connection line cl1. In an example, the first connection line cl1 is located in the first conductive layer, the first peripheral reset signal line PVint1 is located in the first signal line layer, and the plurality of first reset signal lines Vint1 are located in the first signal line layer.

[0189] In some embodiments, a plurality of second reset signal lines Vint2 located in the display area DA are respectively connected to a second peripheral reset signal line PVint2 located in the peripheral area PA. Optionally, a corresponding second reset signal line in the plurality of second reset signal lines Vint2 is connected to the second peripheral reset signal line PVint2 through a second connection line cl2. In one example, the second connection line cl2 is located in the second conductive layer, the second peripheral reset signal line PVint2 is located in the first signal line layer, and the plurality of second reset signal lines Vint2 are located in the first signal line layer.

[0190] In some embodiments, a plurality of third voltage supply lines Vss1 located in the display area DA are respectively connected to a second peripheral voltage supply line PVss located in the peripheral area PA. Optionally, a corresponding third voltage supply line in the plurality of third voltage supply lines Vss1 is connected to the second peripheral voltage supply line PVss through a third connection line cl3. In one example, the third connection line cl3 is located in the second conductive layer, the second peripheral voltage supply line PVss is located in the first signal line layer, and the plurality of third voltage supply lines Vss1 are located in the first signal line layer.

[0191] Fig.14 Schematic diagram showing a voltage supply network, a first reset signal network, a second reset signal network and an anode layer in an array substrate according to some embodiments of the present disclosure. Fig.14 In some embodiments, the vias connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network are substantially outside the region of the plurality of sub-pixel openings SA. In some embodiments, the orthographic projection of the pixel defining layer on the substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the conductive material in the vias connecting the signal lines of the voltage supply network, the first reset signal network, and the second reset signal network on the substrate.

[0192] In some embodiments, the array substrate includes a plurality of first connection vias cv1, which respectively connect a plurality of first reset signal lines Vint1 and a plurality of third reset signal lines Vint3. Optionally, the plurality of first connection vias cv1 are substantially outside the region of the plurality of sub-pixel openings SA. Optionally, the orthographic projection of the pixel defining layer on the base substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the conductive material in the plurality of first connection vias cv1 on the base substrate.

[0193] In some embodiments, the array substrate includes a plurality of second connection vias cv2, which are respectively connected to a plurality of second reset signal lines Vint2 and a plurality of fourth reset signal lines Vint4. Optionally, the plurality of second connection vias cv2 are substantially outside the region of the plurality of sub-pixel openings SA. Optionally, the orthographic projection of the pixel defining layer on the base substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the conductive material in the plurality of second connection vias cv2 on the base substrate.

[0194] In some embodiments, the array substrate includes a plurality of third connection vias cv3 respectively connecting a plurality of third voltage supply lines Vss1 and a plurality of fourth voltage supply lines Vss2. Optionally, the plurality of third connection vias cv3 are substantially outside the region of the plurality of sub-pixel openings SA. Optionally, the orthographic projection of the pixel defining layer on the substrate substantially covers (e.g., at least 80% coverage, at least 85% coverage, at least 90% coverage, at least 95% coverage, at least 99% coverage, or completely covers) the orthographic projection of the conductive material in the plurality of third connection vias cv3 on the substrate.

[0195] In another aspect, the present invention provides a display device, comprising an array substrate as described herein or manufactured by the method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo albums, GPS, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a micro light emitting diode display device. Optionally, the display device is a mini light emitting diode display device.

[0196] On the other hand, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes forming a pixel driving circuit having a first reset transistor and a second reset transistor. Optionally, at least a portion of the gate of the first reset transistor in the current row pixel driving circuit and at least a portion of the gate of the second reset transistor in the previous row pixel driving circuit are part of the overall structure. Optionally, the gate of the first reset transistor in the current row pixel driving circuit and the gate of the second reset transistor in the previous row pixel driving circuit are arranged along a direction that is not parallel to the extension direction of the reset control signal line.

[0197] For the purpose of illustration and description, the above description of the embodiments of the present invention has been given. It is not exhaustive, nor is it intended to limit the present invention to the precise form or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments are selected and described to explain the principles of the present invention and its best mode practical application, so that those skilled in the art can understand the various embodiments of the present invention and the various modifications suitable for the specific use or implementation under consideration. The scope of the present invention is intended to be defined by the appended claims and their equivalents, wherein all terms are meant to have the broadest reasonable meaning unless otherwise stated. Therefore, the term "the present invention" and the like do not necessarily limit the scope of the claims to a specific embodiment, and the reference to the exemplary embodiments of the present invention does not mean a limitation of the present invention, and such limitation should not be inferred. The present invention is limited only by the spirit and scope of the appended claims. In addition, these claims may involve the use of "first", "second", etc., followed by a noun or element. These terms should be understood as nomenclature, and should not be interpreted as limiting the number of elements modified by these nomenclatures, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. In addition, the elements and assemblies in this disclosure are not intended to be contributed to the public, regardless of whether the element or assembly is clearly described in the appended claims.

Claims

1. An array substrate, comprising a pixel driving circuit having a first reset transistor and a second reset transistor; in, At least a portion of the gate of the first reset transistor in the current row of pixel driving circuits and at least a portion of the gate of the second reset transistor in the previous row of pixel driving circuits are part of an integral structure; as well as The gate of the first reset transistor in the current row pixel driving circuit and the gate of the second reset transistor in the previous row pixel driving circuit are arranged along a direction that is not parallel to an extending direction of a reset control signal line.

2. The array substrate according to claim 1, wherein: A channel direction of the first reset transistor is not parallel to a channel direction of the second reset transistor; and A channel direction of the first reset transistor and a channel direction of the second reset transistor intersect each other, forming a non-zero angle.

3. The array substrate according to claim 1, further comprising a plurality of first reset signal lines, a plurality of second reset control signal lines and a plurality of second reset signal lines; in, The plurality of second reset control signal lines include a second reset control signal line of a current stage; In the same row of pixel driving circuits, the orthographic projection of a corresponding first reset signal line among the multiple first reset signal lines on the substrate is located between the orthographic projection of the second reset control signal line of the current level on the substrate and the orthographic projection of a corresponding second reset signal line among the multiple second reset signal lines on the substrate.

4. The array substrate according to claim 1, wherein: The pixel driving circuit also includes a data writing transistor, a compensation transistor and a driving transistor; The array substrate comprises a semiconductor material layer; The semiconductor material layer comprises: a continuous line including the active layer and the second electrode of the compensation transistor and the second electrode of the first reset transistor; and branches, which branch off from said continuous line; wherein the branch is connected to the gate of the driving transistor; and An orthographic projection of the branch on the base substrate does not overlap with an orthographic projection of an electrode block including a gate of the data writing transistor and a gate of the compensation transistor on the base substrate.

5. The array substrate according to claim 1, further comprising a plurality of first reset control signal lines; in, Each of the plurality of first reset control signal lines includes a main line portion extending in a direction substantially parallel to a first direction, and a protrusion protruding in a direction away from the main line portion in a direction substantially parallel to a second direction different from the first direction; The protrusion includes the at least a portion of the gate of the second reset transistor in the previous row pixel driving circuit; and The main line portion includes the at least a portion of the gate of the first reset transistor in the current row pixel driving circuit.

6. The array substrate according to claim 1, further comprising a plurality of first reset control signal lines and a plurality of second reset control signal lines; in, the gate of the first reset transistor includes a first portion from a corresponding first reset control signal line of the plurality of first reset control signal lines and a second portion from a corresponding second reset control signal line of the plurality of second reset control signal lines; as well as An orthographic projection of the first portion on the substrate at least partially overlaps an orthographic projection of the second portion on the substrate.

7. The array substrate according to any one of claims 1 to 6, further comprising a voltage supply network; in, The voltage supply network comprises a plurality of third voltage supply lines and a plurality of fourth voltage supply lines; Each of the plurality of third voltage supply lines is connected to one or more fourth voltage supply lines of the plurality of fourth voltage supply lines; as well as Each of the plurality of fourth voltage supply lines is connected to one or more third voltage supply lines of the plurality of third voltage supply lines; The plurality of third voltage supply lines are located in the first signal line layer; as well as The plurality of fourth voltage supply lines are located in a second signal line layer, and the second signal line layer is located at a side of the first signal line layer away from the base substrate.

8. The array substrate according to claim 7, further comprising a plurality of light emitting control signal lines and a plurality of second reset signal lines; in, The orthographic projection of a corresponding third voltage supply line among the multiple third voltage supply lines on the substrate is located between the orthographic projection of a corresponding light-emitting control signal line among the multiple light-emitting control signal lines on the substrate and the orthographic projection of a corresponding second reset signal line among the multiple second reset signal lines on the substrate.

9. The array substrate according to any one of claims 1 to 7, further comprising a first reset signal network and a second reset signal network; in, The first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines; The second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines; Each of the plurality of first reset signal lines is connected to one or more third reset signal lines of the plurality of third reset signal lines; Each of the plurality of third reset signal lines is connected to one or more first reset signal lines of the plurality of first reset signal lines; Each of the plurality of second reset signal lines is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines; and Each of the plurality of fourth reset signal lines is connected to one or more second reset signal lines of the plurality of second reset signal lines.

10. The array substrate according to any one of claims 1 to 6, further comprising a plurality of data lines, a plurality of second voltage supply lines, a plurality of third reset signal lines, a plurality of fourth reset signal lines and a plurality of fourth voltage supply lines; in, A corresponding fourth voltage supply line among the plurality of fourth voltage supply lines is located between two adjacent data lines among the plurality of data lines configured to provide data signals to two adjacent columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the plurality of second voltage supply lines configured to provide first reference voltage signals to two adjacent columns of pixel driving circuits; A corresponding third reset signal line among the plurality of third reset signal lines is located between two adjacent data lines among the plurality of data lines configured to provide data signals to two adjacent columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the plurality of second voltage supply lines configured to provide first reference voltage signals to two adjacent columns of pixel driving circuits; and A corresponding fourth reset signal line among the multiple fourth reset signal lines is located between two adjacent data lines among the multiple data lines that are configured to provide data signals to two adjacent columns of pixel driving circuits, and is located between two adjacent second voltage supply lines among the multiple second voltage supply lines that are configured to provide first reference voltage signals to two adjacent columns of pixel driving circuits.

11. The array substrate according to any one of claims 1 to 10, wherein: The pixel driving circuit also includes a storage capacitor and a compensation transistor; wherein the storage capacitor comprises a first capacitor electrode and a second capacitor electrode; The second capacitor electrode is configured to be provided with a first reference voltage signal; An orthographic projection of the overall structure including the second capacitor electrode on the substrate at least partially overlaps with an orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

12. The array substrate according to claim 11, wherein: The integral structure including the second capacitor electrode includes a main body and an extension extending in a direction away from the main body; The extension portion E includes a first portion, a second portion and a third portion; The first portion connects the main body and the second portion; The second portion connects the first portion and the third portion; The first portion and the third portion extend respectively along a direction substantially parallel to the second direction; as well as The second portion extends in a direction substantially parallel to the first direction.

13. The array substrate according to claim 12, wherein: An orthographic projection of the third portion on the substrate at least partially overlaps with an orthographic projection of the portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

14. The array substrate according to claim 11, further comprising a node connection line and a plurality of gate lines; in, The node connection line is connected to the second electrode of the compensation transistor at a position between a corresponding gate line among the plurality of gate lines and a capacitor electrode of the storage capacitor; The orthographic projection of the node connection line on the substrate does not overlap with the orthographic projection of the plurality of gate lines on the substrate; as well as An orthographic projection of the second electrode of the compensation transistor on the base substrate partially overlaps with an orthographic projection of the corresponding gate line on the base substrate.

15. The array substrate according to claim 11, further comprising a node connection line and a plurality of data lines; in, The second capacitor electrode spaces the node connection line apart from a corresponding data line among the plurality of data lines configured to provide a data signal to the pixel driving circuit.

16. The array substrate according to claim 12, further comprising a node connection line and a plurality of data lines; in, The extending portion spaces the node connection line apart from a corresponding data line among the plurality of data lines configured to provide a data signal to the pixel driving circuit.

17. The array substrate according to any one of claims 1 to 8 and claims 10 to 16, further comprising a shielding block and a plurality of first reset signal lines; in, The pixel driving circuit further includes a compensation transistor; The shielding block is connected to a corresponding first reset signal line among the plurality of first reset signal lines; as well as An orthographic projection of the shielding block on the substrate at least partially overlaps with an orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the compensation transistor on the substrate.

18. The array substrate according to any one of claims 1 to 17, wherein: The pixel driving circuit also includes a compensation transistor and a data writing transistor; Among them, at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data writing transistor in the previous column pixel driving circuit are part of the overall structure.

19. The array substrate according to claim 18, further comprising a plurality of gate lines; in, The overall structure including at least a portion of the gate of the compensation transistor in the current column pixel driving circuit and at least a portion of the gate of the data writing transistor in the previous column pixel driving circuit is connected to one gate line among the plurality of gate lines.

20. The array substrate according to any one of claims 1 to 7 and claims 10 to 18, further comprising an anti-interference block and a plurality of second reset signal lines; in, The anti-interference block is connected to a corresponding second reset signal line among the plurality of second reset signal lines; and An orthographic projection of the anti-interference block on the substrate at least partially overlaps with an orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the first reset transistor on the substrate.

21. The array substrate according to any one of claims 1 to 19, further comprising an anti-interference block and a plurality of constant voltage signal lines; in, The anti-interference block is connected to a corresponding constant voltage signal line among the plurality of constant voltage signal lines; The plurality of constant voltage signal lines are configured to provide a constant voltage signal to the anti-interference block; as well as An orthographic projection of the anti-interference block on the substrate at least partially overlaps with an orthographic projection of a portion of the semiconductor material layer located between the two channel portions of the first reset transistor on the substrate.

22. The array substrate according to any one of claims 1 to 6, further comprising a voltage supply network, a first reset signal network, a second reset signal network, and a pixel defining layer defining a plurality of sub-pixel openings; in, The voltage supply network comprises a plurality of third voltage supply lines and a plurality of fourth voltage supply lines; The first reset signal network includes a plurality of first reset signal lines and a plurality of third reset signal lines; The second reset signal network includes a plurality of second reset signal lines and a plurality of fourth reset signal lines; A via connecting a signal line of the voltage supply network, the first reset signal network, and the second reset signal network is substantially located outside the region of the plurality of sub-pixel openings; as well as The orthographic projection of the pixel defining layer on the base substrate substantially covers the orthographic projection of the conductive material in the via hole connecting the signal line of the voltage supply network, the first reset signal network, and the second reset signal network on the base substrate.

23. A display device comprising the array substrate according to any one of claims 1 to 22 and one or more integrated circuits connected to the array substrate.

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