Display substrate and display device

Abstract

The invention provides a display substrate and a display device. The display substrate comprises a substrate body, a plurality of sub-pixels and first scanning lines, each sub-pixel comprises a sub-pixel driving circuit, each sub-pixel driving circuit comprises a driving transistor and a compensation transistor, a grid electrode of each compensation transistor is coupled with the corresponding first scanning line, a first electrode of each compensation transistor is coupled with a second electrode of the corresponding driving transistor, and a second electrode of each compensation transistor is coupled with the corresponding first scanning line. The second electrode of the compensation transistor is coupled with the grid electrode of the driving transistor; the compensation transistor comprises a compensation active layer, the compensation active layer comprises a first channel part, a second channel part and a first conductor part, and the first conductor part is respectively coupled with the first channel part and the second channel part; at least part of the orthographic projection of the first conductor part on the substrate is located between the orthographic projection of the first scanning line on the substrate and the orthographic projection of the grid electrode of the driving transistor on the substrate.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] With the continuous advancement of display technology, the market demand and expectations for smart terminal display devices are increasing, and the average daily usage time and frequency of smart terminal display devices are also increasing. Currently, the display technologies used in smart terminal display devices mainly include liquid crystal display technology and organic light-emitting diode display technology. Organic light-emitting diode display technology can achieve beneficial effects such as fast response speed, wide display viewing angle, and lightness. Therefore, organic light-emitting diode display technology is increasingly used in smart terminal display devices.

[0003] Summary of the Invention

[0004] An object of the present disclosure is to provide a display substrate and a display device.

[0005] In order to achieve the above objectives, the present disclosure provides the following technical solutions:

[0006] A first aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of sub-pixels and a first scan line each disposed on the base substrate, wherein the first scan line includes at least a portion extending along a first direction; the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor and a compensation transistor, a gate of the compensation transistor being coupled to the corresponding first scan line, a first electrode of the compensation transistor being coupled to a second electrode of the driving transistor, and a second electrode of the compensation transistor being coupled to the gate of the driving transistor;

[0007] The compensation transistor includes a compensation active layer, which includes a first channel portion, a second channel portion and a first conductor portion, wherein the first conductor portion is coupled to the first channel portion and the second channel portion, respectively; at least a portion of an orthographic projection of the first conductor portion on the substrate is located between an orthographic projection of the first scan line on the substrate and an orthographic projection of the gate of the driving transistor on the substrate.

[0008] Optionally, the compensation transistor includes a first compensation gate and a second compensation gate, wherein an orthographic projection of the first compensation gate on the base substrate covers an orthographic projection of the first channel portion on the base substrate, and an orthographic projection of the second compensation gate on the base substrate covers an orthographic projection of the second channel portion on the base substrate;

[0009] The first compensation gate is coupled to the corresponding first scan line. At least a portion of the first compensation gate is located between the first scan line to which it is coupled and the gate of the driving transistor. The first scan line is multiplexed as the second compensation gate.

[0010] Optionally, the display substrate further includes a data line and a second scan line, the second scan line includes at least a portion extending along the first direction, and the sub-pixel driving circuit further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding second scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0011] In the same sub-pixel, the gate of the data writing transistor is located on a side of the first scanning line facing the gate of the driving transistor.

[0012] Optionally, the data writing transistor includes a data active layer, and the gate of the data writing transistor includes a gate main portion and a gate extension portion coupled to each other, an orthographic projection of the gate main portion on the base substrate at least partially overlaps with an orthographic projection of the data active layer on the base substrate, and the gate extension portion is coupled to the corresponding second scan line;

[0013] The gate main body and the gate of the driving transistor are arranged along a first direction, at least part of the gate extension portion and the gate of the driving transistor are arranged along a second direction, and the first direction intersects with the second direction; the gate main body and the gate extension portion are arranged in the same layer or in different layers.

[0014] Optionally, the sub-pixel driving circuit also includes a first conductive connection portion and a first reset transistor, the first end of the first conductive connection portion is coupled to the gate of the driving transistor, and the second end of the first conductive connection portion is coupled to the second electrode of the first reset transistor; the second scanning line is at least partially arranged around the second end of the first conductive connection portion.

[0015] Optionally, the gate of the data writing transistor is provided in the same layer and material as the first scan line, the second scan line is provided in a different layer from the first scan line, and the second scan line is provided in the same layer and material as the first conductive connection portion.

[0016] Optionally, the second scan line includes a plurality of straight-side portions and a plurality of curved-side portions, the straight-side portions and the curved-side portions are alternately arranged along a first direction, the curved-side portions are arranged around the second end of the first conductive connection portion, the straight-side portions include a protruding end, at least a portion of the positive projection of the protruding end on the substrate is arranged along the second direction with the positive projection of the gate of the driving transistor on the substrate, and the protruding end is coupled to the gate of the data writing transistor.

[0017] Optionally, the display substrate further includes a first initialization signal line, the first initialization signal line includes at least a portion extending along the second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line;

[0018] The orthographic projection of the first initialization signal line on the base substrate is located between the orthographic projection of the gate of the driving transistor on the base substrate and the orthographic projection of the data line on the base substrate.

[0019] Optionally, the display substrate further includes a power line and the first initialization signal line. The power line and the data line are provided in the same layer and material, and the first initialization signal line is located between the power line and the data line.

[0020] Optionally, the display substrate further includes a second initialization signal line, a third initialization signal line and a third scan line, the third scan line including at least a portion extending along the first direction; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a second reset transistor and a third reset transistor, the gate of the second reset transistor and the gate of the third reset transistor are both coupled to the corresponding same third scan line; the first electrode of the second reset transistor is coupled to the second initialization signal line, and the second electrode of the second reset transistor is coupled to the anode of the light-emitting element; the first electrode of the third reset transistor is coupled to the third initialization signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the driving transistor.

[0021] Optionally, the second scanning line and the first scanning line are provided in different layers, and an orthographic projection of the second scanning line on the substrate at least partially overlaps with an orthographic projection of the first scanning line on the substrate;

[0022] The display substrate includes a second gate metal layer and a first source / drain metal layer. The second initialization signal line is provided in the same layer and material as the first source / drain metal layer. The third initialization signal line is provided in the same layer and material as the second gate metal layer.

[0023] Optionally, the display substrate further includes a power line; the first reset transistor includes a first reset active layer, the first reset active layer includes a third channel portion, a fourth channel portion and a second conductor portion, and the second conductor portion is coupled to the third channel portion and the fourth channel portion respectively;

[0024] The orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the second initialization signal line on the substrate; and / or, the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line on the substrate; and / or, the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the power line on the substrate.

[0025] Optionally, the display substrate further includes a power line and a first conductive connection portion, wherein a first end of the first conductive connection portion is coupled to the gate of the driving transistor, and a second end of the first conductive connection portion is coupled to the second electrode of the compensation transistor; the sub-pixel driving circuit further includes a storage capacitor, wherein a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power line;

[0026] The compensation active layer further includes a conductor extension portion, the conductor extension portion is coupled to the first conductor portion, and an orthographic projection of the conductor extension portion on the substrate at least partially overlaps with an orthographic projection of the second electrode on the substrate; and / or,

[0027] The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate; and / or,

[0028] The orthographic projection of the second electrode on the base substrate at least partially overlaps with the orthographic projection of the first conductor portion on the base substrate.

[0029] Optionally, the display substrate further includes a shading layer, the orthographic projection of the shading layer on the base substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the base substrate, and at least partially overlaps with the orthographic projection of the compensation active layer on the base substrate.

[0030] Optionally, the sub-pixel further includes a light-emitting element, the light-emitting element including an anode; the sub-pixel driving circuit further includes a light-emitting control transistor and a second conductive connection portion, the first electrode of the light-emitting control transistor is coupled to the second electrode of the driving transistor, the first end of the second conductive connection portion is coupled to the second electrode of the light-emitting control transistor, and the second end of the second conductive connection portion is coupled to the anode through a first via hole;

[0031] The sub-pixel further includes a pixel opening area, and an orthographic projection of the pixel opening area on the base substrate does not overlap with an orthographic projection of the first via hole on the base substrate.

[0032] Optionally, the sub-pixel further includes a light-emitting element, which includes an anode; the anode in at least some of the sub-pixels includes an anode main portion and an anode virtual portion; the orthographic projection of the anode main portion on the substrate at least partially overlaps with the orthographic projection of the compensation active layer included in the sub-pixel to which it belongs on the substrate; the orthographic projection of the anode virtual portion on the substrate at least partially overlaps with the orthographic projection of the compensation active layer included in the sub-pixel adjacent to it along the first direction on the substrate.

[0033] Optionally, the display substrate includes red sub-pixels, green sub-pixels, and blue sub-pixels; at least some of the sub-pixels include red sub-pixels and blue sub-pixels, and the adjacent sub-pixels include green sub-pixels.

[0034] A second aspect of the present disclosure provides a display substrate, comprising: a base substrate, and a plurality of sub-pixels, a second scan line, and a data line, each disposed on the base substrate, wherein the second scan line includes at least a portion extending along a first direction, the sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit including a first conductive connection portion, a driving transistor, a compensation transistor, and a data writing transistor;

[0035] The first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor via the first conductive connection portion; the compensation transistor includes a compensation active layer, the compensation active layer includes a first channel portion, a second channel portion, and a first conductor portion, the first conductor portion is coupled to the first channel portion and the second channel portion, respectively; at least a portion of an orthographic projection of the first conductor portion on the substrate is located between an orthographic projection of the second scan line on the substrate and an orthographic projection of the gate of the driving transistor on the substrate;

[0036] The gate of the data writing transistor is coupled to the corresponding second scan line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0037] At least a portion of the second scan line is disposed around one end of the first conductive connection portion.

[0038] Optionally, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second plate on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate; and / or,

[0039] An orthographic projection of the first conductor portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate.

[0040] Optionally, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second plate on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate; and / or,

[0041] The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate; and / or,

[0042] An orthographic projection of the first conductor portion on the base substrate at least partially overlaps with an orthographic projection of the power line on the base substrate.

[0043] Based on the technical solution of the above-mentioned display substrate, a third aspect of the present disclosure provides a display device including the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0045] FIG1 is a schematic diagram of a light shielding layer layout of a display substrate provided by an embodiment of the present disclosure;

[0046] FIG2 is a schematic diagram of the active layer layout of a display substrate provided in an embodiment of the present disclosure;

[0047] FIG3 is a schematic diagram of the layout of the first gate metal layer of a display substrate provided by an embodiment of the present disclosure;

[0048] FIG4 is a schematic diagram of the layout of the active layer and the first gate metal layer of the display substrate provided by an embodiment of the present disclosure;

[0049] FIG5 is a schematic diagram of the layout of the second gate metal layer of a display substrate provided by an embodiment of the present disclosure;

[0050] FIG6 is a schematic diagram showing the layout of a second gate metal layer added on the basis of FIG4 ;

[0051] FIG7 is a schematic diagram of a first layout of a first source / drain metal layer of a display substrate provided by an embodiment of the present disclosure;

[0052] FIG8 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG6 ;

[0053] FIG9 is a schematic diagram of a layout in which a first source / drain metal layer is added on the basis of FIG4 ;

[0054] FIG10 is a schematic diagram of the layout of the second source / drain metal layer of the display substrate provided by an embodiment of the present disclosure;

[0055] FIG11 is a schematic diagram of a layout in which a second source / drain metal layer is added on the basis of FIG8 ;

[0056] FIG12 is a schematic diagram showing the layout of a first source-drain metal layer and a second source-drain metal layer provided in an embodiment of the present disclosure;

[0057] FIG13 is a schematic diagram showing a via hole in which a light shielding layer and a second planar layer are added on the basis of FIG11;

[0058] FIG14 is a schematic diagram of a via hole formed on an interlayer insulating layer according to an embodiment of the present disclosure;

[0059] FIG15 is a schematic diagram of a via hole formed on the first planar layer according to an embodiment of the present disclosure;

[0060] FIG16 is a schematic diagram of a via hole formed on the second planar layer according to an embodiment of the present disclosure;

[0061] FIG17 is a schematic diagram of the layout of the anode layer provided in an embodiment of the present disclosure;

[0062] FIG18 is a schematic diagram of a layout with an anode layer added on the basis of FIG13;

[0063] FIG19 is a circuit schematic diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0064] FIG20 is a driving timing diagram of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0065] FIG21 is a schematic cross-sectional view of each film layer of a display substrate provided by an embodiment of the present disclosure;

[0066] FIG22 is a second schematic diagram of the layout of the first source / drain metal layer in the display substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0067] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below with reference to the accompanying drawings.

[0068] The present disclosure provides a display substrate, which includes multiple sub-pixels. The sub-pixels include a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit adopts an 8T1C (i.e., 8 transistors and 1 storage capacitor) circuit structure, and the transistors in the sub-pixel driving circuit all adopt low-temperature polysilicon transistors.

[0069] As shown in FIG19 , the display substrate further includes a power supply line VDD, an emission control signal line EM, a data line DA, a first scan line GA1, a second scan line GA2, a third scan line GA3, a first initialization signal line Vinit1, a second initialization signal line Vinit2, a third initialization signal line Vinit3, and a reset signal line RST. The sub-pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst.

[0070] The gate of the first transistor T1 is coupled to the corresponding reset signal line RST, the first electrode of the first transistor T1 is coupled to the first initialization signal line Vinit1, and the second electrode of the first transistor T1 is coupled to the gate of the third transistor T3 (ie, the N1 node).

[0071] A gate of the second transistor T2 is coupled to the corresponding first scan line GA1 , a first electrode of the second transistor T2 is coupled to the second electrode of the third transistor T3 , and a second electrode of the second transistor T2 is coupled to the gate of the third transistor T3 .

[0072] A gate of the fourth transistor T4 is coupled to the corresponding second scan line GA2 , a first electrode of the fourth transistor T4 is coupled to the corresponding data line DA, and a second electrode of the fourth transistor T4 is coupled to the first electrode of the third transistor T3 (ie, node N2 ).

[0073] A gate of the fifth transistor T5 is coupled to the corresponding light emitting control signal line EM, a first electrode of the fifth transistor T5 is coupled to the power line VDD, and a second electrode of the fifth transistor T5 is coupled to the first electrode of the third transistor T3.

[0074] The gate of the sixth transistor T6 is coupled to the corresponding light-emitting control signal line EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the third transistor T3 (i.e., the N3 node), the second electrode of the sixth transistor T6 is coupled to the anode Ano of the light-emitting element (i.e., the N4 node), and the cathode of the light-emitting element is connected to the negative power supply signal VSS.

[0075] A gate of the seventh transistor T7 is coupled to the corresponding third scan line GA3 , a first electrode of the seventh transistor T7 is coupled to the second initialization signal line Vinit2 , and a second electrode of the seventh transistor T7 is coupled to the anode Ano of the light emitting element.

[0076] A gate of the eighth transistor T8 is coupled to the corresponding third scan line GA3 , a first electrode of the eighth transistor T8 is coupled to the third initialization signal line Vinit3 , and a second electrode of the eighth transistor T8 is coupled to the first electrode of the third transistor T3 .

[0077] The first plate Cst1 of the storage capacitor Cst is coupled to the gate of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power line VDD. Exemplarily, the gate of the third transistor T3 is reused as the first plate Cst1.

[0078] As shown in FIG19 and FIG20, the display substrate includes multiple driving cycles, each driving cycle includes a writing frame and a holding frame. The working process of the sub-pixel driving circuit in each driving cycle is as follows:

[0079] In the write frame, at moment P1 (i.e., circle 1 in FIG2 ), the light-emitting control signal transmitted by the light-emitting control signal line EM is set to a high level, the fifth transistor T5 and the sixth transistor T6 are both turned off, and the N1 node, the N2 node, and the N3 node are all in a floating state. At moment P2 (i.e., circle 2 in FIG2 ), the third scan signal transmitted by the third scan line GA3 is set to a low level, the seventh transistor T7 and the eighth transistor T8 are both turned on, and the third initialization signal transmitted by the third initialization signal line Vinit3 performs an initial Bias refresh on the N2 node for a new frame, while the second initialization signal transmitted by the second initialization signal line Vinit2 resets the N4 node in time. At moment P3 (i.e., circle 3 in FIG2 ), the reset signal transmitted by the reset signal line RST is set to a low level, the first transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 initializes the N1 node. At time P4 (i.e., circle 4 in Figure 2), the first scan signal transmitted by the first scan line GA1 is set to a low level, the first transistor T1 and the second transistor T2 are turned on at the same time, and the first initialization signal transmitted by the first initialization signal line Vinit1 initializes the N1 node, completing the initialization of all three nodes in the floating state. At time P5 (i.e., circle 5 in Figure 2), the second scan signal transmitted by the second scan line GA2 is set to a low level, the fourth transistor T4 is turned on, and a new frame of data signal is written. At times P5 to P6 (i.e., circles 5 and 6 in Figure 2), the threshold voltage Vth compensation of the third transistor T3 continues through the data signal information stored in the N2 node and the parasitic capacitance. At time P6, the first scan signal transmitted by the first scan line GA1 is set to a high level, the second transistor T2 is turned off, and the writing is completed. At time P7 (i.e., circle 7 in Figure 2), the third scan signal transmitted by the third scan line GA3 is set to a low level again, and the N2 node and the N4 node are reset and refreshed again before emitting light, keeping the source and drain of the third transistor T3 in the same state before the new frame is written. At time P8 (i.e., circle 8 in Figure 2 ), the light control signal transmitted by the light control signal line EM is set to a low level, and the fifth transistor T5 and the sixth transistor T6 are turned on, charging the light emitting element and emitting light during the write frame. In the low-frequency display hold frame, at times P9 and P10 (i.e., circles 9 and 10 in Figure 2 ), the third scan signal transmitted by the third scan line GA3 is set to a low level, and the seventh transistor T7 and the eighth transistor T8 are both turned on, which can refresh the bias of the N2 node and reset the N4 node.

[0080] Exemplarily, the reset signal line RST coupled to the sub-pixel driving circuit is provided with a signal by a group of emission control shift register units (EM GOAs). For example, the signal transmitted by the reset signal line RST coupled to the sub-pixel driving circuit in the nth row is provided by the EM GOA in the (n-7th) row. The signals transmitted by the second scan line GA2 and the third scan line GA3 can be provided by independent gate shift register units (Gate GOAs), but are not limited thereto.

[0081] In the sub-pixel driving circuit of the above structure, an eighth transistor T8 and a third initialization signal line Vinit3 are added. By refreshing the voltage of the N2 node through timing control, low-frequency and low-power display can be achieved, and the low-frequency flicker problem can be improved.

[0082] Consumers are pursuing low-frequency, low-power consumption, and reduced low-frequency flicker while also demanding higher-resolution display products. However, limited by the size of display products, the layout space for sub-pixels is significantly restricted. Therefore, it is necessary to consider the operating principle, working status, and potential failures of each signal line, and rationally arrange the design to avoid these failures.

[0083] Referring to Figures 2 to 4 , an embodiment of the present disclosure provides a display substrate, including: a base substrate, and a plurality of sub-pixels and a first scan line GA1 each disposed on the base substrate. The first scan line GA1 includes at least a portion extending along a first direction. The sub-pixels include a sub-pixel driving circuit, the sub-pixel driving circuit including a driving transistor (i.e., the third transistor T3) and a compensation transistor (i.e., the second transistor T2). The gate T2-g of the compensation transistor is coupled to the corresponding first scan line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate T3-g of the driving transistor.

[0084] The compensation transistor includes a compensation active layer 22, which includes a first channel portion 221, a second channel portion 222 and a first conductor portion 223, wherein the first conductor portion 223 is coupled to the first channel portion 221 and the second channel portion 222, respectively; at least part of the orthographic projection of the first conductor portion 223 on the substrate is located between the orthographic projection of the first scan line GA1 on the substrate and the orthographic projection of the gate T3-g of the driving transistor on the substrate.

[0085] Exemplarily, the display substrate includes a plurality of sub-pixels, and the plurality of sub-pixel driving circuits included in the plurality of sub-pixels are distributed in an array. The plurality of sub-pixel driving circuits are divided into a plurality of rows of sub-pixel driving circuits and a plurality of columns of sub-pixel driving circuits. The plurality of rows of sub-pixel driving circuits are arranged along a second direction, and each row of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a first direction. The plurality of columns of sub-pixel driving circuits are arranged along a first direction, and each column of sub-pixel driving circuits includes a plurality of sub-pixel driving circuits arranged along a second direction. Exemplarily, the first direction and the second direction intersect. For example, the first direction includes a transverse direction, and the second direction includes a longitudinal direction.

[0086] Exemplarily, the sub-pixel includes a sub-pixel driving circuit and a light-emitting element. The sub-pixel driving circuit is coupled to an anode of the light-emitting element and is configured to provide a driving signal to the light-emitting element to drive the light-emitting element to emit light.

[0087] Exemplarily, the display substrate includes a plurality of first scan lines GA1, the plurality of first scan lines GA1 being arranged along the second direction, and the first scan lines GA1 including at least a portion extending along the first direction. For example, the plurality of first scan lines GA1 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the first scan lines GA1 are respectively coupled to the gates T2-g of the compensation transistors in the corresponding row of sub-pixel driving circuits.

[0088] Exemplarily, the compensation transistor includes a dual-gate transistor, and the first scan line GA1 is coupled to two gates of the compensation transistor respectively. For example, the first scan line GA1 is multiplexed as at least one gate of the compensation transistor.

[0089] Exemplarily, the compensation transistor includes a compensation active layer 22, the compensation active layer 22 including a first channel portion 221, a second channel portion 222, and a first conductor portion 223. The first conductor portion 223 is respectively coupled to the first channel portion 221 and the second channel portion 222. For example, the first conductor portion 223 forms an integral structure with the first channel portion 221 and the second channel portion 222.

[0090] Illustratively, at least a portion of the orthographic projection of the first channel portion 221 on the base substrate is located between the orthographic projection of the first scan line GA1 on the base substrate and the orthographic projection of the gate T3 - g of the driving transistor on the base substrate.

[0091] Illustratively, the first channel portion 221 and the first conductor portion 223 are arranged along the first direction, and the second channel portion 222 and the first conductor portion 223 are arranged along the second direction.

[0092] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiments of the present disclosure, the compensation transistor includes a compensation active layer 22. At least a portion of the orthographic projection of the first conductor portion 223 of the compensation active layer 22 on the base substrate is located between the orthographic projection of the first scan line GA1 on the base substrate and the orthographic projection of the gate electrode T3-g of the drive transistor on the base substrate. Compared to conventional layouts, this arrangement enables the compensation transistor to form a dual-gate inverted structure. That is, within the same sub-pixel drive circuit layout area, both the first conductor portion 223 and the first compensation gate electrode T2-g1 can be located in the area between the first scan line GA1 and the gate electrode T3-g of the drive transistor. This effectively reduces the vertical design space occupied by the sub-pixel drive circuit, facilitating the development of high-resolution display substrates.

[0093] Moreover, since the gate T2-g of the compensation transistor is coupled to the first scan line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate T3-g of the driving transistor, that is, the compensation transistor itself is coupled to the first scan line GA1 and the driving transistor, therefore, at least part of the compensation active layer 22 is set in the area between the first scan line GA1 and the gate T3-g of the driving transistor, and no defects will be caused due to the difference in potential between each other.

[0094] Therefore, the display substrate provided in the embodiment of the present disclosure comprehensively considers the working principle, working state, possible defects, etc. of the sub-pixel driving circuit and the signal line, reasonably arranges the design, improves the resolution, and avoids defects.

[0095] As shown in FIG2 to FIG4, in some embodiments, the compensation transistor includes a first compensation gate T2-g1 and a second compensation gate T2-g2, wherein the orthographic projection of the first compensation gate T2-g1 on the substrate covers the orthographic projection of the first channel portion 221 on the substrate, and the orthographic projection of the second compensation gate T2-g2 on the substrate covers the orthographic projection of the second channel portion 222 on the substrate.

[0096] The first compensation gate T2-g1 is coupled to the corresponding first scan line GA1, and at least a portion of the first compensation gate T2-g1 is located between the coupled first scan line GA1 and the gate T3-g of the driving transistor. The first scan line GA1 is multiplexed as the second compensation gate T2-g2.

[0097] Exemplarily, the first compensation gate T2 - g1 and the second compensation gate T2 - g2 are integrated with the first scan line GA1 to which they are coupled.

[0098] This arrangement enables the compensation transistor to form a dual-gate inverted structure. Specifically, within the same sub-pixel driver circuit layout area, both the first conductor portion 223 and the first compensation gate T2-g1 can be positioned between the first scan line GA1 and the gate T3-g of the driver transistor, effectively reducing the vertical design space occupied by the sub-pixel driver circuit. Furthermore, because the gate T2-g of the compensation transistor is coupled to the first scan line GA1, the first electrode of the compensation transistor is coupled to the second electrode of the driver transistor, and the second electrode of the compensation transistor is coupled to the gate T3-g of the driver transistor—that is, the compensation transistor itself is coupled to both the first scan line GA1 and the driver transistor—positioning at least a portion of the compensation active layer 22 between the first scan line GA1 and the gate T3-g of the driver transistor prevents defects caused by potential differences between them.

[0099] As shown in FIG3, FIG4, and FIG7 to FIG13, in some embodiments, the display substrate further includes a data line DA and a second scan line GA2, the second scan line GA2 includes at least a portion extending along the first direction, and the sub-pixel driving circuit further includes a data writing transistor (i.e., the fourth transistor T4), a gate T4-g of the data writing transistor is coupled to the corresponding second scan line GA2, a first electrode of the data writing transistor is coupled to the corresponding data line DA, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor;

[0100] As shown in FIG3 , in the same sub-pixel, the gate T4 - g of the data writing transistor is located on the side of the first scanning line GA1 facing the gate T3 - g of the driving transistor.

[0101] Exemplarily, the display substrate further includes a plurality of data lines DA and a plurality of second scan lines GA2. The plurality of data lines DA are arranged along the first direction, and the data lines DA include at least a portion extending along the second direction. The plurality of second scan lines GA2 are arranged along the second direction, and the second scan lines GA2 include at least a portion arranged along the first direction.

[0102] Exemplarily, the multiple data lines DA correspond one-to-one to the multiple columns of sub-pixel driving circuits, the data lines DA are respectively coupled to each sub-pixel driving circuit in a corresponding column of sub-pixel driving circuits, and the second scanning line GA2 is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0103] Exemplarily, the first scan line GA1 and the second scan line GA2 are independent of each other and can independently control the transmission of scan signals. The first scan line GA1 controls the on / off switching of the compensation transistor, and the second scan line GA2 controls the on / off switching of the data write transistor. Therefore, the compensation transistor and the data write transistor can be driven independently.

[0104] Exemplarily, the compensation transistor and the data write transistor are driven independently, and the refresh rate and data signal writing are controlled by the data write transistor. The compensation transistor is driven by a group of emission control shift register units (EM GOAs). Since the priority level time of the scanning signal output by the EM GOA is longer, the Vth sampling time can be increased, thereby improving the compensation rate and the low grayscale uniformity of the display substrate.

[0105] In the display substrate provided by the above-described embodiment, the compensation transistor and the data write transistor can be independently controlled, achieving a high compensation rate and uniform low-grayscale display across the display substrate. By arranging the data write transistor's gate T4-g within the same sub-pixel, with the gate T4-g located on the side of the first scan line GA1 facing the gate T3-g of the drive transistor, this not only avoids layout conflicts between the gate T4-g of the data write transistor and the first scan line GA1 but also effectively reduces the vertical design space occupied by the sub-pixel drive circuit, facilitating the development of high-resolution display substrates.

[0106] As shown in FIG2 to FIG4, in some embodiments, the data write transistor includes a data active layer 24, and the gate T4-g of the data write transistor includes a gate body portion T4-g1 and a gate extension portion T4-g2 coupled to each other, wherein the orthographic projection of the gate body portion T4-g1 on the base substrate at least partially overlaps with the orthographic projection of the data active layer 24 on the base substrate, and the gate extension portion T4-g2 is coupled to the corresponding second scan line GA2;

[0107] The gate main body T4-g1 and the gate T3-g of the driving transistor are arranged along a first direction, at least a portion of the gate extension portion T4-g2 and the gate T3-g of the driving transistor are arranged along a second direction, and the first direction intersects with the second direction; the gate main body T4-g1 and the gate extension portion T4-g2 are arranged on the same layer or on different layers.

[0108] Exemplarily, the gate extension portion T4-g2 can serve as a part of the first scan line GA1, that is, the gate extension portion T4-g2 is located in the first source and drain metal layer, or the gate extension portion T4-g2 can also be located in other film layers, for example, in the second gate metal layer.

[0109] Exemplarily, the gate main portion T4-g1 and the gate extension portion T4-g2 are formed as an integral structure. The gate main portion T4-g1 includes at least a portion extending along the first direction, and the gate extension portion T4-g2 includes at least a portion extending along a third direction, wherein the third direction intersects the first direction and the second direction.

[0110] Exemplarily, the orthographic projection of the gate extension portion T4 - g2 on the base substrate does not overlap with the orthographic projection of the data active layer 24 on the base substrate.

[0111] The above-mentioned setting method enables the gate T4-g of the data writing transistor to be arranged around the gate T3-g of the driving transistor, and can be arranged along the boundary extension direction of the gate T3-g of the driving transistor, thereby maximizing the use of the peripheral space of the gate T3-g of the driving transistor, which is conducive to the high-resolution development of the display substrate.

[0112] As shown in Figures 4, 6, 8 and 9, in some embodiments, the sub-pixel driving circuit also includes a first conductive connection portion 31 and a first reset transistor (i.e., a first transistor T1), the first end of the first conductive connection portion 31 is coupled to the gate T3-g of the driving transistor, and the second end of the first conductive connection portion 31 is coupled to the second electrode of the first reset transistor; the second scanning line GA2 is at least partially arranged around the second end of the first conductive connection portion 31.

[0113] Exemplarily, the gate T4-g of the data writing transistor is provided in the same layer and material as the first scan line GA1, the second scan line GA2 is provided in a different layer from the first scan line GA1, and the second scan line GA2 is provided in the same layer and material as the first conductive connection portion 31. The first conductive connection portion 31 is provided in the same layer and material as the first source and drain metal layer in the display substrate.

[0114] The above-mentioned setting of the second scanning line GA2 at least partially surrounds the second end of the first conductive connection part 31, so that the second scanning line GA2 can bypass the first conductive connection part 31, which not only avoids the short circuit between the second scanning line GA2 and the first conductive connection part 31, but also enables the second scanning line GA2 to maintain a suitable safety distance from the first conductive connection part, thereby avoiding the jump of the scanning signal transmitted on the second scanning line GA2 from affecting the potential of the first conductive connection part 31, thereby ensuring the working stability and reliability of the sub-pixel driving circuit.

[0115] As shown in Figures 4, 6, 7, 8 and 9, in some embodiments, the second scan line GA2 includes a plurality of straight-side portions GA21 and a plurality of curved-side portions GA22, the straight-side portions GA21 and the curved-side portions GA22 are alternately arranged along a first direction, the curved-side portion GA22 is arranged around the second end of the first conductive connection portion 31, the straight-side portion GA21 includes a protruding end GA21-T, at least a portion of the orthographic projection of the protruding end GA21-T on the substrate is arranged along the second direction with the orthographic projection of the gate T3-g of the driving transistor on the substrate, and the protruding end GA21-T is coupled to the gate T4-g of the data writing transistor.

[0116] Illustratively, the adjacent straight side portions GA21 and the curved side portions GA22 are coupled, and the straight side portions GA21 and the curved side portions GA22 form an integral structure.

[0117] Exemplarily, the curved edge portion GA22 half surrounds the second end of the first conductive connection portion 31. The straight edge portion GA21 includes at least a portion extending along the first direction. The first conductive connection portion 31 includes at least a portion extending along the second direction.

[0118] Illustratively, at least a portion of the orthographic projection of the protruding end GA21-T on the base substrate is located between the orthographic projection of the curved edge portion GA22 on the base substrate and the orthographic projection of the gate T3-g of the driving transistor on the base substrate.

[0119] Exemplarily, the orthographic projection of the protruding end GA21-T on the base substrate has an overlapping area with the orthographic projection of the gate extension portion T4-g2 on the base substrate, and in the overlapping area, the protruding end GA21-T and the gate extension portion T4-g2 are coupled through a via.

[0120] This arrangement enables the curved edge GA22 of the second scan line GA2 to form a "gate"-like routing pattern, preventing the transition of the scan signal transmitted on the second scan line GA2 from affecting the potential of the first conductive connection portion 31, thereby ensuring the operational stability and reliability of the sub-pixel driving circuit. It also ensures electrical connection between the second scan line GA2 and the gate T4-g of the data write transistor.

[0121] As shown in Figures 8 and 12, in some embodiments, the display substrate includes a reset signal line RST, the gate of the first reset transistor is coupled to the corresponding reset signal line RST, the orthographic projection of the curved edge portion GA22 on the base substrate overlaps with the orthographic projection of the reset signal line RST on the base substrate; and / or, the orthographic projection of the curved edge portion GA22 on the base substrate overlaps with the orthographic projection of the first scanning line GA1 on the base substrate.

[0122] Exemplarily, the display substrate includes a plurality of reset signal lines RST, the plurality of reset signal lines RST being arranged along the second direction, and the reset signal lines RST including at least a portion extending along the first direction. The plurality of reset signal lines RST correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the reset signal line RST is respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits.

[0123] Exemplarily, the overlapping area between the orthographic projection of the curved edge portion GA22 on the base substrate and the orthographic projection of the reset signal line RST on the base substrate is less than or equal to 10% of the area of ​​the curved edge portion GA22. Furthermore, the overlapping area between the orthographic projection of the curved edge portion GA22 on the base substrate and the orthographic projection of the reset signal line RST on the base substrate can be set to be less than or equal to 5% of the area of ​​the curved edge portion GA22.

[0124] Exemplarily, the overlapping area between the orthographic projection of the curved edge portion GA22 on the base substrate and the orthographic projection of the first scan line GA1 on the base substrate is less than or equal to 30% of the area of ​​the curved edge portion GA22. Furthermore, the overlapping area between the orthographic projection of the curved edge portion GA22 on the base substrate and the orthographic projection of the first scan line GA1 on the base substrate can be set to be less than or equal to 20% of the area of ​​the curved edge portion GA22.

[0125] The above configuration can avoid crosstalk between the second scan line GA2 and the reset signal line RST, and avoid crosstalk between the second scan line GA2 and the first scan line GA1 to the greatest extent.

[0126] As shown in Figures 7, 8, 10 and 11, in some embodiments, the display substrate further includes a power line VDD, and the orthographic projection of the power line VDD on the base substrate has a first overlapping area with the orthographic projection of the first conductive connection portion 31 on the base substrate, and the first overlapping area is greater than or equal to 80% of the area of ​​the first conductive connection portion 31.

[0127] Exemplarily, the first overlapping area is greater than or equal to 90% of the area of ​​the first conductive connection portion 31 .

[0128] Exemplarily, the display substrate includes a plurality of power lines VDD, the plurality of power lines VDD being arranged along the first direction, and the power lines VDD including at least a portion extending along the second direction. The plurality of power lines VDD correspond one-to-one to the plurality of columns of sub-pixel driver circuits, and the power lines VDD are respectively coupled to each sub-pixel driver circuit in a corresponding column of sub-pixel driver circuits.

[0129] Exemplarily, the power line VDD is provided in the same layer and with the same material as the source / drain metal layer in the display substrate.

[0130] The above-mentioned setting of the first overlapping area being greater than or equal to 80% of the area of ​​the first conductive connection portion 31 enables the power line VDD to better shield the potential on the first conductive connection portion 31 (i.e., the potential of the N1 node). Therefore, in the display substrate provided by the above embodiment, through a reasonable layout, the power line VDD can better shield the potential of the N1 node, thereby reducing the risk of crosstalk in the sub-pixel driving circuit during the display process.

[0131] As shown in Figures 10 to 12, in some embodiments, the display substrate further includes a first initialization signal line Vinit1, which includes at least a portion extending along the second direction; the first electrode of the first reset transistor is coupled to the first initialization signal line Vinit1.

[0132] Exemplarily, the display substrate includes a plurality of first initialization signal lines Vinit1, the plurality of first initialization signal lines Vinit1 being arranged along a first direction, and the first initialization signal lines Vinit1 including at least a portion extending along a second direction. The first initialization signal lines Vinit1 correspond one-to-one with multiple columns of sub-pixel driver circuits, and the first initialization signal lines Vinit1 are respectively coupled to each sub-pixel driver circuit in a corresponding column of sub-pixel driver circuits.

[0133] Illustratively, the orthographic projection of the first initialization signal line Vinit1 on the substrate is located between the orthographic projection of the gate electrode T3-g of the drive transistor and the orthographic projection of the data line DA on the substrate. Routing the first initialization signal line Vinit1 in this manner can shield the N1 node from crosstalk caused by transitions of the data signal transmitted on the data line DA.

[0134] Exemplarily, the display substrate further includes a power line VDD and a first initialization signal line Vinit1. The power line VDD and the data line DA are provided in the same layer and material, and the first initialization signal line Vinit1 is located between the power line VDD and the data line DA. For example, the first initialization signal line Vinit1 is provided in the same layer and material as a second source / drain metal layer in the display substrate.

[0135] Exemplarily, the overlap area between the orthographic projection of the power line VDD on the substrate and the underlying metal layers (e.g., the light shielding layer LS, the first gate metal layer, the second gate metal layer, and the first source / drain metal layer) is greater than or equal to 50% of the area of ​​the power line VDD. Furthermore, the overlap area between the orthographic projection of the power line VDD on the substrate and the underlying metal layers can be set to be greater than or equal to 70% of the area of ​​the power line VDD, but is not limited to this. This configuration is beneficial for improving the transmittance of high-resolution display substrates.

[0136] As shown in Figures 4 to 11, in some embodiments, the display substrate further includes a second initialization signal line Vinit2, a third initialization signal line Vinit3 and a third scan line GA3, and the third scan line GA3 includes at least a portion extending along the first direction; the sub-pixel further includes a light-emitting element; the sub-pixel driving circuit further includes a second reset transistor (i.e., a seventh transistor T7) and a third reset transistor (i.e., an eighth transistor T8), and the gate of the second reset transistor and the gate of the third reset transistor are both coupled to the corresponding same third scan line GA3; the first electrode of the second reset transistor is coupled to the second initialization signal line Vinit2, and the second electrode of the second reset transistor is coupled to the anode Ano of the light-emitting element; the first electrode of the third reset transistor is coupled to the third initialization signal line Vinit3, and the second electrode of the third reset transistor is coupled to the first electrode of the driving transistor.

[0137] Exemplarily, the display substrate further includes a plurality of second initialization signal lines Vinit2, the plurality of second initialization signal lines Vinit2 being arranged along a second direction, and the second initialization signal lines Vinit2 including at least a portion extending along the first direction. The plurality of second initialization signal lines Vinit2 correspond one-to-one to the plurality of rows of sub-pixel driver circuits, and the second initialization signal lines Vinit2 are respectively coupled to each second reset transistor in a corresponding row of sub-pixel driver circuits.

[0138] Exemplarily, the display substrate further includes a plurality of third initialization signal lines Vinit3, the plurality of third initialization signal lines Vinit3 being arranged along the second direction, and the third initialization signal lines Vinit3 including at least a portion extending along the first direction. The plurality of third initialization signal lines Vinit3 correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the third initialization signal lines Vinit3 are respectively coupled to each third reset transistor in a corresponding row of sub-pixel driving circuits.

[0139] Exemplarily, the display substrate further includes a plurality of third scan lines GA3, the plurality of third scan lines GA3 being arranged along the second direction, and the third scan lines GA3 including at least a portion extending along the first direction. The plurality of third scan lines GA3 are coupled to the plurality of rows of sub-pixel driver circuits, and the third scan lines GA3 are respectively coupled to the gates of the second reset transistors and the gates of the third reset transistors in a corresponding row of sub-pixel driver circuits.

[0140] The second initialization signal line Vinit2 transmits a second initialization signal to reset the anode of the light-emitting element (i.e., node N4), ensuring sub-pixel brightness during low grayscale display. The second initialization signal line Vinit2 is provided in the same layer and material as the first source and drain metal layer in the display substrate, thereby improving the conductivity of the second initialization signal line Vinit2 and facilitating display uniformity across the display substrate.

[0141] In some embodiments, the second scan line and the first scan line are arranged in different layers, and the orthographic projection of the second scan line on the base substrate at least partially overlaps with the orthographic projection of the first scan line on the base substrate.

[0142] Exemplarily, the display substrate includes a second gate metal layer and a first source / drain metal layer, the second initialization signal line is provided in the same layer and material as the first source / drain metal layer, and the third initialization signal line is provided in the same layer and material as the second gate metal layer.

[0143] The second initialization signal line and the third initialization signal line are made of different layers of metal. In this way, the second initialization signal line and the third initialization signal line, both of which are used to transmit constant voltage signals, can adopt a stacked routing design, that is, the orthographic projection of the second initialization signal line on the base substrate and the orthographic projection of the third initialization signal line on the base substrate at least partially overlap, which is beneficial to improving the transmittance of the display substrate.

[0144] As shown in FIG2 , FIG4 , FIG6 and FIG8 , in some embodiments, the display substrate further includes a power supply line VDD; the first reset transistor includes a first reset active layer 21, the first reset active layer 21 includes a third channel portion 213, a fourth channel portion 214 and a second conductor portion 215, and the second conductor portion 215 is coupled to the third channel portion 213 and the fourth channel portion 214, respectively;

[0145] The orthographic projection of the second conductor portion 215 on the base substrate at least partially overlaps with the orthographic projection of the second initialization signal line Vinit2 on the base substrate; and / or, the orthographic projection of the second conductor portion 215 on the base substrate at least partially overlaps with the orthographic projection of the third initialization signal line Vinit3 on the base substrate; and / or, the orthographic projection of the second conductor portion 215 on the base substrate at least partially overlaps with the orthographic projection of the power line VDD on the base substrate.

[0146] Exemplarily, the first reset transistor comprises a dual-gate transistor, wherein the orthographic projection of the gate of the first reset transistor on the substrate overlaps the orthographic projection of the third channel portion 213 on the substrate, and overlaps the orthographic projection of the fourth channel portion 214 on the substrate. The second conductor portion 215 forms an integral structure with the third channel portion 213 and the fourth channel portion 214. Exemplarily, the second conductor portion 215 forms an n-type structure with the third channel portion 213 and the fourth channel portion 214, and the third channel portion 213 and the fourth channel portion 214 are arranged along the first direction.

[0147] The above configuration enables the second conductor portion 215 to be shielded by the second initialization signal line Vinit2 and / or the third initialization signal line Vinit3, which is beneficial to improving the working stability of the first reset transistor.

[0148] As shown in FIG2 , FIG5 and FIG6 , in some embodiments, the display substrate further includes a power line VDD and a first conductive connection portion 31, wherein a first end of the first conductive connection portion 31 is coupled to the gate T3-g of the driving transistor, and a second end of the first conductive connection portion 31 is coupled to the second electrode of the compensation transistor; the sub-pixel driving circuit further includes a storage capacitor Cst, wherein a first plate Cst1 of the storage capacitor Cst is coupled to the gate T3-g of the driving transistor, and a second plate Cst2 of the storage capacitor Cst is coupled to the corresponding power line VDD;

[0149] The compensation active layer 22 further includes a conductor extension 224, the conductor extension 224 is coupled to the first conductor portion 223, and the orthographic projection of the conductor extension 224 on the substrate at least partially overlaps with the orthographic projection of the second electrode Cst2 on the substrate; and / or,

[0150] The orthographic projection of the first conductor portion 223 on the substrate does not overlap with the orthographic projection of the first conductive connection portion 31 on the substrate; and / or,

[0151] The orthographic projection of the second electrode plate Cst2 on the base substrate at least partially overlaps with the orthographic projection of the first conductor portion 223 on the base substrate.

[0152] Illustratively, an orthographic projection of the first electrode plate Cst1 on the base substrate at least partially overlaps with an orthographic projection of the second electrode plate Cst2 on the base substrate.

[0153] Exemplarily, the conductor extension portion 224 and the first conductor portion 223 form an integral structure.

[0154] Illustratively, the orthographic projection of the conductor extension portion 224 on the base substrate is located between the orthographic projection of the first conductor portion 223 on the base substrate and the orthographic projection of the gate T3 - g of the driving transistor on the base substrate.

[0155] The above-mentioned setting method increases the capacitance formed by the first conductor part 223, which is beneficial to improving the capacitance formed by the first conductor part 223 during the light-emitting stage, and at the same time can increase the stability of the node voltage of the first conductor part 223, and can effectively improve the low-frequency flicker problem.

[0156] As shown in Figures 1, 2 and 13, in some embodiments, the display substrate further includes a light-shielding layer LS, and the orthographic projection of the light-shielding layer LS on the base substrate at least partially overlaps with the orthographic projection of the active layer 23 of the driving transistor on the base substrate, and at least partially overlaps with the orthographic projection of the compensation active layer 22 on the base substrate.

[0157] Exemplarily, the light shielding layer LS is connected to a power signal and is located between the active layer and the base substrate.

[0158] The above configuration enables the light-shielding layer LS to block and shield the active layer 23 of the driving transistor and the compensation active layer 22 , thereby facilitating improvement of the working stability of the driving transistor and the compensation transistor.

[0159] Exemplarily, the overlapping area between the orthographic projection of the light-shielding layer LS on the base substrate and the orthographic projection of the metal layer in the display substrate on the base substrate is greater than or equal to 60% of the area of ​​the light-shielding layer LS. Furthermore, the overlapping area between the orthographic projection of the light-shielding layer LS on the base substrate and the orthographic projection of the metal layer in the display substrate on the base substrate can be greater than or equal to 80% of the area of ​​the light-shielding layer LS. This configuration is beneficial for improving the optical transmittance of the display substrate.

[0160] As shown in FIG4 , in some embodiments, the sub-pixel driving circuit further includes a power control transistor (i.e., a fifth transistor T5) and a light emission control transistor (i.e., a sixth transistor T6). The display substrate further includes a plurality of light emission control signal lines EM, the plurality of light emission control signal lines EM being arranged along the second direction, and the light emission control signal lines EM including at least a portion extending along the first direction. The plurality of light emission control signal lines EM correspond one-to-one to the plurality of rows of sub-pixel driving circuits, and the light emission control signal lines EM are respectively coupled to each power control transistor and each light emission control transistor in a corresponding row of sub-pixel driving circuits.

[0161] As shown in Figures 12, 13, 16, 17, and 18, in some embodiments, the sub-pixel further includes a light-emitting element, and the light-emitting element includes an anode Ano; the sub-pixel driving circuit further includes a light-emitting control transistor and a second conductive connection portion 32, wherein a first electrode of the light-emitting control transistor is coupled to a second electrode of the driving transistor, a first end of the second conductive connection portion 32 is coupled to the second electrode of the light-emitting control transistor, and a second end of the second conductive connection portion 32 is coupled to the anode Ano through a first via Via1;

[0162] The sub-pixel further includes a pixel opening area 40 , and an orthographic projection of the pixel opening area 40 on the base substrate does not overlap with an orthographic projection of the first via hole Via1 on the base substrate.

[0163] Exemplarily, the display substrate includes a pixel defining layer, and the pixel defining layer defines the pixel opening area 40 .

[0164] The above-mentioned arrangement that the orthographic projection of the pixel opening area 40 on the base substrate does not overlap with the orthographic projection of the first via hole Via1 on the base substrate is beneficial for improving the flatness of the anode Ano in the sub-pixel, thereby improving the display uniformity of the display substrate.

[0165] As shown in Figures 2, 4, 17 and 18, in some embodiments, the sub-pixel further includes a light-emitting element, and the light-emitting element includes an anode Ano; the anode Ano in at least some of the sub-pixels includes an anode main portion Ano1 and an anode virtual portion Ano2; the orthographic projection of the anode main portion Ano1 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the sub-pixel to which it belongs on the substrate; the orthographic projection of the anode virtual portion Ano2 on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the sub-pixel adjacent to it along the first direction on the substrate.

[0166] Exemplarily, the anode main portion Ano1 and the anode dummy portion Ano2 are formed into an integrated structure.

[0167] Illustratively, the orthographic projection of the anode main portion Ano1 on the base substrate at least partially overlaps with the orthographic projection of the first conductor portion 223 in the compensation active layer 22 included in the sub-pixel to which it belongs on the base substrate. The orthographic projection of the anode main portion Ano1 on the base substrate at least partially overlaps with the orthographic projection of the first channel portion 221 in the compensation active layer 22 included in the sub-pixel to which it belongs on the base substrate. The orthographic projection of the anode main portion Ano1 on the base substrate at least partially overlaps with the orthographic projection of the second channel portion 222 in the compensation active layer 22 included in the sub-pixel to which it belongs on the base substrate.

[0168] Illustratively, the orthographic projection of the anode dummy portion Ano2 on the base substrate at least partially overlaps with the orthographic projection of the first conductor portion 223 in the compensation active layer 22 included in the sub-pixel adjacent to it along the first direction on the base substrate. The orthographic projection of the anode dummy portion Ano2 on the base substrate at least partially overlaps with the orthographic projection of the first channel portion 221 in the compensation active layer 22 included in the sub-pixel adjacent to it along the first direction on the base substrate. The orthographic projection of the anode dummy portion Ano2 on the base substrate at least partially overlaps with the orthographic projection of the second channel portion 222 in the compensation active layer 22 included in the sub-pixel adjacent to it along the first direction on the base substrate.

[0169] In the display substrate provided by the above embodiment, the corresponding compensation active layer 22 is shielded by the anode main portion Ano1 and the anode dummy portion Ano2, which can effectively prevent the display substrate from displaying abnormalities under strong light.

[0170] In some embodiments, the display substrate includes red sub-pixels, green sub-pixels, and blue sub-pixels; the at least some sub-pixels include red sub-pixels and blue sub-pixels, and the adjacent sub-pixels include green sub-pixels.

[0171] Illustratively, the orthographic projection of the anode main portion Ano1 in the red sub-pixel on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the sub-pixel to which it belongs on the substrate; the orthographic projection of the anode virtual portion Ano2 in the red sub-pixel on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the green sub-pixel adjacent to it along the first direction on the substrate.

[0172] Illustratively, the orthographic projection of the anode main portion Ano1 in the blue sub-pixel on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the sub-pixel to which it belongs on the substrate; the orthographic projection of the anode virtual portion Ano2 in the blue sub-pixel on the substrate at least partially overlaps with the orthographic projection of the compensation active layer 22 included in the green sub-pixel adjacent to it along the first direction on the substrate.

[0173] As shown in FIG21 , the display substrate exemplarily includes a buffer layer BF, an active layer poly, a first gate insulating layer GI1, a first gate metal layer gate1, a second gate insulating layer GI2, a second gate metal layer gate2, an interlayer insulating layer ILD, a first source / drain metal layer SD1, a first planarizing layer PLN1, a second source / drain metal layer SD2, a second planarizing layer PLN2, an anode layer ANO, a light-emitting functional layer EL, a cathode layer cath, a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2, which are sequentially stacked in a direction away from the base substrate 70. The display substrate may further include, but is not limited to, a passivation layer PVX.

[0174] As shown in FIG. 2 , FIG. 2 illustrates an active layer 25 of the power control transistor, an active layer 26 of the light emission control transistor, an active layer 27 of the second reset transistor, and an active layer 28 of the third reset transistor.

[0175] As shown in FIG. 7 and FIG. 14 to FIG. 16 , FIG. 7 illustrates a third conductive connection portion 33 , a fourth conductive connection portion 34 , a fifth conductive connection portion 35 , a sixth conductive connection portion 36 , a seventh conductive connection portion 37 and an eighth conductive connection portion 38 .

[0176] The third conductive connection portion 33 is coupled to the second plate Cst2 of the storage capacitor Cst through the ninth via Via9, the third conductive connection portion 33 is coupled to the second electrode of the power control transistor through the twelfth via Via12, and the third conductive connection portion 33 is coupled to the power line VDD through the fifteenth via Via15.

[0177] The fourth conductive connection portion 34 is coupled to the first electrode of the driving transistor through the tenth via hole Via10 , and the fourth conductive connection portion 34 is coupled to the second electrode of the third reset transistor through the thirteenth via hole Via13 .

[0178] The fifth conductive connection part 35 is coupled to the second electrode of the light emitting control transistor through the eleventh via Via11, the fifth conductive connection part 35 is coupled to the second conductive connection part 32 through the eighteenth via Via18, and the second conductive connection part 32 is coupled to the anode corresponding to the first via Via1.

[0179] The sixth conductive connection portion 36 is coupled to the first electrode of the data writing transistor through the seventh via hole Via7 , and the sixth conductive connection portion 36 is coupled to the data line DA through the seventeenth via hole Via17 .

[0180] The seventh conductive connection portion 37 is coupled to the first electrode of the first reset transistor through the fourth via Via4 , and the seventh conductive connection portion 37 is coupled to the first initialization signal line Vinit1 through the sixteenth via Via16 .

[0181] The eighth conductive connection portion 38 is coupled to the third initialization signal line Vinit3 through the second via Via2 , and the eighth conductive connection portion 38 is coupled to the first electrode of the eighth transistor T8 through the third via Via3 .

[0182] The first conductive connection portion 31 is coupled to the second electrode of the first reset transistor through the fifth via hole Via5 , and the first conductive connection portion 31 is coupled to the gate electrode T3 - g of the driving transistor through the eighth via hole Via8 .

[0183] The gate T4 - g of the data writing transistor is coupled to the second scan line GA2 through a sixth via hole Via6 .

[0184] A first electrode of the second reset transistor is coupled to the second initialization signal line Vinit2 through a fourteenth via hole Via14 .

[0185] The present disclosure also provides a display substrate, comprising: a base substrate, and a plurality of sub-pixels, a second scan line, and a data line, each of which is disposed on the base substrate, wherein the second scan line includes at least a portion extending along a first direction, the sub-pixels include a sub-pixel driving circuit, and the sub-pixel driving circuit includes a first conductive connection portion, a driving transistor, a compensation transistor, and a data writing transistor;

[0186] The first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor via the first conductive connection portion. The compensation transistor includes a compensation active layer, the compensation active layer includes a first channel portion, a second channel portion, and a first conductor portion, the first conductor portion being coupled to the first channel portion and the second channel portion, respectively. At least a portion of an orthographic projection of the first conductor portion on the substrate is located between an orthographic projection of the second scan line on the substrate and an orthographic projection of the gate of the driving transistor on the substrate.

[0187] The gate of the data writing transistor is coupled to the corresponding second scanning line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; at least a portion of the second scanning line is arranged around one end of the first conductive connection portion.

[0188] According to the specific structure of the above-mentioned display substrate, in the display substrate provided by the embodiment of the present disclosure, at least a portion of the orthographic projection of the first conductor portion on the base substrate is arranged to be located between the orthographic projection of the second scan line on the base substrate and the orthographic projection of the gate of the driving transistor on the base substrate; compared with the conventional layout method, the above-mentioned arrangement method enables the compensation transistor to form a dual-gate inverted structure, that is, within the same sub-pixel driving circuit layout area, the first conductor portion and the first compensation gate can both be arranged in the area between the second scan line and the gate of the driving transistor, effectively compressing the vertical design space occupied by the sub-pixel driving circuit, which is conducive to the high-resolution development of the display substrate.

[0189] In the display substrate provided by the embodiment of the present disclosure, at least a portion of the second scan line is arranged around one end of the first conductive connection portion, so that the second scan line can bypass the first conductive connection portion, which not only avoids a short circuit between the second scan line and the first conductive connection portion, but also enables the second scan line to maintain a suitable safety distance from the first conductive connection portion, thereby avoiding the jump of the scan signal transmitted on the second scan line from affecting the potential of the first conductive connection portion, thereby ensuring the working stability and reliability of the sub-pixel driving circuit.

[0190] In some embodiments, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second plate on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate; and / or,

[0191] An orthographic projection of the first conductor portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate.

[0192] The above configuration is beneficial for improving the capacitance formed by the first conductor part during the light-emitting stage, while increasing the stability of the node voltage of the first conductor part and the voltage stability of the first conductive connection part, and can effectively improve the low-frequency flicker problem.

[0193] In some embodiments, the display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second plate on the base substrate at least partially overlaps with an orthographic projection of the first conductor portion on the base substrate; and / or,

[0194] The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate; and / or,

[0195] The orthographic projection of the first conductor portion on the substrate at least partially overlaps with the orthographic projection of the power line on the substrate; and / or,

[0196] The orthographic projection of the first conductive connection portion on the base substrate at least partially overlaps with the orthographic projection of the power line on the base substrate.

[0197] It is worth noting that the specific structure of the first conductive connection part 31 in the above embodiment can be seen in FIG22 , but is not limited to this structure.

[0198] The above configuration is beneficial for improving the capacitance formed by the first conductor part during the light-emitting stage, while increasing the stability of the node voltage of the first conductor part and the voltage stability of the first conductive connection part, and can effectively improve the low-frequency flicker problem.

[0199] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0200] In the display substrate provided in the above embodiment, the compensation transistor includes a compensation active layer. At least a portion of the orthographic projection of the first conductor portion of the compensation active layer on the base substrate is located between the orthographic projection of the first scan line on the base substrate and the orthographic projection of the gate of the drive transistor on the base substrate. Compared to conventional layouts, this arrangement enables the compensation transistor to form a dual-gate inverted structure. That is, within the same sub-pixel drive circuit layout area, the first conductor portion and the first compensation gate can both be located in the area between the first scan line and the gate of the drive transistor. This effectively reduces the vertical design space occupied by the sub-pixel drive circuit and facilitates the development of high-resolution display substrates. Furthermore, because the gate of the compensation transistor is coupled to the first scan line, the first electrode of the compensation transistor is coupled to the second electrode of the drive transistor, and the second electrode of the compensation transistor is coupled to the gate of the drive transistor, that is, the compensation transistor itself is coupled to both the first scan line and the drive transistor. Therefore, arranging at least a portion of the compensation active layer in the area between the first scan line and the gate of the drive transistor does not cause defects due to the difference in potential between them. Therefore, the display substrate provided in the above embodiment comprehensively considers the working principle, working state, possible defects, etc. of the sub-pixel driving circuit and the signal line, and reasonably arranges the design, improves the resolution, and avoids defects.

[0201] The display device provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when it includes the above-mentioned display substrate, which will not be described in detail here.

[0202] It should be noted that the signal line extending along the X-direction means that the signal line includes a main portion and a secondary portion connected to the main portion, the main portion is a line, a line segment, or a strip-shaped body, the main portion extends along the X-direction, and the length of the main portion extending along the X-direction is greater than the length of the secondary portion extending along other directions.

[0203] It should be noted that the display device can be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, a tablet computer, etc., wherein the display device also includes a flexible circuit board, a printed circuit board and a backplane.

[0204] It should be noted that the layout area occupied by the sub-pixel driving circuit may be an area that can accommodate the sub-pixel driving circuit. Exemplarily, the area may be a rectangular area, but is not limited thereto.

[0205] It should be noted that the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer. Or, for example, a film layer in the same layer may be a film layer formed by using the same film forming process to form a specific pattern, and then patterning the film layer using the same mask through a single composition process to form a layer structure. Depending on the specific pattern, a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

[0206] In the various method embodiments of the present disclosure, the serial numbers of the steps cannot be used to limit the order of the steps. For ordinary technicians in this field, without paying any creative work, changes to the order of the steps are also within the scope of protection of the present disclosure.

[0207] It should be noted that the various embodiments in this specification are described in a progressive manner. Similar parts between the various embodiments can be referred to in conjunction with each other. Each embodiment focuses on the differences from other embodiments. In particular, the method embodiments are described briefly because they are generally similar to the product embodiments. For relevant parts, refer to the description of the product embodiments.

[0208] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect", "couple" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0209] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0210] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0211] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A base substrate and a plurality of sub-pixels and a first scan line each disposed on the base substrate, wherein the first scan line includes at least a portion extending along a first direction, the sub-pixel includes a sub-pixel driving circuit, the sub-pixel driving circuit includes a driving transistor and a compensation transistor, a gate of the compensation transistor is coupled to the corresponding first scan line, a first electrode of the compensation transistor is coupled to a second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor; The compensation transistor includes a compensation active layer, and the compensation active layer includes a first channel portion, a second channel portion and a first conductor portion, wherein the first conductor portion is coupled to the first channel portion and the second channel portion, respectively; at least a portion of an orthographic projection of the first conductor portion on the substrate is located between an orthographic projection of the first scan line on the substrate and an orthographic projection of the gate of the driving transistor on the substrate.

2. The display substrate according to claim 1, wherein: The compensation transistor comprises a first compensation gate and a second compensation gate, wherein the orthographic projection of the first compensation gate on the substrate covers the orthographic projection of the first channel portion on the substrate, and the orthographic projection of the second compensation gate on the substrate covers the orthographic projection of the second channel portion on the substrate; The first compensation gate is coupled to the corresponding first scan line, at least a portion of the first compensation gate is located between the first scan line coupled thereto and the gate of the driving transistor, and the first scan line is multiplexed as the second compensation gate.

3. The display substrate according to claim 1, wherein: The display substrate further includes a data line and a second scan line, the second scan line includes at least a portion extending along the first direction, the sub-pixel driving circuit further includes a data writing transistor, a gate of the data writing transistor is coupled to the corresponding second scan line, a first electrode of the data writing transistor is coupled to the corresponding data line, and a second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; In the same sub-pixel, the gate of the data writing transistor is located on a side of the first scanning line facing the gate of the driving transistor.

4. The display substrate according to claim 3, wherein: The data writing transistor comprises a data active layer, the gate of the data writing transistor comprises a gate main body and a gate extension part coupled to each other, the orthographic projection of the gate main body on the base substrate at least partially overlaps with the orthographic projection of the data active layer on the base substrate, and the gate extension part is coupled to the corresponding second scanning line; The gate main body and the gate of the driving transistor are arranged along a first direction, at least a portion of the gate extension portion and the gate of the driving transistor are arranged along a second direction, and the first direction intersects with the second direction; The gate main body and the gate extension are arranged in the same layer or in different layers.

5. The display substrate according to claim 3, wherein: The sub-pixel driving circuit also includes a first conductive connection portion and a first reset transistor, wherein the first end of the first conductive connection portion is coupled to the gate of the driving transistor, and the second end of the first conductive connection portion is coupled to the second electrode of the first reset transistor; the second scanning line is at least partially arranged around the second end of the first conductive connection portion.

6. The display substrate according to claim 5, wherein: The gate of the data writing transistor is provided at the same layer and material as the first scanning line, the second scanning line is provided at a different layer from the first scanning line, and the second scanning line is provided at the same layer and material as the first conductive connecting portion.

7. The display substrate according to claim 5, wherein: The second scan line includes a plurality of straight-side portions and a plurality of curved-side portions, the straight-side portions and the curved-side portions are alternately arranged along a first direction, the curved-side portions are arranged around the second end of the first conductive connection portion, the straight-side portions include a protruding end, at least a portion of an orthographic projection of the protruding end on the substrate is arranged along the second direction with an orthographic projection of the gate of the driving transistor on the substrate, and the protruding end is coupled to the gate of the data writing transistor.

8. The display substrate according to claim 5, wherein: The display substrate further includes a first initialization signal line, the first initialization signal line includes at least a portion extending along the second direction; a first electrode of the first reset transistor is coupled to the first initialization signal line; The orthographic projection of the first initialization signal line on the base substrate is located between the orthographic projection of the gate of the driving transistor on the base substrate and the orthographic projection of the data line on the base substrate.

9. The display substrate according to claim 8, wherein: The display substrate further includes a power line and the first initialization signal line. The power line and the data line are provided in the same layer and material, and the first initialization signal line is located between the power line and the data line.

10. The display substrate according to claim 5, wherein: The display substrate also includes a second initialization signal line, a third initialization signal line and a third scan line, the third scan line includes at least a portion extending along the first direction; the sub-pixel also includes a light-emitting element; the sub-pixel driving circuit also includes a second reset transistor and a third reset transistor, the gate of the second reset transistor and the gate of the third reset transistor are both coupled to the corresponding same third scan line; the first electrode of the second reset transistor is coupled to the second initialization signal line, and the second electrode of the second reset transistor is coupled to the anode of the light-emitting element; the first electrode of the third reset transistor is coupled to the third initialization signal line, and the second electrode of the third reset transistor is coupled to the first electrode of the driving transistor.

11. The display substrate according to claim 10, wherein: The second scanning line and the first scanning line are arranged in different layers, and the orthographic projection of the second scanning line on the substrate at least partially overlaps with the orthographic projection of the first scanning line on the substrate; The display substrate comprises a second gate metal layer and a first source-drain metal layer, the second initialization signal line is provided in the same layer and material as the first source-drain metal layer, and the third initialization signal line is provided in the same layer and material as the second gate metal layer.

12. The display substrate according to claim 10, wherein: The display substrate further includes a power supply line; the first reset transistor includes a first reset active layer, the first reset active layer includes a third channel portion, a fourth channel portion and a second conductor portion, and the second conductor portion is coupled to the third channel portion and the fourth channel portion respectively; The orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the second initialization signal line on the substrate; And / or, the orthographic projection of the second conductor portion on the substrate at least partially overlaps with the orthographic projection of the third initialization signal line on the substrate; And / or, an orthographic projection of the second conductor portion on the substrate at least partially overlaps with an orthographic projection of the power line on the substrate.

13. The display substrate according to claim 1, wherein: The display substrate further includes a power line and a first conductive connection portion, wherein a first end of the first conductive connection portion is coupled to a gate of the driving transistor, and a second end of the first conductive connection portion is coupled to a second electrode of the compensation transistor; the sub-pixel driving circuit further includes a storage capacitor, wherein a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to a corresponding power line; The compensation active layer further includes a conductor extension portion, the conductor extension portion is coupled to the first conductor portion, and an orthographic projection of the conductor extension portion on the substrate at least partially overlaps with an orthographic projection of the second electrode plate on the substrate; and / or, The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate; and / or, The orthographic projection of the second electrode plate on the substrate at least partially overlaps with the orthographic projection of the first conductor portion on the substrate.

14. The display substrate according to claim 1, wherein: The display substrate further includes a shading layer, the orthographic projection of the shading layer on the base substrate at least partially overlaps with the orthographic projection of the active layer of the driving transistor on the base substrate, and at least partially overlaps with the orthographic projection of the compensation active layer on the base substrate.

15. The display substrate according to claim 1, wherein: The sub-pixel further includes a light-emitting element, and the light-emitting element includes an anode; the sub-pixel driving circuit further includes a light-emitting control transistor and a second conductive connection portion, a first electrode of the light-emitting control transistor is coupled to a second electrode of the driving transistor, a first end of the second conductive connection portion is coupled to a second electrode of the light-emitting control transistor, and a second end of the second conductive connection portion is coupled to the anode through a first via hole; The sub-pixel further includes a pixel opening area, and an orthographic projection of the pixel opening area on the base substrate does not overlap with an orthographic projection of the first via hole on the base substrate.

16. The display substrate according to claim 1, wherein: The sub-pixel further includes a light-emitting element, wherein the light-emitting element includes an anode; the anode in at least some of the sub-pixels includes an anode main portion and an anode dummy portion; The orthographic projection of the anode main body on the base substrate at least partially overlaps with the orthographic projection of the compensation active layer included in the sub-pixel to which it belongs on the base substrate; An orthographic projection of the anode dummy portion on the base substrate at least partially overlaps with an orthographic projection of a compensation active layer included in a sub-pixel adjacent to the anode dummy portion along the first direction on the base substrate.

17. The display substrate according to claim 16, wherein: The display substrate includes a red sub-pixel, a green sub-pixel and a blue sub-pixel; at least part of the sub-pixels include a red sub-pixel and a blue sub-pixel, and the adjacent sub-pixels include a green sub-pixel.

18. A display substrate, comprising: A base substrate and a plurality of sub-pixels, a second scan line, and a data line all disposed on the base substrate, wherein the second scan line includes at least a portion extending along a first direction, the sub-pixel includes a sub-pixel driving circuit, and the sub-pixel driving circuit includes a first conductive connection portion, a driving transistor, a compensation transistor, and a data writing transistor; The first electrode of the compensation transistor is coupled to the second electrode of the driving transistor, and the second electrode of the compensation transistor is coupled to the gate of the driving transistor through the first conductive connection portion; the compensation transistor includes a compensation active layer, and the compensation active layer includes a first channel portion, a second channel portion and a first conductor portion, and the first conductor portion is coupled to the first channel portion and the second channel portion respectively; at least a part of the orthographic projection of the first conductor portion on the substrate is located between the orthographic projection of the second scanning line on the substrate and the orthographic projection of the gate of the driving transistor on the substrate; The gate of the data writing transistor is coupled to the corresponding second scanning line, the first electrode of the data writing transistor is coupled to the corresponding data line, and the second electrode of the data writing transistor is coupled to the first electrode of the driving transistor; At least a portion of the second scan line is disposed around one end of the first conductive connection portion.

19. The display substrate according to claim 18, wherein: The display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second plate on the substrate at least partially overlaps with an orthographic projection of the first conductor portion on the substrate; and / or, An orthographic projection of the first conductor portion on the base substrate at least partially overlaps with an orthographic projection of the first conductive connection portion on the base substrate.

20. The display substrate according to claim 18, wherein: The display substrate further includes a power line; the sub-pixel driving circuit further includes a storage capacitor, a first plate of the storage capacitor is coupled to the gate of the driving transistor, and a second plate of the storage capacitor is coupled to the corresponding power line; an orthographic projection of the second plate on the substrate at least partially overlaps with an orthographic projection of the first conductor portion on the substrate; and / or, The orthographic projection of the first conductor portion on the substrate does not overlap with the orthographic projection of the first conductive connection portion on the substrate; and / or, The orthographic projection of the first conductor part on the substrate is parallel to the orthographic projection of the power line on the substrate. The orthographic projections on the base substrate at least partially overlap.

21. A display device comprising the display substrate according to any one of claims 1 to 20.

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