Display substrate and display device

Abstract

A display substrate comprises a substrate, a plurality of first pixel circuits (11) and a plurality of first light-emitting elements (13), wherein the first pixel circuits (11) and the first light-emitting elements (13) are located in a first display area (A1). The at least one first pixel circuit (11) is electrically connected to the at least two first light emitting elements (13). The at least one first pixel circuit (11) comprises at least one reset transistor (T1, T7, T8). The orthographic projection of the at least one first light-emitting element (13) on the substrate at least partially overlaps the orthographic projection of the reset transistor (T1, T7, T8) of the at least one first pixel circuit (11) on the substrate.

Description

Display substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present disclosure provide a display substrate and a display device.

[0006] In one aspect, this embodiment provides a display substrate comprising: a substrate; a plurality of first pixel circuits located in a first display area; and a plurality of first light-emitting elements. At least one first pixel circuit is electrically connected to at least two first light-emitting elements. At least one first pixel circuit includes at least one reset transistor. The orthographic projection of the at least one first light-emitting element on the substrate at least partially overlaps with the orthographic projection of the reset transistor of the at least one first pixel circuit on the substrate.

[0007] In some exemplary embodiments, the plurality of first light-emitting elements include: a plurality of first light-emitting elements emitting light of different colors, wherein the orthographic projections of the plurality of first light-emitting elements emitting light of the same color on the substrate at least partially overlap with the orthographic projections of the reset transistors of the plurality of first pixel circuits on the substrate.

[0008] In some exemplary embodiments, an orthographic projection of an anode of the at least one first light-emitting element on the substrate includes an orthographic projection of an active layer of the at least one reset transistor on the substrate.

[0009] In some exemplary embodiments, the at least one first pixel circuit includes: a first reset transistor and a second reset transistor. The orthographic projection of the first reset transistor of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of one first light-emitting element on the substrate, and the orthographic projection of the second reset transistor of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of another first light-emitting element emitting light of the same color on the substrate.

[0010] In some exemplary embodiments, an orthographic projection of the first light-emitting element on the substrate overlaps with the second reset transistor, and an orthographic projection of the first pixel circuit connected to the first light-emitting element on the substrate does not overlap with the orthographic projection of the first pixel circuit on the substrate.

[0011] In some exemplary embodiments, the plurality of first light-emitting elements are divided into a plurality of light-emitting units, each light-emitting unit including: a first light-emitting element that emits a first color light, a first light-emitting element that emits a second color light, and two first light-emitting elements that emit a third color light. The first light-emitting element that emits the first color light is electrically connected to a first pixel circuit; the first light-emitting element that emits the second color light is electrically connected to a first pixel circuit; and the two first light-emitting elements that emit the third color light are electrically connected to the same first pixel circuit.

[0012] In some exemplary embodiments, the first light-emitting element emitting a first color light and the first light-emitting element emitting a second color light in the light-emitting unit are arranged in the same row, the two first light-emitting elements emitting a third color light are arranged in the same row, and the four first light-emitting elements in the light-emitting unit are arranged in different columns. The first color light is red, the second color light is blue, and the third color light is green.

[0013] In some exemplary embodiments, the first display area includes a plurality of circuit islands spaced apart from each other and arranged in an array, each circuit island including three first pixel circuits arranged sequentially along a first direction; two adjacent rows of circuit islands are staggered. The three first pixel circuits in the circuit islands are electrically connected to four first light-emitting elements in a light-emitting unit.

[0014] In some exemplary embodiments, any two adjacent first pixel circuits in the circuit island region are symmetrically arranged about a midline of the two adjacent first pixel circuits along the first direction.

[0015] In some exemplary embodiments, the data line connected to the first pixel circuit connected to the first light-emitting element emitting the third color light is configured to provide a data signal to a plurality of first pixel circuits arranged in alternate rows.

[0016] In some exemplary embodiments, the first pixel circuit connected to the two first light-emitting elements that emit the third color light in the light-emitting unit is located between the first pixel circuit connected to the first light-emitting element that emits the first color light and the first pixel circuit connected to the first light-emitting element that emits the second color light.

[0017] In some exemplary embodiments, each first pixel circuit in the circuit island region includes: a driving transistor, a first reset transistor, a second reset transistor, and a third reset transistor. The first reset transistor is configured to reset the second electrode of the driving transistor, the second reset transistor is configured to reset the anode of the first light-emitting element connected to the first pixel circuit, and the third reset transistor is configured to reset the first electrode of the driving transistor. The active layers of the first reset transistors of the three first pixel circuits in the circuit island region are interconnected as an integrated structure, the active layers of the second reset transistors of the three first pixel circuits are interconnected as an integrated structure, and the active layers of the third reset transistors of the three first pixel circuits are interconnected as an integrated structure.

[0018] In some exemplary embodiments, the integral structure of the active layer of the first reset transistor of the three first pixel circuits in the circuit island area, the integral structure of the active layer of the second reset transistor of the three first pixel circuits, and the integral structure of the active layer of the third reset transistor of the three first pixel circuits have an orthographic projection on the substrate that at least partially overlaps with the orthographic projection of different first light-emitting elements emitting third color light on the substrate.

[0019] In some exemplary embodiments, the integrated structure of the active layers of three second reset transistors in a circuit island area and the integrated structure of the active layers of three first reset transistors in an adjacent circuit island area in the second direction have an orthographic projection on the substrate that at least partially overlaps with the orthographic projection on the substrate of the same first light-emitting element that emits third color light; the first light-emitting element that emits third color light is connected to a first pixel circuit in the circuit island area and has no overlap with the orthographic projection on the substrate of the transistors of the first pixel circuit other than the second reset transistor; the second direction intersects with the first direction.

[0020] In some exemplary embodiments, each first pixel circuit in the circuit island region includes at least: a driving transistor, a first reset transistor, and a second reset transistor, wherein the first reset transistor is configured to reset the second electrode of the driving transistor, and the second reset transistor is configured to reset the anode of the first light-emitting element connected to the first pixel circuit. Within the circuit island region, the active layers of the first reset transistor and the second reset transistor of a third first pixel circuit along the first direction are aligned in a second direction, where the second direction intersects the first direction. The orthographic projection of the active layer of the first reset transistor of the third first pixel circuit on the substrate at least partially overlaps with the orthographic projection of a first light-emitting element emitting light of a third color on the substrate, and the orthographic projection of the active layer of the second reset transistor of the third first pixel circuit on the substrate at least partially overlaps with the orthographic projection of another first light-emitting element emitting light of the third color on the substrate.

[0021] In some exemplary embodiments, the anode of the one first light-emitting element emitting third color light includes the orthographic projection of the active layer of the first reset transistor of the third first pixel circuit on the substrate, and the orthographic projection of the anode of the other first light-emitting element emitting third color light includes the orthographic projection of the active layer of the second reset transistor of the third first pixel circuit on the substrate.

[0022] In some exemplary embodiments, the display substrate includes, in a direction perpendicular to the display substrate, a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on the substrate. The sixth conductive layer includes at least a plurality of auxiliary electrodes; the orthographic projections of the auxiliary electrodes on the substrate encompass the orthographic projections of the light-emitting region of the first light-emitting element on the substrate.

[0023] In some exemplary embodiments, the plurality of auxiliary electrodes are connected via a plurality of auxiliary connecting bars to form a mesh structure, and the mesh structure is connected to the first voltage signal.

[0024] On the other hand, this embodiment provides a display device, comprising the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, wherein the orthographic projection of the sensor on the display substrate at least partially overlaps with the first display area of ​​the display substrate.

[0025] On the other hand, this embodiment provides a display substrate comprising: a substrate, a plurality of first pixel circuits located in a first display area, and a plurality of first light-emitting elements. At least one of the plurality of first pixel circuits is electrically connected to one first light-emitting element, and at least one first pixel circuit is electrically connected to at least two first light-emitting elements. The first pixel circuit includes: at least one reset transistor. The orthographic projections of the at least two first light-emitting elements electrically connected to the same first pixel circuit on the substrate at least partially overlap with the orthographic projections of the reset transistors of the plurality of first pixel circuits on the substrate.

[0026] In some exemplary embodiments, the anode of each of the at least two first light-emitting elements electrically connected to the same first pixel circuit includes an orthographic projection of an active layer of at least one reset transistor on the substrate.

[0027] In some exemplary embodiments, the first pixel circuit includes: a first reset transistor and a second reset transistor. An orthographic projection of one of two first light-emitting elements electrically connected to the same first pixel circuit on the substrate at least partially overlaps with an orthographic projection of the first reset transistor on the substrate; and an orthographic projection of the other of the at least two first light-emitting elements on the substrate at least partially overlaps with an orthographic projection of the second reset transistor on the substrate.

[0028] In some exemplary embodiments, an orthographic projection of the first light-emitting element on the substrate overlaps with the second reset transistor, and an orthographic projection of the first pixel circuit connected to the first light-emitting element on the substrate does not overlap with the orthographic projection of the first pixel circuit on the substrate.

[0029] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0030] Summary of the Figures

[0031] The accompanying drawings are used to provide an understanding of the technical solution of the present application and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application and do not constitute a limitation on the technical solution of the present application.

[0032] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0033] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0034] FIG3 is a timing diagram of the operation of the pixel circuit provided in FIG2 ;

[0035] 4A and 4B are partial schematic diagrams of a first display area according to at least one embodiment of the present disclosure;

[0036] FIG5 is a schematic diagram of a circuit arrangement of a first display area according to at least one embodiment of the present disclosure;

[0037] FIG6 is a partial top view of the first display area according to at least one embodiment of the present disclosure;

[0038] FIG7A is a schematic diagram of the first display area after the first semiconductor layer is formed in FIG6 ;

[0039] FIG7B is a schematic diagram of a circuit island region in FIG7A ;

[0040] FIG8A is a schematic diagram of the first display area after the first conductive layer is formed in FIG6 ;

[0041] FIG8B is a schematic diagram of the first conductive layer in FIG8A ;

[0042] FIG8C is a schematic diagram of a circuit island region in FIG8A ;

[0043] FIG9A is a schematic diagram of the first display area after the second conductive layer is formed in FIG6 ;

[0044] FIG9B is a schematic diagram of the second conductive layer in FIG9A ;

[0045] FIG9C is a schematic diagram of a circuit island region in FIG9A ;

[0046] FIG10A is a schematic diagram of the first display region after the second semiconductor layer is formed in FIG6 ;

[0047] FIG10B is a schematic diagram of a circuit island region in FIG10A;

[0048] FIG11A is a schematic diagram of the first display area after the third conductive layer is formed in FIG6 ;

[0049] FIG11B is a schematic diagram of the third conductive layer in FIG11A ;

[0050] FIG11C is a schematic diagram of a circuit island region in FIG11A ;

[0051] FIG12 is a schematic diagram of a circuit island region after forming a fifth insulating layer in FIG6;

[0052] FIG13A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG6;

[0053] FIG13B is a schematic diagram of the fourth conductive layer in FIG13A;

[0054] FIG13C is a schematic diagram of a circuit island region in FIG13A;

[0055] FIG14 is a schematic diagram of a circuit island region after forming a seventh insulating layer in FIG6;

[0056] FIG15A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG6 ;

[0057] FIG15B is a schematic diagram of the fifth conductive layer in FIG15A;

[0058] FIG15C is a schematic diagram of a circuit island region in FIG15A;

[0059] FIG16 is a schematic diagram of a circuit island region after forming an eighth insulating layer in FIG6 ;

[0060] FIG17A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG6 ;

[0061] FIG17B is a schematic diagram of the sixth conductive layer in FIG17A;

[0062] FIG18 is a schematic diagram of the first display area after the tenth insulating layer is formed in FIG6 ;

[0063] FIG19A is a schematic diagram of the first display area after the anode layer is formed in FIG6;

[0064] FIG19B is a schematic diagram of the anode layer in FIG19A;

[0065] FIG20 is a schematic diagram of the stacking of the first semiconductor layer, the sixth conductive layer, and the anode layer in FIG6 ;

[0066] FIG21 is another partial schematic top view of the circuit structure layer of the first display area according to at least one embodiment of the present disclosure;

[0067] FIG22A is a schematic diagram of the first display region after the first semiconductor layer is formed in FIG21;

[0068] FIG22B is a schematic diagram of a circuit island region in FIG22A;

[0069] FIG23A is a schematic diagram of the first display area after the first conductive layer is formed in FIG21;

[0070] FIG23B is a schematic diagram of a circuit island region in FIG23A;

[0071] FIG24A is a schematic diagram of the first display area after the second conductive layer is formed in FIG21;

[0072] FIG24B is a schematic diagram of a circuit island region in FIG24A;

[0073] FIG25A is a schematic diagram of the first display region after the second semiconductor layer is formed in FIG21;

[0074] FIG25B is a schematic diagram of a circuit island region in FIG25A;

[0075] FIG26A is a schematic diagram of the first display area after the third conductive layer is formed in FIG21;

[0076] FIG26B is a schematic diagram of a circuit island region in FIG26A;

[0077] FIG27 is a schematic diagram of a circuit island region after forming a fifth insulating layer in FIG21;

[0078] FIG28A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG21;

[0079] FIG28B is a schematic diagram of the fourth conductive layer in FIG28A ;

[0080] FIG28C is a schematic diagram of a circuit island in FIG28A;

[0081] FIG29 is a schematic diagram of a circuit island region after forming a seventh insulating layer in FIG21;

[0082] FIG30 is a schematic diagram of the fifth conductive layer in FIG21;

[0083] FIG31 is a schematic diagram of the first display area after a sixth conductive layer is formed on the side of the fifth conductive layer away from the substrate in FIG21;

[0084] FIG32 is a schematic diagram showing the positional relationship between the first pixel circuit of the circuit structure layer and the anode layer of the light-emitting structure layer shown in FIG21;

[0085] FIG33 is another partial schematic top view of the first display area according to at least one embodiment of the present disclosure;

[0086] FIG34A is a schematic diagram of the first display region after the first semiconductor layer is formed in FIG33 ;

[0087] FIG34B is a schematic diagram of a circuit island in FIG34A;

[0088] FIG35A is a schematic diagram of the first display area after the first conductive layer is formed in FIG33 ;

[0089] FIG35B is a schematic diagram of a circuit island region in FIG35A;

[0090] FIG36A is a schematic diagram of the first display area after the second conductive layer is formed in FIG33 ;

[0091] FIG36B is a schematic diagram of a circuit island in FIG36A;

[0092] FIG37A is a schematic diagram of the first display region after the second semiconductor layer is formed in FIG33 ;

[0093] FIG37B is a schematic diagram of a circuit island region in FIG37A;

[0094] FIG38A is a schematic diagram of the first display area after the third conductive layer is formed in FIG33 ;

[0095] FIG38B is a schematic diagram of a circuit island in FIG38A;

[0096] FIG39 is a schematic diagram of a circuit island region after forming a fifth insulating layer in FIG33;

[0097] FIG40A is a schematic diagram of the first display area after the fourth conductive layer is formed in FIG33;

[0098] FIG40B is a schematic diagram of the fourth conductive layer in FIG40A;

[0099] FIG40C is a schematic diagram of a circuit island in FIG40A;

[0100] FIG41 is a schematic diagram of a circuit island region after forming a seventh insulating layer in FIG33;

[0101] FIG42A is a schematic diagram of the first display area after the fifth conductive layer is formed in FIG33;

[0102] FIG42B is a schematic diagram of the fifth conductive layer in FIG42A;

[0103] FIG42C is a schematic diagram of a circuit island in FIG42A;

[0104] FIG43 is a schematic diagram of a circuit island region after the eighth insulating layer is formed in FIG33;

[0105] FIG44A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG33;

[0106] FIG44B is a schematic diagram of the sixth conductive layer in FIG44A ;

[0107] FIG45 is a schematic diagram of the stacking of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer, and the anode layer in FIG33 ;

[0108] FIG46 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0109] Details

[0110] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0111] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0112] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0113] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0114] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, removable connections, or integral connections; they can refer to mechanical connections or connections; they can refer to direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the circumstances.

[0115] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with multiple functions.

[0116] In this specification, a transistor refers to a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0117] In this specification, the first electrode can be referred to as the drain and the second electrode as the source, or vice versa. When using transistors with opposite polarity or when the direction of current changes during circuit operation, the functions of "source" and "drain" are sometimes interchanged. Therefore, in this specification, the terms "source" and "drain" can be interchanged. Furthermore, the gate electrode can also be referred to as the control electrode.

[0118] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0119] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0120] The term "light transmittance" in this disclosure refers to the ability of light to pass through a medium, and is the percentage of the luminous flux passing through a transparent or translucent body to the incident luminous flux.

[0121] In this disclosure, the terms "approximately" and "substantially" are used without strict boundaries, allowing for process and measurement errors. In this disclosure, "same" can include both completely identical and substantially identical values, and "substantially identical" means values ​​within a 10% difference.

[0122] In this disclosure, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. In this disclosure, "A extends along direction B" means "the main portion of A extends along direction B."

[0123] With the continuous development of display technology, cameras are usually installed on display devices to meet the needs of shooting or face recognition. In order to maximize the screen-to-body ratio, technologies such as bangs screen, water drop screen, and hollowing out in the screen have appeared one after another. These technologies are achieved by making holes in part of the display area and placing a camera below the hole area to reduce the area occupied by the camera, thereby increasing the screen-to-body ratio. However, the above technologies require digging out part of the display area, which will cause part of the display image to be unable to be displayed, and the screen-to-body ratio cannot be further increased. In order to avoid punching holes in the display area and to make a true full screen possible while ensuring the practicality of the display substrate, the pixel circuit external method or the pixel circuit internal method is usually adopted in the camera area under the screen.

[0124] The external pixel circuit method involves placing the pixel circuit connected to the light-emitting element in the under-screen camera area in the normal display area. By separating the light-emitting element and the pixel circuit, the light transmittance of the under-screen camera area is improved. Since the under-screen camera area does not have a pixel circuit, there is no other light-shielding layer in this area except for the anode of the light-emitting element, which can achieve a higher light transmittance. However, under this method, the pixel circuit and the light-emitting element need to be electrically connected via conductive connecting wires. Due to the limited arrangement space of the conductive connecting wires, the size (e.g., aperture) of the under-screen camera area of ​​the display substrate using the external pixel circuit method is limited. Increasing the aperture of the under-screen camera area usually requires increasing the masking process for the conductive connecting wires, resulting in increased costs. Moreover, the conductive connecting wires are usually made of transparent conductive materials, such as indium tin oxide (ITO). Due to the large square resistance of ITO, the conductive connecting wires are loaded heavily, which can easily affect the brightness of the light-emitting element in the under-screen camera area, reducing the brightness of the under-screen camera area, thereby causing poor display in the under-screen camera area, such as vertical display defect (mura).

[0125] The built-in pixel circuit method refers to setting up a light-emitting element and the pixel circuit connected to the light-emitting element in the under-screen camera area. Compared with the external pixel circuit method, the electrical connection between the pixel circuit and the light-emitting element in the under-screen camera area using the built-in method does not require long conductive connecting wires, which can avoid the poor display of the under-screen camera area caused by the conductive connecting wires. In addition, the built-in method has no restrictions on the size of the under-screen camera area and can support under-screen camera areas with large apertures. However, as the pixel density (PPI, Pixels Per Inch) of the under-screen camera area increases, the built-in pixel circuit method is difficult to meet the requirements of high transmittance and good display effects.

[0126] This embodiment provides a display substrate and a display device, which can improve the light transmittance of the under-screen camera area of ​​a display substrate using a pixel circuit built-in method.

[0127] This embodiment provides a display substrate, comprising: a substrate; a plurality of first pixel circuits located in a first display area; and a plurality of first light-emitting elements. At least one first pixel circuit is electrically connected to at least two first light-emitting elements. At least one first pixel circuit includes at least one reset transistor. The orthographic projection of the at least one first light-emitting element on the substrate at least partially overlaps with the orthographic projection of the reset transistor of the at least one first pixel circuit on the substrate.

[0128] In some examples, multiple first pixel circuits can be divided into two groups. The first pixel circuits in the first group of first pixel circuits are connected to the first light-emitting element in a one-drive-one manner, that is, each first pixel circuit in the first group of first pixel circuits can be electrically connected to a first light-emitting element, configured to drive the connected first light-emitting element to emit light. The first pixel circuits in the second group of first pixel circuits can be connected to the first light-emitting element in a one-drive-many manner, that is, each first pixel circuit in the second group of first pixel circuits can be electrically connected to at least two first light-emitting elements, configured to drive the at least two connected first light-emitting elements to emit light. However, this embodiment is not limited to this. In other examples, multiple first pixel circuits can all be connected to the first light-emitting element in a one-drive-many manner, that is, each first pixel circuit can be connected to at least two first light-emitting elements to drive the at least two connected first light-emitting elements to emit light.

[0129] In some examples, the orthographic projection of the first light-emitting element on the substrate may at least partially overlap with the orthographic projection of a reset transistor of a first pixel circuit on the substrate; for another example, the orthographic projection of the first light-emitting element on the substrate may at least partially overlap with the orthographic projection of reset transistors of multiple first pixel circuits on the substrate. This embodiment is not limited to this.

[0130] The display substrate provided in this embodiment employs an integrated pixel circuit method and utilizes the first pixel circuit to drive the first light-emitting element in at least one-to-many manner in the first display area. This allows the number of first pixel circuits in the first display area to be less than the number of first light-emitting elements, thereby improving light transmittance in the first display area. In some examples, when the pixel density in the first display area increases, this embodiment can increase the light-transmitting area by reducing the number of first pixel circuits, thereby increasing light transmittance in the first display area and maintaining the display quality in the first display area.

[0131] In some exemplary embodiments, the plurality of first light-emitting elements may include: a plurality of first light-emitting elements emitting light of different colors. The orthographic projection of at least one first light-emitting element among the plurality of first light-emitting elements emitting light of the same color on the substrate at least partially overlaps with the orthographic projection of the reset transistor of at least one first pixel circuit on the substrate. For example, the orthographic projection of at least one first light-emitting element on the substrate may at least partially overlap with the orthographic projection of the reset transistor of a first pixel circuit that has no electrical connection on the substrate; or, the orthographic projection of at least one first light-emitting element on the substrate may at least partially overlap with the orthographic projection of the reset transistor of a corresponding electrically connected first pixel circuit on the substrate. In this example, the reset transistor of the first pixel circuit may be disposed below the first light-emitting element emitting light of the same color to optimize the circuit layout and increase the light-transmitting area of ​​the first display area.

[0132] In some exemplary embodiments, the orthographic projection of the anode of at least one first light-emitting element on the substrate may include the orthographic projection of the active layer of at least one reset transistor on the substrate. For example, the orthographic projection of the anode of at least one first light-emitting element on the substrate may include the orthographic projection of the active layer of a reset transistor on the substrate. In this example, by providing the anode of the first light-emitting element to cover the active layer of the reset transistor, shielding the reset transistor is achieved, thereby increasing the light-transmitting area of ​​the first display area.

[0133] In some exemplary embodiments, at least one first pixel circuit may include: a first reset transistor and a second reset transistor. The orthographic projection of the first reset transistor of at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of a first light-emitting element on the substrate, and the orthographic projection of the second reset transistor of at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of another first light-emitting element emitting light of the same color on the substrate. In this example, by arranging that the first reset transistor and the second reset transistor of the same first pixel circuit are blocked by different first light-emitting elements, it is helpful to optimize the circuit layout, thereby increasing the light-transmitting area of ​​the first display area. In some examples, the orthographic projection of the first light-emitting element on the substrate that overlaps with the second reset transistor may not overlap with the orthographic projection of the first pixel circuit to which the first light-emitting element is connected. For example, a first pixel circuit may be electrically connected to at least two first light-emitting elements, and one of the at least two first light-emitting elements may not overlap with the orthographic projection of the first pixel circuit to which it is connected on the substrate. Instead, the first light-emitting element may be used to block the reset transistor of another first pixel circuit (such as the second reset transistor) to optimize the blocking effect of the first light-emitting element on the first pixel circuit, thereby increasing the light-transmitting area of ​​the first display area.

[0134] In some exemplary embodiments, the plurality of first light-emitting elements may be divided into a plurality of light-emitting units, each of which may include: a first light-emitting element that emits a first color light, a first light-emitting element that emits a second color light, and two first light-emitting elements that emit a third color light. The first light-emitting element that emits the first color light is electrically connected to a first pixel circuit; the first light-emitting element that emits the second color light is electrically connected to a first pixel circuit; and two first light-emitting elements that emit the third color light are electrically connected to the same first pixel circuit. In this example, by reducing the number of first pixel circuits to which the first light-emitting elements that emit the third color light are electrically connected, the number of first pixel circuits in the first display area can be reduced, thereby facilitating improved light transmittance in the first display area.

[0135] In some exemplary embodiments, the first light-emitting element emitting the first color light and the first light-emitting element emitting the second color light in the light-emitting unit can be arranged in the same row, the two first light-emitting elements emitting the third color light can be arranged in the same row, and the four first light-emitting elements in the light-emitting unit can be arranged in different columns. The first color light can be red light, the second color light can be blue light, and the third color light can be green light. However, this embodiment is not limited to this. The arrangement of the first light-emitting elements and the connection method of the first pixel circuit in this example can maximize the light transmittance of the first display area while ensuring the white balance of the light.

[0136] In some exemplary embodiments, the first display area may include: a plurality of circuit islands spaced apart and arranged in an array, each circuit island including: three first pixel circuits arranged sequentially along a first direction; two adjacent rows of circuit islands are staggered. The three first pixel circuits in the circuit islands are electrically connected to the four first light-emitting elements in a single light-emitting unit. This arrangement of the first pixel circuits in this example facilitates increasing the light-transmitting area of ​​the first display area.

[0137] The solution of this embodiment is illustrated below through some examples.

[0138] Figure 1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1 , the display substrate may include a display area AA and a peripheral area BB located outside the display area AA. The display area AA of the display substrate may include at least a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, this embodiment is not limited to this.

[0139] In some examples, as shown in Figure 1, the first display area A1 may be a light-transmitting display area, and may also be referred to as an under-screen camera (FDC, Full Display With Camera) area. The second display area A2 may be referred to as a normal display area. For example, the orthographic projection of a sensor (such as a camera or other hardware) on the display substrate may be located within the first display area A1 of the display substrate. In some examples, as shown in Figure 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the first display area A1. However, this embodiment is not limited to this. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be less than or equal to the size of the inscribed circle of the first display area A1.

[0140] In some examples, as shown in FIG1 , the first display area A1 can be located at the top center of the display area AA. The second display area A2 can surround the first display area A1. However, this embodiment is not limited to this. For example, the first display area A1 can be located at other locations, such as the upper left corner, lower left corner, lower right corner, or upper right corner of the display area AA. For example, the second display area A2 can surround at least one side of the first display area A1.

[0141] In some examples, as shown in FIG1 , the display area AA may be a rectangle, such as a rounded rectangle. The first display area A1 may be circular or elliptical. However, this embodiment is not limited thereto. For example, the first display area A1 may be a rectangle, a semicircle, a pentagon, or other shapes.

[0142] In some examples, the display area AA may be provided with a plurality of sub-pixels. At least one sub-pixel may include a pixel circuit and a light-emitting element. The pixel circuit may be configured to drive the connected light-emitting element. For example, the pixel circuit may be configured to provide a driving current to drive the light-emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0143] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The light-emitting color of the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0144] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight transistors (i.e., a first transistor T1 to an eighth transistor T8) and a storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a drive transistor, the fourth transistor T4 may also be referred to as a data write transistor, the fifth transistor T5 may also be referred to as a first light-emitting control transistor, the sixth transistor T6 may also be referred to as a second light-emitting control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0145] In some examples, the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be first-type transistors, such as P-type transistors, and the second transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0146] In some examples, the first type of transistor of the pixel circuit (for example, including the first transistor T1, the third transistor T3 to the eighth transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0147] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0148] In some examples, as shown in FIG2 , the gate of the third transistor T3 is electrically connected to the first node N1, the first electrode of the third transistor T3 is electrically connected to the second node N2, and the second electrode of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the third node N3. The first transistor T1 can be configured to reset the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is electrically connected to the fourth node N4. The seventh transistor T7 can be configured to reset the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is electrically connected to the second node N2. The eighth transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0149] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second transistor T2 and the third transistor T3, the second node N2 is the connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8 and the third transistor T3, the third node N3 is the connection point of the first transistor T1, the third transistor T3, the second transistor T2 and the sixth transistor T6, and the fourth node N4 is the connection point of the sixth transistor T6, the seventh transistor T7 and the light emitting element EL.

[0150] FIG3 is an operating timing diagram of the pixel circuit shown in FIG2. The operating process of the pixel circuit shown in FIG2 will be described below with reference to FIG3. In the pixel circuit, the first transistor T1, the third transistor T3 to the eighth transistor T8 are P-type transistors, and the second transistor T2 is an N-type transistor.

[0151] In some examples, as shown in FIG. 2 and FIG. 3 , during a frame display period, the operation process of the pixel circuit may include at least: a first stage S1 , a second stage S2 , a third stage S3 , and a fourth stage S4 .

[0152] The first stage S1 is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh transistor T7 and the eighth transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The eighth transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be supplied to the second node N2. The seventh transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0153] The second stage S2 is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second transistor T2. The first transistor T1 and the second transistor T2 are turned on, causing the first initial signal line provided by the first initial signal line INIT1 to be supplied to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. During this stage, the light-emitting element EL does not emit light.

[0154] The third stage S3 is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4, and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5 and the sixth transistor T6 are disconnected.

[0155] In the fourth stage S4, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the light-emitting element EL to emit light.

[0156] During the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third transistor T3 is: I=K×(Vgs-Vth) 2 =K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata]2 ;

[0157] Wherein, I is the driving current flowing through the third transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0158] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0159] Figures 4A and 4B are partial schematic diagrams of the first display area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figures 1, 4A, and 4B, the first display area A1 of the display substrate may include multiple first light-emitting elements 13 and multiple first pixel circuits 11. The multiple first pixel circuits 11 are electrically connected to the multiple first light-emitting elements 13. The second display area A2 may include multiple second light-emitting elements 14 and multiple second pixel circuits 12. The circuit structures of the first pixel circuits 11 and the second pixel circuits 12 in this example can be the same, for example, they can be the 8T1C structure described above.

[0160] In some examples, as shown in Figure 1, at least one second pixel circuit 12 is electrically connected to at least one second light-emitting element 14. For example, multiple second pixel circuits 12 and multiple second light-emitting elements 14 can be electrically connected in a one-to-one correspondence, and one second pixel circuit 12 can be configured to drive one second light-emitting element 14 to emit light. The orthographic projection of the second light-emitting element 14 on the substrate may at least partially overlap with the orthographic projection of the connected second pixel circuit 12 on the substrate. However, this embodiment is not limited to this. In other examples, multiple second pixel circuits can be configured to drive one second light-emitting element, or one second pixel circuit can be configured to drive multiple second light-emitting elements.

[0161] In some examples, as shown in Figures 4A and 4B, the plurality of first light-emitting elements 13 in the first display area may include: a plurality of first light-emitting elements 13a emitting a first color light, a plurality of first light-emitting elements 13c emitting a second color light, and a plurality of first light-emitting elements 13b and 13d emitting a third color light. In some examples, the first color light may be red light (R), the second color light may be blue light (B), and the third color light may be green light (G). This embodiment is not limited to this.

[0162] In some examples, as shown in Figures 4A and 4B, the plurality of first light-emitting elements 13 in the first display area can be arranged in a Pentile structure. The first light-emitting elements 13b and 13d emitting the third color light can be alternately arranged in the kth row at a certain interval, and the first light-emitting element 13a emitting the first color light and the first light-emitting element 13c emitting the second color light can be alternately arranged in the k+1th row; the first light-emitting elements 13b and 13d emitting the third color light can be alternately arranged in the k+2th row adjacent to the k+1th row at a certain interval, and in the k+3th row adjacent to the k+2th row, the first light-emitting element 13a emitting the first color light and the first light-emitting element 13c emitting the second color light can be alternately arranged. Multiple rows of first light-emitting elements 13 can be repeatedly arranged according to the above rules. The first light-emitting element 13a emitting the first color light and the first light-emitting element 13c emitting the second color light can be alternately arranged in the jth column, and the first light-emitting elements 13b and 13d emitting the third color light can be arranged at a certain interval in the j+1th column adjacent to the jth column. The first light-emitting element 13a emitting the first color light and the first light-emitting element 13c emitting the second color light can be alternately arranged in the j+2th column adjacent to the j+1th column, and the first light-emitting elements 13b and 13d emitting the third color light can be arranged at a certain interval in the j+3th column. According to the above rules, multiple columns of first light-emitting elements 13 can be repeatedly arranged. Wherein, k and j are both integers. In the present disclosure, multiple first light-emitting elements 13 arranged along the first direction X can be referred to as a row of first light-emitting elements, and multiple first light-emitting elements 13 arranged along the second direction Y can be referred to as a column of first light-emitting elements.

[0163] In some examples, as shown in Figures 4A and 4B, a light-emitting unit P in the first display area may include: four first light-emitting elements 13, namely, a first light-emitting element 13a that emits first color light, a first light-emitting element 13c that emits second color light, and two first light-emitting elements 13b and 13d that emit third color light. The first light-emitting element 13a that emits first color light and the first light-emitting element 13c that emits second color light within the light-emitting unit P can be arranged in the same row, the two first light-emitting elements 13b and 13d that emit third color light can be arranged in the same column, and the four first light-emitting elements 13 included in the light-emitting unit P can be arranged in different columns. As shown in Figure 4A, the row containing the first light-emitting element 13a that emits first color light and the first light-emitting element 13c that emits second color light within a light-emitting unit P can be located above the row containing the two first light-emitting elements 13b and 13d that emit third color light. As shown in FIG4B , the row where the first light emitting element 13 a emitting the first color light and the first light emitting element 13 c emitting the second color light in a light emitting unit P are located can be located in the next row where the two first light emitting elements 13 b and 13 d emitting the third color light are located. However, this embodiment is not limited to this.

[0164] In some examples, as shown in Figures 4A and 4B, the first light-emitting element 13a emitting light of the first color has a first light-emitting region 130a, the first light-emitting element 13c emitting light of the second color has a second light-emitting region 130c, the first light-emitting element 13b emitting light of the third color has a third light-emitting region 130b, and the first light-emitting element 13d emitting light of the third color has a fourth light-emitting region 130d. The first light-emitting region 130a, the second light-emitting region 130c, the third light-emitting region 130b, and the fourth light-emitting region 130d can be substantially circular or elliptical. The first light-emitting region 130a of the first light-emitting element 13a emitting light of the first color can be smaller than the second light-emitting region 130c of the first light-emitting element 13c emitting light of the second color. The second light-emitting region 130c of the first light-emitting element 13c emitting light of the second color can be larger than the third light-emitting region 130b of the first light-emitting element 13b emitting light of the third color and the fourth light-emitting region 130d of the first light-emitting element 13d emitting light of the third color. The third light emitting region 130b and the fourth light emitting region 130d may be substantially the same. In this example, the light emitting region of the light emitting element may be a portion of the light emitting element located at a pixel opening of the pixel definition layer.

[0165] Figure 5 is a schematic diagram of the circuit arrangement of the first display area of ​​at least one embodiment of the present disclosure. Figure 5 shows a schematic diagram of the arrangement of the first pixel circuit of the local area of ​​the first display area in Figures 4A and 4B. In some examples, as shown in Figure 5, the first display area may include: a plurality of circuit island areas A11 separated from each other. Each circuit island area A11 may include a plurality of first pixel circuits 11, for example, three first pixel circuits 11. In a plane parallel to the display substrate, the plurality of circuit island areas A11 may be arranged in multiple rows and columns. The plurality of circuit island areas A11 arranged along the first direction X may be referred to as a row of circuit island areas, and the plurality of circuit island areas A11 arranged along the second direction Y may be referred to as a column of circuit island areas. The center lines of the plurality of circuit island areas A11 in a column of circuit island areas in the first direction X may be roughly aligned. Two adjacent circuit island areas A11 in a row of circuit island areas may be arranged one column apart. For example, if a circuit island area A11 in the i-th row of circuit island areas is located in the m+2th column, then a circuit island area adjacent to the circuit island area A11 in the i-th row can be located in the m-th column or the m+4th column. Two adjacent circuit island areas A11 in a column of circuit island areas can be arranged in alternate rows. For example, if a circuit island area in the m-th column of circuit island areas is located in the i-th row, then a circuit island area adjacent to the circuit island area in the m-th column can be located in the i-2th row or the i+2th row. Wherein, i and m are both integers. In this example, the circuit island areas A11 in adjacent rows can be misaligned in the second direction Y, and the circuit island areas A11 in adjacent columns can be misaligned in the first direction X.

[0166] In some examples, as shown in Figures 4A, 4B, and 5, a single circuit island A11 in the first display area may include: three first pixel circuits 11 (for example, including first pixel circuits 11a, 11b, and 11c) arranged in sequence along the first direction X. The three first pixel circuits 11 are electrically connected to four first light-emitting elements 13, and the four first light-emitting elements 13 connected to the three first pixel circuits 11 may belong to one light-emitting unit P. The first pixel circuit 11a may be electrically connected to a first light-emitting element 13a that emits a first color of light and is configured to drive the first light-emitting element 13a to emit light. The first pixel circuit 11b may be electrically connected to two first light-emitting elements 13b and 13d that emit a third color of light and is configured to drive the two first light-emitting elements 13b and 13d that emit the same color of light to emit light. The first pixel circuit 11c may be electrically connected to a first light-emitting element 13c that emits a second color of light and is configured to drive the first light-emitting element 13c that emits the second color of light to emit light.

[0167] In some examples, as shown in FIG4A to FIG5 , the gap between adjacent circuit islands A11 in a row of circuit islands may be greater than or equal to the length of a first pixel circuit along the first direction X. For example, the offset distance L1 between two adjacent rows of circuit islands may be greater than 1 times the length of the first pixel circuit along the first direction X and less than 3 times the length of the first pixel circuit along the first direction X, for example, approximately 2 times or 1.5 times the length of the first pixel circuit along the first direction X. However, this embodiment is not limited to this.

[0168] In some examples, as shown in Figures 4A and 4B, within the first display area, the orthographic projections of the first light-emitting element 13a and the first pixel circuit 11a to which it is connected on the substrate may at least partially overlap, and the orthographic projections of the first light-emitting element 13c and the first pixel circuit 11c to which it is connected on the substrate may at least partially overlap. The orthographic projections of the first light-emitting element 13b and the first pixel circuit 11b to which it is connected on the substrate may at least partially overlap, and the orthographic projections of the first light-emitting element 13d and the first pixel circuit 11b to which it is connected on the substrate may not overlap.

[0169] In this example, by setting the same first pixel circuit to drive two first light-emitting elements that emit third color light, the number of first pixel circuits required in the circuit island area can be reduced, the space occupied by the first pixel circuit in the first display area can be saved, and the wiring space can be saved, thereby increasing the light transmittance of the first display area.

[0170] Figure 6 is a partial top view schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 6 is a partial top view schematic diagram of the first display area shown in Figure 4A. In some examples, as shown in Figure 6, the first display area may include: a first light-transmitting area A12a, a second light-transmitting area A12b, and a third light-transmitting area A12c. The first light-transmitting area A12a may be located in the interval area between adjacent circuit island areas along the first direction X, and may be surrounded by the first light-emitting element 13c of a light-emitting unit, the first light-emitting element 13a of a light-emitting unit adjacent to the light-emitting unit along the first direction X, the first light-emitting element 13d of the light-emitting unit, the first light-emitting element 13b adjacent to the first light-emitting element 13d along the second direction Y, and the connecting lines between two circuit island areas adjacent to each other along the first direction X. The second light-transmitting area A12b and the third light-transmitting area A12c may be located in the interval between adjacent circuit islands along the second direction Y. The second light-transmitting area A12b may be surrounded by the first light-emitting elements 13b, 13c, and 13d of a light-emitting unit, the first light-emitting element 13a of a light-emitting unit adjacent to the light-emitting unit along the second direction Y, and the connecting traces between adjacent circuit islands. The third light-transmitting area A12c may be surrounded by the first light-emitting element 13d of a light-emitting unit, the first light-emitting elements 13b and 13a of the light-emitting unit adjacent to the light-emitting unit along the first direction X, the first light-emitting element 13c of the light-emitting unit adjacent to the light-emitting unit along the second direction Y, and the connecting traces between adjacent circuit islands.

[0171] In some examples, in a direction perpendicular to the display substrate, the display substrate may include: a substrate, and a circuit structure layer and a light-emitting structure layer disposed on the substrate. The light-emitting structure layer may be located on a side of the circuit structure layer away from the substrate. The circuit structure layer of the first display area may include: a plurality of first pixel circuits, and the light-emitting structure layer of the first display area may include: a plurality of first light-emitting elements.

[0172] In some examples, the circuit structure layer may include: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer and a tenth insulating layer may be disposed on the side of the sixth conductive layer away from the substrate. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to tenth insulating layers may be organic insulating layers. This embodiment is not limited thereto. In other examples, an insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer. In other examples, an insulating layer may be disposed on the side of the sixth conductive layer away from the substrate.

[0173] In some examples, the light-emitting structure layer may include: an anode layer, a pixel definition layer, an organic light-emitting layer, and a cathode layer, which are sequentially arranged on the circuit structure layer. The anode layer may be electrically connected to the pixel circuit of the circuit structure layer, the organic light-emitting layer may be connected to the anode layer, and the cathode layer may be connected to the organic light-emitting layer. The organic light-emitting layer may emit light of a corresponding color when driven by the anode layer and the cathode layer.

[0174] The structure of the display substrate is explained below by taking the example of the preparation process of the display substrate as an example. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0175] The “A and B are arranged in the same layer” mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, or the surfaces of A and B close to the substrate are at substantially the same distance from the substrate, or the surfaces of A and B close to the substrate are in direct contact with the same film layer. The “thickness” of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, “the orthographic projection of B is within the range of the orthographic projection of A” or “the orthographic projection of A includes the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. The “shape of A” mentioned in the present disclosure refers to the shape of the orthographic projection of A on the substrate.

[0176] The following describes the circuit structure layer using three first pixel circuits in a circuit island area of ​​the first display area as an example. This example uses the first pixel circuit as the aforementioned 8T1C structure as an example. The first first pixel circuit (i.e., the first pixel circuit 11a) may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a storage capacitor; the second first pixel circuit (i.e., the first pixel circuit 11b) may include: a first transistor 31b, a second transistor 32b, a third transistor 33b, a fourth transistor 34b, a fifth transistor 35b, a sixth transistor 36b, a seventh transistor 37b, an eighth transistor 38b, and a storage capacitor. The third first pixel circuit (i.e., the first pixel circuit 11c) may include: a first transistor 31c, a second transistor 32c, a third transistor 33c, a fourth transistor 34c, a fifth transistor 35c, a sixth transistor 36c, a seventh transistor 37c, an eighth transistor 38c, and a storage capacitor. The connection relationship between the eight transistors and the storage capacitor in each first pixel circuit can be referred to the equivalent circuit diagram shown in FIG. 2 .

[0177] In some examples, the preparation process of the display substrate may include the following operations.

[0178] (1) Provide a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, the rigid substrate can be, but is not limited to, one or more of glass and quartz; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In some examples, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The material of the first flexible material layer and the second flexible material layer can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The material of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0179] (2) Forming a first semiconductor layer. In some examples, a first semiconductor thin film is deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a first semiconductor layer disposed on the substrate. In some examples, the first semiconductor layer can be made of amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene, or polythiophene.

[0180] FIG. 7A is a schematic diagram of a first display region after forming a first semiconductor layer in FIG. 6. FIG. 7B is a schematic diagram of a circuit island region in FIG. 7A.

[0181] In some examples, as shown in FIGS. 7A and 7B, the first semiconductor layer of the first display region may at least include: active layers of multiple first-type transistors of multiple first pixel circuits (for example, including: the first active layer 310a of the first transistor of the first pixel circuit 11a, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor; the first active layer 310b of the first transistor of the first pixel circuit 11b, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor; the first active layer 310c of the first transistor of the first pixel circuit 11c, the third active layer 330c of the third transistor, the fourth active layer 340c of the fourth transistor, the fifth active layer 350c of the fifth transistor, the sixth active layer 360c of the sixth transistor, the seventh active layer 370c of the seventh transistor, and the eighth active layer 380c of the eighth transistor).

[0182] In some examples, as shown in FIG. 7B, the first semiconductor layer patterns of the first pixel circuits 11a and 11b in a circuit island region may be substantially symmetric about a first center line O1, and the first semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetric about a second center line O2. As shown in FIG. 7A, the first semiconductor layer patterns of different circuit island regions may be independent of each other.

[0183] In some examples, as shown in FIG. 7B, the first active layer 310a of the first pixel circuit 11a and the first active layer 310b of the first pixel circuit 11b may be an integrally connected structure. The shape of the integrally connected structure of the first active layers 310a and 310b may be substantially in the shape of a "ji" character. The third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, the sixth active layer 360b, the seventh active layer 370b of the first pixel circuit 11b, and the third active layer 330c, the fourth active layer 340c, the fifth active layer 350c, the sixth active layer 360c, and the seventh active layer 370c of the first pixel circuit 11c may be an integrally connected structure, wherein the fifth active layer 350b of the first pixel circuit 11b and the fifth active layer 350c of the first pixel circuit 11c may be directly connected.

[0184] In some examples, as shown in FIG7B , the first semiconductor layer pattern of the first pixel circuit 11a is used as an example for illustration. The first active layer 310a and the fourth active layer 340a of the first pixel circuit 11a can be located on one side of the third active layer 330a along the second direction Y, and the fifth active layer 350a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a can be located on the side of the third active layer 330a opposite to the second direction Y. The first active layer 310a and the seventh active layer 370a can be aligned in the second direction Y. In some examples, the third active layer 330a can be approximately U-shaped, the fourth active layer 340a, the sixth active layer 360a, the seventh active layer 370a, and the eighth active layer 380a can be approximately I-shaped, and the fifth active layer 350a can be approximately L-shaped. However, this embodiment is not limited to this. The arrangement and shape of the first semiconductor layer pattern of the first pixel circuits 11 b and 11 c are similar to those of the first pixel circuit 11 a , and therefore are not further described herein.

[0185] In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region located between the first region and the second region. The material of the first semiconductor layer may include, for example, polysilicon. The channel region may not be doped with impurities and have semiconductor properties. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities and therefore have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors may be interpreted as wiring doped with impurities, which can be used to electrically connect the transistors. This embodiment is not limited to this.

[0186] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate forming the aforementioned structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer, and the first insulating layer may also be referred to as a first gate insulating layer.

[0187] Figure 8A is a schematic diagram of the first display area after the first conductive layer is formed in Figure 6. Figure 8B is a schematic diagram of the first conductive layer in Figure 8A. Figure 8C is a schematic diagram of a circuit island area in Figure 8A.

[0188] In some examples, as shown in Figures 8A to 8C, the first conductive layer of the first display area may include at least: multiple first scan lines (for example, including first scan lines GL1(i), GL1(i+1)), multiple light-emitting control lines (for example, including light-emitting control lines EML(i), EML(i+1)), multiple first reset control lines (for example, including first reset control lines RST1(i), RST1(i+1)), multiple second reset control lines (for example, including second reset control lines RST2(i), RST2(i+1)), and first electrodes of storage capacitors of multiple first pixel circuits (for example, including first electrodes 391a, 391b, 391c).

[0189] In some examples, the first scan line GL1(i) can be located on one side of the first electrode (e.g., 391a, 391b, and 391c) of the storage capacitor of the first pixel circuit in the second direction Y, and the first reset control line RST1(i) can be located on one side of the first scan line GL1(i) in the second direction Y. The emission control line EML(i) can be located on a side of the first electrode (e.g., 391a, 391b, and 391c) of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y, and the second reset control line RST2(i) can be located on a side of the emission control line EML(i) in the opposite direction of the second direction Y.

[0190] In some examples, the first reset control line RST1(i), the first scan line GL1(i), the second reset control line RST2(i), and the emission control line EML(i) can bend around the spacing area between adjacent circuit islands in the first direction X. For example, the first reset control line RST1(i) and the first scan line GL1(i) can bend around one side of the spacing area of ​​the circuit islands along the second direction Y, and the second reset control line RST2(i) and the emission control line EML(i) can bend around the side of the spacing area opposite to the second direction Y. In this example, by arranging the routing of the first conductive layer to bend around the spacing area between the circuit islands, light transmittance in the first display area is improved.

[0191] In some examples, the shape of the first reset control line RST1(i) can be substantially a zigzag line extending along the first direction X. Within the circuit island, the overlapping region of the first reset control line RST1(i) and the first active layers of the three first pixel circuits can serve as the gates of the first transistors of the three first pixel circuits (e.g., including the gate of the first transistor 31a, the gate of the first transistor 31b, and the gate of the first transistor 31c).

[0192] In some examples, the shape of the first scan line GL1(i) can be substantially a zigzag line extending along the first direction X. Within the circuit island area, the overlapping region of the first scan line GL1(i) and the fourth active layers of the three first pixel circuits can serve as the gates of the fourth transistors of the three first pixel circuits (e.g., including the gates of the fourth transistor 34a, the gates of the fourth transistor 34b, and the gates of the fourth transistor 34c).

[0193] In some examples, the shape of the light emission control line EML(i) can be substantially a zigzag line extending along the first direction X. Within the circuit island area, the overlapping region of the light emission control line EML(i) and the fifth active layer of the three first pixel circuits can serve as the gates of the fifth transistors of the three first pixel circuits (for example, including the gates of the fifth transistors 35a, 35b, and 35c), and the overlapping region of the light emission control line EML(i) and the sixth active layer of the three first pixel circuits can serve as the gates of the sixth transistors of the three first pixel circuits (for example, including the gates of the sixth transistors 36a, 36b, and 36c).

[0194] In some examples, the shape of the second reset control line RST2(i) can be substantially a zigzag line extending along the first direction X. Within the circuit island area, the overlapping region of the second reset control line RST2(i) and the seventh active layer of the three first pixel circuits can serve as the gates of the seventh transistors of the three first pixel circuits (e.g., including the gates of the seventh transistors 37a, 37b, and 37c), and the overlapping region of the second reset control line RST2(i) and the eighth active layer of the three first pixel circuits can serve as the gates of the eighth transistors of the three first pixel circuits (e.g., including the gates of the eighth transistors 38a, 38b, and 38c).

[0195] In some examples, the first electrode 391a of the storage capacitor of the first pixel circuit 11a can also serve as the gate of the third transistor 33a, the first electrode 391b of the storage capacitor of the first pixel circuit 11b can also serve as the gate of the third transistor 33b, and the first electrode 391c of the storage capacitor of the first pixel circuit 11c can also serve as the gate of the third transistor 33c. The orthographic projections of the first electrodes 391a, 391b, and 391c on the substrate can be roughly rectangular, such as a rounded rectangle or a rectangle with chamfered corners. This embodiment is not limited to this.

[0196] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate forming the aforementioned structure. The second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer, and the second insulating layer may also be referred to as a second gate insulating layer.

[0197] Figure 9A is a schematic diagram of the first display area after the second conductive layer is formed in Figure 6. Figure 9B is a schematic diagram of the second conductive layer in Figure 9A. Figure 9C is a schematic diagram of a circuit island area in Figure 9A.

[0198] In some examples, as shown in Figures 9A to 9C, the second conductive layer of the first display area may include at least: a plurality of second scanning auxiliary lines (for example, including second scanning auxiliary lines GL2b(i), GL2b(i+1)), and a plurality of second electrodes of the storage capacitors of the first pixel circuits (for example, including second electrodes 392a, 392b, and 392c).

[0199] In some examples, the second scan auxiliary line GL2b(i) can be shaped substantially like a zigzag line extending along the first direction X. Within the circuit island region, the second scan auxiliary line GL2b(i) can be located on one side of the second electrode (e.g., 392a, 392b, and 392c) of the storage capacitor of the first pixel circuit in the second direction Y. The second scan auxiliary line GL2b(i) can bypass the spacing region of the circuit island region from one side in the second direction Y and be located on the opposite side of the first scan line GL1(i) in the second direction Y.

[0200] In some examples, within the circuit island region, the orthographic projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate can be approximately a rectangular structure with a hollowed-out region. The orthographic projection of the hollowed-out region on the substrate can be approximately a rectangle, and the rectangle can have rounded or chamfered corners. The second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c can be an interconnected, integral structure. The second electrodes 392a and 392b can be approximately symmetrical about the first centerline O1, and the second electrodes 392b and 392c can be approximately symmetrical about the second centerline O2.

[0201] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate having the aforementioned pattern formed thereon. The second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO). In some examples, the third insulating layer may also be referred to as a third gate insulating layer.

[0202] Fig. 10A is a schematic diagram of the first display region after the second semiconductor layer is formed in Fig. 6. Fig. 10B is a schematic diagram of a circuit island region in Fig. 10A.

[0203] In some examples, as shown in Figures 10A and 10B, the second semiconductor layer of the first display area may include at least: active layers of second type transistors of multiple first pixel circuits (for example, including: the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b, and the second active layer 320c of the second transistor 32c of the first pixel circuit 11c).

[0204] In some examples, within the circuit island region, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetrical about the first center line O1 , and the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be substantially symmetrical about the second center line O2 .

[0205] In some examples, the second active layers 320a, 320b, and 320c can be substantially L-shaped. The overlapping region between the second scanning auxiliary line GL2b(i) and the second active layer 320a can serve as the bottom gate of the second transistor 32a, the overlapping region between the second scanning auxiliary line GL2b(i) and the second active layer 320b can serve as the bottom gate of the second transistor 32b, and the overlapping region between the second scanning auxiliary line GL2b(i) and the second active layer 320c can serve as the bottom gate of the second transistor 32c.

[0206] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer, and the fourth insulating layer may also be referred to as a fourth gate insulating layer.

[0207] Figure 11A is a schematic diagram of the first display area after the third conductive layer is formed in Figure 6. Figure 11B is a schematic diagram of the third conductive layer in Figure 11A. Figure 11C is a schematic diagram of a circuit island area in Figure 11A.

[0208] In some examples, the third conductive layer of the first display area may include at least: a plurality of second scan lines (for example, including second scan lines GL2(i) and GL2(i+1)), a plurality of first initial signal lines (for example, including first initial signal lines INIT1(i) and INIT1(i+1)), a plurality of second initial signal lines (for example, including second initial signal lines INIT2(i) and INIT2(i+1)), and a plurality of third initial signal lines (for example, including third initial signal lines INIT3(i) and INIT3(i+1)). The shapes of the first initial signal lines, the second scan lines, the second initial signal lines, and the third initial signal lines may each be substantially zigzag lines extending along the first direction X.

[0209] In some examples, within the circuit island area, the first initial signal line INIT1(i) can be located on one side of the second scan line GL2(i) in the second direction Y, the third initial signal line INIT3(i) and the second initial signal line INIT2(i) can be located on one side of the second scan line GL2(i) in the opposite direction of the second direction Y, and the second initial signal line INIT2(i) can be located on one side of the third initial signal line INIT3(i) in the opposite direction of the second direction Y.

[0210] In some examples, the orthographic projection of the first initial signal line INIT1(i) on the substrate may at least partially overlap with the orthographic projection of the first reset control line RST1(i) on the substrate. For example, the orthographic projection of the first initial signal line INIT1(i) on the substrate may include the orthographic projection of the first reset control line RST1(i) on the substrate. The orthographic projection of the second scan line GL2(i) on the substrate may at least partially overlap with the orthographic projection of the second scan auxiliary line GL2b(i) on the substrate. For example, the orthographic projection of the second scan line GL2(i) on the substrate may include the orthographic projection of the second scan auxiliary line GL2b(i) on the substrate. The orthographic projection of the third initial signal line INIT3(i) on the substrate may at least partially overlap with the orthographic projection of the emission control line EML(i) on the substrate. For example, the orthographic projection of the third initial signal line INIT3(i) on the substrate may include the orthographic projection of the emission control line EML(i) on the substrate. The orthographic projection of the second initial signal line INIT2(i) on the substrate may at least partially overlap with the orthographic projection of the second reset control line RST2(i) on the substrate. For example, the orthographic projection of the second initial signal line INIT2(i) on the substrate may include the orthographic projection of the second reset control line RST2(i) on the substrate. This example avoids occupying excessive routing space by stacking the routing of different conductive layers (e.g., the first conductive layer, the second conductive layer, and the third conductive layer), which helps save wiring space and thereby improves the light transmittance of the first display area.

[0211] (7) Forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate having the aforementioned pattern, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer. In some examples, the fifth insulating layer may also be referred to as an interlayer insulating layer.

[0212] FIG12 is a schematic diagram of a circuit island region after the fifth insulating layer is formed in FIG6. In some examples, as shown in FIG12, the fifth insulating layer in the first display region may have a plurality of vias, such as first to twenty-fourth vias V1 to V24, twenty-sixth to twenty-ninth vias V26 to V29, thirty-first to forty-fourth vias V31 to V44, forty-sixth to forty-ninth vias V46 to V49, and fifty-second to fifty-sixth vias V52 to V56.

[0213] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first through holes V1 to V24 and the twenty-sixth through holes V26 to V29 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer and the fourth insulating layer in the thirty-first through holes V31 to V36 can be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the thirty-seventh through holes V37 to V39 can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the fortieth through holes V40 to V44 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in the fortieth through holes V46 to V49 and the fifty-second through holes V52 to V56 can be removed to expose a portion of the surface of the third conductive layer.

[0214] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate having the aforementioned pattern, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source / drain metal layer.

[0215] Figure 13A is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 6. Figure 13B is a schematic diagram of the fourth conductive layer in Figure 13A. Figure 13C is a schematic diagram of a circuit island area in Figure 13A.

[0216] In some examples, as shown in Figures 13A to 13C, the fourth conductive layer of the first display area may include at least: multiple connecting electrodes (for example, including the first connecting electrode 401 to the eighteenth connecting electrode 418, and the twentieth connecting electrode 420 to the twenty-eighth connecting electrode 428).

[0217] In some examples, the first connection electrode 401 can be shaped substantially as a strip extending along the second direction Y. One end of the first connection electrode 401 can be electrically connected to the first active layer 310a of the first transistor 31a of the first pixel circuit 11a through a first via V1, and the other end can be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a through a thirty-second via V32, and electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through a fourth via V4. The first connection electrode 401 is electrically connected to the second electrode of the first transistor 31a, the second electrode of the second transistor 32a, the second electrode of the third transistor 33a, and the first electrode of the sixth transistor 36a. The first connection electrode 401 can serve as a third node of the first pixel circuit 11a.

[0218] In some examples, the second connection electrode 402 can be shaped substantially as a strip extending along the second direction Y. One end of the second connection electrode 402 can be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a through the thirty-first via hole V31, and the other end can be electrically connected to the first electrode 391a of the storage capacitor of the first pixel circuit 11a through the thirty-seventh via hole V37. The second connection electrode 402 is electrically connected to the first electrode of the second transistor 32a, the gate of the third transistor 33a, and the first electrode 391a of the storage capacitor. The second connection electrode 402 can serve as the first node of the first pixel circuit 11a.

[0219] In some examples, the third connection electrode 403 may be substantially rectangular in shape. The third connection electrode 403 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the second via hole V2.

[0220] In some examples, the fourth connection electrode 404 can be shaped substantially like a zigzag line extending along the second direction Y. One end of the fourth connection electrode 404 can be electrically connected to the third active layer 330a of the third transistor 33a of the first pixel circuit 11a via a third via V3, and the other end can be electrically connected to the eighth active layer 380a of the eighth transistor 38a of the first pixel circuit 11a via a ninth via V9. The fourth connection electrode 404 is electrically connected to the first electrode of the third transistor 33a, the second electrode of the fourth transistor 34a, the second electrode of the fifth transistor 35a, and the first electrode of the eighth transistor 38a. The fourth connection electrode 404 can serve as the second node of the first pixel circuit 11a.

[0221] In some examples, the fifth connection electrode 405 may be shaped substantially as a strip structure extending along the second direction Y. One end of the fifth connection electrode 405 may be electrically connected to the fifth active layer 350 a of the fifth transistor 35 a of the first pixel circuit 11 a through a fifth via hole V5, and the other end may be electrically connected to the second electrode 392 a of the storage capacitor of the first pixel circuit 11 a through a fortieth via hole V40.

[0222] In some examples, the sixth connection electrode 406 may be substantially rectangular in shape. The sixth connection electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through a sixth via hole V6.

[0223] In some examples, the seventh connection electrode 407 may be shaped substantially like a dumbbell. One end of the seventh connection electrode 407 may be electrically connected to the seventh active layer 370a of the seventh transistor 37a of the first pixel circuit 11a through a seventh via hole V7, and the other end may be electrically connected to the second initial signal line INIT2(i) through a fifty-second via hole V52.

[0224] In some examples, the shape of the eighth connection electrode 408 can be substantially a zigzag shape extending along the second direction Y. One end of the eighth connection electrode 408 can be electrically connected to the eighth active layer 380 a of the eighth transistor 38 a of the first pixel circuit 11 a through an eighth via V8, and the other end can be electrically connected to the third initial signal line INIT3(i) through a forty-seventh via V47.

[0225] In some examples, the ninth connection electrode 409 may be shaped substantially as a strip structure extending along the first direction X. One end of the ninth connection electrode 409 may be electrically connected to the second electrode 392 a of the storage capacitor of the first pixel circuit 11 a through a forty-first via hole V41 , and the other end may be electrically connected to the second electrode 392 b of the storage capacitor of the first pixel circuit 11 b through a forty-second via hole V42 .

[0226] In some examples, the tenth connection electrode 410 may be shaped substantially like an arch extending along the first direction X. Two ends of the tenth connection electrode 410 may be electrically connected to the first initial signal line INIT1(i) through a fifty-fifth via hole V55 and a fifty-sixth via hole V56, respectively, and the other end may be electrically connected to the integrated structure of the first active layer 310a of the first pixel circuit 11a and the first active layer 310b of the first pixel circuit 11b through a tenth via hole V10.

[0227] In some examples, the eleventh connection electrode 411 can be shaped substantially as a strip extending along the second direction Y. One end of the eleventh connection electrode 411 can be electrically connected to the first active layer 310b of the first transistor 31b of the first pixel circuit 11b through the eleventh via V11, and the other end can be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b through the thirty-fourth via V34, and electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the fourteenth via V14. The eleventh connection electrode 411 is electrically connected to the second electrode of the first transistor 31b, the second electrode of the second transistor 32b, the second electrode of the third transistor 33b, and the first electrode of the sixth transistor 36b. The eleventh connection electrode 411 can serve as a third node of the first pixel circuit 11b.

[0228] In some examples, the twelfth connection electrode 412 can be shaped substantially as a strip extending along the second direction Y. One end of the twelfth connection electrode 412 can be electrically connected to the second active layer 320b of the second transistor 32b of the first pixel circuit 11b via a thirty-third via hole V33, and the other end can be electrically connected to the first electrode 391b of the storage capacitor of the first pixel circuit 11b via a thirty-eighth via hole V38. The twelfth connection electrode 412 is electrically connected to the first electrode of the second transistor 32b, the gate of the third transistor 33b, and the first electrode 391b of the storage capacitor. The twelfth connection electrode 412 can serve as a first node of the first pixel circuit 11b.

[0229] In some examples, the thirteenth connection electrode 413 may be substantially rectangular in shape. The thirteenth connection electrode 413 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the twelfth via hole V12.

[0230] In some examples, the shape of the fourteenth connecting electrode 414 can be substantially a zigzag line extending along the second direction Y. One end of the fourteenth connecting electrode 414 can be electrically connected to the third active layer 330b of the third transistor 33b of the first pixel circuit 11b through the thirteenth via hole V13, and the other end can be electrically connected to the eighth active layer 380b of the eighth transistor 38b of the first pixel circuit 11b through the nineteenth via hole V19. The fourteenth connecting electrode 414 is electrically connected to the first electrode of the third transistor 33b, the second electrode of the fourth transistor 34b, the second electrode of the fifth transistor 35b, and the first electrode of the eighth transistor 38b. The fourteenth connecting electrode 414 can serve as the second node of the first pixel circuit 11b.

[0231] In some examples, the shape of the fifteenth connection electrode 415 can be substantially a strip structure extending along the second direction Y. One end of the fifteenth connection electrode 415 can be electrically connected to the integrated structure of the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b and the fifth active layer 350c of the fifth transistor 35c of the first pixel circuit 11c through a fifteenth via hole V15, and the other end can be electrically connected to the integrated structure of the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c through a forty-third via hole V43.

[0232] In some examples, the shape of the sixteenth connection electrode 416 may be substantially rectangular. The sixteenth connection electrode 416 may be electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the sixteenth via hole V16.

[0233] In some examples, the shape of the seventeenth connection electrode 417 can be substantially dumbbell-shaped. One end of the seventeenth connection electrode 417 can be electrically connected to the seventh active layer 370b of the seventh transistor 37b of the first pixel circuit 11b through the seventeenth via hole V17, and the other end can be electrically connected to the second initial signal line INIT2(i) through the fifty-third via hole V53.

[0234] In some examples, the shape of the eighteenth connection electrode 418 can be substantially a zigzag line extending along the second direction Y. One end of the eighteenth connection electrode 418 can be electrically connected to the eighth active layer 380 b of the eighth transistor 38 b of the first pixel circuit 11 b through an eighteenth via hole V18, and the other end can be electrically connected to the third initial signal line INIT3(i) through a forty-eighth via hole V48.

[0235] In some examples, the shape of the twentieth connection electrode 420 may be substantially a zigzag shape extending along the first direction X. One end of the twentieth connection electrode 420 may be electrically connected to the first active layer 310 c of the first transistor 31 c of the first pixel circuit 11 c through a twentieth via hole V20, and the other end may be electrically connected to the first initial signal line INIT1(i) through a forty-sixth via hole V46.

[0236] In some examples, the twenty-first connection electrode 421 can be shaped substantially as a strip extending along the second direction Y. One end of the twenty-first connection electrode 421 can be electrically connected to the first active layer 310c of the first transistor 31c of the first pixel circuit 11c via a twenty-first via hole V21, and the other end can be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c via a thirty-sixth via hole V36, and electrically connected to the sixth active layer 360c of the sixth transistor 36c of the first pixel circuit 11c via a twenty-fourth via hole V24. The twenty-first connection electrode 421 is electrically connected to the second electrode of the first transistor 31c, the second electrode of the second transistor 32c, the second electrode of the third transistor 33c, and the first electrode of the sixth transistor 36c. The twenty-first connection electrode 421 can serve as a third node of the first pixel circuit 11c.

[0237] In some examples, the shape of the twenty-second connection electrode 422 can be substantially a strip-shaped structure extending along the second direction Y. One end of the twenty-second connection electrode 422 can be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c through the thirty-fifth via hole V35, and the other end can be electrically connected to the first electrode 391c of the storage capacitor of the first pixel circuit 11c through the thirty-ninth via hole V39. The twenty-second connection electrode 422 is electrically connected to the first electrode of the second transistor 32c, the gate of the third transistor 33c, and the first electrode 391c of the storage capacitor. The twenty-second connection electrode 422 can serve as the first node of the first pixel circuit 11c.

[0238] In some examples, the shape of the twenty-third connection electrode 423 may be substantially rectangular. The twenty-third connection electrode 423 may be electrically connected to the fourth active layer 340c of the fourth transistor 34c of the first pixel circuit 11c through the twenty-second via hole V22.

[0239] In some examples, the shape of the twenty-fourth connecting electrode 424 can be substantially a zigzag line extending along the second direction Y. One end of the twenty-fourth connecting electrode 424 can be electrically connected to the third active layer 330c of the third transistor 33c of the first pixel circuit 11c through the twenty-third via hole V23, and the other end can be electrically connected to the eighth active layer 380c of the eighth transistor 38c of the first pixel circuit 11c through the twenty-ninth via hole V29. The twenty-fourth connecting electrode 424 is electrically connected to the first electrode of the third transistor 33c, the second electrode of the fourth transistor 34c, the second electrode of the fifth transistor 35c, and the first electrode of the eighth transistor 38c. The twenty-fourth connecting electrode 424 can serve as the second node of the first pixel circuit 11c.

[0240] In some examples, the twenty-fifth connection electrode 425 may be substantially in the shape of a strip structure extending along the first direction X. The twenty-fifth connection electrode 425 may be electrically connected to the second electrode 392 c of the storage capacitor of the first pixel circuit 11 c through a forty-fourth via hole V44 .

[0241] In some examples, the twenty-sixth connection electrode 426 may be substantially rectangular in shape. The twenty-sixth connection electrode 426 may be electrically connected to the sixth active layer 360 c of the sixth transistor 36 c of the first pixel circuit 11 c through a twenty-sixth via hole V26 .

[0242] In some examples, the twenty-seventh connection electrode 427 may be shaped substantially like a dumbbell. One end of the twenty-seventh connection electrode 427 may be electrically connected to the seventh active layer 370 c of the seventh transistor 37 c of the first pixel circuit 11 c through a twenty-seventh via hole V27, and the other end may be electrically connected to the second initial signal line INIT2(i) through a fifty-fourth via hole V54.

[0243] In some examples, the shape of the twenty-eighth connection electrode 428 can be substantially a zigzag line extending along the second direction Y. One end of the twenty-eighth connection electrode 428 can be electrically connected to the eighth active layer 380 c of the eighth transistor 38 c of the first pixel circuit 11 c through a twenty-eighth via hole V28, and the other end can be electrically connected to the third initial signal line INIT3(i) through a forty-ninth via hole V49.

[0244] In some examples, within the circuit island, first pixel circuits 11a and 11b can be approximately symmetrical about a first centerline O1, and first pixel circuits 11b and 11c can be approximately symmetrical about a second centerline O2. In this example, any two adjacent first pixel circuits within the circuit island can be arranged approximately symmetrically about their centerlines, thereby saving circuit space.

[0245] In some examples, the first pixel circuits within a row of circuit islands arranged along a first direction X can be aligned in the first direction X, and the first pixel circuits within a column of circuit islands arranged along a second direction Y can be staggered in the second direction Y. For example, the spacing region between two adjacent circuit islands in a row of circuit islands can be aligned with the second first pixel circuit in a circuit island in the next row of circuit islands in the second direction Y. This example illustrates three circuit islands in the mth column, i-th row, the m+2th column, i-th row, and the m+1th column, i+1th row, as well as the third first pixel circuit in the m-1th column, i+1th row, and the first first pixel circuit in the m+1th column, i+1th row.

[0246] (9) Forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and then a seventh insulating film is coated. The seventh insulating film and the sixth insulating film are patterned by a patterning process to form the sixth insulating layer and the seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

[0247] Figure 14 is a schematic diagram of a circuit island region after the seventh insulating layer is formed in Figure 6. In some examples, as shown in Figure 14, the seventh insulating layer in the first display area can have multiple vias, such as vias 61 to 68 (V61 to V68). The seventh and sixth insulating layers within vias 61 to V68 can be removed to expose a portion of the surface of the fourth conductive layer.

[0248] (10) Forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate having the aforementioned pattern, and the fifth conductive film is patterned by a patterning process to form a fifth conductive layer on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source / drain metal layer.

[0249] Figure 15A is a schematic diagram of the first display area after the fifth conductive layer is formed in Figure 6. Figure 15B is a schematic diagram of the fifth conductive layer in Figure 15A. Figure 15C is a schematic diagram of a circuit island area in Figure 15A.

[0250] In some examples, as shown in Figures 15A to 15C, the fifth conductive layer of the first display area may include at least: a plurality of data lines (for example, including data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), a plurality of first anode connecting electrodes (for example, including first anode connecting electrodes 451a, 451b and 451c), a plurality of first shielding electrodes (for example, including first shielding electrodes 511a, 511b and 511c), and a plurality of first power connection lines (for example, including first power connection lines 512a, 512b and 512c).

[0251] In some examples, the plurality of data lines may be substantially in the shape of a zigzag extending along the second direction Y. The data lines DL(j) and DL(j+1) may be adjacent, and the data lines DL(j+2) and DL(j+3) may be adjacent. The data line DL(j+1) may be electrically connected to the third connection electrode 403 through the sixty-first via hole V61, thereby being electrically connected to the first electrode of the fourth transistor 34a of the first pixel circuit 11a. The data line DL(j+2) may be electrically connected to the thirteenth connection electrode 413 through the sixty-fourth via hole V64, thereby being electrically connected to the first electrode of the fourth transistor 34b of the first pixel circuit 11b. The data line DL(j+3) may be electrically connected to the twenty-third connection electrode 423 through the sixty-sixth via hole V66, thereby being electrically connected to the first electrode of the fourth transistor 34c of the first pixel circuit 11c.

[0252] In some examples, four data lines may be provided throughout each circuit island, and three of the four data lines may be electrically connected to the three first pixel circuits in the circuit island, respectively. Four data lines DL(j), DL(j+1), DL(j+2), and DL(j+3) may extend through the i-th row and m-th column circuit island, and three of the data lines DL(j+1), DL(j+2), and DL(j+3) may be electrically connected to the three first pixel circuits in the i-th row and m-th column circuit island, respectively. Four data lines DL(j+4), DL(j+5), DL(j+6), and DL(j+7) may extend through the i-th row and m+2 column circuit island, and three of the data lines DL(j+5), DL(j+6), and DL(j+7) may be electrically connected to the three first pixel circuits in the i-th row and m+2 column circuit island, respectively. Four data lines DL(j+2), DL(j+3), DL(j+4), and DL(j+5) can run through the circuit island area of ​​the i+1th row and the m+1th column, and three of the data lines DL(j+3), DL(j+4), and DL(j+5) can be electrically connected to the three first pixel circuits in the circuit island area of ​​the i+1th row and the m+1th column, respectively. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) can be configured to provide data signals to the first pixel circuit (e.g., the first pixel circuit 11b) connected to the first light-emitting element emitting light of the third color. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) can be configured to provide data signals to multiple first pixel circuits arranged in alternate rows. For example, data lines DL(j) and DL(j+4) are not electrically connected to the first pixel circuit in the i-th row circuit island area, but are electrically connected to the first pixel circuit in the i+1-th row circuit island area; data lines DL(j+2) and DL(j+6) are electrically connected to the first pixel circuit in the i-th row circuit island area, but are not electrically connected to the first pixel circuit in the i+1-th row circuit island area. In this example, the data line that provides a data signal to the first pixel circuit (for example, the first pixel circuit 11b) connected to the first light-emitting element emitting the third color light is electrically connected to the multiple first pixel circuits arranged in alternate rows, and provides data signals to the multiple first pixel circuits arranged in alternate rows. The arrangement of the data lines in this example is conducive to wiring arrangement.

[0253] In some examples, the first shielding electrodes 511a, 511b, and 511c may be shaped as irregular polygons. The first shielding electrodes 511a and 511b may be substantially symmetrical about the first centerline O1, and the first shielding electrodes 511b and 511c may be substantially symmetrical about the second centerline O2. The first shielding electrodes 511a and 511b may be an integral structure connected to each other. The first shielding electrodes 511a and 511b may be located between the data lines DL(j+1) and DL(j+2). The integral structure of the first shielding electrodes 511a and 511b may be electrically connected to the ninth connecting electrode 409 via the sixty-third via hole V63, thereby electrically connecting to the second electrodes of the storage capacitors of the first pixel circuits 11b and 11c. The first shielding electrode 511c may be located on the side of the data line DL(j+3) away from the data line DL(j+2). The first shielding electrode 511c may be electrically connected to the twenty-fifth connecting electrode 425 via the sixty-eighth via hole V68, thereby electrically connecting to the second electrode of the storage capacitor of the first pixel circuit 11c.

[0254] In some examples, the orthographic projection of the first shielding electrode 511a on the substrate can cover the orthographic projection of the second connecting electrode 402 on the substrate, thereby shielding the first node of the first pixel circuit 11a; the orthographic projection of the first shielding electrode 511b on the substrate can cover the orthographic projection of the twelfth connecting electrode 412 on the substrate, thereby shielding the first node of the first pixel circuit 11b; the orthographic projection of the first shielding electrode 511c on the substrate can cover the orthographic projection of the twenty-second connecting electrode 422 on the substrate, thereby shielding the first node of the first pixel circuit 11c, thereby shielding the influence of other signals on the first nodes of the first pixel circuits 11a, 11b and 11c.

[0255] In some examples, the orthographic projection of the first shielding electrode 511a on the substrate can cover the orthographic projection of the first connecting electrode 401 on the substrate, thereby shielding the third node of the first pixel circuit 11a; the orthographic projection of the first shielding electrode 511b on the substrate can cover the orthographic projection of the eleventh connecting electrode 411 on the substrate, thereby shielding the third node of the first pixel circuit 11b; the orthographic projection of the first shielding electrode 511c on the substrate can cover the orthographic projection of the twenty-first connecting electrode 421 on the substrate, thereby shielding the thirteenth node of the first pixel circuit 11c, thereby shielding the influence of other signals on the third nodes of the first pixel circuits 11a, 11b and 11c.

[0256] In some examples, the first shielding electrodes of adjacent circuit islands can be electrically connected via a first power connection line. The shapes of the first power connection lines 512a, 512b, and 512c can all be roughly zigzag lines extending along the second direction Y. The first power connection line 512a can be located on the side of the first shielding electrode 511c away from the data line DL(j+3). The first power connection line 512a can connect to the first shielding electrodes 511b in adjacent circuit islands in the same column of circuit islands. For example, one end of a first power connection line 512a can be connected to the first shielding electrode 511b in the circuit island in the m+1th column of the i-1th row, and after going around the side of the first shielding electrode 511c in the circuit island in the m+1th column of the i-1th row, the other end can be connected to the first shielding electrode 511b in the circuit island in the m+1th column of the i+1th row. The first power connection line 512a and the first shielding electrode 511b to which it is connected can be an integrated structure connected to each other.

[0257] In some examples, the first power connection line 512b can connect the first shielding electrode 511a in one circuit island (e.g., the circuit island in the i-th row and m-th column) to the first shielding electrode 511c in the circuit island in the adjacent left column (e.g., the circuit island in the i+1-th row and m-1-th column). The first power connection line 512a and the connected first shielding electrode can be an integrated structure connected to each other.

[0258] In some examples, the first power connection line 512c can connect the first shielding electrode 511c in one circuit island (e.g., the circuit island in the i-th row and m-th column) to the first shielding electrode 511a in the circuit island in the adjacent row and right column (e.g., the circuit island in the i+1-th row and m+1-th column). The first power connection line 512c and the connected first shielding electrode can be an integrated structure connected to each other.

[0259] In this example, the first voltage signal can be transmitted along the second direction Y through the connection between the first shielding electrode and the first power connection line, and the first voltage signal can be transmitted along the first direction X through the second electrode of the storage capacitor of the first pixel circuit and the connection electrode.

[0260] In some examples, the shapes of the first anode connection electrodes 451a, 451b, and 451c can be substantially rectangular. The first anode connection electrode 451a can be located between the first power connection lines 512a and 512b, and the first anode connection electrode 451b can be located between the first power connection line 512a and the data line DL(j+2). The first anode connection electrode 451c can be located between the data line DL(j+3) and the first power connection line 512c.

[0261] In some examples, the first anode connection electrode 451a can be electrically connected to the sixth connection electrode 406 through the sixty-second via hole V62, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 451b can be electrically connected to the sixteenth connection electrode 416 through the sixty-fifth via hole V65, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 451c can be electrically connected to the twenty-sixth connection electrode 426 through the sixty-seventh via hole V67, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11c.

[0262] (11) Forming an eighth insulating layer. In some examples, an eighth insulating layer is coated on the substrate having the aforementioned pattern, and the eighth insulating layer is patterned by a patterning process to form the eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second planar layer.

[0263] FIG16 is a schematic diagram of a circuit island region after the eighth insulating layer is formed in FIG6 . In some examples, as shown in FIG16 , the eighth insulating layer in the first display region may be provided with a plurality of vias, such as vias 71 through 73. The eighth insulating layer within vias 71 through 73 may be removed, exposing a portion of the surface of the fifth conductive layer.

[0264] (12) Forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate having the aforementioned pattern, and the sixth conductive film is patterned by a patterning process to form a sixth conductive layer on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source / drain metal layer.

[0265] Fig. 17A is a schematic diagram of the first display area after the sixth conductive layer is formed in Fig. 6. Fig. 17B is a schematic diagram of the sixth conductive layer in Fig. 17A.

[0266] In some examples, as shown in Figures 17A and 17B, the sixth conductive layer of the first display area may include at least: a plurality of auxiliary electrodes (for example, including auxiliary electrodes 461a, 461b, 461c and 461d), a plurality of auxiliary connecting bars (for example, including auxiliary connecting bars 462a, 462b, 462c, 462d and 462f), a plurality of second anode connecting electrodes (for example, including second anode connecting electrodes 452a, 452b, 452c and 452d), and a plurality of anode connecting bars 453.

[0267] In some examples, the shapes of the second anode connection electrodes 452a, 452b, 452c, and 452d can all be substantially rectangular. The second anode connection electrode 452a can be electrically connected to the first anode connection electrode 451a through the seventy-first via hole V71 to achieve electrical connection with the sixth transistor of the first pixel circuit 11a. The second anode connection electrode 452c can be electrically connected to the first anode connection electrode 451c through the seventy-third via hole V73 to achieve electrical connection with the sixth transistor of the first pixel circuit 11c. The second anode connection electrode 452b can be electrically connected to the first anode connection electrode 451b through the seventy-second via hole V72 to achieve electrical connection with the sixth transistor of the first pixel circuit 11b.

[0268] In some examples, second anode connection electrode 452b can be electrically connected to second anode connection electrode 452d via an anode connection bar 453. Second anode connection electrodes 452b, 452d, and anode connection bar 453 can be an interconnected, integral structure. Second anode connection electrode 452d connected to second anode connection electrode 452b in the i-th row, m-th column circuit island region can be located in the i+1-th row, m+1-th column circuit island region. Anode connection bar 453 can be substantially L-shaped.

[0269] In some examples, the auxiliary electrodes 461a, 461b, 461c, and 461d can be approximately circular or elliptical in shape. Auxiliary electrode 461a can be located below the anode of the first light-emitting element 13a, auxiliary electrode 461b can be located below the anode of the first light-emitting element 13b, auxiliary electrode 461c can be located below the anode of the first light-emitting element 13c, and auxiliary electrode 461d can be located below the anode of the first light-emitting element 13d. The auxiliary electrodes can flatten the anode, ensuring the flatness of the anode surface near the substrate, reducing color shift caused by uneven anodes, and shielding the anode from the effects of the underlying pixel circuitry.

[0270] In some examples, adjacent auxiliary electrodes may be connected by auxiliary connecting bars. The shape of the auxiliary connecting bar 462a may be roughly a cross of bars extending along the first direction X and the second direction Y. The auxiliary connecting bar 462a may be located in the circuit island area, and the four ends of the auxiliary connecting bar 462a are respectively connected to the four auxiliary electrodes 461a, 461b, 461c and 461d. The auxiliary connecting bars 462b, 462c, 462d and 462f may each be a strip structure extending in one direction. The auxiliary connecting bars 462b, 462c, 462d and 462f may be located in the spacing area between adjacent circuit island areas in a row of circuit island areas. Auxiliary connecting bar 462b can connect adjacent auxiliary electrodes 461c and 461d, auxiliary connecting bar 462c can connect adjacent auxiliary electrodes 461c and 461b, auxiliary connecting bar 462d can connect adjacent auxiliary electrodes 461b and 461a, and auxiliary connecting bar 462f can connect adjacent auxiliary electrodes 461a and 461d. In the interval area between adjacent circuit islands, four auxiliary connecting bars 462b, 462c, 462d, and 462f, and four auxiliary electrodes 461a, 461b, 461c, and 461d can be connected in sequence to form a grid.

[0271] In some examples, a plurality of auxiliary electrodes and a plurality of auxiliary connection blocks are electrically connected to form a mesh structure. A plurality of auxiliary electrodes and a plurality of auxiliary connection blocks can be an integrated structure connected to each other. The integrated structure of the auxiliary electrodes and the auxiliary connection blocks can be electrically connected to the first power connection line located in the fifth conductive layer in the peripheral area (or the second display area) to achieve transmission of the first voltage signal, so that the first voltage signal of the first display area is uniformed. However, this embodiment is not limited to this. In other examples, the integrated structure of the auxiliary electrodes and the auxiliary connection blocks can be electrically connected to the first power connection line or the first shielding electrode located in the fifth conductive layer through a via opened in the eighth insulating layer of the first display area to achieve transmission of the first voltage signal.

[0272] (13) Forming a ninth insulating layer and a tenth insulating layer. In some examples, a ninth insulating layer is coated on the substrate on which the aforementioned pattern is formed, and the ninth insulating layer is patterned by a patterning process to form a ninth insulating layer. Subsequently, a tenth insulating layer is coated on the substrate on which the aforementioned pattern is formed, and the tenth insulating layer is patterned by a patterning process to form a tenth insulating layer. In some examples, the ninth insulating layer may also be referred to as a third flat layer, and the tenth insulating layer may also be referred to as a fourth flat layer.

[0273] FIG18 is a schematic diagram of the first display area after the tenth insulating layer is formed in FIG6 . In some examples, as shown in FIG18 , the tenth insulating layer in the first display area may have multiple vias, such as vias V81 to V84. The tenth and ninth insulating layers within vias V81 to V84 may be removed to expose a portion of the surface of the sixth conductive layer.

[0274] At this point, the circuit structure layer can be prepared. The film structure of the circuit structure layer in the second display area is similar to that of the first display area, so it will not be described in detail here.

[0275] In this example, by providing the ninth insulating layer and the tenth insulating layer, the flatness of the anode layer can be further ensured.

[0276] (14) Forming a light-emitting structure layer. In some examples, an anode film is deposited on the substrate having the aforementioned pattern, and the anode film is patterned by a patterning process to form an anode layer.

[0277] FIG19A is a schematic diagram of the first display area after the anode layer is formed in FIG6 . FIG19B is a schematic diagram of the anode layer in FIG19A . In some examples, as shown in FIG19A and FIG19B , the anode layer of the first display area may include at least: anodes of a plurality of first light-emitting elements (e.g., anode 131 a of first light-emitting element 13 a, anode 131 b of first light-emitting element 13 b, anode 131 c of first light-emitting element 13 c, and anode 131 d of first light-emitting element 13 d), and a plurality of third anode connecting electrodes (e.g., third anode connecting electrodes 132 a, 132 b, 132 c, and 132 d).

[0278] In some examples, the shapes of the anodes 131a, 131b, 131c, and 131d can be approximately circular or elliptical. The shapes of the third anode connection electrodes 132a, 132b, 132c, and 132d can be approximately rectangular. The anode 131a and the third anode connection electrode 132a can be interconnected as a single unit. The third anode connection electrode 132a can be electrically connected to the second anode connection electrode 452a via the 81st via hole V81 to achieve electrical connection with the first pixel circuit 11a. The anode 131b and the third anode connection electrode 132b can be interconnected as a single unit. The third anode connection electrode 132b can be electrically connected to the second anode connection electrode 452b via the 82nd via hole V82 to achieve electrical connection with the first pixel circuit 11b. The anode 131c and the third anode connection electrode 132c can be interconnected as a single unit. The third anode connection electrode 132c can be electrically connected to the second anode connection electrode 452c via the 83rd via hole V83 to achieve electrical connection with the first pixel circuit 11c. The anode 131d and the third anode connection electrode 132d can be an integrated structure connected to each other. The third anode connection electrode 132d can be electrically connected to the second anode connection electrode 452d through the 84th via V84. Since the second anode connection electrodes 452d and 452b are an integrated structure, the third anode connection electrode 132d is electrically connected to the first pixel circuit 11b.

[0279] In some examples, the orthographic projection of the anode 131a on the substrate may include the orthographic projection of the auxiliary electrode 461a on the substrate. The orthographic projection of the anode 131b on the substrate may include the orthographic projection of the auxiliary electrode 461b on the substrate. The orthographic projection of the anode 131c on the substrate may include the orthographic projection of the auxiliary electrode 461c on the substrate. The orthographic projection of the anode 131d on the substrate may include the orthographic projection of the auxiliary electrode 461d on the substrate. In this example, by providing an auxiliary electrode below the anode, it is possible not only to ensure the flatness of the anode, but also to shield the influence of the pixel circuit on the anode layer. However, this embodiment is not limited to this. In other examples, the orthographic projection of the auxiliary electrode on the substrate may coincide with the orthographic projection of the corresponding anode on the substrate.

[0280] Figure 20 is a schematic diagram of the stacking of the first semiconductor layer, the sixth conductive layer, and the anode layer in Figure 6. In some examples, as shown in Figure 20, the orthographic projection of the anode 131b of the first light-emitting element 13b on the substrate may partially overlap with the orthographic projection of the seventh active layer of the seventh transistor (i.e., the second reset transistor) and the eighth active layer of the eighth transistor (i.e., the third reset transistor) of the connected first pixel circuit 11b on the substrate. The orthographic projection of the anode 131d of the first light-emitting element 13d on the substrate may not overlap with the orthographic projection of the connected first pixel circuit 11b on the substrate. The orthographic projection of the anode 131d of the first light-emitting element 13d on the substrate may partially overlap with the orthographic projection of the integrated structure of the first active layer of the first transistor (i.e., the first reset transistor) of the two first pixel circuits on the substrate.

[0281] In some examples, a pixel definition film is applied to the substrate on which the aforementioned pattern is formed, and a pixel definition layer is formed through masking, exposure, and development processes. The pixel definition layer can be formed with multiple pixel openings exposing the anode layer (as shown in FIG6 ). An organic light-emitting layer is formed within the aforementioned pixel openings, and the organic light-emitting layer is connected to the anode layer. Subsequently, a cathode film is deposited, and the cathode film is patterned through a patterning process to form a cathode pattern, and the cathode is connected to the organic light-emitting layer.

[0282] In some examples, after preparing the light-emitting structure layer, an encapsulation structure layer can be formed on the cathode. In some examples, the encapsulation structure layer can include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer can be arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer. In some possible implementations, the display substrate can also include other film layers, such as a touch structure layer, a color filter layer, etc., which are not limited in this embodiment.

[0283] In some examples, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The seventh insulating layer, the eighth insulating layer, the ninth insulating layer, and the tenth insulating layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The pixel definition layer can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. The anode layer may be made of a reflective material such as metal, and the cathode layer may be made of a transparent conductive material. However, this embodiment is not limited thereto.

[0284] The structure of the display substrate and its preparation process in this embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure can be modified and patterning processes can be added or removed as needed. The preparation process of this exemplary embodiment can be implemented using currently available manufacturing equipment and is well compatible with existing manufacturing processes. The process is simple to implement, easy to implement, and has high production efficiency, low production costs, and a high yield rate.

[0285] The display substrate of this example reduces the number of first pixel circuits in the first display area, adopts a one-drive-two design for the first light-emitting elements emitting the third color light (that is, one first pixel circuit simultaneously drives two first light-emitting elements emitting the third color light), and performs a routing design that avoids the light-transmitting area in the interval area between adjacent circuit island areas. This can help increase the light transmittance of the first display area, ensure the light white balance of the first display area, and support the PPI improvement of the first display area.

[0286] Figure 21 is another partial top view schematic diagram of the circuit structure layer of the first display area of ​​at least one embodiment of the present disclosure. Figure 21 takes the partial structure in the two-row and five-column circuit island area (the i-th row and the i+1-th row, the m-th column to the m+2-th column, and part of the m-1-th column and part of the m+3-th column) as an example for illustration. The number and order of film layers of the display substrate of this example are the same as the number and order of film layers of the aforementioned embodiment. The preparation process of the display substrate of this example can refer to the description of the aforementioned embodiment. Compared with the aforementioned embodiment, this example disassembles and reassembles the reset transistors (including the first transistor, the seventh transistor, and the eighth transistor) of the three first pixel circuits in the circuit island area. The similar structures of the display substrate of this example and the display substrate of the aforementioned embodiment are omitted or briefly described, and reference can be made to the description of the aforementioned embodiment.

[0287] Figure 22A is a schematic diagram of the first display area after the first semiconductor layer is formed in Figure 21. Figure 22B is a schematic diagram of a circuit island area in Figure 22A. In some examples, as shown in Figures 22A and 22B, the first semiconductor layer of the first display area may include at least: an active layer of multiple first-type transistors of multiple first pixel circuits. The first transistor, seventh transistor, and eighth transistor of three first pixel circuits within a circuit island area are disassembled and reassembled. The first active layer 310a of the first pixel circuit 11a, the first active layer 310b of the first pixel circuit 11b, and the first active layer 310c of the first pixel circuit 11c can be an interconnected integrated structure. The orthographic projection of this integrated structure on the substrate can be roughly a comb-tooth structure. This integrated structure can be located on one side of the third active layers 330a and 330b in the second direction Y.

[0288] In some examples, the seventh active layer 370a of the first pixel circuit 11a, the seventh active layer 370b of the first pixel circuit 11b, and the seventh active layer 370c of the first pixel circuit 11c can be interconnected integral structures, and the orthographic projection of the integral structure on the substrate can be approximately a comb-tooth structure. The integral structure of the three seventh active layers in the circuit island region of the i-th row and m-th column can be adjacent to the integral structure of the three first active layers in the circuit island region of the i+1-th row and m+1-th column. The comb teeth of the integral structure of the three seventh active layers in the circuit island region of the i-th row and m-th column are arranged in opposite directions from the comb teeth of the integral structure of the three first active layers in the circuit island region of the i+1-th row and m+1-th column.

[0289] In some examples, the eighth active layer 380a of the first pixel circuit 11a, the eighth active layer 380b of the first pixel circuit 11b, and the eighth active layer 380c of the first pixel circuit 11c may be an interconnected integral structure, and the integral structure may be located on one side of the integral structure of the three seventh active layers in the opposite direction of the first direction X. The integral structure of the three seventh active layers of the circuit island region may be located in the spacing region between adjacent circuit island regions.

[0290] In some examples, the third active layer 330b, the fourth active layer 340b, the fifth active layer 350b and the sixth active layer 360b of the first pixel circuit 11b and the third active layer 330c, the fourth active layer 340c, the fifth active layer 350c and the sixth active layer 360c of the first pixel circuit 11c can be an interconnected integral structure, wherein the fifth active layers 350b and 350c can be directly connected.

[0291] In some examples, the third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, and the sixth active layer 360b of the first pixel circuit 11a can be substantially symmetrical with the third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, and the sixth active layer 360b of the first pixel circuit 11b about the first center line O1. The third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, and the sixth active layer 360b of the first pixel circuit 11b can be substantially symmetrical with the third active layer 330c, the fourth active layer 340c, the fifth active layer 350c, and the sixth active layer 360c of the first pixel circuit 11c about the second center line O2.

[0292] FIG23A is a schematic diagram of the first display area after the first conductive layer is formed in FIG21 . FIG23B is a schematic diagram of a circuit island in FIG23A . In some examples, as shown in FIG23A and FIG23B , the first conductive layer of the first display area may include at least: a plurality of first scan lines (e.g., first scan lines GL1(i) and GL1(i+1)), a plurality of emission control lines (e.g., emission control lines EML(i) and EML(i+1)), a plurality of first reset control lines (e.g., first reset control lines RST1(i) and RST1(i+1)), a plurality of second reset control lines (e.g., second reset control lines RST2(i) and RST2(i+1)), and a plurality of first electrodes of storage capacitors of first pixel circuits (e.g., first electrodes 391a, 391b, and 391c). The emission control lines may be substantially straight lines extending along the first direction X, and the first scan lines, the first reset control lines, and the second reset control lines may be substantially zigzag lines extending along the first direction X.

[0293] Figure 24A is a schematic diagram of the first display area after the second conductive layer is formed in Figure 21. Figure 24B is a schematic diagram of a circuit island area in Figure 24A. In some examples, as shown in Figures 24A and 24B, the second conductive layer of the first display area may include at least: a plurality of second scanning auxiliary lines (for example, including second scanning auxiliary lines GL2b(i), GL2b(i+1)), a plurality of second electrodes of the storage capacitors of the first pixel circuits (for example, including second electrodes 392a, 392b and 392c), and a first connecting line 393. The first connecting line 393 may be shaped like a strip structure extending along the first direction X. The first connecting line 393 may be configured to achieve electrical connection between the sixth transistor and the seventh transistor of the first pixel circuit 11a.

[0294] Figure 25A is a schematic diagram of the first display area after the second semiconductor layer is formed in Figure 21. Figure 25B is a schematic diagram of a circuit island area in Figure 25A. In some examples, as shown in Figures 25A and 25B, the second semiconductor layer of the first display area may include at least: active layers of the second type transistors of multiple first pixel circuits (for example, including: the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b, and the second active layer 320c of the second transistor 32c of the first pixel circuit 11c). Within the circuit island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be approximately symmetrical about the first center line O1, and the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be approximately symmetrical about the second center line O2.

[0295] FIG26A is a schematic diagram of the first display area after the third conductive layer is formed in FIG21 . FIG26B is a schematic diagram of a circuit island area in FIG26A . In some examples, as shown in FIG26A and FIG26B , the third conductive layer of the first display area may include at least: a plurality of second scan lines (e.g., second scan lines GL2(i) and GL2(i+1)), a plurality of first initial signal lines (e.g., first initial signal lines INIT1(i) and INIT1(i+1)), a plurality of second initial signal lines (e.g., second initial signal lines INIT2(i) and INIT2(i+1)), and a plurality of third initial signal lines (e.g., third initial signal lines INIT3(i) and INIT3(i+1)). The first initial signal lines, the second scan lines, and the second initial signal lines may each be approximately zigzag lines extending along the first direction X. The third initial signal line may be approximately straight lines extending along the first direction X.

[0296] FIG27 is a schematic diagram of a circuit island region after the fifth insulating layer is formed in FIG21. In some examples, as shown in FIG27, the fifth insulating layer in the first display region may have a plurality of vias, such as the second via V2 to the sixth via V6, the twelfth via V12 to the sixteenth via V16, the twenty-second via V22 to the twenty-fifth via V25, the thirty-first via V31 to the forty-fifth via V45, the forty-seventh via V47 to the fiftieth via V50, and the one-hundredth via V103 to the one-hundredth via V104.

[0297] In some examples, the fifth insulating layer, fourth insulating layer, third insulating layer, second insulating layer, and first insulating layer within the second through sixth vias V2 to V6, the twelfth through sixteenth vias V12 to V16, the twenty-second through twenty-fifth vias V25, and the ninety-first through ninety-second vias V91 to V102 can be removed, exposing a portion of the surface of the first semiconductor layer. The fifth insulating layer and fourth insulating layer within the thirty-first through thirty-sixth vias V31 to V36 can be removed, exposing a portion of the surface of the second semiconductor layer. The fifth insulating layer, fourth insulating layer, third insulating layer, and second insulating layer within the thirty-seventh through thirty-ninth vias V37 to V39 can be removed, exposing a portion of the surface of the first conductive layer. The fifth insulating layer, fourth insulating layer, and third insulating layer within the fortieth through forty-fourth through forty-fourth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth through fourteenth The fifth insulating layer in the forty-fifth via hole V45 and the forty-seventh via hole V47 to the fiftieth via hole V50 may be removed to expose a portion of the surface of the third conductive layer.

[0298] Figure 28A is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 21. Figure 28B is a schematic diagram of the fourth conductive layer in Figure 28A. Figure 28C is a schematic diagram of a circuit island area in Figure 28A.

[0299] In some examples, as shown in Figures 28A to 28C, the fourth conductive layer of the first display area may include at least: a plurality of connecting electrodes (for example, including the first connecting electrode 401 to the sixth connecting electrode 406, the ninth connecting electrode 409, the eleventh connecting electrode 411 to the sixteenth connecting electrode 416, the twenty-first connecting electrode 421 to the twenty-sixth connecting electrode 426, and the thirty-first connecting electrode 431 to the thirty-seventh connecting electrode 437).

[0300] In some examples, the shape of the first connection electrode 401 can be substantially a zigzag shape extending along the second direction Y. One end of the first connection electrode 401 can be electrically connected to the first active layer 310a through the ninety-second via hole V92, and the other end can be electrically connected to the second active layer 320a of the second transistor 32a of the first pixel circuit 11a through the thirty-second via hole V32, and electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through the fourth via hole V4.

[0301] In some examples, the second connection electrode 402 may be shaped substantially as a strip structure extending along the second direction Y. One end of the second connection electrode 402 may be electrically connected to the second active layer 320 a of the second transistor 32 a of the first pixel circuit 11 a through a thirty-first via hole V31, and the other end may be electrically connected to the first electrode 391 a of the storage capacitor of the first pixel circuit 11 a through a thirty-seventh via hole V37.

[0302] In some examples, the third connection electrode 403 may be substantially rectangular in shape. The third connection electrode 403 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the second via hole V2.

[0303] In some examples, the fourth connection electrode 404 may be shaped substantially like a zigzag line extending along the second direction Y. One end of the fourth connection electrode 404 may be electrically connected to the third active layer 330 a of the third transistor 33 a of the first pixel circuit 11 a through a third via hole V3, and the other end may be electrically connected to the eighth active layer 380 a of the eighth transistor 38 a of the first pixel circuit 11 a through a ninety-fifth via hole V95.

[0304] In some examples, the fifth connection electrode 405 may be shaped substantially as a strip structure extending along the second direction Y. One end of the fifth connection electrode 405 may be electrically connected to the fifth active layer 350 a of the fifth transistor 35 a of the first pixel circuit 11 a through a fifth via hole V5, and the other end may be electrically connected to the second electrode 392 a of the storage capacitor of the first pixel circuit 11 a through a fortieth via hole V40.

[0305] In some examples, the shape of the sixth connection electrode 406 can be substantially rectangular. The sixth connection electrode 406 can be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through the sixth via hole V6, and can also be electrically connected to one end of the first connection line 393 through the 103rd via hole V103. The other end of the first connection line 393 can be electrically connected to the 35th connection electrode 435 through the 104th via hole V104, and the 35th connection electrode 435 can also be electrically connected to the seventh active layer 370b through the 100th via hole V100. In this example, the sixth transistor and the seventh transistor of the first pixel circuit 11a can be connected via the sixth connection electrode 406, the first connection line 393, and the 35th connection electrode 435.

[0306] In some examples, the ninth connection electrode 409 may be shaped substantially as a strip structure extending along the first direction X. One end of the ninth connection electrode 409 may be electrically connected to the second electrode 392 a of the storage capacitor of the first pixel circuit 11 a through a forty-first via hole V41 , and the other end may be electrically connected to the second electrode 392 b of the storage capacitor of the first pixel circuit 11 b through a forty-second via hole V42 .

[0307] In some examples, the shape of the eleventh connection electrode 411 can be substantially a zigzag shape extending along the second direction Y. One end of the eleventh connection electrode 411 can be electrically connected to the first active layer 310 b of the first pixel circuit 11 b through the ninety-third via hole V93, and the other end can be electrically connected to the second active layer 320 b of the second transistor 32 b of the first pixel circuit 11 b through the thirty-fourth via hole V34, and electrically connected to the sixth active layer 360 b of the sixth transistor 36 b of the first pixel circuit 11 b through the fourteenth via hole V14.

[0308] In some examples, the twelfth connection electrode 412 may be shaped substantially as a strip structure extending along the second direction Y. One end of the twelfth connection electrode 412 may be electrically connected to the second active layer 320 b of the second transistor 32 b of the first pixel circuit 11 b through a thirty-third via hole V33, and the other end may be electrically connected to the first electrode 391 b of the storage capacitor of the first pixel circuit 11 b through a thirty-eighth via hole V38.

[0309] In some examples, the thirteenth connection electrode 413 may be substantially rectangular in shape. The thirteenth connection electrode 413 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the twelfth via hole V12.

[0310] In some examples, the shape of the fourteenth connection electrode 414 can be substantially a zigzag shape extending along the second direction Y. One end of the fourteenth connection electrode 414 can be electrically connected to the third active layer 330 b of the third transistor 33 b of the first pixel circuit 11 b through the thirteenth via hole V13, and the other end can be electrically connected to the eighth active layer 380 b of the first pixel circuit 11 b through the ninety-seventh via hole V97.

[0311] In some examples, the shape of the fifteenth connection electrode 415 can be substantially a strip structure extending along the second direction Y. One end of the fifteenth connection electrode 415 can be electrically connected to the integrated structure of the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b and the fifth active layer 350c of the fifth transistor 35c of the first pixel circuit 11c through a fifteenth via hole V15, and the other end can be electrically connected to the integrated structure of the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c through a forty-third via hole V43.

[0312] In some examples, the shape of the sixteenth connecting electrode 416 can be substantially rectangular. The sixteenth connecting electrode 416 can be electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the sixteenth via hole V16. The sixteenth connecting electrode 416 and the thirty-fourth connecting electrode 434 can be an integral structure connected to each other. The thirty-fourth connecting electrode 434 can be substantially a strip-shaped structure extending along the first direction X. One end of the thirty-fourth connecting electrode 434 is connected to the sixteenth connecting electrode 416, and the other end is electrically connected to the seventh active layer 370b through the one-hundred-first via hole V101.

[0313] In some examples, the shape of the twenty-first connection electrode 421 can be substantially L-shaped. One end of the twenty-first connection electrode 421 can be electrically connected to the first active layer 310c through the ninety-fourth via hole V94, and the other end can be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c through the thirty-sixth via hole V36, and electrically connected to the sixth active layer 360c of the sixth transistor 36c of the first pixel circuit 11c through the twenty-fourth via hole V24.

[0314] In some examples, the shape of the twenty-second connection electrode 422 can be substantially a strip structure extending along the second direction Y. One end of the twenty-second connection electrode 422 can be electrically connected to the second active layer 320 c of the second transistor 32 c of the first pixel circuit 11 c through a thirty-fifth via hole V35, and the other end can be electrically connected to the first electrode 391 c of the storage capacitor of the first pixel circuit 11 c through a thirty-ninth via hole V39.

[0315] In some examples, the shape of the twenty-third connection electrode 423 may be substantially rectangular. The twenty-third connection electrode 423 may be electrically connected to the fourth active layer 340c of the fourth transistor 34c of the first pixel circuit 11c through the twenty-second via hole V22.

[0316] In some examples, the shape of the twenty-fourth connection electrode 424 can be substantially a zigzag line extending along the second direction Y. One end of the twenty-fourth connection electrode 424 can be electrically connected to the third active layer 330 c of the third transistor 33 c of the first pixel circuit 11 c through the twenty-third via hole V23, and the other end can be electrically connected to the eighth active layer 380 c of the eighth transistor 38 c of the first pixel circuit 11 c through the ninety-eighth via hole V98.

[0317] In some examples, the twenty-fifth connection electrode 425 may be substantially in the shape of a strip structure extending along the first direction X. The twenty-fifth connection electrode 425 may be electrically connected to the second electrode 392 c of the storage capacitor of the first pixel circuit 11 c through a forty-fourth via hole V44 .

[0318] In some examples, the twenty-sixth connection electrode 426 may be substantially in the shape of a strip structure extending along the first direction X. The twenty-sixth connection electrode 426 may be electrically connected to the sixth active layer 360 c of the sixth transistor 36 c of the first pixel circuit 11 c through the twenty-fifth via hole V25 , and may also be electrically connected to the seventh active layer 370 c through the ninety-ninth via hole V99 .

[0319] In some examples, the shape of the thirty-first connection electrode 431 can be substantially dumbbell-shaped. One end of the thirty-first connection electrode 431 can be electrically connected to the integrated structure of the three first active layers through the ninety-first via hole V91, and the other end can be electrically connected to the first initial signal line INIT1(i) through the forty-fifth via hole V45.

[0320] In some examples, the shape of the thirty-second connection electrode 432 can be substantially a strip structure extending along the second direction Y. One end of the thirty-second connection electrode 432 can be electrically connected to the integrated structure of the three eighth active layers through the ninety-sixth via hole V96, and the other end can be electrically connected to the third initial signal line INIT3(i) through the forty-eighth via hole V48.

[0321] In some examples, the shape of the thirty-third connection electrode 433 can be substantially L-shaped. One end of the thirty-third connection electrode 433 can be electrically connected to the integrated structure of the three seventh active layers through the one-hundred-second via hole V102, and the other end can be electrically connected to the second initial signal line INIT2(i) through the fiftieth via hole V50.

[0322] In some examples, the thirty-sixth connection electrode 436 and the thirty-seventh connection electrode 437 can be substantially rectangular in shape. The thirty-sixth connection electrode 436 can be electrically connected to the third initial signal line INIT3(i) via a forty-seventh via hole V47, and the thirty-seventh connection electrode 437 can be electrically connected to the third initial signal line INIT3(i) via a forty-ninth via hole V49. This example can facilitate uniformity of the film layer pattern by providing the thirty-sixth and thirty-seventh connection electrodes.

[0323] Figure 29 is a schematic diagram of a circuit island region after the seventh insulating layer is formed in Figure 21. In some examples, as shown in Figure 29, the seventh insulating layer in the first display area can have multiple vias, such as vias 61 to 68 (V61 to V68). The seventh and sixth insulating layers within vias 61 to V68 can be removed to expose a portion of the surface of the fourth conductive layer.

[0324] FIG30 is a schematic diagram of the fifth conductive layer in FIG21. In some examples, as shown in FIG21 and FIG30, the fifth conductive layer of the first display area may include at least: a plurality of data lines (for example, including data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), and DL(j+7)), a plurality of first anode connection electrodes (for example, including first anode connection electrodes 451a, 451b, and 451c), a plurality of first shielding electrodes (for example, including first shielding electrodes 511a, 511b, and 511c), and a plurality of second power connection lines (for example, including second power connection lines 513a, 513b, and 513c).

[0325] In some examples, the second power connection lines 513a, 513b, and 513c can be zigzag lines extending along the second direction Y. One end of the second power connection line 513a can be connected to the integrated structure of the first shielding electrodes 511a and 511b in one circuit island area, and the other end can be connected to the first shielding electrode 511c in another circuit island area. One end of the second power connection line 513b can be connected to the first shielding electrode 511c in one circuit island area, and the other end can be connected to the first shielding electrode 511a in another circuit island area. One end of the second power connection line 513c can be connected to the first shielding electrode 511c in one circuit island area, and the other end can be connected to the first shielding electrode 511b in another circuit island area. The first shielding electrode and the connected second power connection line can be an integrated structure connected to each other. In this example, the connection between the first shielding electrode and the first power connection line can realize the transmission of the first voltage signal along the second direction Y, and the second electrode of the storage capacitor of the first pixel circuit and the connection electrode can realize the transmission of the first voltage signal along the first direction X.

[0326] In some examples, the first anode connection electrode 451a can be electrically connected to the sixth connection electrode 406 through the sixty-second via hole V62, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 451b can be electrically connected to the sixteenth connection electrode 416 through the sixty-fifth via hole V65, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 451c can be electrically connected to the twenty-sixth connection electrode 426 through the sixty-seventh via hole V67, thereby achieving electrical connection with the sixth transistor of the first pixel circuit 11c.

[0327] FIG31 is a schematic diagram of the first display area after a sixth conductive layer is formed on the side of the fifth conductive layer away from the substrate in FIG21. In some examples, as shown in FIG31, the sixth conductive layer in the first display area may include at least: a plurality of auxiliary electrodes (e.g., including auxiliary electrodes 461a, 461b, 461c, and 461d), a plurality of auxiliary connecting bars connecting the plurality of auxiliary electrodes, a plurality of second anode connecting electrodes (e.g., including second anode connecting electrodes 452a, 452b, 452c, and 452d), and a plurality of anode connecting bars 453.

[0328] Figure 32 is a schematic diagram illustrating the positional relationship between the first pixel circuit of the circuit structure layer and the anode layer of the light-emitting structure layer shown in Figure 21. In some examples, as shown in Figure 32, the orthographic projection of the anode 131a of the first light-emitting element 13a on the substrate can at least partially overlap with the orthographic projection of the first pixel circuit 11a to which it is connected. The orthographic projection of the anode 131c of the first light-emitting element 13c on the substrate can at least partially overlap with the orthographic projection of the first pixel circuit 11c to which it is connected.

[0329] In some examples, the orthographic projection of the anode 131b of the first light-emitting element 13b on the substrate at least partially overlaps with the orthographic projection of the eighth transistors of the three first pixel circuits within a circuit island on the substrate. For example, the orthographic projection of the anode 131b of the first light-emitting element 13b on the substrate partially overlaps with the orthographic projection of the integrated structure of the eighth active layers of the three eighth transistors on the substrate.

[0330] In some examples, the orthographic projection of the anode 131d of the first light-emitting element 13d on the substrate at least partially overlaps with the orthographic projection of the seventh transistors of the three first pixel circuits in one circuit island region, and the orthographic projection of the first transistors of the three first pixel circuits in another circuit island region on the substrate. The orthographic projection of the anode 131d of the first light-emitting element 13d on the substrate at least partially overlaps with the orthographic projection of the integrated structure of the seventh active layer of the three first pixel circuits on the substrate, and may also at least partially overlap with the orthographic projection of the integrated structure of the first active layer of another three first pixel circuits on the substrate. The orthographic projection of the anode 131d of the first light-emitting element 13d on the substrate does not overlap with the orthographic projection of the transistors of the connected first pixel circuit other than the second reset transistor (i.e., the seventh transistor) on the substrate.

[0331] This example disassembles and reassembles multiple reset transistors (including the first transistor, the seventh transistor, and the eighth transistor) in the first pixel circuit of the first display area. The multiple first and seventh transistors are placed below the anode of the same first light-emitting element that emits green light, and the multiple eighth transistors are placed below the anode of another first light-emitting element that emits green light. By disassembling and reassembling the reset transistors in this example, the first pixel circuit in the first display area can be rationally arranged to further increase the light transmittance of the first display area while ensuring white balance, thereby improving the performance of the display substrate.

[0332] The rest of the description of the display substrate of this embodiment can refer to the description of the previous embodiment, and will not be repeated here.

[0333] Figure 33 is another partial top view schematic diagram of the first display area of ​​at least one embodiment of the present disclosure. Figure 33 is a partial top view schematic diagram of the first display area shown in Figure 4B. The number and order of film layers of the display substrate of this example are the same as the number and order of film layers of the aforementioned embodiment. The preparation process of the display substrate of this example can refer to the description of the aforementioned embodiment. Compared with the aforementioned embodiment, this example disassembles the reset transistor (including the first transistor and the seventh transistor) of the third first pixel circuit in the circuit island area. The similar structure of the display substrate of this example and the display substrate of the aforementioned embodiment is omitted or briefly described, and reference can be made to the description of the aforementioned embodiment.

[0334] Figure 34A is a schematic diagram of the first display area after the first semiconductor layer is formed in Figure 33. Figure 34B is a schematic diagram of a circuit island in Figure 34A. In some examples, as shown in Figures 34A and 34B, the first semiconductor layer of the first display area may include at least: active layers of multiple first-type transistors of multiple first pixel circuits. The first active layer 310c of the first transistor and the seventh active layer 370c of the seventh transistor of the third first pixel circuit (i.e., the first pixel circuit 11c) within a circuit island are disassembled and reassembled.

[0335] In some examples, the first active layer 310c and the seventh active layer 370c of the first pixel circuit 11c can be aligned in the second direction Y. The first active layer 310c and the seventh active layer 370c of the first pixel circuit 11c in a column of circuit islands can be aligned in the second direction. The first active layer 310c of the first pixel circuit 11c in a row of circuit islands and the seventh active layer 370c of the first pixel circuit 11c in an adjacent row of circuit islands can be aligned in the first direction X. The first active layer 310c and the seventh active layer 370c can be located on a side of the sixth active layer 360c away from the third active layer 330c. The shape of the first active layer 310c can be approximately half of an I-shape. The shape of the seventh active layer 370c can be approximately I-shaped.

[0336] In some examples, the third active layer 330a, the fourth active layer 340a, the fifth active layer 350a, the sixth active layer 360a, and the seventh active layer 370a of the first pixel circuit 11a, the third active layer 330b, the fourth active layer 340b, the fifth active layer 350b, the sixth active layer 360b, and the seventh active layer 370b of the first pixel circuit 11b, and the third active layer 330c, the fourth active layer 340c, the fifth active layer 350c, and the sixth active layer 360c of the first pixel circuit 11c can be interconnected as an integral structure. The seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b can be directly connected, and the fifth active layer 350b of the first pixel circuit 11b and the fifth active layer 350c of the first pixel circuit 11c can be directly connected. The first active layer 310a of the first pixel circuit 11a and the first active layer 310b of the first pixel circuit 11b may be connected to each other as an integrated structure, and the shape of the integrated structure may be approximately an X. The eighth active layer 380b of the first pixel circuit 11b and the eighth active layer 380c of the first pixel circuit 11c may be connected to each other as an integrated structure, and the shape of the integrated structure may be approximately a U.

[0337] In some examples, the first semiconductor layer patterns of the first pixel circuits 11a and 11b within a circuit island can be substantially symmetrical about the first centerline O1. The third active layer 330b, fourth active layer 340b, fifth active layer 350b, sixth active layer 360b, and eighth active layer 380b of the first pixel circuit 11b and the third active layer 330c, fourth active layer 340c, fifth active layer 350c, sixth active layer 360c, and eighth active layer 380c of the first pixel circuit 11c can be substantially symmetrical about the second centerline O2. As shown in FIG. 34A , the first semiconductor layer patterns of different circuit islands can be independent of each other. The seventh active layer 370c of the first pixel circuit 11c in a circuit island area is adjacent to the integrated structure of the first active layers of the first pixel circuits 11a and 11b in the next adjacent column circuit island area, and the first active layer 310c of the first pixel circuit 11c in a circuit island area is adjacent to the seventh active layer 370b and the eighth active layer 380b of the previous adjacent column circuit island area, for example, can be located between the seventh active layer 370b and the eighth active layer 380b.

[0338] FIG35A is a schematic diagram of the first display area after the first conductive layer is formed in FIG33 . FIG35B is a schematic diagram of a circuit island in FIG35A . In some examples, as shown in FIG35A and FIG35B , the first conductive layer of the first display area may include at least: a plurality of first scan lines (e.g., first scan lines GL1(i) and GL1(i+1)), a plurality of emission control lines (e.g., emission control lines EML(i) and EML(i+1)), a plurality of first reset control lines (e.g., first reset control lines RST1(i) and RST1(i+1)), a plurality of second reset control lines (e.g., second reset control lines RST2(i) and RST2(i+1)), and a plurality of first electrodes of storage capacitors of first pixel circuits (e.g., first electrodes 391a, 391b, and 391c). The emission control lines, first reset control lines, first scan lines, and second reset control lines may be substantially zigzag lines extending along the first direction X. Among them, the first reset control line and the first scan line are bent toward the side away from the seventh active layer 370c, and the light-emitting control line and the second reset control line are bent toward the side away from the first active layer 310c, so that the first reset control line, the first scan line, the light-emitting control line and the second reset control line avoid the first light-transmitting area to ensure the area of ​​the first light-transmitting area.

[0339] FIG36A is a schematic diagram of the first display area after the second conductive layer is formed in FIG33 . FIG36B is a schematic diagram of a circuit island in FIG36A . In some examples, as shown in FIG36A and FIG36B , the second conductive layer of the first display area may include at least: a plurality of second scanning auxiliary lines (e.g., including second scanning auxiliary lines GL2b(i) and GL2b(i+1)), and second electrodes of storage capacitors of a plurality of first pixel circuits (e.g., including second electrodes 392a, 392b, and 392c). The second scanning auxiliary lines may be shaped roughly like zigzag lines extending along the first direction X. The second scanning auxiliary lines GL2b(i) may bend away from the seventh active layer 370c and located on the side of the first scanning line GL1(i) opposite to the second direction Y, thereby avoiding the first light-transmitting area.

[0340] Figure 37A is a schematic diagram of the first display area after the second semiconductor layer is formed in Figure 33. Figure 37B is a schematic diagram of a circuit island area in Figure 37A. In some examples, as shown in Figures 37A and 37B, the second semiconductor layer of the first display area may include at least: active layers of the second type transistors of multiple first pixel circuits (for example, including: the second active layer 320a of the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b, and the second active layer 320c of the second transistor 32c of the first pixel circuit 11c). Within the circuit island area, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be approximately symmetrical about the first centerline O1, and the second semiconductor layer patterns of the first pixel circuits 11b and 11c may be approximately symmetrical about the second centerline O2.

[0341] FIG38A is a schematic diagram of the first display area after the third conductive layer is formed in FIG33 . FIG38B is a schematic diagram of a circuit island area in FIG38A . In some examples, as shown in FIG38A and FIG38B , the third conductive layer in the first display area may include at least: a plurality of second scan lines (e.g., second scan lines GL2(i) and GL2(i+1)), a plurality of first initial signal lines (e.g., first initial signal lines INIT1(i) and INIT1(i+1)), a plurality of second initial signal lines (e.g., second initial signal lines INIT2(i) and INIT2(i+1)), and a plurality of third initial signal lines (e.g., third initial signal lines INIT3(i) and INIT3(i+1)). The first initial signal lines, the second scan lines, the second initial signal lines, and the third initial signal lines may each be substantially zigzag lines extending along the first direction X. The orthographic projections of the first initial signal line and the first reset control line on the substrate may at least partially overlap, the orthographic projections of the second scan line and the second auxiliary scan line on the substrate may at least partially overlap, the orthographic projections of the third initial signal line and the light-emitting control line on the substrate may at least partially overlap, and the orthographic projections of the second initial signal line and the second reset control line on the substrate may at least partially overlap. This example utilizes an overlapping design for routing lines on different conductive layers to save wiring space and improve light transmittance in the first display area.

[0342] FIG39 is a schematic diagram of a circuit island region after the fifth insulating layer is formed in FIG33. In some examples, as shown in FIG39, the fifth insulating layer in the first display region may have a plurality of vias, such as first to sixteenth vias V1 to V16, eighteenth to twenty-eighth vias V18 to V28, and thirty-first to fifty-first vias V31 to V51.

[0343] In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer in the first via hole V1 to the sixteenth via hole V16 and the eighteenth via hole V18 to the twenty-eighth via hole V28 can be removed to expose a portion of the surface of the first semiconductor layer. The fifth insulating layer and the fourth insulating layer in the thirty-first via hole V3 to the thirty-sixth via hole V36 can be removed to expose a portion of the surface of the second semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the thirty-seventh via hole V37 to the thirty-ninth via hole V39 can be removed to expose a portion of the surface of the first conductive layer. The fifth insulating layer, the fourth insulating layer, and the third insulating layer in the fortieth via hole V40 to the forty-fourth via hole V44 can be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in the forty-fifth via hole V45 to the fifty-first via hole V51 can be removed to expose a portion of the surface of the third conductive layer.

[0344] Figure 40A is a schematic diagram of the first display area after the fourth conductive layer is formed in Figure 33. Figure 40B is a schematic diagram of the fourth conductive layer in Figure 40A. Figure 40C is a schematic diagram of a circuit island area in Figure 40A.

[0345] In some examples, as shown in Figures 40A to 40C, the fourth conductive layer of the first display area may include at least: a plurality of connecting electrodes (for example, including the first connecting electrode 401 to the sixteenth connecting electrode 416, the twenty-second connecting electrode 422 to the twenty-sixth connecting electrode 426, and the thirty-eighth connecting electrode 438 to the forty-first connecting electrode 441).

[0346] In some examples, the shape of the first connection electrode 401 can be substantially a zigzag shape extending along the second direction Y. One end of the first connection electrode 401 can be electrically connected to the first active layer 310 a through the first via hole V1, and the other end can be electrically connected to the second active layer 320 a of the second transistor 32 a of the first pixel circuit 11 a through the thirty-second via hole V32, and electrically connected to the sixth active layer 360 a of the sixth transistor 36 a of the first pixel circuit 11 a through the fourth via hole V4.

[0347] In some examples, the second connection electrode 402 may be shaped substantially as a strip structure extending along the second direction Y. One end of the second connection electrode 402 may be electrically connected to the second active layer 320 a of the second transistor 32 a of the first pixel circuit 11 a through a thirty-first via hole V31, and the other end may be electrically connected to the first electrode 391 a of the storage capacitor of the first pixel circuit 11 a through a thirty-seventh via hole V37.

[0348] In some examples, the third connection electrode 403 may be substantially rectangular in shape. The third connection electrode 403 may be electrically connected to the fourth active layer 340a of the fourth transistor 34a of the first pixel circuit 11a through the second via hole V2.

[0349] In some examples, the fourth connection electrode 404 may be shaped substantially like a zigzag line extending along the second direction Y. One end of the fourth connection electrode 404 may be electrically connected to the third active layer 330 a of the third transistor 33 a of the first pixel circuit 11 a through a third via hole V3, and the other end may be electrically connected to the eighth active layer 380 a of the eighth transistor 38 a of the first pixel circuit 11 a through a ninth via hole V9.

[0350] In some examples, the fifth connection electrode 405 may be shaped substantially as a strip structure extending along the second direction Y. One end of the fifth connection electrode 405 may be electrically connected to the fifth active layer 350 a of the fifth transistor 35 a of the first pixel circuit 11 a through a fifth via hole V5, and the other end may be electrically connected to the second electrode 392 a of the storage capacitor of the first pixel circuit 11 a through a fortieth via hole V40.

[0351] In some examples, the sixth connection electrode 406 may be substantially rectangular in shape. The sixth connection electrode 406 may be electrically connected to the sixth active layer 360a of the sixth transistor 36a of the first pixel circuit 11a through a sixth via hole V6.

[0352] In some examples, the seventh connection electrode 407 may be shaped substantially like a dumbbell. One end of the seventh connection electrode 407 may be electrically connected to the integrated structure of the seventh active layers 370a and 370b through a seventh via hole V7, and the other end may be electrically connected to the second initial signal line INIT2(i) through a fifty-first via hole V51.

[0353] In some examples, the eighth connection electrode 408 may be substantially L-shaped. One end of the eighth connection electrode 408 may be connected to the eighth active layer 380a through the eighth via V8, and the other end may be electrically connected to the third initial signal line INIT3(i) through the forty-seventh via V47.

[0354] In some examples, the ninth connection electrode 409 may be shaped substantially as a strip structure extending along the first direction X. One end of the ninth connection electrode 409 may be electrically connected to the second electrode 392 a of the storage capacitor of the first pixel circuit 11 a through a forty-first via hole V41 , and the other end may be electrically connected to the second electrode 392 b of the storage capacitor of the first pixel circuit 11 b through a forty-second via hole V42 .

[0355] In some examples, the tenth connection electrode 410 may be shaped substantially like a dumbbell. One end of the tenth connection electrode 410 may be connected to the integrated structure of the first active layers 310a and 310b through the tenth via hole V10, and the other end may be electrically connected to the first initial signal line INIT1(i) through the forty-fifth via hole V45.

[0356] In some examples, the shape of the eleventh connection electrode 411 can be substantially a zigzag shape extending along the second direction Y. One end of the eleventh connection electrode 411 can be electrically connected to the first active layer 310 b of the first pixel circuit 11 b through the eleventh via hole V11, and the other end can be electrically connected to the second active layer 320 b of the second transistor 32 b of the first pixel circuit 11 b through the thirty-fourth via hole V34, and electrically connected to the sixth active layer 360 b of the sixth transistor 36 b of the first pixel circuit 11 b through the fourteenth via hole V14.

[0357] In some examples, the twelfth connection electrode 412 may be shaped substantially as a strip structure extending along the second direction Y. One end of the twelfth connection electrode 412 may be electrically connected to the second active layer 320 b of the second transistor 32 b of the first pixel circuit 11 b through a thirty-third via hole V33, and the other end may be electrically connected to the first electrode 391 b of the storage capacitor of the first pixel circuit 11 b through a thirty-eighth via hole V38.

[0358] In some examples, the thirteenth connection electrode 413 may be substantially rectangular in shape. The thirteenth connection electrode 413 may be electrically connected to the fourth active layer 340b of the fourth transistor 34b of the first pixel circuit 11b through the twelfth via hole V12.

[0359] In some examples, the shape of the fourteenth connection electrode 414 can be substantially a zigzag line extending along the second direction Y. One end of the fourteenth connection electrode 414 can be electrically connected to the third active layer 330 b of the third transistor 33 b of the first pixel circuit 11 b through the thirteenth via hole V13, and the other end can be electrically connected to the eighth active layer 380 b of the first pixel circuit 11 b through the nineteenth via hole V19.

[0360] In some examples, the shape of the fifteenth connection electrode 415 can be substantially a strip structure extending along the second direction Y. One end of the fifteenth connection electrode 415 can be electrically connected to the integrated structure of the fifth active layer 350b of the fifth transistor 35b of the first pixel circuit 11b and the fifth active layer 350c of the fifth transistor 35c of the first pixel circuit 11c through a fifteenth via hole V15, and the other end can be electrically connected to the integrated structure of the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode 392c of the storage capacitor of the first pixel circuit 11c through a forty-third via hole V43.

[0361] In some examples, the shape of the sixteenth connection electrode 416 may be substantially rectangular. The sixteenth connection electrode 416 may be electrically connected to the sixth active layer 360b of the sixth transistor 36b of the first pixel circuit 11b through the sixteenth via hole V16.

[0362] In some examples, the shape of the twenty-second connection electrode 422 can be substantially a strip structure extending along the second direction Y. One end of the twenty-second connection electrode 422 can be electrically connected to the second active layer 320 c of the second transistor 32 c of the first pixel circuit 11 c through a thirty-fifth via hole V35, and the other end can be electrically connected to the first electrode 391 c of the storage capacitor of the first pixel circuit 11 c through a thirty-ninth via hole V39.

[0363] In some examples, the shape of the twenty-third connection electrode 423 may be substantially rectangular. The twenty-third connection electrode 423 may be electrically connected to the fourth active layer 340c of the fourth transistor 34c of the first pixel circuit 11c through the twenty-second via hole V22.

[0364] In some examples, the shape of the twenty-fourth connection electrode 424 can be substantially a zigzag line extending along the second direction Y. One end of the twenty-fourth connection electrode 424 can be electrically connected to the third active layer 330 c of the third transistor 33 c of the first pixel circuit 11 c through the twenty-third via hole V23, and the other end can be electrically connected to the eighth active layer 380 c of the eighth transistor 38 c of the first pixel circuit 11 c through the twenty-eighth via hole V28.

[0365] In some examples, the twenty-fifth connection electrode 425 may be substantially in the shape of a strip structure extending along the first direction X. The twenty-fifth connection electrode 425 may be electrically connected to the second electrode 392 c of the storage capacitor of the first pixel circuit 11 c through a forty-fourth via hole V44 .

[0366] In some examples, the twenty-sixth connection electrode 426 may be substantially in the shape of a strip structure extending along the first direction X. The twenty-sixth connection electrode 426 may be electrically connected to the sixth active layer 360 c of the sixth transistor 36 c of the first pixel circuit 11 c through the twenty-fifth via hole V25 , and may also be electrically connected to the seventh active layer 370 c through the twenty-sixth via hole V26 .

[0367] In some examples, the shape of the thirty-eighth connection electrode 438 can be substantially U-shaped. One end of the thirty-eighth connection electrode 438 can be electrically connected to the integrated structure of the eighth active layers 380 b and 380 c through the eighteenth via hole V18, another end can be electrically connected to the third initial signal line INIT3(i) through the forty-eighth via hole V48, and another end can be electrically connected to the third initial signal line INIT3(i) through the forty-ninth via hole V49.

[0368] In some examples, the thirty-ninth connection electrode 439 may be shaped substantially like a dumbbell. One end of the thirty-ninth connection electrode 439 may be electrically connected to the first active layer 310c through the twentieth via hole V20, and the other end may be electrically connected to the first initial signal line INIT1(i) through the forty-sixth via hole V46.

[0369] In some examples, the shape of the fortieth connection electrode 440 can be substantially a zigzag shape extending along the second direction Y. One end of the fortieth connection electrode 440 can be connected to the first active layer 310c through the twenty-first via hole V21, and the other end can be electrically connected to the second active layer 320c of the second transistor 32c of the first pixel circuit 11c through the thirty-sixth via hole V36, and electrically connected to the sixth active layer 360c of the sixth transistor 36c of the first pixel circuit 11c through the twenty-fourth via hole V24.

[0370] In some examples, the forty-first connection electrode 441 may be shaped substantially like a dumbbell. One end of the forty-first connection electrode 441 may be connected to the seventh active layer 370c through the twenty-seventh via hole V27, and the other end may be electrically connected to the second initial signal line INIT2(i) through the fiftieth via hole V50.

[0371] Figure 41 is a schematic diagram of a circuit island region after the seventh insulating layer is formed in Figure 33. In some examples, as shown in Figure 41, the seventh insulating layer in the first display area can be provided with a plurality of vias, such as vias 61 to 68 (V61 to V68). The seventh and sixth insulating layers within vias 61 to V68 can be removed to expose a portion of the surface of the fourth conductive layer.

[0372] Figure 42A is a schematic diagram of the first display area after the fifth conductive layer is formed in Figure 33. Figure 42B is a schematic diagram of the fifth conductive layer in Figure 42A. Figure 42C is a schematic diagram of a circuit island in Figure 42A.

[0373] In some examples, as shown in Figures 42A to 42C, the fifth conductive layer of the first display area may include at least: multiple data lines (for example, including data lines DL(j), DL(j+1), DL(j+2), DL(j+3), DL(j+4), DL(j+5), DL(j+6), DL(j+7)), multiple first anode connecting electrodes (for example, including first anode connecting electrodes 451a, 451b and 451c), and multiple first shielding electrodes (for example, including first shielding electrodes 511a, 511b and 511c).

[0374] In some examples, the first anode connection electrodes 451a, 451b, and 451c can be substantially dumbbell-shaped. The first anode connection electrode 451a can be electrically connected to the sixth connection electrode 406 through the sixty-second via hole V62, thereby electrically connecting to the sixth transistor of the first pixel circuit 11a. The first anode connection electrode 451b can be electrically connected to the sixteenth connection electrode 416 through the sixty-fifth via hole V65, thereby electrically connecting to the sixth transistor of the first pixel circuit 11b. The first anode connection electrode 451c can be electrically connected to the twenty-sixth connection electrode 426 through the sixty-seventh via hole V67, thereby electrically connecting to the sixth transistor of the first pixel circuit 11c.

[0375] In some examples, the first shielding electrodes 511a and 511b can be interconnected integral structures. The first shielding electrodes 511a and 511b can be substantially symmetrical about the first centerline O1. The orthographic projection of the first shielding electrode 511a on the substrate can cover the orthographic projection of the second connecting electrode 402 on the substrate, thereby shielding the first node of the first pixel circuit 11a. The orthographic projection of the first shielding electrode 511b on the substrate can cover the orthographic projection of the twelfth connecting electrode 412 on the substrate, thereby shielding the first node of the first pixel circuit 11b. The orthographic projection of the first shielding electrode 511c on the substrate can cover the orthographic projection of the twenty-second connecting electrode 422 on the substrate, thereby shielding the first node of the first pixel circuit 11c, thereby shielding the first nodes of the first pixel circuits 11a, 11b, and 11c from the influence of other signals.

[0376] In some examples, the plurality of data lines may be substantially in the shape of a zigzag extending along the second direction Y. The data lines DL(j) and DL(j+1) may be adjacent, and the data lines DL(j+2) and DL(j+3) may be adjacent. The data line DL(j+1) may be electrically connected to the third connection electrode 403 through the sixty-first via hole V61, thereby being electrically connected to the first electrode of the fourth transistor 34a of the first pixel circuit 11a. The data line DL(j+2) may be electrically connected to the thirteenth connection electrode 413 through the sixty-fourth via hole V64, thereby being electrically connected to the first electrode of the fourth transistor 34b of the first pixel circuit 11b. The data line DL(j+3) may be electrically connected to the twenty-third connection electrode 423 through the sixty-sixth via hole V66, thereby being electrically connected to the first electrode of the fourth transistor 34c of the first pixel circuit 11c.

[0377] In some examples, four data lines can be set through each circuit island area, and three of the four data lines can be electrically connected to the three first pixel circuits in the circuit island area respectively. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) can be configured to provide data signals to the first pixel circuit (for example, the first pixel circuit 11b) connected to the first light-emitting element that emits the third color light. The data lines DL(j), DL(j+2), DL(j+4), and DL(j+6) can be configured to provide data signals to multiple first pixel circuits arranged in alternate rows. For example, the data lines DL(j) and DL(j+4) are not electrically connected to the first pixel circuit in the i-th row circuit island area, but are electrically connected to the first pixel circuit in the i+1-th row circuit island area; the data lines DL(j+2) and DL(j+6) are electrically connected to the first pixel circuit in the i-th row circuit island area, but are not electrically connected to the first pixel circuit in the i+1-th row circuit island area. In this example, a data line that provides a data signal to a first pixel circuit (e.g., first pixel circuit 11b) connected to a first light-emitting element emitting light of the third color is electrically connected to a plurality of first pixel circuits arranged in alternate rows, providing data signals to the plurality of first pixel circuits arranged in alternate rows. The arrangement of the data lines in this example facilitates wiring layout.

[0378] FIG43 is a schematic diagram of a circuit island region after the eighth insulating layer is formed in FIG33 . In some examples, as shown in FIG43 , the eighth insulating layer in the first display region may be provided with a plurality of vias, such as vias 71 to 75 V71. The eighth insulating layer within vias 71 to 75 V75 may be removed to expose a portion of the surface of the fifth conductive layer.

[0379] FIG44A is a schematic diagram of the first display area after the sixth conductive layer is formed in FIG33 . FIG44B is a schematic diagram of the sixth conductive layer in FIG44A . In some examples, as shown in FIG44A and FIG44B , the sixth conductive layer in the first display area may include at least: a third power connection line 463, a plurality of second anode connection electrodes (e.g., including second anode connection electrodes 452a, 452b, 452c, and 452d), and a plurality of anode connection bars 453.

[0380] In some examples, the second anode connection electrodes 452a and 452c can be roughly dumbbell-shaped, and the second anode connection electrodes 452b and 452d can both be roughly rectangular. The second anode connection electrode 452a can be electrically connected to the first anode connection electrode 451a through the seventy-first via hole V71 to achieve electrical connection with the sixth transistor of the first pixel circuit 11a. The second anode connection electrode 452c can be electrically connected to the first anode connection electrode 451c through the seventy-third via hole V73 to achieve electrical connection with the sixth transistor of the first pixel circuit 11c. The second anode connection electrode 452b can be electrically connected to the first anode connection electrode 451b through the seventy-second via hole V72 to achieve electrical connection with the sixth transistor of the first pixel circuit 11b. The second anode connection electrode 452b can be electrically connected to the second anode connection electrode 452d through the anode connection bar 453. The second anode connection electrodes 452b, 452d and the anode connection bar 453 can be an integrated structure connected to each other. The second anode connection electrode 452d connected to the second anode connection electrode 452b of the i-th row, m-th column circuit island area can be located between the i-th row, m-th column circuit island area and the i-th row, m+2 column circuit island area and close to the i-1-th row circuit island area. The anode connection bar 453 can be substantially L-shaped.

[0381] In some examples, the third power connection line 463 can have a mesh structure, for example, including an extension along the second direction Y and an extension whose extension direction intersects both the first direction X and the second direction Y. The third power connection line 463 can be electrically connected to the integrated structure of the first shielding electrodes 511a and 511b through the seventy-fourth via V74, and can also be electrically connected to the first shielding electrode 511c through the seventy-fifth via V75. In this example, the third power connection line 463 can achieve mesh transmission of the first voltage signal within the first display area, thereby ensuring the uniformity of the first voltage signal.

[0382] FIG45 is a schematic diagram of the stacking of the first semiconductor layer, the first conductive layer, the second conductive layer, the second semiconductor layer, the third conductive layer, and the anode layer in FIG33. In some examples, as shown in FIG33 and FIG45, the anode layer of the first display area may include at least: anodes of a plurality of first light-emitting elements (e.g., anode 131a of first light-emitting element 13a, anode 131b of first light-emitting element 13b, anode 131c of first light-emitting element 13c, and anode 131d of first light-emitting element 13d), and a plurality of third anode connecting electrodes (e.g., third anode connecting electrodes 132a, 132b, 132c, and 132d).

[0383] In some examples, the shapes of anodes 131a, 131b, 131c, and 131d can be approximately circular or elliptical. The shapes of third anode connection electrodes 132a, 132b, 132c, and 132d can be approximately rectangular. Anode 131a and third anode connection electrode 132a can be interconnected as a single unit. Third anode connection electrode 132a can be electrically connected to second anode connection electrode 452a to achieve electrical connection with first pixel circuit 11a. Anode 131b and third anode connection electrode 132b can be interconnected as a single unit. Third anode connection electrode 132b can be electrically connected to second anode connection electrode 452b to achieve electrical connection with first pixel circuit 11b. Anode 131c and third anode connection electrode 132c can be interconnected as a single unit. Third anode connection electrode 132c can be electrically connected to second anode connection electrode 452c to achieve electrical connection with first pixel circuit 11c. Anode 131d and third anode connection electrode 132d can be interconnected as a single unit. The third anode connection electrode 132d may be electrically connected to the second anode connection electrode 452d. Since the second anode connection electrodes 452d and 452b are an integral structure, the third anode connection electrode 132d is electrically connected to the first pixel circuit 11b.

[0384] In some examples, the orthographic projection of the first light-emitting element 13d and the connected first pixel circuit 11b on the substrate does not overlap, and the orthographic projection of the first light-emitting element 13d and a first transistor on the substrate at least partially overlap. The orthographic projection of the first light-emitting element 13b and the connected first pixel circuit 11b on the substrate may not overlap or partially overlap, and the first light-emitting element 13b may at least partially overlap with the orthographic projection of a seventh transistor on the substrate. The orthographic projection of the first light-emitting element 13a and the connected first pixel circuit 11a on the substrate at least partially overlap, and the orthographic projection of the first light-emitting element 13c and the connected first pixel circuit 11c on the substrate at least partially overlap.

[0385] In some examples, as shown in Figures 33 and 45, the first transistor 31c of the first pixel circuit 11c can be located below a first light-emitting element 13d, and the seventh transistor 37c of the first pixel circuit 11c can be located below a first light-emitting element 13b. The first transistor 31c and the seventh transistor 37c of the first pixel circuit 11c are located below different first light-emitting elements that emit green light. The orthographic projection of the anode 131b of the first light-emitting element 13b on the substrate can cover the orthographic projection of the first active layer 310c of the first transistor of the first pixel circuit 11c on the substrate; the orthographic projection of the anode 131d of the first light-emitting element 13d on the substrate can cover the orthographic projection of the seventh active layer 370c of the seventh transistor of the first pixel circuit 11c on the substrate.

[0386] The display substrate of this example disassembles the reset transistor of the third first pixel circuit within the circuit island area and places it beneath a different first light-emitting element. This prevents the reset transistor from being blocked by the anode of the light-emitting element, which would otherwise affect the light transmittance of the first display area. This example improves the light transmittance of the first display area. Compared to the previous two examples, the display substrate of this example achieves better light transmittance.

[0387] The rest of the description about the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0388] The above embodiments are merely examples. Some features of the above embodiments may be combined with each other. This embodiment does not limit this.

[0389] In other examples, the reset transistor of the first first pixel circuit in the circuit island area can be disassembled, for example, the first transistor of the first first pixel circuit is placed under the first light-emitting element that emits green light, and the seventh transistor of the first first pixel circuit is placed under another first light-emitting element that emits green light.

[0390] In other examples, the reset transistors of two first pixel circuits (e.g., the first first pixel circuit and the second first pixel circuit, or the first first pixel circuit and the third first pixel circuit, or the second first pixel circuit and the third first pixel circuit) within the circuit island region can be disassembled and reassembled. For example, the first transistors of the reassembled two first pixel circuits can be placed below a first light-emitting element that emits green light, and the seventh transistors of the reassembled two first pixel circuits can be placed below another first light-emitting element that emits green light.

[0391] In other examples, the reset transistor of at least one first pixel circuit in the circuit island area can be disassembled (or disassembled and reassembled), and the at least one disassembled or reassembled reset transistor can be placed below the first light-emitting element that emits red light, or placed below the first light-emitting element that emits blue light, or a part of the reset transistors can be placed below the first light-emitting element that emits red light, and another part of the reset transistors can be placed below the first light-emitting element that emits blue light.

[0392] In other examples, the reset transistors of at least one first pixel circuit in the circuit island area can be disassembled (or disassembled and reassembled), and the disassembled or reassembled multiple reset transistors are placed under the same first light-emitting element. For example, the disassembled or reassembled reset transistors are all placed under the first light-emitting element that emits green light, and the number of reset transistors placed under different first light-emitting elements that emit green light can be different. For example, reset transistors are placed under two first light-emitting elements that emit green light electrically connected to the same first pixel circuit, and one reset transistor is placed under one of the first light-emitting elements, and two or three reset transistors can be placed under the other first light-emitting element.

[0393] The display substrate provided in this embodiment utilizes a first pixel circuit to drive a first light-emitting element in a first display area using at least one-to-many configuration. This allows the number of first pixel circuits in the first display area to be less than the number of first light-emitting elements, thereby improving light transmittance in the first display area. Furthermore, by adjusting the position of the reset transistor in the first pixel circuit in the first display area, the anode of the first light-emitting element can be used to shield the first pixel circuit, thereby improving light transmittance in the first display area.

[0394] This embodiment further provides a display substrate, comprising: a substrate, and a plurality of first pixel circuits and a plurality of first light-emitting elements located in a first display area. At least one of the plurality of first pixel circuits is electrically connected to a first light-emitting element, and at least one first pixel circuit is electrically connected to at least two first light-emitting elements. The first pixel circuit includes: at least one reset transistor. The orthographic projections of the at least two first light-emitting elements electrically connected to the same first pixel circuit on the substrate at least partially overlap with the orthographic projections of the reset transistors of the plurality of first pixel circuits on the substrate.

[0395] In some exemplary embodiments, the anode of each of the at least two first light-emitting elements electrically connected to the same first pixel circuit includes an orthographic projection of an active layer of at least one reset transistor on the substrate.

[0396] In some exemplary embodiments, the first pixel circuit includes: a first reset transistor and a second reset transistor. An orthographic projection of one of two first light-emitting elements electrically connected to the same first pixel circuit on the substrate at least partially overlaps with an orthographic projection of the first reset transistor on the substrate; and an orthographic projection of the other of the at least two first light-emitting elements on the substrate at least partially overlaps with an orthographic projection of the second reset transistor on the substrate.

[0397] In some exemplary embodiments, the orthographic projection of the first light-emitting element on the substrate overlaps with the second reset transistor, and the orthographic projection of the first pixel circuit connected to the first light-emitting element on the substrate may not overlap.

[0398] The description of the display substrate of this example can refer to the description of the aforementioned embodiment, so it will not be repeated here.

[0399] Figure 46 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 46 , this embodiment provides a display device comprising: a display substrate 91; and a sensor 92 located on the light-emitting side of the light-emitting structure layer, away from the display substrate 91. Sensor 92 may be located on the non-display surface of the display substrate 91. The orthographic projection of sensor 92 on the display substrate 91 may overlap with the first display area A1.

[0400] In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a static image or a dynamic image, wherein the dynamic image may be a video) display function. For example, the display device may be: a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a painting screen, a personal digital assistant (PDA), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information query device (such as business query equipment for e-government, banks, hospitals, power departments, etc.), a monitor, and the like. For another example, the display device may also be a microdisplay, a VR device or an AR device containing a microdisplay, and the like.

[0401] The drawings in this disclosure only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of the present disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments. It should be noted that the above-mentioned embodiments or implementation methods are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents shown and described in detail herein. Various modifications, replacements or omissions can be made to the form and details of the implementation without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising: A substrate including a first display area; A plurality of first pixel circuits and a plurality of first light-emitting elements are located in the first display area; At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to at least two first light emitting elements; The at least one first pixel circuit comprises: at least one reset transistor; An orthographic projection of at least one first light emitting element among the plurality of first light emitting elements on the substrate at least partially overlaps with an orthographic projection of a reset transistor of the at least one first pixel circuit on the substrate.

2. The display substrate according to claim 1, wherein: The plurality of first light emitting elements include: a plurality of first light emitting elements emitting light of different colors; The orthographic projections of the plurality of first light emitting elements emitting light of the same color on the substrate at least partially overlap with the orthographic projections of the reset transistors of the plurality of first pixel circuits on the substrate.

3. The display substrate according to claim 1 or 2, wherein: The orthographic projection of the anode of the at least one first light-emitting element on the substrate includes the orthographic projection of the active layer of the at least one reset transistor on the substrate.

4. The display substrate according to claim 2, wherein: The at least one first pixel circuit comprises: a first reset transistor and a second reset transistor; The orthographic projection of the first reset transistor of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of a first light-emitting element on the substrate, and the orthographic projection of the second reset transistor of the at least one first pixel circuit on the substrate at least partially overlaps with the orthographic projection of another first light-emitting element emitting light of the same color on the substrate.

5. The display substrate according to claim 4, wherein: The orthographic projection of the first light-emitting element on the substrate overlaps with the second reset transistor, and the orthographic projection of the first pixel circuit connected to the first light-emitting element on the substrate does not overlap with the orthographic projection of the first pixel circuit on the substrate.

6. The display substrate according to any one of claims 1 to 5, wherein: The plurality of first light-emitting elements are divided into a plurality of light-emitting units, each of which includes: a first light-emitting element emitting a first color light, a first light-emitting element emitting a second color light, and two first light-emitting elements emitting a third color light; The first light-emitting element emitting the first color light is electrically connected to a first pixel circuit; the first light-emitting element emitting the second color light is electrically connected to a first pixel circuit; and the two first light-emitting elements emitting the third color light are electrically connected to the same first pixel circuit.

7. The display substrate according to claim 6, wherein: The first light emitting element emitting the first color light and the first light emitting element emitting the second color light in the light emitting unit are arranged in the same row, the two first light emitting elements emitting the third color light are arranged in the same row, and the four first light emitting elements in the light emitting unit are arranged in different columns; The first color light is red light, the second color light is blue light, and the third color light is green light.

8. The display substrate according to claim 6 or 7, wherein: The first display area includes: a plurality of circuit island areas separated from each other and arranged in an array, each circuit island area includes: three first pixel circuits arranged in sequence along a first direction; two adjacent rows of circuit island areas are staggered; The three first pixel circuits in the circuit island area are electrically connected to four first light-emitting elements in one light-emitting unit.

9. The display substrate according to claim 8, wherein: Any two adjacent first pixel circuits in the circuit island area are symmetrically arranged about a midline of the two adjacent first pixel circuits along the first direction.

10. The display substrate according to claim 8, wherein: The data line connected to the first pixel circuit connected to the first light emitting element emitting the third color light is configured to provide data signals to a plurality of first pixel circuits arranged in alternate rows.

11. The display substrate according to claim 8, wherein: The first pixel circuit connected to the two first light emitting elements emitting the third color light in the light emitting unit is located between the first pixel circuit connected to the first light emitting element emitting the first color light and the first pixel circuit connected to the first light emitting element emitting the second color light.

12. The display substrate according to claim 8, wherein: Each first pixel circuit in the circuit island region comprises: a driving transistor, a first reset transistor, a second reset transistor and a third reset transistor, wherein the first reset transistor is configured to reset the second electrode of the driving transistor, the second reset transistor is configured to reset the anode of the first light-emitting element connected to the first pixel circuit, and the third reset transistor is configured to reset the first electrode of the driving transistor; The active layers of the first reset transistors of the three first pixel circuits in the circuit island area are interconnected as an integrated structure, the active layers of the second reset transistors of the three first pixel circuits are interconnected as an integrated structure, and the active layers of the third reset transistors of the three first pixel circuits are interconnected as an integrated structure.

13. The display substrate according to claim 12, wherein: The integrated structure of the active layer of the first reset transistor of the three first pixel circuits in the circuit island area, the integrated structure of the active layer of the second reset transistor of the three first pixel circuits, and the integrated structure of the active layer of the third reset transistor of the three first pixel circuits are projected on the substrate, and at least partially overlap with the orthographic projection of different first light-emitting elements emitting third color light on the substrate.

14. The display substrate according to claim 12, wherein: The integral structure of the active layers of the three second reset transistors in one circuit island and the integral structure of the active layers of the three first reset transistors in the adjacent circuit island in the second direction are projected on the substrate in a manner that at least partially overlaps with the projection of the first light-emitting element emitting the third color light on the substrate; The first light-emitting element emitting third color light is connected to a first pixel circuit in the circuit island area, and has no overlap with the positive projection of transistors of the first pixel circuit except the second reset transistor on the substrate; the second direction intersects the first direction.

15. The display substrate according to claim 8, wherein: Each first pixel circuit in the circuit island region at least comprises: a driving transistor, a first reset transistor, and a second reset transistor, wherein the first reset transistor is configured to reset the second electrode of the driving transistor, and the second reset transistor is configured to reset the anode of the first light-emitting element connected to the first pixel circuit; The active layer of the first reset transistor and the active layer of the second reset transistor of the third first pixel circuit along the first direction in the circuit island area are aligned in a second direction, and the second direction intersects the first direction; The orthographic projection of the active layer of the first reset transistor of the third first pixel circuit on the substrate at least partially overlaps with the orthographic projection of a first light-emitting element emitting third color light on the substrate, and the orthographic projection of the active layer of the second reset transistor of the third first pixel circuit on the substrate at least partially overlaps with the orthographic projection of another first light-emitting element emitting third color light on the substrate.

16. The display substrate according to claim 15, wherein: The orthographic projection of the anode of the one first light-emitting element emitting the third color light on the substrate includes the orthographic projection of the active layer of the first reset transistor of the third first pixel circuit on the substrate, and the orthographic projection of the anode of the other first light-emitting element emitting the third color light on the substrate includes the orthographic projection of the active layer of the second reset transistor of the third first pixel circuit on the substrate.

17. The display substrate according to any one of claims 1 to 16, wherein: In a direction perpendicular to the display substrate, the display substrate comprises: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer and a sixth conductive layer arranged on the substrate; The sixth conductive layer at least includes: a plurality of auxiliary electrodes; the orthographic projection of the auxiliary electrodes on the substrate includes the orthographic projection of the light emitting region of the first light emitting element on the substrate.

18. The display substrate according to claim 17, wherein: The plurality of auxiliary electrodes are connected through a plurality of auxiliary connecting bars to form a mesh structure, and the mesh structure is connected to a first voltage signal.

19. A display device, comprising a display substrate as claimed in any one of claims 1 to 18, and a sensor located on a non-display surface side of the display substrate, wherein an orthographic projection of the sensor on the display substrate at least partially overlaps with a first display area of ​​the display substrate.

20. A display substrate, comprising: A substrate including a first display area; A plurality of first pixel circuits and a plurality of first light-emitting elements are located in the first display area; At least one first pixel circuit among the plurality of first pixel circuits is electrically connected to one first light emitting element, and at least one first pixel circuit is electrically connected to at least two first light emitting elements; The first pixel circuit includes: at least one reset transistor; The orthographic projections of at least two first light-emitting elements electrically connected to the same first pixel circuit on the substrate at least partially overlap with the orthographic projections of the reset transistors of the plurality of first pixel circuits on the substrate.

21. The display substrate according to claim 20, wherein: The orthographic projection of the anode of each of the at least two first light-emitting elements electrically connected to the same first pixel circuit on the substrate includes the orthographic projection of the active layer of at least one reset transistor on the substrate.

22. The display substrate according to claim 20, wherein: The first pixel circuit includes: a first reset transistor and a second reset transistor; An orthographic projection of one of the two first light-emitting elements electrically connected to the same first pixel circuit on the substrate at least partially overlaps with an orthographic projection of the first reset transistor on the substrate; an orthographic projection of another first light-emitting element of the at least two first light-emitting elements on the substrate at least partially overlaps with an orthographic projection of the second reset transistor on the substrate.

23. The display substrate according to claim 22, wherein: The orthographic projection of the first light-emitting element on the substrate overlaps with the second reset transistor, and the orthographic projection of the first pixel circuit connected to the first light-emitting element on the substrate does not overlap with the orthographic projection of the first pixel circuit on the substrate.

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