Display substrate and display device

Abstract

The invention discloses a display substrate which comprises a plurality of pixel driving circuits and a plurality of data signal line groups. One column of pixel driving circuits is divided into n pixel driving circuit groups, and one data signal line group is electrically connected with one column of pixel driving circuits. The data signal line group electrically connected with the mth column of pixel driving circuit comprises a first data signal line, the data signal line group electrically connected with the (m + 1) th column of pixel driving circuit comprises a second data signal line, and the first data signal line and the second data signal line are located between the mth column of pixel driving circuit and the (m + 1) th column of pixel driving circuit. The plurality of anode patch cords electrically connected with the (m + 1) th column of pixel driving circuit comprise a first anode patch cord, and the first anode patch cord comprises a first anode patch part on the same layer as the data signal line. In the row direction, the first anode switching part is located between the first data signal line electrically connected with the mth column of pixel driving circuit and the second data signal line electrically connected with the (m + 1) th column of pixel driving circuit.

Description

Display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] At present, OLED (Organic Light-Emitting Diode) display devices are widely used due to their self-luminescence, fast response, wide viewing angle and ability to be manufactured on flexible substrates. OLED display devices include multiple sub-pixels, each of which includes a pixel driving circuit and a light-emitting device. The pixel driving circuit drives the light-emitting device to emit light, thereby achieving display.

[0003] Summary of the Invention

[0004] On the one hand, a display substrate is provided. The display substrate includes a substrate and a driving circuit layer located on the substrate. The driving circuit layer includes: a plurality of pixel driving circuits and a plurality of data signal line groups, the plurality of pixel driving circuits are arranged in multiple rows and columns, and one column of pixel driving circuits is divided into n pixel driving circuit groups. One data signal line group is electrically connected to a column of pixel driving circuits; the data signal line group includes n data signal lines extending in the column direction and arranged at intervals in the row direction, and one data signal line is electrically connected to all the pixel driving circuits in one pixel driving circuit group. Two adjacent columns of pixel driving circuits are respectively the mth column pixel driving circuit and the m+1th column pixel driving circuit. The data signal line group electrically connected to the mth column pixel driving circuit includes at least one first data signal line, and the first data signal line is located between the mth column pixel driving circuit and the m+1th column pixel driving circuit. Furthermore, the data signal line group electrically connected to the pixel driving circuit of the m+1th column includes at least one second data signal line, and the second data signal line is located between the pixel driving circuit of the mth column and the pixel driving circuit of the m+1th column. A plurality of anode transfer lines are electrically connected to the driving output terminals of the plurality of pixel driving circuits, respectively; wherein the plurality of anode transfer lines electrically connected to the pixel driving circuit of the m+1th column include at least one first anode transfer line, and the first anode transfer line includes: a first anode transfer portion on the same layer as the data signal line. Along the row direction, the first anode transfer portion is located between the first data signal line electrically connected to the pixel driving circuit of the mth column and the second data signal line electrically connected to the pixel driving circuit of the m+1th column. wherein n is a positive integer greater than 2, and m is a positive integer.

[0005] In some embodiments, the display substrate further comprises an anode layer, the anode layer being located on a side of the drive circuit layer away from the substrate. The anode layer comprises a plurality of anodes; the plurality of anodes comprises a first anode and a second anode, and the first anodes and the second anodes are alternately arranged along a column direction. The first anode transition portion extends along a column direction, an orthographic projection of the first anode transition portion on the substrate overlaps with an orthographic projection of the first anode on the substrate, and an orthographic projection of the first anode transition portion on the substrate overlaps with an orthographic projection of the second anode on the substrate, and the first anode transition portion is electrically connected to the second anode.

[0006] In some embodiments, along a column direction, orthographic projections of the first anode and the second anode on the substrate are located between orthographic projections of two ends of the first anode transfer portion on the substrate.

[0007] In some embodiments, the data signal line group electrically connected to the pixel driver circuit in the mth column includes at least one third data signal line, and the third data signal line is located on a side of the pixel driver circuit in the mth column away from the pixels of the pixel driver circuit in the (m+1)th column. The plurality of anode transfer lines electrically connected to the pixel driver circuit in the mth column includes at least one second anode transfer line, and the second anode transfer line includes a second anode transfer portion on the same layer as the data signal line. Along the row direction, the second anode transfer portion is located on a side of the pixel driver circuit in the mth column away from the pixels of the pixel driver circuit in the (m+1)th column.

[0008] In some embodiments, the second anode transition portion extends along the column direction, the orthographic projection of the second anode transition portion on the substrate overlaps with the orthographic projection of the first anode on the substrate, the second anode transition portion is electrically connected to the first anode, and the orthographic projection of the second anode transition portion on the substrate overlaps with the orthographic projection of the second anode on the substrate.

[0009] In some embodiments, along the column direction, the orthographic projections of the first anode and the second anode on the substrate are located between the orthographic projections of two ends of the second anode transfer portion on the substrate.

[0010] In some embodiments, the plurality of columns of pixel driving circuits further include an m+2th column pixel driving circuit, and the m+2th column pixel driving circuit is located on a side of the m+1th column pixel driving circuit away from the mth column pixel driving circuit. The data signal line group electrically connected to the m+1th column pixel driving circuit includes at least one fourth data signal line, and the fourth data signal line is located between the m+1th column pixel driving circuit and the m+2th column pixel driving circuit. The data signal line group electrically connected to the m+2th column pixel driving circuit includes at least one fifth data signal line, and the fifth data signal line is located between the m+1th column pixel driving circuit and the m+2th column pixel driving circuit. The plurality of anode transfer lines electrically connected to the m+2th column pixel driving circuit include a third anode transfer line, and the third anode transfer line includes: a third anode transfer portion on the same layer as the data signal line. Along the row direction, the third anode transfer portion is located between the fourth data signal line electrically connected to the pixel driving circuit of the (m+1)th column and the fifth data signal line electrically connected to the pixel driving circuit of the (m+2)th column.

[0011] In some embodiments, the plurality of anodes further include a third anode, and along the row direction, the third anode overlaps the first anode, and the third anode overlaps the second anode. The third anode transition portion extends along the column direction, and along the column direction, the boundary of the orthographic projection of the third anode transition portion on the substrate overlaps the boundary of the orthographic projection of the third anode on the substrate, and the third anode transition portion is electrically connected to the third anode.

[0012] In some embodiments, along the column direction, an orthographic projection of the third anode on the substrate is located between orthographic projections of two ends of the third anode transfer portion on the substrate.

[0013] In some embodiments, in the same column of pixel driving circuits, the number of the pixel driving circuits in each pixel driving circuit group is equal.

[0014] In some embodiments, the multiple data signal lines in one of the data signal line groups are divided into a first part of data signal lines and a second part of data signal lines, the first part of data signal lines and the second part of data signal lines are respectively located on both sides of the pixel driving circuit, and the number of the data signal lines in the first part of data signal lines is equal to the number of the data signal lines in the second part of data signal lines.

[0015] In some embodiments, the pixel driving circuit includes: a driving transistor, a data writing transistor, a data transfer unit, and a first light-emitting control transistor. The first electrode of the driving transistor and the second electrode of the data writing transistor are electrically connected to the second electrode of the first light-emitting control transistor. The first electrode of the data writing transistor is electrically connected to the data signal line via the data transfer unit. Along the column direction, the data writing transistor is located on a side of the first light-emitting control transistor away from the driving transistor, and the first electrode of the data writing transistor is located on a side of the second electrode of the data writing transistor away from the data writing transistor.

[0016] In some embodiments, the pixel driving circuit further includes a second light emission control transistor and a second reset transistor, wherein the second electrode of the second light emission control transistor is electrically connected to the second electrode of the second reset transistor. In the column direction, the second reset transistor is located on a side of the second light emission control transistor away from the driving transistor, and in the row direction, the second light emission control transistor is adjacent to the first light emission control transistor, and the second reset transistor is adjacent to the data writing transistor.

[0017] In some embodiments, the pixel driving circuits in the same column include: a first portion of pixel driving circuits electrically connected to the second portion of data signal lines, and a second portion of pixel driving circuits electrically connected to the first portion of data signal lines. The data write transistor of the first portion of pixel driving circuits is located between the second reset transistor and the second portion of data signal lines, and the data write transistor of the second portion of pixel driving circuits is located on a side of the second reset transistor away from the first portion of data signal lines. At least one pixel driving circuit in the second portion of pixel driving circuits includes a first data transfer portion, the first data transfer portion being electrically connected to the first electrode of the data write transistor and the data signal line, respectively; the first data transfer portion includes a relief portion, the relief portion being located on a side of the second reset transistor away from the second light-emitting control transistor.

[0018] In some embodiments, the driving circuit layer further includes a second initialization signal line, the second initialization signal line including a first connection portion, the first electrode of the second reset transistor being electrically connected to the first connection portion of the second initialization signal line. Along the column direction, the second initialization signal line is located on a side of the second reset transistor away from the second emission control transistor, and the avoidance portion is located on a side of the first connection portion away from the second emission control transistor.

[0019] In some embodiments, the driver circuit layer further includes a plurality of first power signal lines extending in the column direction and arranged in the row direction, the first power signal lines being electrically connected to the pixel driver circuit. Along the row direction, the first portion of the data signal lines and the second portion of the data signal lines are respectively located on either side of the first power signal lines.

[0020] In some embodiments, the avoiding portion crosses over the first power signal line electrically connected to the second portion of the pixel driving circuit.

[0021] In some embodiments, one data signal line group includes two data signal lines. The driving circuit layer includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer, and a second routing metal layer stacked on the substrate. Both data signal lines in one data signal line group are located in the second routing metal layer.

[0022] In some embodiments, one data signal line group includes four data signal lines. The driving circuit layer further includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer, a second routing metal layer, and a third routing metal layer stacked on the base substrate. At least some of the data signal lines in the data signal line group are located in the second routing metal layer, and / or at least some of the data signal lines in the data signal line group are located in the third routing metal layer.

[0023] In another aspect, a display device is provided, comprising: a display substrate as described in any one of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0025] FIG1 is a structural diagram of a display device according to some embodiments;

[0026] FIG2 is a structural diagram of a display substrate according to some embodiments;

[0027] FIG3 is a cross-sectional view of a display substrate according to some embodiments;

[0028] FIG4 is an equivalent circuit diagram of multiple pixel driving circuits in a display substrate according to some possible implementations;

[0029] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0030] FIG6 is an equivalent circuit diagram of a plurality of pixel driving circuits in a display substrate according to some embodiments;

[0031] FIG7 is a connection diagram of a pixel driving circuit and a light emitting layer according to some embodiments;

[0032] FIG8 is a film layer diagram of the first semiconductor layer in FIG7 ;

[0033] FIG9 is a film layer diagram of the first gate metal layer in FIG7 ;

[0034] FIG10 is a film layer diagram of the first semiconductor layer and the first gate metal layer in FIG7 ;

[0035] FIG11 is a film layer diagram of the second gate metal layer in FIG7 ;

[0036] FIG12 is a film layer diagram of the first semiconductor, the first gate metal layer, and the second gate metal layer in FIG7 ;

[0037] FIG13 is a film layer diagram of the first routing metal layer in FIG7 ;

[0038] FIG14 is a film layer diagram of the first semiconductor, the first gate metal layer, the second gate metal layer and the first wiring metal layer in FIG7 ;

[0039] FIG15 is a film layer diagram of the second routing metal layer in FIG7;

[0040] FIG16 is a film layer diagram of the first semiconductor, the first gate metal layer, the second gate metal layer, the first routing metal layer and the second routing metal layer in FIG7 ;

[0041] FIG17 is a film layer diagram of an anode layer according to some embodiments;

[0042] FIG18 is a connection diagram between a pixel driving circuit and a light emitting layer according to some other embodiments;

[0043] FIG19 is a diagram of the conjunctiva layer of the first trace metal layer in FIG18;

[0044] FIG20 is a film layer diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer and the first wiring metal layer in FIG18;

[0045] FIG21 is a film layer diagram of the second metal wiring layer in FIG18;

[0046] FIG22 is a film layer diagram of the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first routing metal layer, and the second metal routing layer in FIG18 ;

[0047] FIG23 is a film layer diagram of the anode layer in FIG18;

[0048] FIG24 is an equivalent circuit diagram of a plurality of pixel driving circuits in a display substrate according to some other embodiments;

[0049] FIG25 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B1 in FIG24 ;

[0050] FIG26 is a partial film layer diagram of B1 in FIG24;

[0051] FIG27 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B2 in FIG24 ;

[0052] FIG28 is a partial film layer diagram of B2 in FIG24;

[0053] FIG29 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B3 in FIG24 ;

[0054] FIG30 is a partial film layer diagram of B3 in FIG24;

[0055] FIG31 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B4 in FIG24 ;

[0056] Figure 32 is a partial film layer diagram of B4 in Figure 24. DETAILED DESCRIPTION

[0057] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0058] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0059] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature designated "first" or "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0060] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0061] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0062] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0063] As used herein, the term "if" is optionally interpreted to mean "when" or "at the time of" depending on the context. Similarly, the phrases "if it is determined that" or "if [stated condition or event] is detected" are optionally interpreted to mean "upon determining" or "in response to determining that" depending on the context.

[0064] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0065] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0066] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0067] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0068] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0069] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0070] In the circuit structure provided in the embodiments of the present disclosure, the first electrode of each transistor is one of the source and the drain, and the second electrode of each transistor is the other of the source and the drain. Since the source and drain of the transistor can be structurally symmetrical, the source and drain can be structurally identical. In other words, the first electrode and the second electrode of the transistor in the embodiments of the present disclosure can be structurally identical.

[0071] FIG1 is a structural diagram of a display device according to some embodiments. Referring to FIG1 , some embodiments of the present disclosure provide a display device 200 , which includes a display substrate 100 .

[0072] Exemplarily, the display device 200 further includes a frame and other electronic accessories.

[0073] Exemplarily, the display device 200 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0074] Exemplarily, the display device 200 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0075] FIG. 2 is a structural diagram of a display substrate according to some embodiments, and FIG. 3 is a cross-sectional diagram of a display substrate according to some embodiments.

[0076] Some embodiments of the present disclosure provide a display substrate 100. As shown in Figures 2 and 3 , the display substrate 100 includes an active area (AA), also known as an effective display area. The active area AA includes a plurality of pixel regions P, which may be arranged in an array.

[0077] Exemplarily, the plurality of pixel regions P may include a plurality of sub-pixel regions P0, and one sub-pixel region P0 corresponds to the smallest unit for displaying a picture on the display substrate 100. The plurality of sub-pixel regions may include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region. The first sub-pixel region, the second sub-pixel region, and the third sub-pixel region respectively emit three primary colors of light. For example, the first sub-pixel region may emit red light, the second sub-pixel region may emit green light, and the third sub-pixel region may emit blue light. Based on this, by adjusting the brightness (grayscale) of the sub-pixel regions of different colors, the display of multiple colors can be achieved through color combination and superposition, thereby realizing full-color display of the display substrate 100.

[0078] In some examples, a sub-pixel region includes a pixel driving circuit Q and a light-emitting device O electrically connected to the pixel driving circuit Q. The pixel driving circuit Q can be adjusted based on multiple different types of signal lines to generate a driving signal, and each light-emitting device O can emit light under the driving effect of the driving signal generated by the corresponding pixel driving circuit Q. Based on this, the pixel driving circuits Q in multiple sub-pixel regions can drive the corresponding light-emitting devices O to emit light, so that the display substrate 100 can display an image in the display area AA.

[0079] Continuing with Figures 2 and 3 , the display substrate 100 further includes a substrate 10, and a driving circuit layer 20 and a light-emitting device layer 210 stacked on the substrate 10. The driving circuit layer 20 may include a plurality of pixel driving circuits Q. The light-emitting device layer 210 is located on one side of the driving circuit layer 20 and includes a plurality of light-emitting devices O, which are electrically connected to the pixel driving circuits Q in the driving circuit layer 20.

[0080] In some examples, the substrate 10 may be a flexible substrate. For example, the material of the substrate 10 may be an organic material. For example, the material of the substrate 10 may be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0081] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0082] In some examples, the light-emitting device O includes an anode, a light-emitting portion, and a cathode that are stacked in sequence. In some examples, an electron transport portion is further provided between the cathode and the light-emitting portion, and a hole transport portion is further provided between the anode and the light-emitting portion. Exemplarily, the light-emitting device O can be an OLED light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device, that is, the light-emitting device O can be any other light-emitting device (for example, a light-emitting device that emits light by discharge), as long as they can emit light so that the display substrate 100 can display a picture.

[0083] In some examples, the plurality of pixel driving circuits Q and the plurality of light-emitting devices O may be coupled in a one-to-one correspondence. In other examples, one pixel driving circuit Q may be coupled to multiple light-emitting devices O, or multiple pixel driving circuits Q may be coupled to one light-emitting device O.

[0084] Below, the present disclosure takes the coupling of a pixel driving circuit Q and a light-emitting device O as an example to schematically illustrate the structure of the display substrate 100 .

[0085] FIG. 4 is an equivalent circuit diagram of a plurality of pixel driving circuits in a display substrate according to some implementations.

[0086] In some embodiments, as shown in Figures 3 and 4 , the driver circuit layer 20 is located on one side of the substrate 10. The driver circuit layer 20 includes a plurality of pixel driver circuits Q and a plurality of data signal lines Data. Each data signal line Data drives a column driver circuit Q, and the data signal line Data is configured to provide a data write signal to the pixel driver circuit Q.

[0087] The plurality of pixel driving circuits Q are arranged in multiple rows and columns. For the convenience of description, the plurality of pixel driving circuits Q are described in this disclosure by taking a matrix arrangement as an example.

[0088] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.

[0089] In some examples, as shown in Figure 5, the pixel driving circuit Q can be a "7T1C" or "8T1C" pixel driving circuit Q, where "T" represents a thin film transistor, and the number before "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number before "C" represents the number of storage capacitors C.

[0090] In some embodiments, as shown in FIG5 , the pixel driving circuit Q may be a “7T1C” pixel driving circuit Q. The pixel driving circuit Q may include: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first emission control transistor T5, a second emission control transistor T6, a second reset transistor T7, and a capacitor Cst.

[0091] Because the pixel driving circuit Q needs to be electrically connected to multiple different types of signal lines, multiple different types of signal lines are also shown in FIG5 . The multiple different types of signal lines may include: a first scanning signal line G1, a second scanning signal line G2, a data signal line Data, an enable signal line EM, a first power signal line VDD, a third scanning signal line G3, a first initialization signal line Vinit1, and a second initialization signal line Vinit2.

[0092] The connection method of the above-mentioned first scanning signal line G1, second scanning signal line G2, data signal line Data, enable signal line EM, first power signal line VDD, third scanning signal line G3, first initialization signal line Vinit1, and second initialization signal line Vinit2 with the pixel driving circuit can be referred to as shown in Figure 4, and the arrangement method of the first scanning signal line G1, second scanning signal line G2, data signal line Data, enable signal line EM, first power signal line VDD, third scanning signal line G3, first initialization signal line Vinit1, and second initialization signal line Vinit2 on the driving circuit layer 20 will be described in detail below.

[0093] The control electrode c1 of the first reset transistor T1 is electrically connected to the third scan signal line G3 , the first electrode a1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1 , and the second electrode b1 of the first reset transistor T1 is electrically connected to the first node N1 .

[0094] The control electrode c2 of the compensation transistor T2 is electrically connected to the second scan signal line G2 , the first electrode a2 of the compensation transistor T2 is electrically connected to the third node N3 , and the second electrode b2 of the compensation transistor T2 is electrically connected to the first node N1 .

[0095] In some examples, the second scan signal line G2 used to drive the pixel driving circuit Q in the nth row can be multiplexed as the third scan signal line G3 of the pixel driving circuit Q in the (n+7th) row. Based on this, when the second scan signal line G2 drives the compensation transistor T2 of the pixel driving circuit Q in the nth row to turn on, it can also drive the first reset transistor T1 of the pixel driving circuit Q in the (n+7th) row to reset the first node N1.

[0096] Exemplarily, the second scanning signal line G2 for driving the pixel driving circuit Q in the n-th row includes two branches, namely a first branch and a second branch. The first branch of the second scanning signal line G2 for the pixel driving circuit Q in the n-th row is electrically connected to the pixel driving circuit Q in the n-th row to drive the compensation transistor T2 of the pixel driving circuit Q in the n-th row to turn on. The second branch of the second scanning signal line G2 for the pixel driving circuit Q in the n-th row is electrically connected to the pixel driving circuit Q in the n+7th row to drive the first reset transistor T1 of the pixel driving circuit Q in the n+7th row to turn on, thereby resetting the first node N1.

[0097] Based on this, there is no need to provide a separate third scan signal line G3 , which can reduce the number of wirings in the display substrate 100 and facilitate the layout of other wirings in the display substrate 100 .

[0098] The control electrode c3 of the driving transistor T3 is electrically connected to the first node N1 , the first electrode a3 of the driving transistor T3 is electrically connected to the second node N2 , and the second electrode b3 of the driving transistor T3 is electrically connected to the third node N3 .

[0099] The control electrode c4 of the data writing transistor T4 is electrically connected to the first scanning signal line G1, the first electrode a4 of the data writing transistor T4 is electrically connected to the data signal line Data, and the second electrode b4 of the data writing transistor T4 is electrically connected to the second node N2.

[0100] The control electrode c5 of the first light emission control transistor T5 is electrically connected to the enable signal line EM, the first electrode a5 of the first light emission control transistor T5 is electrically connected to the first power signal line VDD, and the second electrode b5 of the first light emission control transistor T5 is electrically connected to the second node N2.

[0101] A control electrode c6 of the second light-emitting control transistor T6 is electrically connected to the enable signal line EM, a first electrode a6 of the second light-emitting control transistor T6 is electrically connected to a third node N3, a second electrode b6 of the second light-emitting control transistor T6 is electrically connected to a fourth node N4, and the fourth node N4 is electrically connected to the anode of the light-emitting device O. The cathode of the light-emitting device O is electrically connected to the second power signal line VSS. The voltage value of the third power signal provided by the third power signal line VSS is lower than the voltage value of the first power signal provided by the first power signal line VDD.

[0102] The control electrode c7 of the second reset transistor T7 is electrically connected to the second reset signal line, the first electrode a7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2, the second electrode b7 of the second reset transistor T7 is electrically connected to the fourth node N4, and the fourth node N4 is electrically connected to the anode of the light-emitting device O.

[0103] The storage capacitor Cts and the second plate Cst- 2 of the storage capacitor Cst are electrically connected to the control electrode c1 of the driving transistor T3 , and the first plate Cst- 1 of the storage capacitor Cst is electrically connected to the first power signal line VDD.

[0104] In some examples, the second reset signal line and the first scan signal line G1 can respond to the same signal line. This can also be understood as the first scan signal line G1 being multiplexed as the second reset signal line. Based on this, during the data write phase, the second reset transistor T7 is synchronously used to reset the fourth node N4 (the anode of the light-emitting device O). In other words, resetting the fourth node N4 (the anode of the light-emitting device O) before the light-emitting phase helps improve the brightness uniformity of the display substrate 100. Furthermore, multiplexing the first scan signal line G1 as the second reset signal line can reduce the number of signal lines in the display substrate 100, thereby simplifying the wiring layout of the display substrate 100.

[0105] It should be noted that each subpixel in the display device 200 is driven by multiple transistors (TFTs) to emit light. Using TFT driving technology can improve display speed, contrast, brightness, and resolution. However, TFTs exhibit a hysteresis effect. This hysteresis effect is an uncertainty in the electrical characteristics of a TFT under a certain bias voltage. That is, the current flowing through the TFT depends not only on the current bias voltage but also on the state of the TFT at the previous moment. The hysteresis effect of a TFT is related to the TFT's gate dielectric, semiconductor material, and the interface state traps between them. During the light-emitting phase, the hysteresis effect of the TFT can cause the current to decrease within a frame, which the human eye perceives as flicker, thereby affecting the display quality of the display device 200.

[0106] To improve the hysteresis effect of the driving transistor T3 in the pixel driving circuit Q, the threshold voltage of the pixel circuit is usually compensated to improve the brightness uniformity of the entire display screen. Specifically, the threshold voltage of the pixel circuit can be compensated when data is written.

[0107] In some embodiments, the driving process of the pixel driving circuit Q shown in FIG5 is as follows: one frame period includes an initialization phase, a writing phase, and a light emitting phase.

[0108] Initialization stage: The first reset signal transmitted by the third scanning signal line G3 is a valid signal. At this time, the first reset transistor T1 is turned on, and the first initialization signal transmitted by the first initialization signal line Vinit1 is transmitted to the first node N1, and the first node N1 is reset, so as to improve the stability of the driving transistor T3 included in the first pixel driving circuit.

[0109] Writing phase: The second scanning signal transmitted by the second scanning signal line G2 is a valid signal, and the compensation transistor T2 is turned on. Also, the first scanning signal transmitted by the first scanning signal line G1 is a valid signal, and the data writing transistor T4 is turned on. The data writing signal transmitted by the data signal line Data can be sequentially transmitted through the data writing transistor T4, the driving transistor T3, and the compensation transistor T2 to the first node N1, compensating the first node N1. The potential of the first node N1 gradually rises to Vdata + Vth.

[0110] Where Vdata is the voltage value of the data write signal provided by the data signal line Data, and Vth is the threshold voltage of the driving transistor T3 in the first pixel driving circuit. The charging process is completed when the potential of the first node N1 reaches Vdata + Vth. Subsequently, the storage capacitor Cst is discharged to keep the driving transistor T3 included in the first pixel driving circuit continuously turned on, ensuring that the light-emitting device O emits light.

[0111] During the light-emitting phase, the enable signal transmitted by the enable signal line EM is valid, and both the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on. The storage capacitor Cst is discharged to keep the drive transistor T3 included in the first pixel drive circuit continuously turned on.

[0112] Based on this, the constant voltage power signal provided by the first power signal line VDD can flow through the first light emission control transistor T5, the driving transistor T3, and the second light emission control transistor T6 in sequence to the anode of the light emitting device O, and the cathode of the light emitting device O can be electrically connected to the second power signal line Vss, thereby driving the light emitting device O to emit light. The first power signal line VDD can be a high power signal line, and the third power signal line Vss can be a low power signal line.

[0113] It should be noted that a "valid signal" refers to a signal that can turn on the transistor to which it is electrically connected. For example, if the first scanning signal line Gate1 is electrically connected to a P-type transistor, the valid signal is a low voltage signal. Alternatively, if the first scanning signal line Gate1 is electrically connected to an N-type transistor, the valid signal is a high voltage signal. The same applies to other signal lines.

[0114] In some examples, the seven transistors may all be P-type transistors.

[0115] In the case that the seven transistors are all P-type transistors, the “valid signal” can be understood as a low voltage signal, that is, the seven transistors can all be turned on under the control of the low level signal.

[0116] In some examples, the seven transistors may all be low-temperature polysilicon (LTPS) transistors. That is, the first reset transistor T1, the compensation transistor T2, the drive transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 may all be LTPS transistors.

[0117] In some examples, the first reset transistor T1 and the compensation transistor T2 may be N-type transistors. N-type transistors can help reduce the risk of transistor leakage. This reduces the risk of leakage in the first reset transistor T1 and the compensation transistor T2, and helps ensure the stability of the voltage at the first node N1, thereby ensuring the stability of the driving transistor T3, thereby improving the brightness retention rate of the light-emitting device O within a frame.

[0118] When the first reset transistor T1 and the compensation transistor T2 are N-type transistors, the “valid signal” can be understood as a high voltage signal, that is, the first reset transistor T1 and the compensation transistor T2 can be turned on under the control of the high voltage signal.

[0119] In some examples, the first reset transistor T1 and the compensation transistor T2 may be indium gallium zinc oxide (IGZO) transistors. Oxide transistors have a smaller off-leakage current, thereby reducing the leakage current of the first node N1 through the first reset transistor T1 during the light emitting phase.

[0120] In some other embodiments, the pixel driving circuit Q is an "8T1C" pixel driving circuit Q. In this case, the pixel driving circuit Q further includes a third reset transistor T8. The control electrode of the third reset transistor T8 is electrically connected to the third reset signal line R3, the first electrode of the third reset transistor T8 is electrically connected to the third initialization signal line V3, and the second electrode of the third reset transistor T8 is electrically connected to the second node N2.

[0121] In some examples, the third reset transistor T8 may be a p-type transistor.

[0122] In some examples, the third reset signal line R3 and the second reset signal line may respond to the same signal line, which can also be understood as the second reset signal line being multiplexed into the third reset signal line R3.

[0123] In other examples, the third reset signal line R3 and the second reset signal line R3 may respond to different signal lines.

[0124] For example, the third initialization signal transmitted by the third initialization signal line V3 can be a high voltage signal. Furthermore, the high voltage signal can be used to reset the second node N2, which is equivalent to resetting the first electrode of the driving transistor T3. This fixes the initial state of the driving transistor T3 before the data writing phase, facilitating a stable state of the driving transistor T3 during the data writing phase and significantly improving the hysteresis effect of the driving transistor T3.

[0125] The inventors have found that when the display substrate 100 is working, the same data signal line Data is used to drive a column of pixel driving circuits Q. That is, one data signal line Data drives a column of sub-pixel regions P0. The refresh time length of any sub-pixel region P0 in a column of sub-pixel regions P0 is Wherein, F is the refresh rate of the display substrate 100 , and H is the number of rows of the pixel driving circuits Q in the display substrate 100 .

[0126] Based on this, when the display substrate 100 is driven with a high refresh frequency, the row period of the display substrate 100 becomes shorter, that is, the row period of each pixel driving circuit Q becomes shorter, which makes the refresh time of the pixel driving circuit Q shorter, resulting in a shorter writing phase, that is, the threshold compensation time of the pixel driving circuit Q becomes shorter, and the threshold compensation effect of the pixel driving circuit Q is poor, which in turn leads to poor display uniformity of the display substrate 100.

[0127] In some examples, a "high refresh rate" may be a frequency higher than 120 Hz. For example, the high refresh rate may be in the range of 120 Hz to 240 Hz, 120 Hz to 300 Hz, or 120 Hz to 480 Hz.

[0128] Take the refresh frequency of the display substrate 100 as an example, which is about 240 Hz: the refresh time of a pixel driving circuit Q is about The refresh time of the pixel driving circuit Q is short, and the charging time is also short, which easily leads to incomplete threshold compensation of the pixel driving circuit Q, thereby affecting the display uniformity of the display substrate 100 .

[0129] For example, taking a 16-inch display substrate 100 with a resolution of 2560*1600 as an example, the refresh time of each pixel driving circuit Q is approximately 1.6μs. Therefore, a display substrate 100 with a higher resolution and a higher refresh rate will result in a shorter refresh time for the pixel driving circuit Q. The pixel driving circuit Q does not have sufficient time for threshold compensation, which can easily lead to poor display uniformity across the display substrate 100.

[0130] Moreover, as consumers' display demands become more and more demanding, the refresh rate and resolution requirements for the display substrate 100 are getting higher and higher, which in turn will cause the refresh time of each sub-pixel (pixel driving circuit Q) to become shorter and shorter, and the charging time to become shorter and shorter. It is difficult to compensate for the threshold voltage within the limited charging time, resulting in poor display effect.

[0131] Figure 6 is an equivalent circuit diagram of multiple pixel driving circuits in a display substrate according to some embodiments, Figure 7 is a connection diagram of a pixel driving circuit and a light-emitting layer according to some embodiments, Figure 8 is a film layer diagram of the first semiconductor layer in Figure 7, Figure 9 is a film layer diagram of the first gate metal layer in Figure 7, Figure 10 is a film layer diagram of the first semiconductor and the first gate metal layer in Figure 7, Figure 11 is a film layer diagram of the second gate metal layer in Figure 7, Figure 12 is a film layer diagram of the first semiconductor, the first gate metal layer, and the second gate metal layer in Figure 7, Figure 13 is a film layer diagram of the first wiring metal layer in Figure 7, Figure 14 is a film layer diagram of the first semiconductor, the first gate metal layer, the second gate metal layer, and the first wiring metal layer in Figure 7, Figure 15 is a film layer diagram of the second wiring metal layer in Figure 7, Figure 16 is a film layer diagram of the first semiconductor, the first gate metal layer, the second gate metal layer, the first wiring metal layer, and the second wiring metal layer in Figure 7, and Figure 17 is a film layer diagram of the anode layer according to some embodiments.

[0132] It should be noted that Figures 6 and 7 illustrate the structures of the individual pixel driving circuits, and do not illustrate all of the pixel driving circuits Q in the display substrate 100. Two rows and three columns of pixel driving circuits Q are used as an example. That is, Figure 7 illustrates six pixel driving circuits and their electrically connected data signal lines Data.

[0133] Based on this, in combination with Figures 6 to 17, the driving circuit layer 20 of the display substrate 100 provided in some embodiments of the present disclosure includes a first semiconductor layer POLY, a first gate metal layer Gate1, a second gate metal layer Gate2, a first routing metal layer SD1 and a second routing metal layer SD2 stacked on the substrate 10.

[0134] As shown in Figures 7, 8, and 10, a first semiconductor layer POLY is located on a base substrate 10. The first semiconductor layer POLY may include the first and second electrodes of the seven transistors in the aforementioned "7T1C" pixel driver circuit. For example, the first semiconductor layer POLY includes the first electrode a4 and the second electrode b4 of the data write transistor T4. In the case of an "8T1C" pixel driver circuit Q, the first semiconductor layer POLY includes the first and second electrodes of the third reset transistor T8.

[0135] In some examples, the material of the first semiconductor layer POLY may include amorphous silicon, single crystal silicon, or polycrystalline silicon semiconductor material.

[0136] As shown in Figures 7, 9, and 10, the first gate metal layer Gate1 is located on the side of the first semiconductor layer POLY away from the substrate 10. The first gate metal layer Gate1 can include the control electrodes of the seven transistors in the aforementioned "7T1C" pixel driver circuit. For example, the first gate metal layer Gate1 includes the control electrode of the data write transistor T4. In the case of an "8T1C" pixel driver circuit Q, the first gate metal layer Gate1 also includes the control electrode of the third reset transistor T8.

[0137] Exemplarily, the material of the first gate metal layer Gate1 includes a conductive metal, and the conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0138] Illustratively, a first gate insulating layer is provided between the first semiconductor layer POLY and the first gate metal layer Gate1 , and the first gate insulating layer electrically insulates the first semiconductor layer POLY from the first gate metal layer Gate1 .

[0139] For example, the material of the first gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer may include silicon dioxide, but the present disclosure is not limited thereto.

[0140] In addition, the first gate metal layer Gate1 can also be used to form a plurality of first scan signal lines G1 extending along the row direction X and arranged in the column direction Y, and a plurality of enable signal lines EM extending along the row direction X and arranged in the column direction Y.

[0141] Based on this, the first scan signal line G1 can include a first part and a second part. The first part of the first scan signal line G1 can be multiplexed as the control electrode c4 of the data writing transistor T4, and the second part of the first scan signal line G1 can be multiplexed as the control electrode c7 of the second reset transistor T7.

[0142] The enable signal line EM may include a first portion and a second portion. The first portion of the enable signal line EM may be multiplexed as the control electrode c5 of the first emission control transistor T5 , and the second portion of the enable signal line EM may be multiplexed as the control electrode c6 of the second emission control transistor T6 .

[0143] It should be noted that the orthographic projection of the first semiconductor layer POLY on the substrate 10 overlaps with the orthographic projection of the first gate metal layer Gate1 on the substrate 10. The portion of the first semiconductor layer POLY covered by the first gate metal layer Gate1 constitutes the channel portion of each transistor, and the portion of the first semiconductor layer POLY not covered by the first gate metal layer Gate1 is a conductive portion, constituting the first electrode or the second electrode of each transistor.

[0144] 7 , 11 and 12 , the second gate metal layer Gate2 is located on a side of the first gate metal layer Gate1 away from the first semiconductor POLY1 .

[0145] For example, the second gate metal layer Gate2 may be made of the same material as the first gate metal layer Gate1. It is understood that in other examples, the second gate metal layer Gate2 may be made of a different material than the first gate metal layer Gate1. The embodiments of the present disclosure are not limited thereto.

[0146] For example, a second gate insulating layer may be provided between the second gate metal layer Gate2 and the first gate metal layer Gate1 , so as to electrically insulate the second gate metal layer Gate2 from the first gate metal layer Gate1 .

[0147] For example, the material of the second gate insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer may include silicon dioxide, but the present disclosure is not limited thereto.

[0148] Furthermore, the first gate metal layer Gate1 can also be used to form a plurality of first initialization signal lines Vinit1 extending along the row direction X and arranged in the column direction Y, and a plurality of second initialization signal lines Vinit2 extending along the row direction X and arranged in the column direction Y.

[0149] Furthermore, the second plate Cst-2 of the storage capacitor Cst can be located on the first gate metal layer Gate1, and the first plate Cst-1 of the storage capacitor Cst can be located on the second gate metal layer Gate2. The orthographic projection of the second plate Cst-2 of the storage capacitor Cst on the base substrate 10 at least partially overlaps with the orthographic projection of the first plate Cst-1 of the storage capacitor Cst on the base substrate 10 to form the storage capacitor Cst.

[0150] The second plate Cst-2 of the storage capacitor Cst located on the first gate metal layer Gate1 can be reused as the control electrode c1 of the drive transistor T3. This eliminates the need for a separate control electrode c1 of the drive transistor T3, simplifying the manufacturing process of the pixel drive circuit Q. Furthermore, the second plate Cst-2 of the storage capacitor Cst can be reused as the control electrode c1 of the drive transistor T3, allowing for a direct electrical connection between the second plate Cst-2 of the storage capacitor Cst and the control electrode c1 of the drive transistor T3, eliminating the need for a separate connection portion. This also facilitates the layout of the pixel drive circuit Q.

[0151] 7 , 13 and 14 , the first routing metal layer SD1 is located on a side of the second gate metal layer Gate2 away from the first gate metal layer Gate1 .

[0152] For example, the material package of the first wiring metal layer SD1 may be a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0153] For example, a first planarization layer (PLN) is provided between the first wiring metal layer SD1 and the second gate metal layer Gate2 to electrically insulate the first wiring metal layer SD1 from the second gate metal layer Gate2.

[0154] Exemplarily, the material of the first planarization layer is generally an organic material. For example, the material of the first planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0155] Furthermore, the first routing metal layer SD1 can be used to form a plurality of second scanning signal lines G2 extending in the row direction X and arranged in the column direction Y, and a plurality of third scanning signal lines G3 extending in the row direction X and arranged in the column direction Y. Furthermore, the first routing metal layer SD1 can be used to form a plurality of conductive portions, which are used to connect transistors within the pixel driving circuit Q or transistors and signal lines.

[0156] 7 , 15 and 16 , the second routing metal layer SD2 is located on a side of the first routing metal layer SD1 away from the first gate metal layer Gate1 .

[0157] In some examples, the material of the second routing metal layer SD2 can be the same as that of the first routing metal layer SD1. It is understood that the material of the second routing metal layer SD2 can be different from that of the first routing metal layer SD1. The embodiments of the present disclosure are not limited to this.

[0158] Exemplarily, a second planarization layer is provided between the second routing metal layer SD2 and the first routing metal layer SD1 , and the second planarization layer electrically insulates the second routing metal layer SD2 from the first routing metal layer SD1 .

[0159] Exemplarily, the material of the second planarization layer is generally an organic material. For example, the material of the second planarization layer may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0160] In addition, the second wiring metal layer SD2 can also be used to form a plurality of first power signal lines VDD arranged along the row direction X and extending in the column direction Y. The first power signal line VDD is configured as a constant voltage signal for providing a first power signal to the pixel driving circuit Q.

[0161] As shown in Figures 7 and 17 , the light-emitting device layer 210 includes an anode layer 211, which is located on a side of the second routing metal layer SD2 away from the first routing metal layer SD1. Anode layer 211 includes multiple anodes W. These anodes include a first anode W1, a second anode W2, and a third anode W3. The first anode W1 can be electrically connected to the pixel driver circuit Q in the (m+1)th column, the second anode W2 can be electrically connected to the pixel driver circuit Q in the (m)th column, and the third anode W3 can be electrically connected to the pixel driver circuit Q in the (m+2)th column.

[0162] The first anode W1, the second anode W2, and the third anode W3 in the anode layer 211 are respectively anodes of the light-emitting devices O in different sub-pixel regions P0. Based on this, the plurality of pixel driving circuits Q in the display substrate 100 can be used to drive the light-emitting devices O electrically connected thereto, so that the display substrate 100 displays images.

[0163] As shown in Figures 6 to 17 , multiple data signal line groups D are formed on the display substrate 100. Each data signal line group D is electrically connected to a column of pixel driving circuits Q. Each data signal line group D includes n data signal lines Data extending along the column direction Y and spaced apart along the row direction X. Correspondingly, a column of pixel driving circuits Q can be divided into n pixel driving circuit groups E, where n is a positive integer greater than 2.

[0164] Based on this, different data signal lines Data within the same data signal line group D can be electrically connected to different pixel driving circuit groups E in the same column of pixel driving circuits Q, and one data signal line Data is electrically connected to all pixel driving circuits Q in one pixel driving circuit group E. This is equivalent to the pixel driving circuits Q in the same column being driven by multiple data signal lines Data in the same data signal line group D, that is, one data signal line Data is used to drive some of the pixel driving circuits Q in one column of pixel driving circuits Q.

[0165] In this way, the way in which one data signal line group D drives a column of pixel driving circuits Q can reduce the number (number of rows) of pixel drivers Q driven by each data signal line Data, relative to the way in which the same column of pixel driving circuits Q is driven by one data signal line Data. Furthermore, the refresh time of the pixel driving circuit Q can be increased, that is, the threshold compensation time of the pixel driving circuit Q can be increased, the threshold compensation effect of the pixel driving circuit Q can be improved, and the display uniformity of the display substrate 100 can be improved. Therefore, the display substrate 100 provided in the embodiment of the present disclosure can be applied to a display device 200 with high resolution and high refresh rate, thereby improving the user experience. In addition, the display substrate 100 provided in the embodiment of the present disclosure is also applicable to a display device 200 with a low refresh rate, which is beneficial to saving power consumption.

[0166] In some embodiments, as shown in Figures 6 to 17 , the data signal lines Data within the multiple data signal line groups D can be located in the second metal routing layer SD2. However, the disclosed embodiments are not limited thereto. For example, when the drive circuit layer 20 of the display substrate 100 further includes a third metal routing layer SD3, the data signal lines Data within the multiple data signal line groups D can be located in the second metal routing layer SD2 and / or the third metal routing layer SD3. This structure will be described in detail below.

[0167] First, an example is given in which the data signal lines Data in the plurality of data signal line groups D are located in the second metal wiring layer SD.

[0168] In some examples, taking n=2 as an example, a data signal line group D includes two data signal lines Data extending along the column direction Y and spaced apart along the row direction X, and a column of pixel driving circuits Q is divided into two pixel driving circuit groups E. Since FIG6 illustrates two rows of pixel driving circuits, two adjacent pixel driving circuits Q in the column direction Y in FIG6 are pixel driving circuits Q in different pixel driving circuit groups E.

[0169] The two data signal lines Data in a data signal line group D may be a first data signal line Data and a second data signal line Data. The two pixel driving circuit groups E in a column of pixel driving circuits Q may be a first pixel driving circuit group E and a second pixel driving circuit group E.

[0170] With this arrangement, the first data signal line Data can be electrically connected to all pixel driving circuits Q in the first pixel driving circuit group E, and the second data signal line Data can be electrically connected to all pixel driving circuits Q in the second pixel driving circuit group E. Based on this, both the first data signal line Data and the second data signal line Data are used to drive one pixel driving circuit group E. That is, one data signal line Data is used to drive part of the pixel driving circuits Q in a column of pixel driving circuits Q. This is beneficial for increasing the refresh time of the pixel driving circuit Q, which can increase the threshold compensation time of the pixel driving circuit Q, improve the threshold compensation effect of the pixel driving circuit Q, and improve the display uniformity of the display substrate 100. Wherein, F is the refresh rate of the display substrate 100, and H is the number of rows of pixel driving circuits Q in the display substrate 100.

[0171] In some embodiments, as shown in conjunction with FIG6 and FIG7 , in the same column of pixel driving circuits Q, the number of pixel driving circuits Q in each pixel driving circuit group E is approximately equal. This is equivalent to evenly dividing all pixel driving circuits Q in the same column of pixel driving circuits Q into a plurality of pixel driving circuit groups E. The number of pixel driving circuits Q driven by different signal lines Data within the same data signal line D can be the same.

[0172] It should be noted that due to certain uncontrollable errors (for example, multiple pixel driving circuits Q in the same column of pixel driving circuits Q cannot be equally divided), in the same column of pixel driving circuits Q, when the difference in the number of pixel driving circuits Q in two pixel driving circuit groups E fluctuates within 5% of the number of pixel driving circuits Q in one of the pixel driving circuit groups E, it can also be considered that the number of pixel driving circuits Q in the two pixel driving circuit groups E is equal.

[0173] Based on this, the refresh time lengths of the pixel driving circuits Q in different pixel driving circuit groups E in the same column of pixel driving circuits Q can be approximately Not only can the refresh time of the pixel driving circuit Q be the above refresh time The refresh time lengths of the pixel driving circuits Q in different pixel driving circuit groups E in the same column of pixel driving circuits Q can also be made equal, which is beneficial to improving the display uniformity of the display substrate 100.

[0174] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), the error floating range of the refresh time of the pixel driving circuit Q is It can also be considered that the refresh time of the pixel driving circuit Q satisfies the requirement of

[0175] In some examples, taking n=2 as an example, the two data signal lines Data in a data signal line group D may be a first data signal line Data and a second data signal line Data, respectively. The two pixel driving circuit groups E in a column of pixel driving circuits Q may be a first pixel driving circuit group E and a second pixel driving circuit group E, respectively.

[0176] When the number of pixel driving circuits Q in the first pixel driving circuit group E is approximately equal to the number of pixel driving circuits Q in the second pixel driving circuit group E, it is equivalent to dividing a column of pixel driving circuits Q into two equal parts. Based on this, the refresh time of the pixel driving circuit Q is approximately That is, the refresh time of the pixel driving circuit Q is the above refresh time The refresh time of the pixel driving circuit Q is increased by 2 times, which can improve the threshold compensation of the high-pixel driving circuit Q. Moreover, in the same column of pixel driving circuits Q, the refresh time of any pixel driving circuit Q in the first pixel driving circuit group E and any pixel driving circuit Q in the second pixel driving circuit group E can be made approximately equal, which is beneficial to improving the display uniformity of the display substrate 100.

[0177] In some embodiments, within the same column of pixel driving circuits Q, multiple pixel driving circuit groups E are sequentially arranged along the column direction Y. Centrally arranging the pixel driving circuits Q within each pixel driving circuit group E facilitates electrical connection between subsequent pixel driving circuits Q and their corresponding data signal lines Data, thereby simplifying the layout of the display substrate 100.

[0178] For example, when a column of pixel driving circuits Q includes four pixel driving circuit groups E, the four pixel driving circuit groups E are respectively a first pixel driving circuit group E, a second pixel driving circuit group E, a third pixel driving circuit group E, and a fourth pixel driving circuit group E. In this case, along the column direction, the first pixel driving circuit group E, the second pixel driving circuit group E, the third pixel driving circuit group E, and the fourth pixel driving circuit group E are arranged in sequence.

[0179] In another embodiment, within the same column of pixel driving circuits Q, the pixel driving circuits Q in multiple pixel driving circuit groups E are alternately arranged in the column direction Y. Dispersing the pixel driving circuits Q within each pixel driving circuit group E can improve the flexibility and applicability of the layout of the pixel driving circuits Q within the display substrate 100.

[0180] In some embodiments, as shown in FIG7 , two adjacent columns of pixel driving circuits Q are respectively the m-th column pixel driving circuit Q and the m+1-th column pixel driving circuit Q. The data signal line group D electrically connected to the m-th column pixel driving circuit Q includes at least one first data signal line Data1-1, and the first data signal line Data1-1 is located between the m-th column pixel driving circuit Q and the m+1-th column pixel driving circuit Q. The data signal line group D electrically connected to the m+1-th column pixel driving circuit Q includes at least one second data signal line Data2-1, and the second data signal line Data2-1 is located between the m-th column pixel driving circuit Q and the m+1-th column pixel driving circuit Q. Wherein, m is a positive integer.

[0181] The first data signal line Data1-1 electrically connected to the pixel driving circuit Q in the mth column and the second data signal line Data2-1 electrically connected to the pixel driving circuit Q in the m+1th column are arranged adjacent to each other and are both arranged between the pixel driving circuit Q in the mth column and the pixel driving circuit Q in the m+1th column. This can reduce the overlap area between the orthographic projection of the data signal line Data on the substrate 10 and the orthographic projection of the pixel driving circuit Q on the substrate 10, prevent the data signal line Data from affecting the stability of the pixel driving circuit Q, and facilitate improving display uniformity of the display substrate 100.

[0182] In some examples, the plurality of data signal lines Data in one data signal line group D are all located on one side of a column of pixel driving circuits Q electrically connected to the one data signal line group D.

[0183] All data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the m-th column are first data signal lines Data1-1. That is, all data signal lines Data (first data signal lines Data1-1) in the data signal line group D electrically connected to the pixel driving circuit Q in the m-th column are located between the pixel driving circuit Q in the m-th column and the pixel driving circuit Q in the (m+1)-th column. Centrally arranging all data signal lines Data in one data signal line group D can simplify the layout of the data signal lines Data in the display substrate 100.

[0184] All data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the (m+1)th column are second data signal lines Data2-1. That is, all data signal lines Data (second data signal lines Data2-1) in the data signal line group D electrically connected to the pixel driving circuit Q in the (m)th column are located between the pixel driving circuit Q in the (m)th column and the pixel driving circuit Q in the (m+1)th column. Centrally arranging all data signal lines Data in one data signal line group D can simplify the layout of the data signal lines Data in the display substrate 100.

[0185] In other examples, as shown in Figure 7, multiple data signal lines Data in a data signal line group D are divided into a first part of data signal lines Data-1 and a second part of data signal lines Data-2, and the first part of data signal lines Data-1 and the second part of data signal lines Data-2 are respectively located on both sides of a column of pixel driving circuits Q electrically connected to the data signal line group D.

[0186] With such an arrangement, the first part of the data signal lines Data-1 and the second part of the data signal lines Data-2 in a group of data signal line groups D can be distributed on both sides of the pixel driving circuit Q, and the spacing between the first part of the data signal lines Data-1 and the second part of the data signal lines Data-2 in a group of data signal line groups D can be increased to improve the problem of crosstalk between multiple data signal lines Data, which is beneficial to improving the display uniformity of the display substrate 100.

[0187] The multiple data signal lines Data of the data signal line group D electrically connected to the pixel drive circuit Q in the m-th column are divided into two parts. The first part of the data signal lines Data-1 is the first data signal line Data1-1, which is located between the pixel drive circuit Q in the m-th column and the pixel drive circuit Q in the m+1-th column. The second part of the data signal lines Data-2 is the third data signal line Data1-2, which is located on the side of the pixel drive circuit Q in the m-th column away from the pixel drive circuit Q in the m+1-th column. When m is a positive integer greater than or equal to 4, the third data signal line Data1-2 is located between the pixel drive circuit Q in the m-th column and the pixel drive circuit Q in the m-1-th column.

[0188] With such an arrangement, the first part of the data signal lines Data-1 (first data signal line Data1-1) and the second part of the data signal lines Data-2 (third data signal line Data1-2) in a group of data signal line groups D can be distributed on both sides of the pixel driving circuit Q, and the spacing between the first part of the data signal lines Data-1 (first data signal line Data1-1) and the second part of the data signal lines Data-2 (third data signal line Data1-2) in a group of data signal line groups D can be increased to improve the problem of crosstalk between multiple data signal lines Data, which is beneficial to improving the display uniformity of the display substrate 100.

[0189] The multiple data signal lines Data of the data signal line group D electrically connected to the pixel driving circuit Q in the m+1th column are divided into two parts. The first part of the data signal lines Data-1 is the second data signal line Data2-1, which is located between the pixel driving circuit Q in the mth column and the pixel driving circuit Q in the m+1th column. The second part of the data signal lines Data-2 is the fourth data signal line Data2-2, which is located between the pixel driving circuit Q in the m+1th column and the pixel driving circuit Q in the m+2th column.

[0190] With such an arrangement, the first part of the data signal lines Data-1 (the second data signal line Data2-1) and the second part of the data signal lines Data-2 (the fourth data signal line Data2-2) in a group of data signal line groups D can be distributed on both sides of the pixel driving circuit Q, and the spacing between the first part of the data signal lines Data-1 (the second data signal line Data2-1) and the second part of the data signal lines Data-2 (the fourth data signal line Data2-2) in a group of data signal line groups D can be increased to improve the problem of crosstalk between multiple data signal lines Data, which is beneficial to improving the display uniformity of the display substrate 100.

[0191] It should be noted that, in conjunction with Figure 7, the difference between the pixel driving circuits Q in the upper and lower rows is that they belong to pixel driving circuits Q in different pixel circuit groups E, and they are correspondingly connected to different data signal lines Data in the same data signal line group D. The m+1-th column pixel driving circuit and the data signal line Data electrically connected thereto are used as an example for description. In this case, the pixel driving circuit Q in the first row and second column in Figure 7 is a pixel driving circuit in the m+1-th column pixel driving circuit, and the pixel driving circuit Q in the second row and second column is another pixel driving circuit in the m+1-th column pixel driving circuit. And, the two data signal lines Data electrically connected to the above-mentioned two pixel driving circuits Q in the m+1-th column pixel driving circuit. Among them, the second data signal line Data2-1 is electrically connected to the pixel driving circuit Q in the second row and second column, and the fourth data signal line Data2-2 is electrically connected to the pixel driving circuit Q in the first row and second column.

[0192] Because the two data signal lines Data electrically connected to the pixel driver circuit in the (m+1)th column are located on either side of it, the spacing between the two data signal lines Data and the data write transistors T4 in their respective pixel driver circuits Q differs. This may result in different structures in the transition sections between the data write transistors T4 in the upper and lower rows of pixel driver circuits Q and the data signal lines Data they are electrically connected to. The structure of the transition section between the data write transistors T4 and the data signal lines Data they are electrically connected to will be explained below.

[0193] In some examples, the number of data signal lines Data in the first portion of data signal lines Data- 1 is approximately equal to the number of data signal lines Data in the second portion of data signal lines Data- 2 .

[0194] The number of data signal lines Data in the first portion of data signal lines Data-1, located on both sides of a column of pixel driver circuits Q, is set to be approximately equal to the number of data signal lines Data in the second portion of data signal lines Data-2. This prevents the problem of short circuits caused by an excessive number of data signal lines Data on one side of the column of pixel driver circuits Q. This is beneficial for improving the quality of the display substrate 100.

[0195] It should be noted that due to certain uncontrollable errors (such as the multiple data signal lines Data within a group of data signal line groups D cannot be equally divided), for the same group of data signal line groups D, the floating range of the difference between the number of data signal lines Data in the first part of the data signal lines Data-1 and the number of data signal lines Data in the second part of the data signal lines Data-2 is within 5% of the number of data signal lines Data in the first part of the data signal lines Data-1 or the number of data signal lines Data in the second part of the data signal lines Data-2, it can also be considered that the number of data signal lines Data in the first part of the data signal lines Data-1 and the number of data signal lines Data in the second part of the data signal lines Data-2 are equal.

[0196] However, the inventors have discovered that, in order to improve the problem of insufficient threshold compensation of the pixel driving circuit Q, the number of data signal lines Data in the display substrate 100 is increased. As a result, the multiple signal lines Data electrically connected to two adjacent columns of pixel driving circuits Q are arranged in close proximity with a small spacing between them. This results in a large parasitic capacitance between adjacent data signal lines Data, leading to a more serious lateral crosstalk problem between adjacent data signal lines Data, thereby reducing the display quality of the display substrate 100.

[0197] For example, when the display substrate 100 is operating, because different data signal lines Data driving different columns of pixel driving circuits Q transmit different data write signals, the data write signal transmitted by any data signal line Data will affect its adjacent data signal line Data, resulting in crosstalk between adjacent data signal lines Data, affecting the display uniformity of the display substrate 100. In other words, crosstalk is likely to occur between the first data signal line Data1-1 and the second data signal line Data2-1.

[0198] Figure 18 is a connection diagram of the pixel driving circuit and the light-emitting layer according to some other embodiments. Figure 19 is a diagram of the junction film layer of the first wiring metal layer in Figure 18, Figure 20 is a diagram of the film layers of the first semiconductor layer, the first gate metal layer, the second gate metal layer, and the first wiring metal layer in Figure 18, Figure 21 is a diagram of the film layers of the second metal wiring layer in Figure 18, Figure 22 is a diagram of the film layers of the first semiconductor layer, the first gate metal layer, the second gate metal layer, the first wiring metal layer, and the second metal wiring layer in Figure 18, and Figure 23 is a diagram of the film layers of the anode layer in Figure 18.

[0199] FIG18 illustrates the structure of each pixel driving circuit, but does not illustrate all rows of pixel driving circuits Q in the display substrate 100. Two rows and three columns of pixel driving circuits Q are used as an example. That is, FIG18 illustrates six pixel driving circuits and their electrically connected data signal lines.

[0200] Based on this, in combination with Figures 18 to 23, the driving circuit layer 20 of the display substrate 100 provided in some embodiments of the present disclosure further includes a plurality of anode transfer lines 30, and the plurality of anode transfer lines 30 are respectively electrically connected to the driving output terminals (fourth nodes N4) of the plurality of pixel driving circuits Q. Among them, the plurality of anode transfer lines 30 electrically connected to the pixel driving circuit Q in the (m+1)th column include at least one first anode transfer line 31, and the first anode transfer line 31 includes a first anode transfer portion 311, and the first anode transfer portion 311 is configured to have a constant voltage potential, and the first anode transfer portion 311 is set on the same layer as the data signal line Data.

[0201] The first anode adapter 311 is used to electrically connect the anode of the light-emitting device O to the output terminal of the pixel driving circuit Q, thereby electrically connecting the anode of the light-emitting device O to the output terminal of the pixel driving circuit Q. Furthermore, during the light-emitting phase, the pixel driving circuit Q can transmit the first power signal received at the first power signal line VDD to the driving output terminal (fourth node N4), and then transmit it to the anode of the light-emitting device O through the first anode adapter 311. The voltage difference is formed with the second power signal provided by the second power signal line connected to the cathode terminal of the light-emitting device O, thereby driving the light-emitting device O to emit light. In other words, the first anode adapter 311 is configured to have a constant voltage potential.

[0202] Placing the first anode transition portion 311 on the same layer as the data signal line Data can reduce the number of film layers sandwiched between the first anode transition portion 311 and the anode layer 211, thereby facilitating electrical connection between the first anode transition portion 311 and the anodes within the anode layer 211. Furthermore, by arranging the first anode transition portion 311 on the same layer as the data signal line Data, the first anode transition portion 311 and the data signal line Data can be formed using the same patterning process, which can help reduce process steps and increase production capacity. However, the disclosed embodiments are not limited to this, and the first anode transition portion 311 and the data signal line Data can also be formed separately using two separate manufacturing processes.

[0203] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0204] Based on this, the first anode transfer portion 311 can be arranged along the row direction X, between the first data signal line Data1-1 electrically connected to the pixel driving circuit Q of the mth column and the second data signal line Data2-1 electrically connected to the pixel driving circuit Q of the (m+1)th column.

[0205] On the basis of being provided on the same layer as the data signal line Data, when the first anode transition portion 311 is provided between the first data signal line Data1-1 and the second data signal line Data2-1, space must be reserved between the first data signal line Data1-1 and the second data signal line Data2-1 to provide the first anode transition portion 311. This helps increase the spacing between the first data signal line Data1-1 and the second data signal line Data2-1. This also helps reduce the parasitic capacitance formed between the first data signal line Data1-1 and the second data signal line Data2-1. Therefore, the problem of a potential jump in the adjacent data signal line Data caused by the data signal line Data transmitting a data write signal can be alleviated, thereby improving the lateral crosstalk problem of the display substrate 100.

[0206] Moreover, since the first anode transition portion 311 is configured to have a constant voltage potential, when the first anode transition portion 311 is set between the first data signal line Data1-1 and the second data signal line Data2-1, the first anode transition portion 311 can be used to isolate the first data signal line Data1-1 and the second data signal line Data2-1, thereby further reducing the parasitic capacitance formed between the first data signal line Data1-1 and the second data signal line Data2-1, reducing the problem of crosstalk between the first data signal line Data1-1 and the second data signal line Data2-1, improving the display uniformity of the display substrate 100, and improving the display effect of the display substrate 100.

[0207] In summary, the display substrate 100 provided in some embodiments of the present disclosure increases the number of data signal lines Data so that one data signal line group D (multiple data signal lines Data) drives a column of pixel driving circuits Q, thereby increasing the refresh time of the pixel driving circuits Q, increasing the charging time of the pixel driving circuits Q, and improving the threshold compensation of the pixel driving circuits Q, thereby further improving the display uniformity of the display substrate 100. At the same time, the display substrate 100 is also provided with a first anode adapter 311 disposed on the same layer as the data signal lines Data. The first anode adapter 311 is used to isolate the first data signal line Data1-1 from the second data signal line Data2-1, thereby reducing the problem of crosstalk between the first data signal line Data1-1 and the second data signal line Data2-1, and further ensuring the display effect of the display substrate 100.

[0208] In some embodiments, as shown in conjunction with FIG18 and FIG23 , the light-emitting device layer 210 in the display substrate 100 further includes an anode layer 211. The anode layer 211 is located on a side of the driving circuit layer 20 away from the substrate 10. The anode layer 211 includes a plurality of anodes W, each of which includes a first anode W1, a second anode W2, and a third anode W3. In the column direction Y, the first anodes W1 and the second anodes W2 are alternately arranged, and in the row direction X, the third anode W3 overlaps with the first anode W1 and overlaps with the second anode W2.

[0209] The first anode W1 and the second anode W2 in the anode layer 211 are respectively anodes of the light-emitting devices O in different sub-pixel regions P0. Based on this, the multiple pixel driving circuits Q in the display substrate 100 can be used to drive the light-emitting devices O electrically connected thereto, so that the display substrate 100 displays images.

[0210] For example, the first anode W1 may be the anode of the light-emitting device O in the red sub-pixel, the second anode W2 may be the anode of the light-emitting device O in the green sub-pixel, and the third anode W3 may be the anode of the light-emitting device O in the blue sub-pixel. However, the embodiments of the present disclosure are not limited thereto. However, the embodiments of the present disclosure are not limited thereto.

[0211] Since the first anode transition portion 311 and the data signal line Data are on the same layer, the first anode transition portion 311 is arranged to extend along the column direction Y. That is, the extension direction of the first anode transition portion 311 is arranged to be substantially the same as the extension direction of the data signal line Data, thereby preventing the first anode transition portion 311 and the data signal line Data from being short-circuited.

[0212] The pixel driving circuit Q in the (m+1)th column can be electrically connected to the second anode W2 via the first anode adapter 311. The orthographic projection of the first anode adapter 311 on the substrate 10 is arranged to overlap with the orthographic projection of the second anode W2 on the substrate 10. The overlapping portion of the orthographic projection of the first anode adapter 311 on the substrate 10 and the orthographic projection of the second anode W2 on the substrate 10 can be connected via a via to electrically connect the first anode adapter 311 and the second anode W2. Furthermore, there is no need to provide a separate connection portion to electrically connect the first anode adapter 311 and the second anode W2, which can help save limited space on the display substrate 100 and facilitate the layout of the display substrate 100.

[0213] The inventors have discovered that when the orthographic projection of the first anode transition portion 311 on the substrate 10 overlaps with the orthographic projection of the second anode W2 on the substrate 10, since the first anode transition portion 311 does not need to be electrically connected to other anodes, the orthographic projection of the first anode transition portion 311 on the substrate 10 is generally set to not overlap with the orthographic projection of the first anode W1 on the substrate 10. Furthermore, since the first anodes W1 and the second anodes W2 are alternately arranged along the column direction Y, the layout of the corresponding second metal trace layer SD2 below the first anodes W1 and the second anodes W2 is essentially the same, differing only in the position of the first anode W1 and the second anode W2 and their respective anode transition portions. In other words, since the first anode W1 does not have a first anode transition portion 311 on its corresponding second metal trace layer SD2, this position is left blank, and this blank space is filled with the flat layer between the second metal trace layer SD2 and the anode layer 211. However, due to the step difference between the blank space and the structure of the second metal wiring layer SD2, a step difference will appear on the surface of the flat layer between the second metal wiring layer SD2 and the first anode W1 away from the substrate, increasing the difficulty of forming the anode layer 211 (first anode W1) thereon, affecting the yield of the light-emitting device O.

[0214] Based on this, in the display substrate 100 provided in some embodiments of the present disclosure, the first anode transition portion 311 is extended to the position corresponding to the first anode W1, so that the orthographic projection of the first anode transition portion 311 on the substrate 10 overlaps with the orthographic projection of the first anode W1 on the substrate 10.

[0215] Such a configuration allows the first anode transition portion 311 to fill the above-mentioned blank space to improve the problem of uneven surface of the flat layer formed between the second metal wiring layer SD2 and the anode layer 211 on the side away from the substrate, which is beneficial to improving the yield of the anode layer 211 formed on the surface of the flat layer on the side away from the substrate.

[0216] In some embodiments, as shown in conjunction with FIG. 18 and FIG. 23 , along the column direction Y, the orthographic projections of the first anode W1 and the second anode W2 on the substrate 10 are located between the orthographic projections of the two ends of the first anode transition portion 311 on the substrate 10. Based on this, the positional relationship between the first anode transition portion 311 and the first anode W1 and the second anode W2 includes the following situations: wherein the two ends of the first anode transition portion 311 include a first end close to the first anode W1 and a second end close to the second anode W2.

[0217] The first type: The orthographic projection of the side of the first end of the first anode adapter 311 away from the second end on the substrate 10 substantially coincides with the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10. Furthermore, the orthographic projection of the side of the second end of the first anode adapter 311 away from the first end on the substrate 10 substantially coincides with the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10. In other words, the side of the first end of the first anode adapter 311 away from the second end is substantially aligned with the side of the first anode W1 away from the second anode W2, and the side of the second end of the first anode adapter 311 away from the first end is substantially aligned with the side of the second anode W2 away from the first anode W1.

[0218] In this configuration, the first anode transition portion 311 is extended to improve the unevenness of the flat layer at corresponding positions of the first anode W1 and the second anode W2 , which is beneficial to improving the yield of the anode layer 211 .

[0219] It should be noted that "substantially overlap" includes both absolute overlap and approximate overlap. Specifically, the floating range of the gap between the orthographic projection of the side of the first end of the first anode transition portion 311 away from the second end on the substrate 10 and the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10 does not exceed an error threshold. Alternatively, the orthographic projection of the side of the first end of the first anode transition portion 311 away from the second end on the substrate 10 and the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10 can be considered to be relatively "overlapping." The error threshold can be less than or equal to 5% of the length of the first anode W1 along the column direction Y.

[0220] Similarly, the floating range of the gap between the orthographic projection of the side of the second end of the first anode transition portion 311 away from the first end on the substrate 10 and the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10 does not exceed an error threshold. Alternatively, the orthographic projection of the side of the second end of the first anode transition portion 311 away from the first end on the substrate 10 and the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10 can be considered to be relatively "overlapping." The error threshold can be less than or equal to 5% of the length of the second anode W2 along the column direction Y.

[0221] The second type: The orthographic projection of the first end of the first anode adapter 311 on the substrate 10 is located outside the orthographic projection of the first anode W1 on the substrate 10. Furthermore, the orthographic projection of the second end of the first anode adapter 311 on the substrate 10 is located outside the orthographic projection of the second anode W2 on the substrate 10. In other words, the first end of the first anode adapter 311 extends outside the first anode W1, and the second end of the first anode adapter 311 extends outside the second anode W2.

[0222] In this configuration, the first anode transition portion 311 is extended, and if space on the display substrate 100 allows, it is extended as far as possible outside the corresponding anode. This prevents the distance between the ends of the first anode transition portion 311 and the first and second anodes W1 and W2 from being too close, which could result in uneven flatness in the flat layer corresponding to the first and second anodes W1 and W2. This further ensures the flatness of the flat layer at the corresponding locations of the first and second anodes W1 and W2, which helps improve the yield of the anode layer 211.

[0223] The third type: The orthographic projection of the side of the first end of the first anode transition portion 311 away from the second end on the substrate 10 substantially coincides with the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10. Furthermore, the orthographic projection of the second end of the first anode transition portion 311 on the substrate 10 is outside the orthographic projection of the second anode W2 on the substrate 10.

[0224] With this configuration, the first anode transition portion 311 is extended as far as possible to the outside of the corresponding anode when space on the display substrate 100 allows, thereby further ensuring the flatness of the flat layer at the corresponding positions of the first anode W1 and the second anode W2 , which is beneficial to improving the yield of the anode layer 211 .

[0225] Fourth type: The orthographic projection of the first end of the first anode transition portion 311 on the substrate 10 is located outside the orthographic projection of the first anode W1 on the substrate 10. Furthermore, the orthographic projection of the side of the second end of the first anode transition portion 311 away from the first end on the substrate 10 substantially coincides with the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10.

[0226] With this configuration, the first anode transition portion 311 is extended as far as possible to the outside of the corresponding anode when space on the display substrate 100 allows, so as to further ensure the flatness of the flat layer at the corresponding positions of the first anode W1 and the second anode W2 , which is beneficial to improving the yield of the anode layer 211 .

[0227] In some embodiments, as shown in conjunction with FIG. 18 to FIG. 23 , the data signal line group D electrically connected to the pixel driving circuit Q in the m-th column includes at least one third data signal line Data1-2, and the third data signal line Data1-2 is located on a side of the pixel driving circuit Q in the m-th column away from the pixel driving circuit Q in the (m+1)-th column, where m is a positive integer.

[0228] The above structure is equivalent to dividing the multiple data signal lines Data of the data signal line group D electrically connected to the pixel driving circuit Q in the m-th column into two parts. The first part of the data signal lines Data is the first data signal line Data1-1, which is located between the pixel driving circuit Q in the m-th column and the pixel driving circuit Q in the m+1-th column. The second part of the data signal lines Data is the third data signal line Data1-2, which is located between the pixel driving circuit Q in the m-th column and the pixel driving circuit Q in the m-1-th column.

[0229] With such an arrangement, the multiple data signal lines Data of a data signal line group D can be distributed on both sides of the pixel driving circuit Q, and the spacing between the multiple data signal lines Data of a data signal line group D can be increased to improve the problem of crosstalk between the multiple data signal lines Data, which is beneficial to improving the display uniformity of the display substrate 100.

[0230] To improve the crosstalk problem between the third data signal lines Data1-2 and other data signal lines, as shown in Figures 18 to 23 , in the anode layer 211 of the display substrate 100 provided in some embodiments of the present disclosure, the plurality of anode W adapter lines 30 electrically connected to the pixel driving circuit Q in the mth column include at least one second anode adapter line 32, the second anode adapter line 32 includes a second anode adapter portion 321, and the second anode adapter portion 321 is on the same layer as the data signal line Data.

[0231] Placing the second anode transition portion 321 on the same layer as the data signal line Data can reduce the number of film layers sandwiched between the second anode transition portion 321 and the anode layer 211, facilitating electrical connection between the second anode transition portion 321 and the anodes within the anode layer 211. Furthermore, by arranging the second anode transition portion 321 on the same layer as the data signal line Data, the second anode transition portion 321 and the data signal line Data can be formed using the same patterning process, which can help reduce process steps and increase production capacity. However, the disclosed embodiments are not limited to this, and the second anode transition portion 321 and the data signal line Data can also be formed separately using two separate manufacturing processes.

[0232] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0233] Along the row direction X, the second anode adapter 321 is located on the side of the mth column pixel driving circuit Q away from the m+1th column pixel driving circuit Q, so as to improve the crosstalk between the third data signal line Data1-2 and other data signal lines.

[0234] When m=1, as shown in Figures 18 to 23 , the second anode adapter 321 can be located between the m-th column pixel driver circuit Q and the third data signal line Data1-2. Since the m-th column pixel driver circuit Q is the first column pixel driver circuit Q, there are no data signal lines electrically connected to other columns of pixel driver circuits Q on the side of the first column pixel driver circuit Q away from the second column pixel driver circuit. Therefore, crosstalk between the first data signal line Data1-1 and the third data signal line Data1-2 electrically connected to the first column pixel driver circuit Q is sufficient to be considered.

[0235] On the basis of being provided on the same layer as the data signal lines Data, when the second anode adapter 321 is provided between the pixel driving circuit Q in the m-th column and the third data signal lines Data1-2, space is reserved between the pixel driving circuit Q in the m-th column and the third data signal lines Data1-2 to accommodate the second anode adapter 321. Furthermore, the first data signal line Data1-1 electrically connected to the pixel driving circuit Q in the m-th column is located on the side of the pixel driving circuit Q in the m-th column close to the pixel driving circuit Q in the m+1-th column. In other words, the capacitance between the first data signal line Data1-1 and the third data signal line Data1-2 can be increased, which helps reduce parasitic capacitance between the first data signal line Data1-1 and the third data signal line Data1-2, thereby reducing crosstalk between the first data signal line Data1-1 and the third data signal line Data1-2. This helps improve display uniformity of the display substrate 100.

[0236] Furthermore, because the second anode transition portion 321 is configured to have a constant voltage potential, when the second anode transition portion 321 is disposed between the first data signal line Data1-1 and the third data signal line Data1-2, the second anode transition portion 321 can be used to isolate the first data signal line Data1-1 from the third data signal line Data1-2, further reducing parasitic capacitance formed between the first data signal line Data1-1 and the third data signal line Data1-2, thereby reducing crosstalk between the first data signal line Data1-1 and the third data signal line Data1-2. The principle of configuring the second anode transition portion 321 to have a constant voltage potential is the same as the principle of configuring the second anode transition portion 321 to have a constant voltage potential, and will not be further described here.

[0237] When m is a positive integer greater than or equal to 4, the multiple columns of pixel driving circuits Q further include an m-1th column pixel driving circuit Q, which is located on a side of the m-1th column pixel driving circuit Q away from the m+1th column pixel driving circuit Q. The data signal line group D electrically connected to the m-th column pixel driving circuit Q includes at least one third data signal line Data1-2, which is located between the m-1th column pixel driving circuit Q and the m-th column pixel driving circuit Q. The data signal line group D electrically connected to the m-1th column pixel driving circuit Q includes at least one seventh data signal line (not shown in the figure), which is located between the m-1th column pixel driving circuit Q and the m-th column pixel driving circuit Q.

[0238] In some examples, all data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the m-1th column are seventh data signal lines. That is, all data signal lines Data (seventh data signal lines) in the data signal line group D electrically connected to the pixel driving circuit Q in the m-th column are located between the pixel driving circuit Q in the m-th column and the pixel driving circuit Q in the m-1th column. Centrally arranging all data signal lines Data in one data signal line group D can simplify the layout of the data signal lines Data in the display substrate 100.

[0239] In other examples, a portion of the data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the m-1th column is the seventh data signal line. That is, another portion of the data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the m-1th column is the eighth data signal line.

[0240] Based on this, it is equivalent to dividing the multiple data signal lines Data of the data signal line group D electrically connected to the pixel driving circuit Q in the m-1th column into two parts. The first part of the data signal lines Data is the seventh data signal line, which is located between the pixel driving circuit Q in the m-1th column and the pixel driving circuit Q in the m-1th column. The second part of the data signal lines Data is the eighth data signal line, which is located on the side of the pixel driving circuit Q in the m-1th column away from the pixel driving circuit Q in the m-1th column.

[0241] Along the row direction X, the second anode transfer portion 321 may be disposed between the third data signal line Data1-2 electrically connected to the pixel driving circuit Q of the mth column and the seventh data signal line electrically connected to the pixel driving circuit Q of the (m-1)th column.

[0242] On the basis of being provided on the same layer as the data signal lines Data, when the second anode transition portion 321 is provided between the third data signal lines Data1-2 and the seventh data signal line, space must be reserved between the third data signal lines Data1-2 and the seventh data signal line to accommodate the second anode transition portion 321. This helps increase the spacing between the third data signal lines Data1-2 and the seventh data signal line. This also helps reduce the parasitic capacitance formed between the third data signal lines Data1-2 and the seventh data signal line. This can alleviate the problem of potential jumps in the adjacent data signal lines Data caused by the data signal lines Data transmitting data write signals, thereby improving the lateral crosstalk problem on the display substrate 100.

[0243] Furthermore, because the second anode transition portion 321 is configured to have a constant voltage potential, when the second anode transition portion 321 is disposed between the third data signal lines Data1-2 and the seventh data signal line, the second anode transition portion 321 can be used to isolate the third data signal lines Data1-2 from the seventh data signal line, further reducing the parasitic capacitance formed between the third data signal lines Data1-2 and the seventh data signal line, thereby reducing the problem of crosstalk between the third data signal lines Data1-2 and the seventh data signal line. The principle of configuring the second anode transition portion 321 to have a constant voltage potential is the same as the principle of configuring the second anode transition portion 321 to have a constant voltage potential, and will not be further described here.

[0244] In some embodiments, as shown in conjunction with FIG18 and FIG23 , since the second anode transition portion 321 and the data signal line Data are on the same layer, the second anode transition portion 321 is arranged to extend along the column direction Y. That is, the extension direction of the second anode transition portion 321 is arranged to be substantially the same as the extension direction of the data signal line Data, thereby preventing the second anode transition portion 321 and the data signal line Data from being short-circuited.

[0245] The pixel driving circuit Q in the mth column can be electrically connected to the first anode W1 via the second anode adapter 321. The orthographic projection of the second anode adapter 321 on the substrate 10 is arranged to overlap with the orthographic projection of the first anode W1 on the substrate 10. The portion where the orthographic projection of the second anode adapter 321 on the substrate 10 overlaps with the orthographic projection of the first anode W1 on the substrate 10 can be connected via a via to electrically connect the second anode adapter 321 to the first anode W1. Furthermore, there is no need to provide a separate connection portion to electrically connect the second anode adapter 321 to the first anode W1, which can help save limited space on the display substrate 100 and facilitate the layout of the display substrate 100.

[0246] The inventors have discovered that when the orthographic projection of the second anode transition portion 321 on the substrate 10 overlaps with the orthographic projection of the first anode W1 on the substrate 10, since the second anode transition portion 321 does not need to be electrically connected to other anodes, the orthographic projection of the second anode transition portion 321 on the substrate 10 is generally set to not overlap with the orthographic projection of the second anode W2 on the substrate 10. Furthermore, since the first anodes W1 and the second anodes W2 are alternately arranged along the column direction Y, the layout of the corresponding second metal trace layer SD2 below the first anodes W1 and the second anodes W2 is essentially the same, differing only in the positions of the first anodes W1 and the second anodes W2 and their respective anode transition portions. As a result, a step difference may also appear on the surface of the flat layer between the second anode W2 and the second metal trace layer SD2 on the side away from the substrate, increasing the difficulty of forming the anode layer 211 (second anode W2) thereon, thereby affecting the yield of the light-emitting device O.

[0247] Based on this, in the display substrate 100 provided in some embodiments of the present disclosure, the second anode transition portion 321 is extended to the position corresponding to the second anode W2, so that the orthographic projection of the second anode transition portion 321 on the substrate 10 overlaps with the orthographic projection of the second anode W2 on the substrate 10.

[0248] Such a configuration allows the second anode transition portion 321 to fill the blank space to improve the problem of uneven surface of the side of the flat layer formed between the second metal wiring layer SD2 and the anode layer 211 away from the substrate, which is beneficial to improving the yield of the anode layer 211 formed on the surface of the side of the flat layer away from the substrate.

[0249] In some embodiments, as shown in conjunction with FIG. 18 and FIG. 23 , along the column direction Y, the orthographic projections of the first anode W1 and the second anode W2 on the substrate 10 are located between the orthographic projections of the two ends of the second anode transition portion 321 on the substrate 10. Based on this, the positional relationship between the second anode transition portion 321 and the first anode W1 and the second anode W2 includes the following situations: wherein the two ends of the second anode transition portion 321 include a first end close to the first anode W1 and a second end close to the second anode W2.

[0250] The first type: The orthographic projection of the side of the first end of the second anode adapter 321 away from the second end on the substrate 10 substantially coincides with the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10. Furthermore, the orthographic projection of the side of the second end of the second anode adapter 321 away from the first end on the substrate 10 substantially coincides with the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10. In other words, the side of the first end of the second anode adapter 321 away from the second end is substantially aligned with the side of the first anode W1 away from the second anode W2, and the side of the second end of the second anode adapter 321 away from the first end is substantially aligned with the side of the second anode W2 away from the first anode W1.

[0251] In this configuration, the second anode transition portion 321 is extended to improve the unevenness of the flat layer at corresponding positions of the first anode W1 and the second anode W2 , which is beneficial to improving the yield of the anode layer 211 .

[0252] It should be noted that "substantially overlap" includes both absolute overlap and approximate overlap. Specifically, the gap between the orthographic projection of the side of the first end of the second anode transition portion 321 away from the second end on the substrate 10 and the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10 must not exceed an error threshold. Alternatively, the orthographic projection of the side of the first end of the second anode transition portion 321 away from the second end on the substrate 10 and the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10 can be considered to be relatively "overlapping." The error threshold can be less than or equal to 5% of the length of the first anode W1 along the column direction Y.

[0253] Similarly, the floating range of the gap between the orthographic projection of the side of the second end of the second anode transition portion 321 away from the first end on the substrate 10 and the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10 does not exceed an error threshold. Alternatively, the orthographic projection of the side of the second end of the second anode transition portion 321 away from the first end on the substrate 10 and the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10 can be considered to be relatively "overlapping." The error threshold can be less than or equal to 5% of the length of the second anode W2 along the column direction Y.

[0254] The second type: The orthographic projection of the first end of the second anode transition portion 321 on the substrate 10 is located outside the orthographic projection of the first anode W1 on the substrate 10. Furthermore, the orthographic projection of the second end of the second anode transition portion 321 on the substrate 10 is located outside the orthographic projection of the second anode W2 on the substrate 10. In other words, the first end of the second anode transition portion 321 extends outside the first anode W1, and the second end of the second anode transition portion 321 extends outside the second anode W2.

[0255] In this configuration, the second anode transition portion 321 is extended, and if space on the display substrate 100 allows, it is extended as far as possible outside the corresponding anode. This prevents the distance between the ends of the second anode transition portion 321 and the first anode W1 and the second anode W2 from being too close, which could result in uneven flatness in the flat layer corresponding to the first anode W1 and the second anode W2. This further ensures the flatness of the flat layer at the corresponding locations of the first anode W1 and the second anode W2, which helps improve the yield of the anode layer 211.

[0256] The third type: The orthographic projection of the side of the first end of the second anode transition portion 321 away from the second end on the substrate 10 substantially coincides with the orthographic projection of the side of the first anode W1 away from the second anode W2 on the substrate 10. Furthermore, the orthographic projection of the second end of the second anode transition portion 321 on the substrate 10 is outside the orthographic projection of the second anode W2 on the substrate 10.

[0257] With this configuration, the second anode transition portion 321 is extended as far as possible to the outside of the corresponding anode when space on the display substrate 100 allows, so as to further ensure the flatness of the flat layer at the corresponding positions of the first anode W1 and the second anode W2 , which is beneficial to improving the yield of the anode layer 211 .

[0258] Fourth type: The orthographic projection of the first end of the second anode transition portion 321 on the substrate 10 is located outside the orthographic projection of the first anode W1 on the substrate 10. Furthermore, the orthographic projection of the side of the second end of the second anode transition portion 321 away from the first end on the substrate 10 substantially coincides with the orthographic projection of the side of the second anode W2 away from the first anode W1 on the substrate 10.

[0259] With this configuration, the second anode transition portion 321 is extended as far as possible to the outside of the corresponding anode when space on the display substrate 100 allows, so as to further ensure the flatness of the flat layer at the corresponding positions of the first anode W1 and the second anode W2 , which is beneficial to improving the yield of the anode layer 211 .

[0260] In some embodiments, as shown in conjunction with FIG. 18 to FIG. 23 , the multiple columns of pixel driving circuits Q further include an m+2-th column pixel driving circuit Q, which is located on a side of the m+1-th column pixel driving circuit Q away from the m-th column pixel driving circuit Q. The data signal line group D electrically connected to the m+1-th column pixel driving circuit Q includes at least one fourth data signal line Data2-2, which is located between the m+1-th column pixel driving circuit Q and the m+2-th column pixel driving circuit Q. The data signal line group D electrically connected to the m+2-th column pixel driving circuit Q includes at least one fifth data signal line Data3-1, which is located between the m+1-th column pixel driving circuit Q and the m+2-th column pixel driving circuit Q.

[0261] The above structure is equivalent to dividing the multiple data signal lines Data of the data signal line group D electrically connected to the pixel driving circuit Q in the m+1th column into two parts. The first part of the data signal lines Data is the second data signal line Data2-1, which is located between the pixel driving circuit Q in the mth column and the pixel driving circuit Q in the m+1th column. The second part of the data signal lines Data is the fourth data signal line Data2-2, which is located on the side of the pixel driving circuit Q in the m+2th column away from the pixel driving circuit Q in the m+1th column.

[0262] With such an arrangement, the multiple data signal lines Data of a data signal line group D can be distributed on both sides of the pixel driving circuit Q, and the spacing between the multiple data signal lines Data of a data signal line group D can be increased to improve the problem of crosstalk between the multiple data signal lines Data, which is beneficial to improving the display uniformity of the display substrate 100.

[0263] In some examples, all of the data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the (m+2)th column are the fifth data signal line Data3-1. That is, all of the data signal lines Data (fifth data signal line Data3-1) in the data signal line group D electrically connected to the pixel driving circuit Q in the (m)th column are located between the pixel driving circuit Q in the (m+1)th column and the pixel driving circuit Q in the (m+2)th column. Centrally arranging all of the data signal lines Data in one data signal line group D can simplify the layout of the data signal lines Data in the display substrate 100.

[0264] In other examples, a portion of the data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the (m+2)th column is the fifth data signal line Data3-1. In other words, another portion of the data signal lines Data in the data signal line group D electrically connected to the pixel driving circuit Q in the (m+2)th column is the sixth data signal line Data3-2.

[0265] Based on this, it is equivalent to dividing the multiple data signal lines Data of the data signal line group D electrically connected to the pixel driving circuit Q in the m+2th column into two parts. The first part of the data signal lines Data is the fifth data signal line Data3-1, which is located between the pixel driving circuit Q in the m+1th column and the pixel driving circuit Q in the m+2th column. The second part of the data signal lines Data is the sixth data signal line Data3-2, which is located between the pixel driving circuit Q in the m+2th column and the pixel driving circuit Q in the m+3th column.

[0266] To improve the crosstalk problem between the fourth data signal line Data2-2 and the fifth data signal line Data3-1. In conjunction with Figures 18 to 23, in the anode layer 211 of the display substrate 100 provided by some embodiments of the present disclosure: the multiple anode W transfer lines 30 electrically connected to the pixel driving circuit Q of the m+2 column include at least one third anode transfer line 33, and the third anode transfer line 33 includes a third anode transfer portion 331, and the third anode transfer portion 331 is a third anode transfer portion 331 on the same layer as the data signal line Data. Along the row direction X, the third anode transfer portion 331 is located between the fourth data signal line Data2-2 electrically connected to the pixel driving circuit Q of the m+1 column and the fifth data signal line Data3-1 electrically connected to the pixel driving circuit Q of the m+2 column.

[0267] Placing the third anode transition portion 331 on the same layer as the data signal line Data can reduce the number of film layers interposed between the third anode transition portion 331 and the anode layer 211, thereby facilitating electrical connection between the third anode transition portion 331 and the anodes within the anode layer 211. Furthermore, by arranging the third anode transition portion 331 on the same layer as the data signal line Data, the third anode transition portion 331 and the data signal line Data can be formed using the same patterning process, which can help reduce process steps and increase production capacity. However, the disclosed embodiments are not limited to this, and the third anode transition portion 331 and the data signal line Data can also be formed separately using two separate manufacturing processes.

[0268] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0269] On the basis of providing the third anode transition portion 331 on the same layer as the data signal line Data, when the third anode transition portion 331 is provided between the fourth data signal line Data2-2 and the fifth data signal line Data3-1, space is reserved between the fourth data signal line Data2-2 and the fifth data signal line Data3-1 to accommodate the third anode transition portion 331. This helps increase the spacing between the fourth data signal line Data2-2 and the fifth data signal line Data3-1. This also helps reduce the parasitic capacitance formed between the fourth data signal line Data2-2 and the fifth data signal line Data3-1. This can alleviate the potential jump of the adjacent data signal line Data caused by the data signal line Data transmitting a data write signal, thereby improving the lateral crosstalk problem of the display substrate 100.

[0270] Furthermore, because the third anode adapter 331 is configured to have a constant voltage potential, when the third anode adapter 331 is disposed between the fourth data signal line Data2-2 and the fifth data signal line Data3-1, the third anode adapter 331 can be used to isolate the fourth data signal line Data2-2 from the fifth data signal line Data3-1, further reducing the parasitic capacitance formed between the fourth data signal line Data2-2 and the fifth data signal line Data3-1, thereby reducing crosstalk between the fourth data signal line Data2-2 and the fifth data signal line Data3-1. The principle behind configuring the third anode adapter 331 to have a constant voltage potential is the same as the principle behind configuring the first anode adapter 311 to have a constant voltage potential, and will not be further elaborated here.

[0271] In some examples, the third anode transition portion 331 is electrically connected to the third anode W3 , and along the row direction X, the third anode W3 overlaps with the first anode W1 , and the third anode W3 overlaps with the second anode W2 .

[0272] The pixel driving circuit Q in the (m+2)th column can be electrically connected to the third anode W3 via the third anode adapter 331. The orthographic projection of the third anode adapter 331 on the substrate 10 is arranged to overlap with the orthographic projection of the third anode W3 on the substrate 10. The overlapping portion of the orthographic projection of the third anode adapter 331 on the substrate 10 and the orthographic projection of the third anode W3 on the substrate 10 can be connected via a via to electrically connect the third anode adapter 331 to the third anode W3. Furthermore, there is no need to provide a separate connection portion to electrically connect the third anode adapter 331 to the third anode W3, which can help save limited space on the display substrate 100 and facilitate the layout of the display substrate 100.

[0273] The inventors have discovered that when the orthographic projection of the third anode transition portion 331 on the substrate 10 overlaps with the orthographic projection of the third anode W3 on the substrate 10, it is sufficient to electrically connect the third anode transition portion 331 to the third anode W3 to drive the light-emitting device O corresponding to the third anode W3 to emit light. It is possible that the orthographic projection of the third anode transition portion 331 on the substrate 10 lies within the orthographic projection of the third anode W3 on the substrate 10. Therefore, the area of ​​the third anode transition portion 331 along the column direction Y that does not overlap with the orthographic projection of the third anode W3 on the substrate 10 can cause a step difference in the surface of the flat layer between the third anode W3 and the second metal trace layer SD2 on the side away from the substrate, increasing the difficulty of forming the anode layer 211 (third anode W3) thereon and affecting the yield of the light-emitting device O.

[0274] Based on this, in the display substrate 100 provided in some embodiments of the present disclosure, the boundary of the orthographic projection of the third anode transition portion 331 on the substrate 10 along the column direction Y is set to roughly coincide with the boundary of the orthographic projection of the third anode W3 on the substrate 10 .

[0275] It should be noted that "substantially overlap" includes both absolute overlap and approximate overlap. Specifically, the floating range of the gap between the boundary of the orthographic projection of the third anode transition portion 331 on the substrate 10 and the boundary of the orthographic projection of the third anode W3 on the substrate 10 along the column direction Y does not exceed a threshold error. Alternatively, the boundary of the orthographic projection of the third anode transition portion 331 on the substrate 10 and the boundary of the orthographic projection of the third anode W3 on the substrate 10 along the column direction Y can be considered to be relatively "overlapping." The threshold error can be less than or equal to 10% of the length of the third anode W3 along the column direction Y.

[0276] Such a configuration is equivalent to extending the third anode transition portion 331 to the same length as the third anode W3 in the column direction Y, thereby improving the problem of uneven flat layer at the corresponding position of the third anode W3 due to the shorter length of the third anode transition portion 331, which is beneficial to improving the yield of the anode layer 211.

[0277] Furthermore, since the third anode transition portion 331 and the data signal line Data are on the same layer, the third anode transition portion 331 is arranged to extend along the column direction Y. In other words, the extension direction of the third anode transition portion 331 is arranged to be substantially the same as the extension direction of the data signal line Data, thereby preventing the third anode transition portion 331 and the data signal line Data from being short-circuited.

[0278] In some embodiments, as shown in conjunction with FIG. 18 and FIG. 23 , along the column direction Y, the orthographic projection of the third anode W3 on the substrate 10 is located between the orthographic projections of the two ends of the third anode transition portion 331 on the substrate 10. Based on this, in addition to the aforementioned "the boundary of the orthographic projection of the third anode transition portion 331 on the substrate 10 along the column direction Y substantially coincides with the boundary of the orthographic projection of the third anode W3 on the substrate 10," the positional relationship between the third anode transition portion 331 and the third anode W3 also includes the following situations:

[0279] The first type: the orthographic projection of one of the two ends of the third anode transition portion 331 on the substrate 10 is located outside the orthographic projection of the third anode W3 on the substrate 10 .

[0280] The second type: the orthographic projections of the two ends of the third anode transition portion 331 on the substrate 10 are both located outside the orthographic projection of the third anode W3 on the substrate 10 .

[0281] In this configuration, the third anode transition portion 331 is extended, and if space on the display substrate 100 permits, it is extended as far as possible outside the corresponding anode. This prevents the problem of uneven flatness of the flat layer corresponding to the third anode W3, which may occur due to the close distance between the ends of the third anode transition portion 331 and the third anode W3. In other words, the flatness of the flat layer at the position corresponding to the third anode W3 can be further ensured, which is beneficial to improving the yield of the anode layer 211.

[0282] The above mainly introduces the positions of the data signal lines and the anode switching parts in conjunction with the relevant drawings. The following will introduce the positions of various transistors and multiple connection parts in the pixel driving circuit Q in conjunction with the relevant drawings.

[0283] In some embodiments, as shown in Figures 18 to 22, the pixel driving circuit Q includes: a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6 and a second reset transistor T7.

[0284] Along the column direction Y, the first reset transistor T1 and the compensation transistor T2 are located on the same side of the driving transistor T3, the data write transistor T4 and the first emission control transistor T5 are located on the same side of the driving transistor T3, and the first reset transistor T1 and the data write transistor T4 are located on both sides of the driving transistor T3. This is equivalent to the first reset transistor T1 and the compensation transistor T2 being located in the upper part of the pixel driving circuit Q, and the data write transistor T4 and the first emission control transistor T5 being located in the lower part of the pixel driving circuit Q.

[0285] Based on this, the data writing transistor T4 is located on the side of the first light-emitting control transistor T5 away from the driving transistor T3. This is equivalent to placing the data writing transistor T4 at the edge of the pixel driving circuit Q, which facilitates the electrical connection between the data writing transistor T4 and the data signal line Data, and prevents the electrical connection between the data writing transistor T4 and the data signal line Data from restricting the layout of other transistors in the pixel driving circuit Q, thereby improving the layout flexibility of the display substrate 100.

[0286] In some examples, the first electrode a1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vinit1. The first initialization signal line Vinit1 is located on a side of the first reset transistor T1 away from the compensation transistor T2 along the column direction Y. This is equivalent to arranging the first initialization signal line Vinit1 at an edge of the pixel driving circuit Q, which facilitates the layout of the first initialization signal line Vinit1 and prevents the first initialization signal line Vinit1 from shorting with other transistors in the pixel driving circuit Q.

[0287] In some examples, the control electrode of the first reset transistor T1 is electrically connected to the third scan signal line G3. The control electrode of the compensation transistor T2 is electrically connected to the second scan signal line G2. The second scan signal line G2 and the third scan signal line G3 are located in the first metal wiring layer SD1.

[0288] The second scan signal line G2 is located between the third scan signal line G3 and the driving transistor T3 along the column direction Y. This arrangement allows the third scan signal line G3 to correspond to the first reset transistor T1, and the second scan signal line G2 to correspond to the compensation transistor T2, facilitating the layout of the second scan signal line G2 and the third scan signal line G3.

[0289] In some examples, the first metal wiring layer SD1 includes a plurality of conductive portions. The plurality of connecting portions includes a first conductive portion PAD1, which is configured to connect the first electrode a1 of the first reset transistor T1 and the first initialization signal line Vinit1.

[0290] Because the first electrode a1 of the first reset transistor T1 is located on a side of the control electrode c1 of the first reset transistor T1 away from the compensation transistor T2, the first conductive portion PAD1 can be located on a side of the third scan signal line G3 away from the second scan signal line G2 to facilitate the layout of the first conductive portion PAD1 and the third scan signal line G3 and prevent the first conductive portion PAD1 and the third scan signal line G3 from crossing and causing a short circuit.

[0291] In some examples, the plurality of connection portions further include a second adapter portion PAD2, one end of which is electrically connected to the control electrode c3 of the driving transistor T3, and the other end of which is electrically connected to the second electrode b2 of the compensation transistor T2 and the second electrode b1 of the first reset transistor T1. Thus, the control electrode c3 of the driving transistor T3 is electrically connected to the second electrode b2 of the compensation transistor T2 and the second electrode b1 of the first reset transistor T1.

[0292] The second transfer portion PAD2 is located on the side of the second scanning signal line G2 close to the driving transistor T3, which is equivalent to setting the second transfer portion PAD2 in the space formed by the first reset transistor T1, the compensation transistor T2 and the driving transistor T3, so that the second transfer portion PAD2 can be electrically connected to the first reset transistor T1, the compensation transistor T2 and the driving transistor T3 respectively, so as to realize the electrical connection between the control electrode c3 of the driving transistor T3 and the second electrode b2 of the compensation transistor T2 and the second electrode b1 of the first reset transistor T1.

[0293] In some examples, the plurality of connection portions further include a third adapter portion PAD3, one end of the third adapter portion PAD3 being electrically connected to the first electrode a3 of the driving transistor T3, and the other end of the third adapter portion PAD3 being electrically connected to the second electrode b4 of the data writing transistor T4 and the second electrode b5 of the first light emission control transistor T5. Thus, the first electrode a3 of the driving transistor T3 is electrically connected to the second electrode b4 of the data writing transistor T4 and the second electrode b5 of the first light emission control transistor T5.

[0294] The third adapter PAD3 is located in the space formed by the driving transistor T3, the data writing transistor T4 and the first light-emitting control transistor T5, so that the third adapter PAD3 can be electrically connected to the driving transistor T3, the data writing transistor T4 and the first light-emitting control transistor T5 respectively, thereby realizing the electrical connection between the first electrode a3 of the driving transistor T3 and the second electrode b4 of the data writing transistor T4 and the second electrode b5 of the first light-emitting control transistor T5.

[0295] In some embodiments, as shown in Figures 18 to 22, when the pixel driving circuit Q further includes a second light-emitting control transistor T6 and a second reset transistor T7, the anode transfer line 30 further includes a fourth conductive portion PAD4 located on the first wiring metal layer SD1, and one end of the fourth conductive portion PAD4 of the anode transfer line 30 is electrically connected to the second electrode of the second light-emitting control transistor T6 and the second electrode of the second reset transistor T7, and the other end of the fourth conductive portion PAD4 can be electrically connected to the anode transfer portion (the first anode transfer portion, the second anode transfer portion or the third anode transfer portion) corresponding to the same anode transfer line 30.

[0296] Along the column direction Y, the fourth conductive portion PAD4 is located between the enable signal line EM and the first scanning signal line G1, and the fourth conductive portion PAD4 is located in the space formed by the second light-emitting control transistor T6 and the second reset transistor T7 and the enable signal line EM and the first scanning signal line G1, so as to facilitate the electrical connection between the fourth conductive portion PAD4 and the second light-emitting control transistor T6 and the second reset transistor T7.

[0297] In some embodiments, as shown in Figures 18 to 22 , along the column direction Y, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, and the second reset transistor T7 within the pixel driving circuit Q are all located on the same side of the driving transistor T3. The second reset transistor T7 is located on the side of the second emission control transistor T6 away from the driving transistor T3.

[0298] Based on this, along the row direction X, the second light emission control transistor T6 is adjacent to the first light emission control transistor T5 , and along the row direction X, the second reset transistor T7 is adjacent to the data writing transistor T4 .

[0299] Because the control electrode of the first emission control transistor T5 is electrically connected to the enable signal line EM, and the control electrode of the second emission control transistor T6 is electrically connected to the enable signal line EM, the second emission control transistor T6 and the first emission control transistor T5 are arranged adjacent to each other along the row direction X. This allows the second emission control transistor T6 and the first emission control transistor T5 to be arranged along the direction in which the enable signal line EM extends. This eliminates the need for a wire to be wound around the enable signal line EM, facilitating the electrical connection of the enable signal line EM to the control electrodes of the first emission control transistor T5 and the second emission control transistor T6.

[0300] In addition, in some examples, the enable signal line EM is located on the first gate metal layer Gate1. The enable signal line EM may include a first portion and a second portion. The first portion of the enable signal line EM may be multiplexed as the control electrode c5 of the first emission control transistor T5, and the second portion of the enable signal line EM may be multiplexed as the control electrode c6 of the second emission control transistor T6. The above structure is conducive to simplifying the structure of the pixel driving circuit Q.

[0301] Because the control electrode of the data write transistor T4 is electrically connected to the first scan signal line G1, and the control electrode of the second reset transistor T7 is electrically connected to the first scan signal line G1, the second reset transistor T7 is arranged adjacent to the data write transistor T4 along the row direction X. This allows the second reset transistor T7 and the data write transistor T4 to be arranged along the direction in which the first scan signal line G1 extends. This eliminates the need for a winding of the first scan signal line G1, facilitating electrical connection between the first scan signal line G1, the control electrode of the second reset transistor T7, and the control electrode of the data write transistor T4.

[0302] In some examples, the first scanning signal line G1 is located in the first gate metal layer Gate1, and the impedance of the first scanning signal line G1 formed is relatively large, which affects the first scanning signal from the first scanning signal line G1 received by the data writing transistor T4 in different pixel units Q, and easily affects the uniformity of the display substrate 100.

[0303] Based on this, the first routing metal layer SD1 of the display substrate 100 may further include a first auxiliary signal line F1, which is connected in parallel with the first scanning signal line G1. This can reduce the resistance of the first scanning signal line G1, improve the problem of high impedance of the first scanning signal line G1, and enhance the uniformity of the display substrate 100.

[0304] In some examples, the orthographic projection of the first auxiliary signal line F1 on the substrate 10 at least partially overlaps with the orthographic projection of the first scan signal line G1 on the substrate 10. The first auxiliary signal line F1 and the first scan signal line G1 can be electrically connected through a via using the overlapping portion thereof, thereby eliminating the need to use other connecting portions to electrically connect the first auxiliary signal line F1 and the first scan signal line G1, thereby reducing space occupied by the display substrate 100.

[0305] Exemplarily, the orthographic projection of the first auxiliary signal line F1 on the substrate 10 partially overlaps with the orthographic projection of the first scanning signal line G1 on the substrate 10 .

[0306] Exemplarily, the orthographic projection of the first auxiliary signal line F1 on the substrate 10 is located within the orthographic projection of the first scanning signal line G1 on the substrate 10 .

[0307] Regardless of any of the above designs, the first auxiliary signal line F1 and the first scanning signal line G1 can be electrically connected through the via hole using the overlapping portion thereof, thereby simplifying the connection method between the first auxiliary signal line F1 and the first scanning signal line G1.

[0308] In some embodiments, as shown in Figures 18 to 22, the same column of pixel driver circuits Q includes a first portion of pixel driver circuits Q1 and a second portion of pixel driver circuits Q2. The first portion of pixel driver circuit Q1 is electrically connected to the second portion of data signal line Data-2, and the second portion of pixel driver circuit Q2 is electrically connected to the first portion of data signal line Data-1. The data write transistor T4 of the first portion of pixel driver circuit Q1 is located between the second reset transistor T7 and the second portion of data signal line Data-2, and the data write transistor T4 of the second portion of pixel driver circuit Q2 is located on a side of the second reset transistor T7 away from the first portion of data signal line Data-1.

[0309] 18 to 22 use the pixel driving circuits Q in the first row of pixel driving circuits as the first part of the pixel driving circuits Q1 of each column, and use the pixel driving circuits Q in the second row of pixel driving circuits as the second part of the pixel driving circuits Q2 of each column.

[0310] At least one pixel driver circuit Q within the second portion of the pixel driver circuit Q2 includes a first data transfer portion L1 located on the first metal layer SD1. The first data transfer portion L1 is configured to electrically connect the pixel driver circuit Q to the data signal line Data. The first data transfer portion L1 includes a relief portion R1 located on a side of the second reset transistor T7 away from the second emission control transistor T6.

[0311] Because the second reset transistor T7 is located between the data write transistor T4 and the first portion of the data signal line Data-1 to which the data write transistor T4 is electrically connected for the pixel drive circuit Q within the second portion of the pixel drive circuit Q2, a relief portion R1 is provided within the first data transfer portion L1. This allows the first data transfer portion L1, which connects the data write transistor T4 and the first portion of the data signal line Data-1, to avoid the second reset transistor T7, thereby preventing a short circuit between the first data transfer portion L1 and the second reset transistor T7.

[0312] In some examples, the avoidance portion R1 may be in a concave shape, or may be in other shapes that bulge toward the side away from the second reset transistor T7 . The embodiments of the present disclosure are not limited thereto.

[0313] In some embodiments, as shown in Figures 18 to 22, the first electrode a7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vinit2. The multiple connection portions in the first routing metal layer SD1 may further include a first connection portion PAD5. The first connection portion PAD5 is used to connect the first electrode a7 of the second reset transistor T7 and the second initialization signal line Vinit2, thereby electrically connecting the first electrode a7 of the second reset transistor T7 and the second initialization signal line Vinit2, which are located on different layers.

[0314] Along the column direction Y, the second initialization signal line Vinit2 is located on a side of the second reset transistor T7 away from the second light control transistor T6 , and the avoidance portion R1 is located on a side of the first connection portion PAD5 away from the second light control transistor T6 .

[0315] Since the first data transfer portion L1 and the first connection portion PAD5 are both located on the first routing metal layer SD1, the avoidance portion R1 is provided on a side of the first connection portion PAD5 away from the second light-emitting control transistor T6. The first data transfer portion L1 can use the avoidance portion R1 to avoid the first connection portion PAD5, thereby preventing the first data transfer portion L1 and the first connection portion PAD5 from being short-circuited.

[0316] In some embodiments, as shown in Figures 18 to 22 , the multiple conductive portions on the first routing metal layer SD1 in the driver circuit layer 20 further include a second connecting portion PAD6. One end of the second connecting portion PAD6 is electrically connected to the first plate Cst-1 of the storage capacitor Cst and the first electrode a5 of the first emission control transistor T5, and the other end of the second connecting portion PAD6 is electrically connected to the first power signal line VDD. This electrically connects the first power signal line VDD to the first plate Cst-1 of the storage capacitor Cst and the first electrode a5 of the first emission control transistor T5.

[0317] In some embodiments, as shown in Figures 18 to 22 , a plurality of first power signal lines VDD are arranged along a row direction X and extend in a column direction Y. Along the row direction X, a first portion of the data signal lines Data-1 and a second portion of the data signal lines Data-2 are respectively located on either side of the first power signal line VDD.

[0318] With this configuration, the first power signal line VDD can be used to increase the spacing between the first portion of the data signal line Data-1 and the second portion of the data signal line Data-2, thereby reducing parasitic capacitance between the first portion of the data signal line Data-1 and the second portion of the data signal line Data-2, and thus reducing crosstalk between the first portion of the data signal line Data-1 and the second portion of the data signal line Data-2. Furthermore, the first power signal line VDD is configured as a constant voltage signal, further reducing crosstalk between the first portion of the data signal line Data-1 and the second portion of the data signal line Data-2, thereby improving the display quality of the display substrate 100.

[0319] In some embodiments, as shown in Figures 18 to 22 , the relief portion R1 of the first data transfer portion L1 crosses over the first power signal line VDD electrically connected to the second portion of the pixel driving circuit Q2 along the row direction X. This is equivalent to positioning the first power signal line VDD between the data write transistor T4 and a portion of the data signal line Data-1 along the row direction X. Adjusting the first power signal line VDD to the center of the pixel driving circuit Q facilitates electrical connection between the first power signal line VDD and the storage capacitor Cst located in the center of the pixel driving circuit Q, thereby facilitating electrical connection between the first power signal line VDD and the second connection portion PAD6, thereby simplifying the wiring layout of the display substrate 100.

[0320] In addition, since the extension direction of the first power signal line VDD intersects with the extension direction of the first data transfer portion L1, the first data transfer portion L1 and the first power signal line VDD are arranged on different layers, so that the avoidance portion R1 of the first data transfer portion L1 crosses the first power signal line VDD electrically connected to the second part of the pixel driving circuit Q2, thereby preventing the avoidance portion R1 of the first data transfer portion L1 from being short-circuited with the first power signal line VDD electrically connected to the second part of the pixel driving circuit Q2.

[0321] It should be noted that “crossing” means that the orthographic projection of the avoidance portion R1 of the first data transfer portion L1 on the substrate 10 overlaps with the orthographic projection of the first power signal line VDD electrically connected to the second part of the pixel driving circuit Q2 on the substrate 10 .

[0322] At least one pixel driver circuit Q within the first portion of the pixel driver circuit Q2 includes a second data transfer portion L2 located on the first metal layer SD1. Because the data write transistor T4 of the first portion of the pixel driver circuit Q1 is located between the second reset transistor T7 and the second portion of the data signal line Data-2, no other transistor is provided between the data write transistor T4 of the first portion of the pixel driver circuit Q1 and the second portion of the data signal line Data-2. This allows the spacing between the data write transistor T4 of the first portion of the pixel driver circuit Q2 and the second portion of the data signal line Data-2 to which it is electrically connected, along the row direction X, to be smaller than the spacing between the data write transistor T4 of the first portion of the pixel driver circuit Q1 and the first portion of the data signal line Data-1 to which it is electrically connected.

[0323] Based on this, the length of the second data transfer portion L2 is shorter than the length of the first data transfer portion L1 along the row direction X. Furthermore, the space occupied by the second data transfer portion L2 on the display substrate 100 can be reduced, thereby saving space on the display substrate 100 and facilitating the layout of other traces within the display substrate 100.

[0324] In some examples, the first data transfer portion L1 includes a first portion and a second portion, and the orthographic projection of the first portion of the first data transfer portion L1 on the substrate 10 overlaps with the orthographic projection of the first electrode a4 of the data write transistor T4 on the substrate 10, so that the first portion of the first data transfer portion L1 and the first electrode a4 of the data write transistor T4 are electrically connected through a via, simplifying the connection method between the first portion of the first data transfer portion L1 and the first electrode a4 of the data write transistor T4. In addition, the orthographic projection of the second portion of the first data transfer portion L1 on the substrate 10 overlaps with the orthographic projection of the first portion of the data signal line Data-1 on the substrate 10, so that the second portion of the first data transfer portion L1 and the first portion of the data signal line Data-1 are electrically connected through a via, simplifying the connection method between the second portion of the first data transfer portion L1 and the first portion of the data signal line Data-1.

[0325] Exemplarily, the orthographic projection of the first part of the first data transfer portion L1 on the substrate 10 roughly coincides with the orthographic projection of the first electrode a4 of the data writing transistor T4 on the substrate 10, and covers the orthographic projection of the second part of the first data transfer portion L1 on the substrate 10 together with the orthographic projection of the first part of the data signal line Data-1 on the substrate 10.

[0326] Based on this, the size of the first data transfer portion L1 can be further reduced, which is beneficial to reducing the space occupied by the second data transfer portion L2 on the display substrate 100, saving space on the display substrate 100 and facilitating the layout of other lines in the display substrate 100.

[0327] In some embodiments, the display substrate 100 further includes a plurality of first and second general initialization signal lines V1 and V1, each extending along the column direction Y. Along the row direction X, three adjacent columns of pixel driver circuits Q constitute a pixel driver circuit unit column. The first initialization signal line Vinit1 electrically connected to each pixel driver circuit Q within the pixel driver circuit unit column can be electrically connected to the first general initialization signal line V1, thereby utilizing the first general initialization signal line V1 to provide a signal to each first initialization signal line Vinit1 within the pixel driver circuit unit column. Furthermore, the second initialization signal line Vinit2 electrically connected to each pixel driver circuit Q within the pixel driver circuit unit column can be electrically connected to a second general initialization signal line (not shown) to utilize the second general initialization signal line to provide a signal to each second initialization signal line Vinit2 within the pixel driver circuit unit column. This facilitates signal provision for the first and second initialization signal lines Vinit1 and Vinit2, simplifying the layout of the display substrate 100.

[0328] In some examples, the first general initialization signal line V1 and the second general initialization signal line V1 may be located on both sides of one pixel driving circuit unit column.

[0329] This prevents the problem of short circuits between signal lines caused by an excessive number of signal lines (the first general initialization signal line V1 and the second general initialization signal line V2) disposed on one side of the pixel driving circuit unit column, thereby improving the quality of the display substrate 100.

[0330] However, the embodiments of the present disclosure are not limited thereto. In other examples, the first general initialization signal line V1 and the second general initialization signal line V2 may be located on the same side of a pixel driving circuit unit column, thereby increasing the flexibility of the wiring layout within the display substrate 100.

[0331] The above description, in conjunction with the relevant drawings, primarily describes the layout of the pixel drive circuit Q and the data signal line Data when the drive circuit layer 20 includes the first semiconductor layer POLY, the first gate metal layer Gate1, the second gate metal layer Gate2, the first routing metal layer SD1, and the second routing metal layer SD2. The following description, in conjunction with the relevant drawings, also describes the layout of the pixel drive circuit Q and the data signal line Data when the drive circuit layer 20 includes the first semiconductor layer POLY, the first gate metal layer Gate1, the second gate metal layer Gate2, the first routing metal layer SD1, the second routing metal layer SD2, and the third metal routing layer SD3.

[0332] Figure 24 is an equivalent circuit diagram of multiple pixel driving circuits in a display substrate according to some other embodiments, and Figure 25 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B1 in Figure 24. Figure 26 is a partial film layer diagram of B1 in Figure 24. Figure 27 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B2 in Figure 24. Figure 28 is a partial film layer diagram of B2 in Figure 24. Figure 29 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B3 in Figure 24. Figure 30 is a partial film layer diagram of B3 in Figure 24. Figure 31 is a partial connection diagram of the pixel driving circuit and the light-emitting layer of B4 in Figure 24. Figure 32 is a partial film layer diagram of B4 in Figure 24.

[0333] In some embodiments, as shown in Figures 25 to 32, the driving circuit layer 20 includes a first semiconductor layer POLY, a first gate metal layer Gate1, a second gate metal layer Gate2, a first wiring metal layer SD1, a second wiring metal layer SD2 and a third metal wiring layer SD3, and the anode layer 211 is located on a side of the third metal wiring layer SD3 away from the second wiring metal layer SD2.

[0334] Based on this, the multiple data signal lines Data in a data signal group D can be located in the second routing metal layer SD2 and / or the third routing metal layer SD3. The locations of the multiple data signal lines Data in a data signal group D can include the following three situations.

[0335] The first type: as shown in FIG7 , the multiple data signal lines Data in a data signal group D are all located in the second routing metal layer SD2 . That is, the multiple data signal lines D are all located in the second routing metal layer SD2 .

[0336] As shown in the above structure, the data signal line Data can be formed together with other conductive parts of the first wiring metal layer SD1 through a single patterning process, which can simplify the manufacturing process of the display substrate 100 .

[0337] The second type: as shown in Figures 25 to 28, multiple data signal lines Data in a data signal group D are all located in the third routing metal layer SD3. That is, multiple data signal lines D are all located in the third routing metal layer SD3.

[0338] Multiple data signal groups D can be set in the third wiring metal layer SD3, which can not only prevent the problem of short circuit between the multiple signal groups D and the multiple conductive parts in the second metal wiring layer SD3, but also increase the flexibility of setting the multiple data signal groups D, which is beneficial to the wiring layout of the display substrate 100.

[0339] The third type: a portion of the data signal lines Data in a data signal group D is located in the second routing metal layer SD2 , and another portion of the data signal lines Data in the same data signal group D is located in the third routing metal layer SD3 .

[0340] The layered arrangement of multiple data signal lines Data not only increases the number of data signal lines Data, thereby increasing the refresh time of the pixel driver circuit, but also increases the flexibility of the arrangement of multiple data signal groups D, facilitating the wiring layout of the display substrate 100. Furthermore, the data signal lines Data located on the first wiring metal layer SD1 can be formed through a single patterning process along with other conductive portions of the first wiring metal layer SD1, simplifying the manufacturing process of the display substrate 100.

[0341] Take the case where the plurality of data signal lines Data in a data signal group D are all located in the third routing metal layer SD3. That is, the case where the plurality of data signal lines D are all located in the third routing metal layer SD3 is described as an example:

[0342] Since the plurality of data signal lines Data are all located in the third routing metal layer SD3, the number of data signal lines Data can be relatively increased. An example is given in which a data signal group D includes four data signal lines Data.

[0343] One data signal line group D includes four data signal lines Data extending along the column direction Y and arranged at intervals along the row direction X, and one column of pixel driving circuits Q is divided into four pixel driving circuit groups E.

[0344] The four data signal lines Data in a data signal line group D may be a first data signal line Data, a second data signal line Data, a third data signal line Data, and a fourth data signal line Data. The four pixel driving circuit groups E in a column of pixel driving circuits Q may be a first pixel driving circuit group E, a second pixel driving circuit group E, a third pixel driving circuit group E, and a fourth pixel driving circuit group E.

[0345] In this way, the first data signal line Data can be electrically connected to all pixel driving circuits Q in the first pixel driving circuit group E, the second data signal line Data can be electrically connected to all pixel driving circuits Q in the second pixel driving circuit group E, the third data signal line Data can be electrically connected to all pixel driving circuits Q in the third pixel driving circuit group E, and the fourth data signal line Data can be electrically connected to all pixel driving circuits Q in the four pixel driving circuit groups E.

[0346] Based on this, any one of the first, second, third, or fourth data signal lines Data is used to drive one pixel driver circuit group E. That is, one data signal line Data is used to drive part of the pixel driver circuits Q in a column of pixel driver circuits Q. This helps increase the refresh time of the pixel driver circuits Q, thereby increasing the threshold compensation time of the pixel driver circuits Q, improving the threshold compensation effect of the pixel driver circuits Q, and enhancing the display uniformity of the display substrate 100. Where F is the refresh rate of the display substrate 100, and H is the number of rows of pixel driver circuits Q in the display substrate 100.

[0347] In some examples, when the number of pixel driving circuits Q in the first pixel driving circuit group E, the second pixel driving circuit group E, the third pixel driving circuit group E, and the fourth pixel driving circuit group E is approximately equal, it is equivalent to dividing a column of pixel driving circuits Q into four equal parts. Based on this, the refresh time of the pixel driving circuit Q is approximately That is, the refresh time of the pixel driving circuit Q is the above refresh time The refresh time of the pixel driving circuit Q is increased by 4 times, and the refresh time of the pixel driving circuit Q is increased by 3 times, which can better improve the threshold compensation of the high pixel driving circuit Q, so as to better improve the display uniformity of the display substrate 100.

[0348] In some examples, a data signal line group D includes four data signal lines Data, which can be grouped in pairs, with two data signal lines Data located on one side of a column of pixel driving circuits Q electrically connected thereto, and the other two data signal lines Data located on the other side of the column of pixel driving circuits Q electrically connected thereto. Based on this, the spacing between the data signal lines Data can be increased to reduce the problem of crosstalk between them.

[0349] Exemplarily, the first data signal line Data is located between the third data signal line Data and a column of pixel driving circuits Q, and the fourth data signal line Data is located between the second data signal line Data and a column of pixel driving circuits Q. However, the embodiments of the present disclosure are not limited thereto.

[0350] It should be noted that when the driver circuit layer 20 includes the third routing metal layer SD3, the solutions described in the above embodiments are applicable regardless of whether the data signal line Data is located in the second routing metal layer SD2, the third routing metal layer SD3, or both. Due to the different film layer locations, additional conductive connection portions may be required to electrically connect the pixel driver circuit Q to the various signal lines. Therefore, this will not be further described here.

[0351] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display substrate, comprising: A substrate and a driving circuit layer located on the substrate; The driving circuit layer includes: a plurality of pixel driving circuits, the plurality of pixel driving circuits are arranged in a plurality of rows and columns, and one column of the pixel driving circuits is divided into n pixel driving circuit groups; A plurality of data signal line groups, one of the data signal line groups is electrically connected to a column of pixel driving circuits; the data signal line group comprises n data signal lines extending in the column direction and arranged at intervals in the row direction, and one of the data signal lines is electrically connected to all the pixel driving circuits in one of the pixel driving circuit groups; Two adjacent columns of pixel driving circuits are respectively an m-th column pixel driving circuit and an m+1-th column pixel driving circuit; the data signal line group electrically connected to the m-th column pixel driving circuit includes at least one first data signal line, and the first data signal line is located between the m-th column pixel driving circuit and the m+1-th column pixel driving circuit; and the data signal line group electrically connected to the m+1-th column pixel driving circuit includes at least one second data signal line, and the second data signal line is located between the m-th column pixel driving circuit and the m+1-th column pixel driving circuit; A plurality of anode adapter wires are electrically connected to the driving output terminals of the plurality of pixel driving circuits respectively; wherein the plurality of anode adapter wires electrically connected to the pixel driving circuit of the m+1th column include at least one first anode adapter wire, and the first anode adapter wire includes: a first anode adapter portion on the same layer as the data signal line; Along the row direction, the first anode transfer portion is located between the first data signal line electrically connected to the pixel driving circuit of the mth column and the second data signal line electrically connected to the pixel driving circuit of the m+1th column; Wherein, n is a positive integer greater than 2, and m is a positive integer.

2. The display substrate according to claim 1, further comprising: an anode layer, located on a side of the driving circuit layer away from the substrate; the anode layer comprises a plurality of anodes; The plurality of anodes include a first anode and a second anode, and along a column direction, the first anode and the second anode are alternately arranged; The first anode transition portion extends along the column direction, the orthographic projection of the first anode transition portion on the substrate overlaps with the orthographic projection of the first anode on the substrate, and the orthographic projection of the first anode transition portion on the substrate overlaps with the orthographic projection of the second anode on the substrate, and the first anode transition portion is electrically connected to the second anode.

3. The display substrate according to claim 2, wherein: Along the column direction, the orthographic projections of the first anode and the second anode on the substrate are located between the orthographic projections of two ends of the first anode transfer portion on the substrate.

4. The display substrate according to claim 2 or 3, wherein: The data signal line group electrically connected to the pixel driving circuit of the mth column includes at least one third data signal line, and the third data signal line is located on a side of the pixel driving circuit of the mth column away from the pixel of the pixel driving circuit of the m+1th column; The plurality of anode transfer lines electrically connected to the pixel driving circuit of the mth column include at least one second anode transfer line, wherein the second anode transfer line includes: a second anode transfer portion in the same layer as the data signal line; Along the row direction, the second anode switching portion is located at a side of the pixel driving circuit of the mth column away from the pixel of the pixel driving circuit of the (m+1)th column.

5. The display substrate according to claim 4, wherein: The second anode transition portion extends along the column direction, the orthographic projection of the second anode transition portion on the substrate overlaps with the orthographic projection of the first anode on the substrate, the second anode transition portion is electrically connected to the first anode, and the orthographic projection of the second anode transition portion on the substrate overlaps with the orthographic projection of the second anode on the substrate.

6. The display substrate according to claim 5, wherein: Along the column direction, the orthographic projections of the first anode and the second anode on the substrate are located between the orthographic projections of two ends of the second anode transfer portion on the substrate.

7. The display substrate according to any one of claims 2 to 6, wherein: The plurality of columns of pixel driving circuits further include an m+2th column of pixel driving circuits, and the m+2th column of pixel driving circuits is located on a side of the m+1th column of pixel driving circuits away from the mth column of pixel driving circuits; The data signal line group electrically connected to the pixel driving circuit of the m+1th column includes at least one fourth data signal line, and the fourth data signal line is located between the pixel driving circuit of the m+1th column and the pixel driving circuit of the m+2th column; the data signal line group electrically connected to the pixel driving circuit of the m+2th column includes at least one fifth data signal line, and the fifth data signal line is located between the pixel driving circuit of the m+1th column and the pixel driving circuit of the m+2th column; The plurality of anode transfer lines electrically connected to the pixel driving circuit of the m+2th column include a third anode transfer line, wherein the third anode transfer line includes: a third anode transfer portion in the same layer as the data signal line; Along the row direction, the third anode switching portion is located between the fourth data signal line electrically connected to the pixel driving circuit of the m+1th column and the fifth data signal line electrically connected to the pixel driving circuit of the m+2th column.

8. The display substrate according to claim 7, wherein: The plurality of anodes further include a third anode, and along the row direction, the third anode overlaps with the first anode, and the third anode overlaps with the second anode; The third anode transition portion extends along the column direction. Along the column direction, the boundary of the orthographic projection of the third anode transition portion on the substrate overlaps with the boundary of the orthographic projection of the third anode on the substrate. The third anode transition portion is electrically connected to the third anode.

9. The display substrate according to claim 8, wherein: Along the column direction, the orthographic projection of the third anode on the substrate is located between the orthographic projections of two ends of the third anode transfer portion on the substrate.

10. The display substrate according to any one of claims 1 to 9, wherein: In the same column of the pixel driving circuits, the number of the pixel driving circuits in each pixel driving circuit group is equal.

11. The display substrate according to any one of claims 1 to 10, wherein: The multiple data signal lines in one data signal line group are divided into a first part of data signal lines and a second part of data signal lines, the first part of data signal lines and the second part of data signal lines are respectively located on both sides of the pixel driving circuit, and the number of the data signal lines in the first part of data signal lines is equal to the number of the data signal lines in the second part of data signal lines.

12. The display substrate according to claim 11, wherein: The pixel driving circuit comprises: a driving transistor, a data writing transistor, a data switching part and a first light emitting control transistor, the first electrode of the driving transistor, the second electrode of the data writing transistor and the second electrode of the first light emitting control transistor are electrically connected, and the first electrode of the data writing transistor is electrically connected to the data signal line through the data switching part; Along the column direction, the data writing transistor is located on a side of the first light emission control transistor away from the driving transistor, and the first electrode of the data writing transistor is located on a side of the second electrode of the data writing transistor away from the data writing transistor.

13. The display substrate according to claim 12, wherein: The pixel driving circuit further includes a second light emission control transistor and a second reset transistor, wherein the second electrode of the second light emission control transistor is electrically connected to the second electrode of the second reset transistor; In the column direction, the second reset transistor is located on a side of the second light emission control transistor away from the driving transistor, and in the row direction, the second light emission control transistor is adjacent to the first light emission control transistor, and the second reset transistor is adjacent to the data writing transistor.

14. The display substrate according to claim 13, wherein: The pixel driving circuit in the same column includes: a first part of the pixel driving circuit electrically connected to the second part of the data signal lines, and a second part of the pixel driving circuit electrically connected to the first part of the data signal lines; The data writing transistor of the first part pixel driving circuit is located between the second reset transistor and the second part data signal line, and the data writing transistor of the second part pixel driving circuit is located on a side of the second reset transistor away from the first part data signal line; At least one of the pixel driving circuits in the second part of the pixel driving circuit includes a first data transfer part, which is electrically connected to the first electrode of the data writing transistor and the data signal line respectively; the first data transfer part includes a avoidance part, and the avoidance part is located on a side of the second reset transistor away from the second light-emitting control transistor.

15. The display substrate according to claim 14, wherein: The driving circuit layer also includes: A second initialization signal line includes a first connection portion, and a first electrode of the second reset transistor is electrically connected to the first connection portion of the second initialization signal line; Along the column direction, the second initialization signal line is located on a side of the second reset transistor away from the second light emission control transistor, and the avoidance portion is located on a side of the first connection portion away from the second light emission control transistor.

16. The display substrate according to claim 14 or 15, wherein: The driving circuit layer further includes a plurality of first power signal lines extending in the column direction and arranged in the row direction, and the first power signal lines are electrically connected to the pixel driving circuit; Along the row direction, the first part of the data signal lines and the second part of the data signal lines are respectively located on both sides of the first power signal line.

17. The display substrate according to any one of claims 16, wherein: The avoidance portion crosses over the first power signal line electrically connected to the second part pixel driving circuit.

18. The display substrate according to any one of claims 11 to 17, wherein: One of the data signal line groups includes two of the data signal lines; The driving circuit layer includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer and a second routing metal layer stacked on the substrate; two data signal lines in one data signal line group are both located in the second routing metal layer.

19. The display substrate according to any one of claims 11 to 17, wherein: One of the data signal line groups includes four data signal lines; The driving circuit layer also includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first routing metal layer, a second routing metal layer and a third routing metal layer stacked on the substrate; At least some of the data signal lines in the data signal line group are located in the second routing metal layer, and / or at least some of the data signal lines in the data signal line group are located in the third routing metal layer.

20. A display device comprising the display substrate according to any one of claims 1 to 19.

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