Built-in self-test circuit for MIV fault testing and MIV fault testing method

Abstract

The present invention discloses a built-in self-test (BIST) circuit and MIV fault testing method for MIV fault testing. The circuit is used to detect the MIV array to be tested between the bottom and top layers of a monolithic three-dimensional integrated circuit in a test mode. The circuit includes a test controller, an address decoding module, a vector generator, a data transmission device, a fault diagnosis module, and a fault location module. The vector generator is used to generate test vectors of length N, including 1 / 0 sequences, 0 / 1 sequences, 00 / 11 sequences, and 11 / 00 sequences. The present invention can detect open circuit faults, stuck-at faults, delayed faults, and possible short circuit faults in complexly distributed MIVs by rapidly switching between two sets of test vectors, and accurately locate the faulty MIV.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit testability design, in particular to a built-in self-test circuit for MIV fault testing and a MIV fault testing method. Background Art

[0002] With the continuous advancement of integrated circuit (IC) technology, three-dimensional (3D) integrated circuits (ICs) have become a highly promising approach to continuing Moore's Law. Various 2.5D (three-dimensional) integration technologies have been proposed, including through-silicon via (TSV)-based 3D integration, interposer-based 2.5D integration, chip-based 3D integration, and monolithic 3D (M3D) integration. These approaches achieve high-density vertical interconnects with diameters and pitches ranging from a few microns (chip / wafer stacking) to a few nanometers (monolithic integration).

[0003] Among these technologies, M3D integration achieves heterogeneous integration of multiple chips through high-density vertical interconnection of nano-scale interlayer vias, and its performance is better than that of traditional TSV-based three-dimensional integrated circuits. However, due to the high-density design of monolithic inter-tier vias (MIV) and the significant increase in the thickness of the interlayer dielectric ILD, MIV becomes more susceptible to electrostatic coupling and defects. Therefore, during the manufacturing process of M3D integrated circuits, MIV must be fault tested. Although MIV testing can be performed together with the logic layer or storage layer of M3D, in order to achieve defect isolation and improve yield, a special test solution needs to be developed based on the characteristics of MIV in M3D ICs to ensure the efficiency of defect screening and the reliability of product quality.

[0004] Currently, there are three main methods for fault testing of MIVs in monolithic three-dimensional integrated circuits. The first is based on row and column scanning, which uses tri-state gates to change the transmission direction of MIV signals. This allows testing of a large number of MIVs with minimal circuit logic overhead. However, due to the high density and large number of MIVs, this method poses significant challenges in circuit wiring and cannot accurately locate the specific MIV with a fault. The second method involves adding a dedicated test layer to test MIVs for faults. While this method reduces testing costs to a certain extent, the dedicated test layer can only test faults in the upper and lower layers of MIVs, resulting in significant circuit area overhead and difficulty in scaling to multiple layers. The third method involves fault testing of MIVs using built-in self-test (BIST) circuits. This method uses specialized circuits to significantly reduce the test circuit footprint and effectively cover common MIV faults. However, in current academic reports, scanning-based BIST circuits suffer from issues such as long test data transmission time and test cycles, while non-scanning BIST circuits cannot accurately locate the specific MIV with a fault. Summary of the Invention

[0005] Purpose of the invention: The purpose of the present invention is to provide a built-in self-test circuit and a MIV fault testing method for MIV fault testing, so as to solve the problems of long test time and insufficient fault location accuracy in the existing MIV fault testing.

[0006] Technical Solution: The built-in self-test circuit for MIV fault testing of the present invention is used to detect the MIV array to be tested between the bottom layer and the top layer of a monolithic three-dimensional integrated circuit in a test mode, wherein the size of the MIV array is M×N. The built-in self-test circuit includes:

[0007] The address decoding module is used to select a row of MIVs to be connected to the built-in self-test circuit according to the address count value, and move the test vector in the vector generator to the input port of the MIV in the row; after completing the fault test of the MIV in the row, the address count value is increased by 1 to select the next row of MIVs to be connected to the built-in self-test circuit;

[0008] A vector generator, used to generate test vectors of 1 / 0 sequence, 0 / 1 sequence, 00 / 11 sequence and 11 / 00 sequence with a length of N;

[0009] a data transfer device for inputting a test vector into the row of MIVs and moving the test response of the row of MIVs into the fault diagnosis module;

[0010] a fault diagnosis module, configured to detect whether a fault occurs in the MIV of the row according to the test response, and store the fault result in a test data register corresponding to each MIV;

[0011] The fault location module is used to identify the location of the faulty MIV according to the fault result.

[0012] Furthermore, the vector generator includes N cascaded first scan registers, the output end of each vector generation shift register is connected to the first input end of a first XOR gate, the second input end of the first XOR gate is connected to the vector hold flip signal XOR, the output end of the first XOR gate is connected to the third input end of a first AND gate, the fourth input end of the first AND gate is connected to the MIV array activation signal And, in the test mode, And=1, and the output end of the first AND gate is connected to the data transmission device;

[0013] For N cascaded first scanning registers, a first two-input selector is connected between the r+1th and r+2th first scanning registers and between the r+2th and r+3th first scanning registers, r is a non-negative integer multiple of 4, and the two input ends of the first two-input selector are respectively connected to the output and reverse output of the first scanning register.

[0014] Further, the control terminal input of the first two input selectors is Switch;

[0015] When Switch = 1 and XOR = 0, the vector generation shift register receives and shifts the test vector of the 1 / 0 sequence of length N from the TPG and stores it in the first scan register;

[0016] When Switch = 1 and XOR = 1, the vector shift register flips the test vector of the 1 / 0 sequence in the first scan register into a test vector of the 0 / 1 sequence;

[0017] When Switch = 0 and XOR = 0, the vector shift register receives and shifts a test vector "0" from the TPG, shifts the test vector of the 1 / 0 sequence in the first scan register, and obtains a test vector of the 00 / 11 sequence of length N;

[0018] When Switch = 0 and XOR = 1, the vector shift register flips the test vector of the 00 / 11 sequence in the first scan register into a test vector of the 11 / 00 sequence.

[0019] Furthermore, the data transmission device includes 2N test transmission tri-state gates, each MIV in the row is connected to a test transmission tri-state gate at both ends, and the MIV is connected to the vector generator and the fault diagnosis module through the test transmission tri-state gates at both ends.

[0020] Furthermore, the transmission direction of the test transmission tri-state gate is from bottom to top, the test transmission tri-state gate at the MIV input end is connected to the vector generator, and the test transmission tri-state gate at the MIV output end is connected to the fault diagnosis module.

[0021] Furthermore, the data transmission device also includes 2N functional transmission three-state gates. In the functional mode, for the uplink MIV, the transmission direction of the functional transmission three-state gate at its input end is from bottom to top and the input is the functional input, and the transmission direction of the functional transmission three-state gate at its output end is from bottom to top and the output is the functional output; for the downlink MIV, the transmission direction of the functional transmission three-state gate at its input end is from top to bottom and the output is the functional output, and the transmission direction of the functional transmission three-state gate at its output end is from top to bottom and the input is the functional input.

[0022] Furthermore, the fault diagnosis module includes: N test data registers of cascaded multiplexed scan chains, in each of the test data registers, a fifth input end of a second XOR gate is connected to a test response of the data transmission device, a sixth input end of the second XOR gate is connected to an output end of a second scan register, and an output end of the second XOR gate is connected to an input end of the second scan register;

[0023] The output end of the second scan register, ie, the output end of the test data register, is connected to the fault location module.

[0024] Furthermore, the fault diagnosis module also includes a second two-input selector, the two input ends of the second two-input selector are respectively connected to the output end of the previous level test data register and the output end of the second XOR gate, and the output end of the second two-input selector is connected to the input end of the second scan register; the second two-input selector is controlled by the MT signal, and when MT=0, the test data register is connected to the output end of the second XOR gate.

[0025] Furthermore, the fault location module includes a priority encoder, a decoder, N first-level D flip-flops and N third-second input selectors;

[0026] The seventh input terminals of the N third two-input selectors are respectively connected to the output terminals of the N test data registers, and the eighth input terminals of the N third two-input selectors are connected to a high level "1";

[0027] The output end of the third second input selector is connected to the priority encoder, which compresses its output into an n-bit SYM signal and generates a fault identification signal Fb to the test controller. n is 2 n ≥N minimum integer value; the decoder DEC reads and decodes the SYM signal, and its decoding output is connected to the D end of N first-level D flip-flops, and the Q ends of the N first-level D flip-flops are respectively used as control ends of N third-second input selectors, which are used to shield the MIV with faults; the fault identification signal Fb is regenerated according to the output of the shielded third-second input selector, until the fault identification signal Fb is a no-fault signal "0", the first-level D flip-flop is reset to complete the fault test of the MIV in this row.

[0028] The MIV fault testing method of the present invention comprises the following steps:

[0029] Connecting the MIV array to be tested between the bottom layer and the top layer of the monolithic three-dimensional integrated circuit to the built-in self-test circuit, wherein the size of the MIV array is M×N;

[0030] The address decoding module selects a row of MIVs to be connected to the built-in self-test circuit based on the address count value, and moves the test vector in the vector generator into the input port of the MIV in the row. After completing the fault test of the MIV in the row, the address count value is increased by 1 to select the next row of MIVs to be connected to the built-in self-test circuit.

[0031] Use a vector generator to generate test vectors of length N, including 1 / 0 sequence, 0 / 1 sequence, 00 / 11 sequence, and 11 / 00 sequence;

[0032] Inputting the test vector into the row MIV using the data transfer device, and moving the test response of the row MIV into the fault diagnosis module;

[0033] Using the fault diagnosis module, detect whether the MIV in the row has a fault according to the test response, and store the fault result in the test data register corresponding to each MIV;

[0034] The fault location module is used to identify the location of the faulty MIV according to the fault result.

[0035] Beneficial Effects: Compared with the prior art, the advantages of the present invention are: (1) The present invention can effectively detect four common faults of ILVs, namely open circuit, short circuit, fixed circuit, and conversion delay, and can accurately locate the above faults; for short circuit faults, it can not only test the short circuit between adjacent MIVs arranged in one dimension, but also be extended to large designs with 2-D arrays or irregular MIV layouts. (2) The test cycle is short, and only one test data shift input is required to complete the test of all MIV rows to be tested, and a second set of test vectors can be converted by shifting one bit of the vector. After two consecutive test cycles, the sequence of 10 is applied to each MIV to be tested, that is, each MIV to be tested first transmits the vector "1" and then transmits the vector "0". BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 FIG. 4 is a diagram of a built-in self-test circuit for a 5×4 MIV array according to an embodiment of the present invention.

[0037] Figure 2 Schematic diagram of the test controller structure in an embodiment of the present invention.

[0038] Figure 3 Schematic diagram of the data sending end of the address decoding module in an embodiment of the present invention.

[0039] Figure 4 Schematic diagram of the data receiving end of the address decoding module in an embodiment of the present invention.

[0040] Figure 5 1 is a circuit diagram of a vector generating shift register in an embodiment of the present invention.

[0041] Figure 6 4 is a circuit diagram of a test data register in a fault diagnosis module according to an embodiment of the present invention.

[0042] Figure 7 This is a flow chart of the MIV fault testing method in an embodiment of the present invention.

[0043] Figure 8 Schematic diagram of test state transition during the test process in an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The built-in self-test circuit for MIV fault testing of the present invention is used to detect M×N groups of MIV arrays to be tested between the bottom layer and the top layer of a monolithic three-dimensional integrated circuit. The built-in self-test circuit includes: a test controller (Test Control), a pattern generator (Pattern Launch), a data transmission device (Data Transmission), a fault diagnosis module (Fault Diagnosis), and a fault localization module (Fault Localization);

[0045] The test controller includes an address decoding module (Decoding Module), an address counter (AddressCounter) and a finite state machine (FSM), which are used to generate address count values and various control signals.

[0046] The vector generator includes N vector generation shift registers with multiplexed scan chains, N first AND gates, and N first XOR gates. Each vector generation shift register includes a first scan register, which consists of a two-input selector Scan Mux and a D flip-flop. Between the r+1 and r+2 first scan registers, and between the r+2 and r+3 first scan registers (where r is a non-negative integer multiple of 4), there is also a vector switching device, which consists of a two-input selector Switch Mux and a NOT gate. For the vector generation shift register, the two-input selector in the scan register is controlled by the TE signal to select the output. The "1" terminal of the selector is connected to the vector input of the TPG, the output of the vector switching device, or the Q terminal of the D flip-flop in the previous scan register, and the "0" terminal is connected to the functional input port FI. The output terminal is connected to the D terminal of the D flip-flop in the scan register. The two-input selector switch mux of the vector switching device is controlled by the Switch signal to select an output. Its "1" terminal is connected to the Q terminal output of the D flip-flop in the r+1st or r+2nd scan register, and its "0" terminal is connected to the inverted output of the Q terminal of the D flip-flop in the r+1st or r+2nd scan register. The output terminal is connected to the D terminal of the D flip-flop in the r+2nd or r+3rd scan register. For the N first XOR gates in the vector generator, one terminal is connected to the Q terminal of the D flip-flop in each scan register, and the other terminal is connected to the send vector hold flip signal XOR. For the N AND gates, one terminal is connected to the output of the N XOR gates, and the other terminal is connected to the MIV array activation signal And. This vector generator can generate two sets of test vectors for detecting possible fault types: a 1 / 0 sequence test vector and a 00 / 11 sequence test vector (i.e., 10 followed by 10 and 0011 followed by 0011), with a sequence length of N.

[0047] The data transmission device includes 2N test transmission tri-state gates and 2N functional transmission tri-state gates, and both ends of the N MIVs in the row are connected to a test transmission tri-state gate and a functional transmission tri-state gate; for each MIV, the transmission direction of its test transmission tri-state gate is from bottom to top, and the input of the test transmission tri-state gate at the input end of the MIV comes from the first AND gate in the vector generator, and the output of the test transmission tri-state gate at the output end of the MIV is connected to one end of the XOR gate in the fault diagnosis module; for the upstream MIV, the transmission direction of the functional transmission tri-state gate at its input end is from bottom to top and the input is the functional input, and the transmission direction of the functional transmission tri-state gate at the output end is from bottom to top and the output is the functional output; for the downstream MIV, the transmission direction of the functional transmission tri-state gate at its input end is from top to bottom and the output is the functional output, and the transmission direction of the functional transmission tri-state gate at the output end is from top to bottom and the input is the functional input.

[0048] The fault diagnosis module includes N test data registers of multiplexed scan chains, wherein the test data register of each multiplexed scan chain consists of a second XOR gate, a two-input selector Test Mux and a second scan register; in the test data register of the multiplexed scan chain, the input of the second XOR gate comes from the output of the test transfer tri-state gate at the output end of the MIV and the Q-end signal value of the D flip-flop in the second scan register, and the output of the second XOR gate is connected to the "0" end of the two-input selector Test Mux; the "1" end of the two-input selector Test Mux is connected to the Q end of the scan register of the previous level, and the output is controlled by the MT signal and connected to the "1" end of the two-input selector Scan Mux in the second scan register of this level.

[0049] The fault location module includes a priority encoder ENC, a decoder DEC, N first-level D flip-flops and N two-input selectors Mux; the "1" end of the two-input selector Mux is connected to the high level value "1", and the "0" end is connected to the Q end of the D flip-flop in the scan register of the fault diagnosis module. The output of the two-input selector is connected to the priority encoder ENC; the priority encoder ENC encodes the output information of the two-input selector into an n-bit SYM signal (n is 2 n ≥N minimum integer value) and generates a fault identification signal Fb to the test controller; the decoder DEC reads and decodes the SYM signal, and its decoding output is connected to the D end of N first-level D flip-flops; the Q ends of the N first-level D flip-flops are respectively connected to the control ends of N two-input selectors in the fault location module.

[0050] The technical solution of the present invention will be further described below with reference to the accompanying drawings. Figure 1 Shown is the test circuit diagram of a 5×4 MIV array.

[0051] like Figure 2Figure 1 shows the structure of the test controller for the built-in self-test circuit. The test controller includes two mandatory terminals: the test enable signal EN and the dedicated test clock TCK. EN and TCK enter the finite state machine (FSM) to generate various control signals. These control signals include dedicated signals such as the clock pulse signals Clk1, Clk2, and Clk3; the vector generation signal Shift; the test vector switching signal Switch; the transmit vector hold flip signal XOR; the MIV array activation signal And; and the switching signals for the tri-state gates in the data transfer device. The test controller also controls the address counter to generate address count values. The scan enable signal TE and the reset signal Rst are also common signals.

[0052] Figure 3 、 Figure 4 The figure shows the structure of the address decoding module in the built-in self-test circuit of the 5×4 MIV array. Figure 3 The schematic diagram of the data sending end of the address decoding module in the test circuit of the present invention includes an address decoder and two-way selectors M1~M 20 ; Figure 4 The schematic diagram of the data receiving end of the address decoding module in the test circuit of the present invention includes an address decoder and three-state gates T1~T 20 The MIVs in the same column are connected to the same vector generator and fault diagnosis module. The finite state machine (FSM) controls the address counter (Address Counter) to generate an address count value, which is sent to the address decoder. Assuming the address count value is "0", the address 0 row is decoded and activated, and the four MIVs to be tested (MIV1 to MIV4) connected to this row are connected to the test circuit. At the data transmitting end, the two-input selectors M1 to M4 control terminals at the input terminals of MIV1 to MIV4 are decoded as "1", thereby selecting the test vector from the vector generator and entering MIV1 to MIV4 from the input ports IN1 to IN4 of MIV1 to MIV4. At the same time, at the data receiving end, the three-state gate control terminals at the output terminals of MIV1 to MIV4 are also decoded as "1", allowing the test vector to enter the fault diagnosis module from the output ports OUT1 to OUT4 of MIV1 to MIV4. When the test of a group of MIVs is completed, the finite state machine (FSM) controls the address counter (Address Counter) to generate a new address count value to activate a new group of MIVs to be tested.

[0053] like Figure 1As shown, a row of four MIVs is connected to a test transmission tri-state gate (i.e., a tri-state gate controlled by the UP signal) and a functional transmission tri-state gate (i.e., a tri-state gate controlled by the EN signal). When the built-in self-test circuit's test controller receives the test enable signal "EN = 1," the FSM generates control signals for the test transmission tri-state gate and the functional transmission tri-state gate. For each MIV under test, "UP = 1" activates the test transmission path and disables the functional transmission path. The data transmission direction of both the upstream and downstream MIVs, which were originally in functional mode, changes to bottom-to-top transmission. FI represents the data input in functional mode, and FO represents the data output in functional mode.

[0054] like Figure 1 As shown, the vector generator consists of four vector generation shift registers (with D flip-flops inputs D1, D2, D3, and D4, and outputs Q1, Q2, Q3, and Q4, using the clock signal Clk1), four first-order AND gates AND1, AND2, AND3, and AND4, and four first-order XOR gates X1, X2, X3, and X4. The vector generation shift registers contain D flip-flops D1 through D4, and vector switching devices are connected between the first and second scan registers, and between the second and third scan registers. For a 5×4 MIV array, the vector generator generates two sets of test vectors: 1010 and 0011. In each test cycle, the test vectors are flipped to 0101 and 1100.

[0055] like Figure 5 The figure shows the circuit diagram of a vector generator shift register. In test mode, the TE signal is set to "1." To generate the first set of test vectors, the FSM controls the Switch signal to "1." The test vector "1010" is input into registers D1, D2, D3, and D4 via the TPG, driven by clock Clk1. To generate the second set of test vectors, the FSM controls the Switch signal to "0." With the test data in registers D1, D2, D3, and D4 set to "1010," the 1-bit vector "0" is shifted in via the TPG, transforming the test data in registers D1, D2, D3, and D4 to "0011."

[0056] from Figure 1Looking at the overall test circuit structure, when the Switch signal is "1," the TPG, driven by clock Clk1, shifts the input registers D1, D2, D3, and D4 into a test vector of "1010." If the XOR signal is 0, the gate inputs of XOR gates X1, X2, X3, and X4 are set to 0, maintaining the "1010" data and transmitting it to the fault diagnosis module via the MIV under test. In the next test cycle, when the XOR signal is 1, the gate inputs of X1, X2, X3, and X4 are set to 1, flipping the original test vector "1010" to generate the next sequence, "0101." During a single test cycle, 1010 (or 0101) passes through each MIV under test. Therefore, after two consecutive test cycles, a 1 / 0 sequence is applied to each MIV under test, meaning that each MIV under test first transmits a "1" vector and then a "0" vector.

[0057] After applying the first set of test vectors, registers D1, D2, D3, and D4 still hold the data value "1010." The FSM generates a clock pulse signal, Clk1, and sends it to the D flip-flop in the vector transmitter. Simultaneously, the test vector switching signal, Switch, is set to "0." The TPG inputs a single bit of "0" into the vector generator shift register, shifting the vector generator shift register by only one bit. The test data in registers D1, D2, D3, and D4 then changes to "0011." "0011" is maintained or flipped through XOR gates X1, X2, X3, and X4 in the same manner as described above. In one test cycle, "0011" is applied to the MIV under test, while in the second test cycle, "1100" is applied to the MIV under test. Therefore, after two consecutive test cycles, the 00 / 11 sequence will be applied to each MIV under test.

[0058] like Figure 1 As shown in Figure 1, the fault diagnosis module includes four test data registers, including XOR gates X5, X6, X7, and X8, a scan register (where the D flip-flop inputs are D5, D6, D7, and D8, the outputs are Q5, Q6, Q7, and Q8, and the clock signal is Clk2), and the control signal of the two-input selector Test Mux is MT. Figure 6The figure shows a circuit diagram of a test data register, which receives and stores test responses from the MIV. When TE is "0," register D0 receives functional data; when TE is "1," register D5 receives test data. When TE is "1," if the MT signal is "1," test data register D5 receives input from the previous scan stage. If the MT signal is "0," test data register D5 receives input from the MIV under test. Therefore, in the MIV test state, the finite state machine controls TE to "1" and MT to "0." In the first set of test vectors, each MIV under test first transmits a vector "1" followed by a vector "0." The first transmitted vector "1" is XORed with the previous state of the test data register Q5 (reset to "0") at XOR gate X5, with the result "1" stored in test data register D5. In the next cycle, vector "0" is transmitted through the MIV to one end of XOR gate X5 and XORed with the previous state of the test data register Q5 (now "1"), with the result "1" stored in test data register D5. This is the case when the MIV under test is fault-free, and test vectors "1" or "0" can be transmitted normally through the MIV under test. If the data value in test data register D5 is set to 0 after two cycles, it indicates that the MIV under test is defective, and the data value is sent to the fault location module.

[0059] like Figure 1 As shown, the fault location module includes four two-input selectors Mux1, Mux2, Mux3, and Mux4, whose control signals are S3, S2, S1, and S0, respectively, which are the first-level D flip-flops D9 and D 10 、D 11 、D 12 The output signal of the priority encoder is the SYM[1:0] signal, which is sent to the decoder. The truth table of the encoder is shown in Table 1, and the truth table of the decoder is shown in Table 2.

[0060] Table 1 Encoder truth table

[0061]

[0062] Table 2 Decoder truth table

[0063]

[0064] like Figure 7 As shown, the MIV fault testing method of the present invention includes the following steps, wherein the test state transition during the test is as follows: Figure 8 shown.

[0065] Step 1. Define the variable Group and initialize Group = 0. In functional mode, the finite state machine (FSM) receives the external test enable signal "EN = 1" to set the built-in self-test circuit to test mode. The FSM enters the "Run-Test / Idle" state and generates the test transmission tri-state gate and functional transmission tri-state gate control signals, namely UP and EN. For each MIV to be tested, "UP = 1" is set, enabling the test transmission path and disabling the functional transmission path. Data for both the uplink and downlink MIVs is transmitted in the same direction.

[0066] Step 2: When the TE signal is asserted, the built-in self-test circuit enters the "Deactivate-ILV" state. In this state, the MIV array activation signal And ensures that the AND gate (And1, And2, And3, And4) inputs are set to "0"; this decouples the MIV array from the vector shift register.

[0067] Step 3: To generate and shift the test vector, the FSM moves to the "Shift-TPG" state to prepare for shifting the test vector "1010." The finite state machine (FSM) sets the vector shift signal (Switch) to 0 and generates a clock pulse signal (Clk1) that is sent to the D flip-flops (D1, D2, D3, and D4) in the vector generator until the Shift signal is pulled low.

[0068] Step 4: After moving the test vector, the decoder enables the row to be tested according to the address in the FSM in the "Generate-ADD" state, and the finite state machine FSM generates an address count value "0" and transmits it to the address decoder, so that the address decoder selects the first MIV group to be tested according to the address count value.

[0069] Step 5: Determine whether the current address count value is the same as the MIV group number M. If they are the same, it means that the test of all rows has been completed. Execute step 15 and set Group = Group + 1; if the test of all rows has not been completed, execute step 6.

[0070] Step 6. The FSM will move to the “Reset” state and reset all D flip-flops in the second scan register in the fault diagnosis module to “0” to capture the test results.

[0071] Step 7. After resetting all D flip-flops in the second scan register, the built-in self-test circuit enters the "XOR-0" state, and the finite state machine FSM generates a vector hold flip control signal XOR, setting the gate input of the XOR gate (X1, X2, X3, X4) in the vector generator to "0". The test data "1010" of the XOR gate (X1, X2, X3, X4) is transmitted to the AND gate to maintain the original data state value.

[0072] Step 8. The FSM moves to the "Activate-ILV" state and generates the MIV array activation signal And, sets the input of the AND gates (And1, And2, And3, And4) to 1, and transmits the test data to the input of the MIV group to be tested (e.g. Figure 3 as shown, for example, IN1 to IN4).

[0073] Step 9: The test vector is transmitted to the next layer, Die2, via the MIV in the selected row of Die1, the bottom layer of the chip. The built-in self-test circuit enters the "Update" state, and the finite state machine (FSM) generates a clock pulse signal, Clk2, which is sent to the D flip-flops (D5, D6, D7, D8) in the fault diagnosis module. The test data arriving from the corresponding MIV is XORed with the previous state data value (Q5, Q6, Q7, Q8), and the result is stored in the corresponding D flip-flop (D5, D6, D7, D8).

[0074] Step 10: The built-in self-test circuit enters the "XOR-1" state. The finite state machine (FSM) generates a vector hold flip control signal, XOR, setting the gate inputs of the XOR gates (X1, X2, X3, and X4) in the vector generator to 1. At this point, the test data input to the AND gates (And1, And2, And3, and And4) is flipped to "0101." After the flipped test data from step 7 is transmitted to the fault diagnosis module via the MIV group under test, it is XORed with the previous state contents (Q5, Q6, Q7, and Q8) in the D flip-flops, updating the data latched in the D flip-flops (D5, D6, D7, and D8).

[0075] Step 11: The FSM sets the control terminals of the four two-input selectors (Mux1, Mux2, Mux3, and Mux4) in the fault location module to "0" to read the fault data. For a 5×4 MIV array, the priority encoder compresses the four bits of fault data into a 2-bit fault location signal (SYM), which indicates the location of the "0" in the fault data and generates a fault identification signal Fb. If the fault identification signal Fb is "1," indicating a fault, proceed to step 12; if the fault identification signal Fb is "0," indicating no fault, proceed to step 13.

[0076] Step 12: The built-in self-test circuit enters the "Location" state, and the finite state machine FSM generates a clock pulse signal Clk3 and sends it to the first-level D flip-flop (D9, D 10 、D 11 、D 12), at the same time, the priority encoder sends the MIV fault position signal SYM to the decoder for decoding, and generates the corresponding fault MIV position shielding signal (S3, S2, S1, S0) and then sends it to the first-level D trigger (D9, D 10 、D 11 、D 12 ), so that the first-level D flip-flop (D9, D 10 、D 11 、D 12 ) transmits the fault MIV position shielding signal to the control end (S3, S2, S1, S0) of the two-input selector in the fault location module, so that the located fault MIV is shielded by the two-way input selector (Mux1, Mux2, Mux3, Mux4), and the shielding result is fed back to the priority encoder ENC. The encoder uses the shielding result as the input signal to regenerate the fault identification signal Fb until the fault identification signal Fb is a no-fault signal "0", and executes step 13.

[0077] like Figure 6 As shown, it is assumed that the fault data information output by the fault diagnosis module is "0110", indicating that the first MIV (from left to right) and the third MIV (from left to right) in the current test MIV group have fault problems; the priority encoder reads the fault data information and generates a fault location signal SYM "11" and a fault identification signal Fb "1"; the finite state machine FSM generates a clock pulse signal Clk3 and sends it to the first-level D flip-flop (D9, D 10 、D 11 、D 12 ); The decoder generates a fault MIV position masking signal "1000" according to the fault location signal "11" and sends it to the control end (S3, S2, S1, S0) of the two-input selector in the fault location module; the encoder uses the masking result "1110" as the input signal to regenerate the fault identification signal Fb "1", and the fault location signal becomes "00"; the finite state machine FSM generates a clock pulse signal Clk3 again and sends it to the first-level D flip-flop (D9, D 10 、D 11 、D 12 ); The decoder generates a fault MIV position masking signal "1111" based on the fault location signal "00" and sends it to the control end (S3, S2, S1, S0) of the two input selectors in the fault location module; the encoder uses the masking result "1111" as the input signal to regenerate the fault identification signal Fb "0", ending the fault location identification.

[0078] Step 13, the finite state machine FSM enters the "Deactivate-ILV" state, controls the MIV array activation signal and the Reset signal, separates the MIV array and the vector shift register again, and resets the first-level D flip-flop (D9, D 10 、D 11 、D 12 ).

[0079] Step 14: The finite state machine FSM enters the "Generate-ADD" state, updates the address count value, changes the address of the row being tested, and repeats steps 5 to 14 until all rows are tested.

[0080] Step 15: If Group = 2, proceed to step 16. Otherwise, the finite state machine (FSM) enters the "Shift-TPG" state, generating a clock pulse signal (Clk1) and sending it to the D flip-flops (D1, D2, D3, and D4) in the vector transmitter. Simultaneously, the test vector switch signal (Switch) is set to "0," and the TPG sends a 1-bit "0" to the vector transmitter shift register. The test vector is shifted by only one bit through the shift register, resulting in a new test vector of "0011." Repeat steps 4 through 14 until all rows have been tested.

[0081] Step 16: Feedback is sent to the FSM and a test completion signal is generated, indicating that all MIV groups to be tested have been tested and the test device returns to the functional mode.

Claims

1. A built-in self-test circuit for MIV fault testing, characterized in that: Used to detect the MIV array to be tested between the bottom layer and the top layer of a monolithic three-dimensional integrated circuit in a test mode, wherein the size of the MIV array is M×N; the built-in self-test circuit includes: The address decoding module is used to select a row of MIVs to be connected to the built-in self-test circuit according to the address count value, and move the test vector in the vector generator to the input port of the MIV in the row; after completing the fault test of the MIV in the row, the address count value is increased by 1 to select the next row of MIVs to be connected to the built-in self-test circuit; A vector generator, used to generate test vectors of 1 / 0 sequence, 0 / 1 sequence, 00 / 11 sequence and 11 / 00 sequence with a length of N; a data transfer device for inputting a test vector into the row of MIVs and moving the test response of the row of MIVs into the fault diagnosis module; a fault diagnosis module, configured to detect whether a fault occurs in the MIV of the row according to the test response, and store the fault result in a test data register corresponding to each MIV; The fault location module is used to identify the location of the faulty MIV according to the fault result.

2. The built-in self-test circuit for MIV fault testing according to claim 1, wherein: The vector generator includes N cascaded first scan registers, the output end of each vector generation shift register is connected to the first input end of a first XOR gate, the second input end of the first XOR gate is connected to the vector hold flip signal XOR, the output end of the first XOR gate is connected to the third input end of a first AND gate, the fourth input end of the first AND gate is connected to the MIV array activation signal And, in the test mode, And=1, and the output end of the first AND gate is connected to the data transmission device; For N cascaded first scanning registers, a first two-input selector is connected between the r+1th and r+2th first scanning registers and between the r+2th and r+3th first scanning registers, r is a non-negative integer multiple of 4, and the two input ends of the first two-input selector are respectively connected to the output and reverse output of the first scanning register.

3. The built-in self-test circuit for MIV fault testing according to claim 2, characterized in that: The control input of the first and second input selectors is Switch; When Switch = 1 and XOR = 0, the vector generation shift register receives and shifts the test vector of the 1 / 0 sequence of length N from the TPG and stores it in the first scan register; When Switch = 1 and XOR = 1, the vector shift register flips the test vector of the 1 / 0 sequence in the first scan register into a test vector of the 0 / 1 sequence; When Switch = 0 and XOR = 0, the vector shift register receives and shifts a test vector "0" from the TPG, shifts the test vector of the 1 / 0 sequence in the first scan register, and obtains a test vector of the 00 / 11 sequence of length N; When Switch = 0 and XOR = 1, the vector shift register flips the test vector of the 00 / 11 sequence in the first scan register into a test vector of the 11 / 00 sequence.

4. The built-in self-test circuit for MIV fault testing according to claim 1, wherein: The data transmission device includes 2N test transmission tri-state gates. Each MIV in the row is connected to a test transmission tri-state gate at both ends. The MIV is connected to the vector generator and the fault diagnosis module through the test transmission tri-state gates at both ends.

5. The built-in self-test circuit for MIV fault testing according to claim 4, characterized in that: The transmission direction of the test transmission tri-state gate is from bottom to top. The test transmission tri-state gate at the input end of the MIV is connected to the vector generator, and the test transmission tri-state gate at the output end of the MIV is connected to the fault diagnosis module.

6. The built-in self-test circuit for MIV fault testing according to claim 4, characterized in that: The data transmission device also includes 2N functional transmission three-state gates. In the functional mode, for the uplink MIV, the transmission direction of the functional transmission three-state gate at its input end is from bottom to top and the input is the functional input, and the transmission direction of the functional transmission three-state gate at its output end is from bottom to top and the output is the functional output; for the downlink MIV, the transmission direction of the functional transmission three-state gate at its input end is from top to bottom and the output is the functional output, and the transmission direction of the functional transmission three-state gate at its output end is from top to bottom and the input is the functional input.

7. The built-in self-test circuit for MIV fault testing according to claim 1, wherein: The fault diagnosis module includes: N test data registers of cascaded multiplexed scan chains, in each of the test data registers, a fifth input end of a second XOR gate is connected to a test response of the data transmission device, a sixth input end of the second XOR gate is connected to an output end of a second scan register, and an output end of the second XOR gate is connected to an input end of the second scan register; The output end of the second scan register, ie, the output end of the test data register, is connected to the fault location module.

8. The built-in self-test circuit for MIV fault testing according to claim 7, wherein: The fault diagnosis module also includes a second two-input selector, the two input ends of the second two-input selector are respectively connected to the output end of the previous level test data register and the output end of the second XOR gate, and the output end of the second two-input selector is connected to the input end of the second scan register; the second two-input selector is controlled by the MT signal, and when MT=0, the test data register is connected to the output end of the second XOR gate.

9. The built-in self-test circuit for MIV fault testing according to claim 1, wherein: The fault location module includes a priority encoder, a decoder, N first-level D flip-flops and N third-second input selectors; The seventh input terminals of the N third two-input selectors are respectively connected to the output terminals of the N test data registers, and the eighth input terminals of the N third two-input selectors are connected to a high level "1"; The output end of the third second input selector is connected to the priority encoder, which compresses its output into an n-bit SYM signal and generates a fault identification signal Fb to the test controller. n is 2 n ≥N minimum integer value; the decoder DEC reads and decodes the SYM signal, and its decoding output is connected to the D end of N first-level D flip-flops, and the Q ends of the N first-level D flip-flops are respectively used as control ends of N third-second input selectors, which are used to shield the MIV with fault; the fault identification signal Fb is regenerated according to the output of the shielded third-second input selector, until the fault identification signal Fb is a no-fault signal "0", the first-level D flip-flop is reset to complete the fault test of the MIV in this row.

10. A MIV fault testing method based on the built-in self-test circuit according to any one of claims 1 to 9, characterized in that: The steps include: Connecting the MIV array to be tested between the bottom layer and the top layer of the monolithic three-dimensional integrated circuit to the built-in self-test circuit, wherein the size of the MIV array is M×N; The address decoding module selects a row of MIVs to be connected to the built-in self-test circuit based on the address count value, and moves the test vector in the vector generator into the input port of the MIV in the row. After completing the fault test of the MIV in the row, the address count value is increased by 1 to select the next row of MIVs to be connected to the built-in self-test circuit. Use a vector generator to generate test vectors of length N, including 1 / 0 sequence, 0 / 1 sequence, 00 / 11 sequence, and 11 / 00 sequence; Inputting the test vector into the row MIV using the data transfer device, and moving the test response of the row MIV into the fault diagnosis module; Using the fault diagnosis module, detect whether the MIV in the row has a fault according to the test response, and store the fault result in the test data register corresponding to each MIV; The fault location module is used to identify the location of the faulty MIV according to the fault result.

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