Binary translation method and device, electronic equipment and readable storage medium

Abstract

The embodiment of the invention provides a binary translation method and device, electronic equipment and a readable storage medium. The method comprises the following steps: aiming at any translated host machine instruction unit, combining a preset mark with a basic block pointer of the host machine instruction unit to obtain a combined body, and inserting the combined body into a preset position in the host machine instruction unit; and in response to a search operation for any basic block pointer, based on a search address indicated by the search operation and the preset mark, obtaining a combination corresponding to the search address as a target combination, and determining the basic block pointer contained in the target combination as a target basic block pointer corresponding to the search operation. And the binary translation performance is ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a binary translation method, device, electronic device and readable storage medium. Background Art

[0002] In the field of computer technology, binary translation technology is usually used, that is, a translator translates client instructions into host instructions, so that a program compiled for one instruction set architecture (ISA) can also run on a hardware platform of another instruction set architecture.

[0003] Currently, translated host instructions are often stored in memory for multiple executions. In some cases, there is a need to find the corresponding basic block pointer according to the translated host instructions (for example, self-modification scenarios). In related technologies, the interval tree algorithm is usually used for search. However, the processing time of the interval tree algorithm increases logarithmically with the increase of data volume, and its complexity is O (logn), which has a high time cost. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a binary translation method, device, electronic device and readable storage medium to solve the problem of high time cost of basic block pointer search. The specific technical solution is as follows: In a first aspect of the present invention, a binary translation method is first provided, the method comprising: For any translated host machine instruction unit, combining a preset mark with a basic block pointer of the host machine instruction unit to obtain a combination, and inserting the combination into a preset position in the host machine instruction unit; In response to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, the assembly corresponding to the search address is obtained as the target assembly, and the basic block pointer contained in the target assembly is determined as the target basic block pointer corresponding to the search operation.

[0005] In a second aspect of the present invention, a binary translation device is provided, the device comprising: A combining module, for combining a preset mark with a basic block pointer of any translated host machine instruction unit to obtain a combination, and inserting the combination into a preset position in the host machine instruction unit; The first acquisition module is used to respond to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, obtain the assembly corresponding to the search address as a target assembly, and determine the basic block pointer contained in the target assembly as the target basic block pointer corresponding to the search operation.

[0006] In a third aspect of the present invention, there is also provided an electronic device, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; The processor is used to implement the method described in the first aspect when executing the program stored in the memory.

[0007] In a fourth aspect of the implementation of the present invention, a computer-readable storage medium is further provided, wherein the computer-readable storage medium stores instructions, which, when executed on a computer, enable the computer to execute the method described in the first aspect above.

[0008] In a fifth aspect of the implementation of the present invention, there is also provided a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute the method described in the first aspect above.

[0009] The binary translation method provided by the embodiment of the present invention combines a preset mark and a basic block pointer and directly inserts the assembly into a preset position in the host machine instruction unit, so that the basic block pointer can be embedded into the host machine instruction unit through the assembly, so that when there is a need to search for a basic block pointer, the target assembly corresponding to the search address can be determined through the preset mark, so that the target basic block pointer corresponding to the search operation can be determined through the target assembly. The embodiment of the present invention can realize the search of the basic block pointer only through the combination of the preset mark and the basic block pointer, with low time cost, and ensures the performance of binary translation. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0011] Figure 1 is a flowchart of a binary translation method in an embodiment of the present invention; Figure 2 It is a flowchart of binary translation provided by an embodiment of the present invention; Figure 3 It is a structural schematic diagram of a combination provided by an embodiment of the present invention; Figure 4is a schematic diagram of an insertion position of a combination provided by an embodiment of the present invention; Figure 5 is a schematic diagram of a host machine instruction unit in an embodiment of the present invention; Figure 6 is a structural schematic diagram of a binary translation device in an embodiment of the present invention; Figure 7 Schematic diagram of an electronic device in an embodiment of the present invention. DETAILED DESCRIPTION

[0012] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0013] The terms "first", "second", etc. in the specification and claims of the present invention are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable when appropriate, so that the embodiments of the present invention can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first", "second", etc. are generally of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, the term "and / or" in the specification and claims is used to describe the association relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present invention, the term "multiple" refers to two or more, and other quantifiers are similar.

[0014] Figure 1 FIG. 1 is a flowchart of a binary translation method according to an embodiment of the present invention. Figure 1 As shown, the method includes: Step 101: for any translated host machine instruction unit, combine a preset mark with a basic block pointer of the host machine instruction unit to obtain a combination, and insert the combination into a preset position in the host machine instruction unit.

[0015] Step 102, in response to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, obtain the assembly corresponding to the search address as the target assembly, and determine the basic block pointer contained in the target assembly as the target basic block pointer corresponding to the search operation.

[0016] For the above steps 101~102, the embodiment of the present invention can be applied to any translator (also referred to as a binary translator). Specifically, the binary translation technology can realize the function of making executable files compatible across ISAs, and can migrate the software ecology of the mature processor (Central Processing Unit, CPU) architecture to the new CPU architecture. Among them, the translator is used to translate the source program A in the client (GUEST) into the target program B in the host (HOST), and execute the target program B in the host. Exemplarily, the client in the embodiment of the present invention can adopt a complex instruction set (Complex Instruction Set Computer, CISC) architecture, and the host can adopt a reduced instruction set (Reduced Instruction Set Computer, RISC) architecture. The instructions in the source program A can be called client instructions, and the instructions in the target program B can be called host instructions. Accordingly, the above-mentioned host instruction unit refers to an instruction block composed of one or more host instructions.

[0017] Furthermore, after reading the binary file, the translator usually translates and executes it in units of basic blocks (TB). Therefore, the host machine instruction unit may include a translated host machine instruction corresponding to a basic block.

[0018] Figure 2 FIG. 1 is a flowchart of a binary translation provided by an embodiment of the present invention. Figure 2 As shown, after the translator reads the executable program (i.e., binary file) of the client platform, it usually translates and executes it at the granularity of basic blocks. Before executing a basic block, the target program is first read from the code cache. If a translated basic block is found, the code block is executed. If the basic block is not found in the code cache, the translation operation is performed and the translated code is placed in the code cache, and then the basic block is executed. After executing a basic block, the code cache is searched for the next basic block, and this cycle is repeated until the program execution ends. Among them, basic block 0 to basic block n correspond to the host machine instruction units after translation of different basic blocks, and each host machine instruction unit contains the translated host machine instructions (Code). On this basis, the above combination can be inserted into the preset position in the host machine instruction unit.

[0019] Wherein, the above-mentioned preset mark can be a predefined string, the above-mentioned host instruction unit can be a host instruction sequence corresponding to a basic block, and correspondingly, the client instruction unit refers to a client instruction sequence corresponding to a basic block. Furthermore, in a binary translator, a basic block data structure is usually used to record metadata information of a basic block, which may include information such as the starting address, length and jump target of the basic block. Accordingly, the above-mentioned basic block pointer refers to a pointer to the basic block data structure in the translator. Furthermore, the basic block pointer of the above-mentioned host instruction unit refers to the basic block pointer of the basic block corresponding to the host instruction unit. Wherein, the above-mentioned basic block pointer can be dynamically allocated for TB by the translator at runtime.

[0020] Optionally, the preset mark is a magic number defined by a macro; the preset mark does not belong to the instruction set of the host machine.

[0021] The preset mark may be a magic number defined by a macro, which may be a fixed width. For example, the preset mark may be #define MAGICNUM 0xdeadbeef or #define MAGICNUM 0xbeef. The preset mark may be set according to actual conditions, and the embodiment of the present invention does not limit this.

[0022] Specifically, since the above-mentioned preset mark is inserted into the host machine instruction unit after being combined with the basic block pointer, in order to avoid the combination from affecting the normal execution of the host machine instructions, the above-mentioned preset mark may be an instruction set that does not belong to the above-mentioned host machine, that is, the preset mark does not conflict with any instruction code included in the host machine instruction set, thereby avoiding recognition errors caused by the conflict between the preset mark and the instruction code during the instruction execution process.

[0023] Optionally, the width of the above-mentioned preset mark can be set based on the host architecture. For example, if the host is a RISC architecture, since the width of basic instructions in various architectures in the RISC architecture (such as ARM architecture, RISC-V architecture, LoongArch architecture, etc.) is 4 bytes, the above-mentioned preset mark can also be defined as 4 bytes.

[0024] Furthermore, for any host machine instruction unit obtained after translation, the embodiment of the present invention can combine a preset tag with a basic block pointer to obtain a combination, and insert the combination into a preset position of the host machine instruction unit. Figure 3 is a schematic diagram of a structure of a combination provided by an embodiment of the present invention, such as Figure 3As shown, the combined structure represents the combined entity, the predefined identification mark corresponds to the above-mentioned preset mark, and the basic block pointer (TB pointer) is the basic block pointer of the basic block corresponding to the host machine instruction unit. Of course, in the above-mentioned combined entity, the TB pointer and the predefined identification mark can also be spliced, that is, the address of the TB pointer is less than the address of the predefined identification mark. The splicing order of the basic block pointer and the preset mark in the above-mentioned combined entity can be set voluntarily, and the embodiment of the present invention does not limit this.

[0025] Among them, the above-mentioned preset position can be the starting position or the ending position of the host machine instruction unit, or it can also be any intermediate position of the host machine instruction unit, which can be set according to actual needs, and the embodiment of the present invention does not limit this. Specifically, the preset mark and the basic block pointer can be directly spliced ​​to obtain an assembly, and the assembly can be inserted into the starting position, the ending position or the intermediate position of the host machine instruction unit. That is, the assembly can be adjacent to the first instruction in the host machine instruction unit, or it can be adjacent to the first instruction in the next instruction unit of the host machine instruction unit, and it can also be adjacent to the intermediate instruction in the host machine instruction unit.

[0026] It should be noted that, since the preset mark and the basic block pointer do not belong to executable host machine instructions, on this basis, if they are executed, an execution error or abnormal interruption may be triggered. Optionally, in the case where the above-mentioned preset position is an intermediate position, in order to avoid affecting the normal execution of the host machine instruction unit, the embodiment of the present invention can also back up the combination contained in the host machine instruction unit to the memory before executing any host machine instruction unit, and replace the combination contained in the host machine instruction unit with a no-operation instruction.

[0027] Optionally, in order to avoid affecting the normal execution of the host machine instruction unit, the embodiment of the present invention can also directly insert the assembly into the starting position or the ending position of the host machine instruction unit, so that when the host machine instruction unit is executed, it can skip the assembly and directly execute the original host machine instruction. Figure 4 Schematic diagram of the insertion position of a combination provided by an embodiment of the present invention, such as Figure 4 As shown, basic block 1 to basic block n correspond to different basic blocks, and accordingly, the translated code areas of basic block 1 to basic block n correspond to the host machine instruction units corresponding to different basic blocks, and the assembly is inserted into the starting position of the host machine instruction unit corresponding to different basic blocks, and the host machine instruction unit corresponding to each TB contains the corresponding host machine instruction (inst).

[0028] The above-mentioned search operation for any basic block pointer refers to the operation of searching for the client instruction basic block pointer through the translated instruction code. Specifically, in the self-modification scenario or some interruption and abnormal simulation scenarios, it is necessary to search for the corresponding TB according to the translated instruction code.

[0029] Exemplarily, the above self-modification scenario refers to the self-modification of the program during operation. Self-modifying code is a dynamic code generation technology in the computer field. It allows the program to directly modify the original machine instructions in the memory or add new machine instructions through memory access instructions during operation, and then execute them, thereby reducing the instruction path length and improving the program execution performance. It is widely used in JAVA virtual machine (Java Virtual Machine, JVM) code and browser engine code. The efficiency of the binary translator in processing self-modifying code directly affects the efficiency of the binary translator in simulating such programs. Therefore, it is a challenge for the binary translation system to efficiently optimize such code.

[0030] After translating a TB, the translator often sets the permissions of the memory page containing the TB to read-only, so that when the program modifies the code corresponding to the TB, a write protection exception (SIGSEGV) will be triggered. Accordingly, the translator can capture the exception and determine the address that needs to be modified by the instruction that triggered the exception in the signal processing function corresponding to SIGSEGV, and use the modified address to find out whether the corresponding TB has been translated. If it has been translated, the TB will be marked as invalid and the permissions of the corresponding memory page will be restored to writable so that the program can modify it. Accordingly, the next time the code is executed, it will be re-translated to generate a new TB.

[0031] Accordingly, in a self-modification scenario in the binary translation field, the embodiment of the present invention can determine that a search operation on a basic block pointer exists when a SIGSEGV signal is captured. Accordingly, in an interrupt or exception situation, the embodiment of the present invention can also determine that a search operation on a basic block pointer exists when an interrupt signal or an exception signal is captured.

[0032] Furthermore, the above-mentioned search address refers to the memory address of the host machine instruction that triggers the search operation, and the above-mentioned search address can be obtained through the signal processing function corresponding to the operation signal that triggers the search operation. For example, in a self-modification scenario, the search address can be obtained through the signal processing function corresponding to the SIGSEGV signal. Correspondingly, in an interrupt or other abnormal situation, the above-mentioned search address can be obtained through the signal processing function corresponding to the interrupt signal or other abnormal signal.

[0033] Furthermore, after obtaining the search address, the embodiment of the present invention can search for the corresponding assembly through the search address. Specifically, since the assembly is obtained by combining the preset tag and the basic block pointer, in order to obtain the basic block pointer corresponding to the search operation, the embodiment of the present invention can search for the corresponding preset tag through the search address, and determine the basic block pointer contained in the target assembly where the preset tag is located as the target basic block pointer.

[0034] Specifically, when searching for the target assembly, it is possible to determine whether the preset mark is found by increasing or decreasing the search address in sequence based on the insertion position of the assembly. Specifically, if the assembly is inserted to the starting position, the preset mark can be found by decreasing the search address. Correspondingly, if the assembly is inserted to the end position, the preset mark can be found by increasing the search address. Correspondingly, if the assembly is inserted to the middle position, the preset mark can be found by traversing the search address in an increasing or decreasing manner.

[0035] Furthermore, after the target basic block pointer is determined, the corresponding client instruction unit can be further processed through the target basic block pointer based on the search operation.

[0036] In summary, the binary translation method provided by the embodiment of the present invention combines a preset mark with the basic block pointer of the host instruction unit after translation to obtain an assembly, and inserts the assembly into a preset position in the host instruction unit; in response to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, obtains the assembly corresponding to the search address as the target assembly, and determines the basic block pointer contained in the target assembly as the target basic block pointer corresponding to the search operation. In this way, the embodiment of the present invention can embed the basic block pointer into the host instruction unit through the assembly by combining the preset mark and the basic block pointer and directly inserting the assembly into the preset position in the host instruction unit, so that when there is a search demand for the basic block pointer, the target assembly corresponding to the search address can be determined by the preset mark, so that the target basic block pointer corresponding to the search operation can be determined by the target assembly. The embodiment of the present invention can realize the search of the basic block pointer only by combining the preset mark and the basic block pointer, with low time cost, and ensures the performance of binary translation.

[0037] Optionally, the preset position may be a starting position of the host machine instruction unit.

[0038] Optionally, the preset position may be the end position of the host machine instruction unit.

[0039] After the above operation of inserting the assembly into the preset position in the host machine instruction unit, the embodiment of the present invention may further include: S21, performing byte alignment processing on each of the host machine instruction units in sequence according to a preset byte size.

[0040] The operation of obtaining the combination corresponding to the search address as the target combination based on the search address indicated by the search operation and the preset mark may specifically include: S1021. Perform byte alignment processing on the search address indicated by the search operation according to the preset byte size to obtain an aligned address.

[0041] S1022: Determine an address to be identified based on the alignment address and / or the byte size of the assembly.

[0042] S1023: Acquire a target assembly based on the address to be identified and the preset mark.

[0043] Among them, the above-mentioned preset byte size can be pre-set and can be set according to the host machine architecture. It should be noted that the preset byte size is used for byte alignment processing. On this basis, the above-mentioned preset byte size can be a power of 2. Exemplarily, the above-mentioned preset byte size can be 16 bytes, of course, it can also be 32 bytes, 8 bytes, etc., which can be set according to the architecture adopted by the host machine, and the embodiment of the present invention does not limit this.

[0044] Specifically, byte alignment refers to the storage and arrangement of data in memory according to certain rules. Byte alignment processing can ensure that the CPU can efficiently access memory data. Specifically, byte alignment processing refers to placing data at an address that satisfies a multiple of its size when storing data in memory. For example, a 4-byte integer data (int) usually needs to be placed at a 4-byte aligned address (such as 0x00, 0x04, 0x08, etc.). On this basis, in an embodiment of the present invention, byte alignment processing is performed on each host machine instruction unit according to a preset byte size, which means that the starting address of each host machine instruction unit is an integer multiple of the preset byte size, so that when the CPU accesses each host machine instruction unit, the number of CPU accesses can be reduced, thereby improving the CPU access efficiency.

[0045] Specifically, the above-mentioned byte alignment processing refers to the case where there is a host machine instruction unit whose starting address is not an integer multiple of the preset byte size, and its starting position can be adjusted by byte padding, that is, some idle bytes are added between different host machine instruction units to ensure that the starting address of each host machine instruction unit is an integer multiple of the preset byte size. It should be noted that the above-mentioned byte alignment processing is performed on the host machine instructions in the host machine instruction unit. If the above-mentioned combination is located at the end position of the host machine instruction unit, then when byte alignment is performed on the next host machine instruction unit of the host machine instruction unit, idle bytes can be added before the combination in the host machine instruction unit, so that the starting address of the next host machine instruction unit is an integer multiple of the preset byte size.

[0046] Furthermore, after byte alignment is performed on each host machine instruction unit, in the process of searching for the target assembly, the search can be performed according to the above-mentioned preset byte size to further reduce the search time.

[0047] Specifically, the above search address can be byte aligned so that the search address is also an integer multiple of the preset byte size to obtain an aligned address. This ensures that the aligned address points to the start or end position of the host machine instruction unit, which can greatly reduce the time to search for the target assembly.

[0048] Specifically, the above-mentioned operation of byte-aligning the search address varies according to the position of the assembly. Specifically, when the assembly is added to the starting position of the host machine instruction unit, the search address is usually larger than the address where the assembly is located. On this basis, the embodiment of the present invention can perform byte-alignment processing on the search address in the direction of decreasing address to obtain an aligned address. Correspondingly, when the assembly is added to the ending position of the host machine instruction unit, the search address is usually smaller than the address where the assembly is located. On this basis, the embodiment of the present invention can perform byte-alignment processing on the search address in the direction of increasing address to obtain an aligned address.

[0049] Specifically, taking the search address as P and the preset byte size as N as an example, if the assembly is added to the starting position of the host machine instruction unit, the alignment address P1=((P)&-(N)), and this formula can be used to align the original address P downward (in the direction of decreasing address) to an integer multiple of N. Correspondingly, if the assembly is added to the end position of the host machine instruction unit, the alignment address P1=(((P) + (N - 1))&-(N)), and this formula can be used to align the original address P upward (in the direction of increasing address) to an integer multiple of N.

[0050] Furthermore, after obtaining the alignment address, the alignment address can be used as the starting address for searching the target assembly to start the search operation. Specifically, since the basic block pointer is dynamically allocated by the translator, it is difficult to identify it. On this basis, since the embodiment of the present invention combines the preset tag with the basic block pointer, the embodiment of the present invention can obtain the target assembly by identifying the preset tag.

[0051] Specifically, since the sizes of the host machine instruction units are different, after the search address is byte-aligned, the obtained alignment address may point to the assembly, or may point to an address in the middle of the host machine instruction unit, so it can be further identified and judged through the preset mark. At the same time, since the assembly contains a preset mark and a basic block pointer, and depending on the insertion position of the assembly, when the alignment address points to the assembly, the alignment address may point to the preset mark in the assembly, or may point to the basic block pointer in the assembly. Therefore, the embodiment of the present invention can determine the address to be identified based on the alignment address and / or the byte size of the assembly, and then obtain the target assembly based on the address to be identified and the preset mark.

[0052] In an embodiment of the present invention, each of the host machine instruction units is byte-aligned in sequence according to a preset byte size; the search address indicated by the search operation is byte-aligned according to the preset byte size to obtain an alignment address; based on the alignment address and / or the byte size of the assembly, the address to be identified is determined; and the target assembly is acquired based on the address to be identified and the preset mark. In this way, by byte-aligning each of the host machine instruction units and the search address according to the preset byte size, it can be ensured that the starting address and alignment address of each host machine instruction unit are both integer multiples of the preset byte size, which can reduce the time cost of subsequently acquiring the target assembly through the alignment address and the preset mark to a certain extent, and further reduce the overhead of acquiring the target assembly.

[0053] Optionally, the preset mark in the assembly is located before the basic block pointer; the operation of determining the address to be identified based on the alignment address and / or the byte size of the assembly, the embodiment of the present invention may specifically include: S31: If the preset position is the starting position of the host machine instruction unit, determine the alignment address as the address to be identified.

[0054] S32: If the preset position is the end position of the host machine instruction unit, determine the address to be identified based on the alignment address and the byte size of the assembly.

[0055] Specifically, when the preset mark in the assembly is located before the basic block pointer, the address of the preset mark is smaller than the address of the basic block pointer. In this case, if the preset position is the starting position of the host machine instruction unit, that is, when the assembly is inserted into the starting position of the host machine instruction unit, then when the alignment address points to the assembly, the alignment address directly points to the preset mark in the assembly. Therefore, the embodiment of the present invention can directly determine the alignment address as the address to be identified.

[0056] Correspondingly, if the preset position is the end position of the host machine instruction unit, that is, when the assembly is inserted into the end position of the host machine instruction unit, when the alignment address points to the assembly, the alignment address directly points to the end position of the basic block pointer in the assembly. Therefore, the embodiment of the present invention can determine the address to be identified based on the alignment address and the byte size of the assembly, so that the address to be identified points to the preset mark. Specifically, the preset mark and the basic block pointer are of fixed size, so the size of the assembly is also fixed. In this case, the embodiment of the present invention can determine the address to be identified by the difference between the alignment address and the byte size of the assembly, that is, the alignment address is offset in the direction of decreasing the address by the byte size of the assembly, so that when the alignment address points to the basic block pointer, it can be moved to the address pointing to the preset mark as the address to be identified. Exemplarily, taking the alignment address as P1 and the byte size of the assembly as S1, P1-S1 can be determined as the address to be identified.

[0057] In the embodiment of the present invention, if the preset position is the starting position of the host machine instruction unit, the alignment address is determined as the address to be identified; if the preset position is the ending position of the host machine instruction unit, the address to be identified is determined based on the alignment address and the byte size of the assembly. In this way, the embodiment of the present invention can determine the address to be identified according to the insertion position of the assembly, ensure that the address to be identified does not point to the basic block pointer, and ensure the accuracy of the subsequent identification of the preset mark.

[0058] Optionally, the operation of acquiring the target assembly based on the address to be identified and the preset mark may specifically include: S41. When the address to be identified is the preset mark, obtain the assembly where the address to be identified is located as a target assembly.

[0059] S42: When the address to be identified is not the preset mark, a new address to be identified is determined based on the address to be identified and the preset byte size, and the operation of acquiring the target assembly based on the address to be identified and the preset mark is performed again.

[0060] After obtaining the address to be identified, it can be identified whether the address to be identified is a preset mark. Specifically, the address to be identified can be accessed to obtain the data stored in the address to be identified, and then the data is compared with the preset mark. If the comparison is consistent, it is determined that the address to be identified is the preset mark. Correspondingly, if the comparison is inconsistent, it is determined that the address to be identified is not the preset mark.

[0061] Further, in the case where the address to be identified is a preset mark, it can be determined that the address to be identified points to the preset mark in the assembly, and since the address to be identified is obtained based on the alignment of the search address, the address to be identified and the search address belong to the same host machine instruction unit, then the assembly where the preset mark pointed to by the address to be identified is located can be directly determined as the target assembly, and accordingly, the basic block pointer contained in the target assembly can be determined as the target basic block pointer for reading. Exemplarily, in the case where the preset mark is located before the basic block pointer in the assembly, if the address to be identified is a preset mark, the sum of the byte sizes of the address to be identified and the preset mark can be determined as the target address, and the target address points to the basic block pointer of the target assembly. At this time, the target basic block pointer corresponding to the search operation can be directly read from the target address. Exemplarily, taking the address to be identified as P2 and the byte size of the preset mark as S as an example, the target basic block pointer can be read from P2+S.

[0062] Furthermore, when the address to be identified is not a preset mark, the host machine instruction unit is often large, and the address to be identified often points to an address in the middle of the host machine instruction unit. In this case, the embodiment of the present invention can redetermine a new address to be identified based on the current address to be identified and the above-mentioned preset byte size, and perform the above-mentioned operation of obtaining the target assembly based on the address to be identified again based on the new address to be identified.

[0063] In the embodiment of the present invention, when the address to be identified is the preset mark, the assembly where the address to be identified is located is obtained as the target assembly; or, when the address to be identified is not the preset mark, a new address to be identified is determined based on the address to be identified and the preset byte size, and the operation of obtaining the target assembly based on the address to be identified and the preset mark is performed again. In this way, the target assembly can be obtained by simply judging whether the address to be identified is the preset mark, and the target assembly can be searched through the preset mark, thereby further reducing the time cost of basic block pointer search and reducing overhead.

[0064] Optionally, the operation of determining a new address to be identified based on the address to be identified and the preset byte size may specifically include: S51: If the preset position is the starting position of the host machine instruction unit, determine the difference between the address to be identified and the preset byte size as a new address to be identified.

[0065] S52: If the preset position is the end position of the host machine instruction unit, determine the sum of the address to be identified and the preset byte size as a new address to be identified.

[0066] Among them, when the address to be identified is not a preset mark, the host machine instruction unit is often large, and the address to be identified often points to an address in the middle of the host machine instruction unit. In this case, the address to be identified can be re-determined.

[0067] Specifically, if the preset position is the starting position of the host machine instruction unit, that is, when the assembly is inserted into the starting position of each host machine instruction unit, the address to be identified at this time is often still greater than the address of the current host machine instruction unit assembly. In order to find the preset mark, the address to be identified can be offset in the direction of the assembly. At this time, the difference between the address to be identified and the preset byte size can be determined as the new address to be identified.

[0068] Correspondingly, if the preset position is the starting position of the host instruction unit, that is, when the assembly is inserted into the end position of each host instruction unit, the address to be identified at this time is often smaller than the address of the current host instruction unit assembly. In order to find the preset mark, the address to be identified can be offset in the direction of the assembly. At this time, the sum of the address to be identified and the preset byte size can be determined as the new address to be identified.

[0069] For example, if the address to be identified is P2 and the preset byte size is N, if the assembly is inserted into the starting position of each host machine instruction unit, the new address to be identified P2 = P2-N. Correspondingly, if the assembly is inserted into the ending position of each host machine instruction unit, the new address to be identified P2 = P2+N.

[0070] For example, Figure 5 is a schematic diagram of a host machine instruction unit in an embodiment of the present invention, such as Figure 5 As shown, the translated code area of ​​basic block 1 represents the host machine instruction unit corresponding to basic block 1 (TB1), the predefined identification mark represents the above-mentioned preset mark, N represents the above-mentioned preset byte size, the translated code area of ​​TB1 contains the corresponding host machine instruction (inst), the translated code pointer represents the search address, and accordingly, the starting position of the translated code pointer after being aligned upward by N bytes represents the above-mentioned alignment address, which is obtained by aligning the search address by N bytes.

[0071] like Figure 5 As shown, the assembly is located at the starting position of the host machine instruction unit, and the preset mark in the assembly is located before the basic block pointer. At this time, the alignment address can be determined as the address to be identified, and it can be seen that the address to be identified does not point to the preset mark. Then, a new address to be identified can be determined based on the address to be identified and the preset byte size, that is, the address to be identified is offset by N bytes in the direction of address decrease, and it is determined again whether the address to be identified is the preset mark. Until the current address to be identified points to the preset mark, the target assembly can be obtained.

[0072] It should be noted that in binary translation systems, there are often scenarios where the basic block pointer (basic block pointer of the client instruction unit) is searched based on the translated code pointer (host instruction address). In related technologies, it is usually implemented through simulation and virtualization tools (Quick EMUlator, QEMU). QEMU is a powerful and flexible simulation and virtualization tool, and is also commonly used as two binary translators at the user level and system level. QEMU uses an interval tree (IntervalTree) to search for basic blocks. When an exception related to self-modifying code occurs, QEMU calls the corresponding search algorithm to search the corresponding TB structure through the program counter (Program Counter, PC) of the instruction to ensure correctness in complex scenarios (such as self-modifying code). However, the search time of the interval tree search method is related to the number of basic blocks n maintained in the tree during the search. The complexity of the insertion, deletion and search operations of the interval tree is usually O (logn), that is, the processing time increases in a logarithmic function as the amount of input data increases, resulting in a large overhead.

[0073] In the embodiment of the present invention, by setting a preset mark, and combining the preset mark with the basic block pointer and inserting it into the translated host machine instruction unit, when there is a need to search for the basic block pointer, the address of the corresponding assembly can be obtained by comparing the preset mark, and then the basic block pointer can be read through the target assembly. In the embodiment of the present invention, only the search address needs to be input to search for the basic block pointer, and the method provided by the embodiment of the present invention is independent of the number of basic blocks. The search cost is related to the alignment unit N and the maximum size of the translated host machine instruction sequence. Usually, only a fixed number of searches m (for example: 20 or 30) is required, which is independent of the number of basic blocks n. In the case of a large number of basic blocks in the translator, the time complexity can be considered to be close to the constant O(1) or O(m), but in the scenario of the binary translator, in most cases m is much smaller than logn. Therefore, the performance of the embodiment of the present invention is significantly better than the method implemented by QEMU in the related technology.

[0074] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0075] Figure 6 FIG. 1 is a schematic diagram of the structure of a binary translation device in an embodiment of the present invention. Figure 6 As shown, the device 20 may include: A combining module 201 is used for combining a preset mark with a basic block pointer of any translated host machine instruction unit to obtain a combination, and inserting the combination into a preset position in the host machine instruction unit; The first acquisition module 202 is used to respond to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, obtain the assembly corresponding to the search address as the target assembly, and determine the basic block pointer contained in the target assembly as the target basic block pointer corresponding to the search operation.

[0076] Optionally, the preset position is a starting position of the host machine instruction unit.

[0077] Optionally, the preset position is the end position of the host machine instruction unit.

[0078] Optionally, the device further comprises: A first alignment module, used to perform byte alignment processing on each of the host machine instruction units in sequence according to a preset byte size; The first acquisition module 202 includes: A second alignment submodule, configured to perform byte alignment processing on the search address indicated by the search operation according to the preset byte size to obtain an alignment address; A first determination submodule, configured to determine an address to be identified based on the alignment address and / or the byte size of the assembly; The second acquisition submodule is used to acquire the target assembly based on the address to be identified and the preset mark.

[0079] Optionally, the preset mark in the combination is located before the basic block pointer; the first determining submodule is specifically used to: If the preset position is the starting position of the host machine instruction unit, determining the alignment address as the address to be identified; If the preset position is the end position of the host machine instruction unit, the address to be identified is determined based on the alignment address and the byte size of the assembly.

[0080] Optionally, the second acquisition submodule is specifically used to: In the case where the address to be identified is the preset mark, obtaining the combination where the address to be identified is located as the target combination; When the address to be identified is not the preset mark, a new address to be identified is determined based on the address to be identified and the preset byte size, and the operation of acquiring the target assembly based on the address to be identified and the preset mark is performed again.

[0081] Optionally, the second acquisition submodule is further specifically used for: If the preset position is the starting position of the host machine instruction unit, the difference between the address to be identified and the preset byte size is determined as a new address to be identified; If the preset position is the end position of the host machine instruction unit, the sum of the address to be identified and the preset byte size is determined as a new address to be identified.

[0082] Optionally, the preset mark is a magic number defined by a macro; the preset mark does not belong to the instruction set of the host machine.

[0083] In summary, the binary translation device provided by the embodiment of the present invention combines a preset mark with the basic block pointer of the host instruction unit after translation to obtain an assembly, and inserts the assembly into a preset position in the host instruction unit; in response to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, obtains the assembly corresponding to the search address as the target assembly, and determines the basic block pointer contained in the target assembly as the target basic block pointer corresponding to the search operation. In this way, the embodiment of the present invention can embed the basic block pointer into the host instruction unit through the assembly by combining the preset mark and the basic block pointer and directly inserting the assembly into the preset position in the host instruction unit, so that when there is a search demand for the basic block pointer, the target assembly corresponding to the search address can be determined by the preset mark, so that the target basic block pointer corresponding to the search operation can be determined by the target assembly. The embodiment of the present invention can realize the search of the basic block pointer only by combining the preset mark and the basic block pointer, with low time cost, and ensures the performance of binary translation.

[0084] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0085] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0086] Regarding the request processing device in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0087] An embodiment of the present invention further provides an electronic device, comprising: a processor and a memory for storing instructions executable by the processor, wherein the processor is configured to execute the above binary translation method.

[0088] Reference Figure 7 , is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. Figure 7 As shown, the electronic device includes: a processor, a memory, a communication interface and a communication bus, and the processor, the memory and the communication interface communicate with each other through the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute the binary translation method of the aforementioned embodiment.

[0089] It should be noted that the electronic devices in the embodiments of the present application include mobile electronic devices and non-mobile electronic devices.

[0090] The processor may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmble Gate Array) or other editable devices, transistor logic devices, hardware components or any combination thereof. The processor may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0091] The communication bus may include a path for transmitting information between the memory and the communication interface. The communication bus may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 3 The fact that only one line is used in the diagram does not mean that there is only one bus or only one type of bus.

[0092] The memory may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable ReadOnly), a CD-ROM (Compact Disa Read Only), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0093] The embodiment of the present invention also provides a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device (server or terminal), the processor can execute Figure 1 The binary translation method shown.

[0094] The present invention also provides a computer program product comprising instructions, which, when executed on a computer, causes the computer to execute Figure 1 The binary translation method shown.

[0095] An embodiment of the present application also provides a chip, which includes a processor and a communication interface, wherein the communication interface is coupled to the processor, and the processor is used to run programs or instructions to implement the various processes of the above-mentioned binary translation method embodiment, and can achieve the same technical effect. To avoid repetition, it will not be repeated here.

[0096] It should be understood that the chip mentioned in the embodiments of the present application can also be called a system-level chip, a system chip, a chip system or a system-on-chip chip, etc.

[0097] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0098] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present invention is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website site, computer, server, or data center to another website site, computer, server, or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a DVD), or a semiconductor medium (eg, a solid state disk (SSD)).

[0099] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0100] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0101] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0102] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0103] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0104] It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

[0105] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0106] The above is a detailed introduction to a binary translation method, device, electronic device and readable storage medium provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A binary translation method, characterized in that: The method comprises: For any translated host machine instruction unit, combining a preset mark with a basic block pointer of the host machine instruction unit to obtain a combination, and inserting the combination into a preset position in the host machine instruction unit; In response to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, the assembly corresponding to the search address is obtained as the target assembly, and the basic block pointer contained in the target assembly is determined as the target basic block pointer corresponding to the search operation.

2. The method according to claim 1, characterized in that The preset position is the starting position of the host machine instruction unit.

3. The method according to claim 1, characterized in that The preset position is the end position of the host machine instruction unit.

4. The method according to claim 2 or 3, characterized in that: After inserting the assembly into a preset position in the host machine instruction unit, the method further includes: Performing byte alignment processing on each of the host machine instruction units in sequence according to a preset byte size; The step of obtaining the combination corresponding to the search address as the target combination based on the search address indicated by the search operation and the preset mark includes: Performing byte alignment processing on the search address indicated by the search operation according to the preset byte size to obtain an alignment address; Determining an address to be identified based on the alignment address and / or the byte size of the assembly; A target assembly is acquired based on the address to be identified and the preset mark.

5. The method according to claim 4, characterized in that The preset mark in the assembly is located before the basic block pointer; and the address to be identified is determined based on the alignment address and / or the byte size of the assembly, including: If the preset position is the starting position of the host machine instruction unit, determining the alignment address as the address to be identified; If the preset position is the end position of the host machine instruction unit, the address to be identified is determined based on the alignment address and the byte size of the assembly.

6. The method according to claim 4, characterized in that The step of acquiring the target assembly based on the address to be identified and the preset mark includes: In the case where the address to be identified is the preset mark, obtaining the combination where the address to be identified is located as the target combination; When the address to be identified is not the preset mark, a new address to be identified is determined based on the address to be identified and the preset byte size, and the operation of acquiring the target assembly based on the address to be identified and the preset mark is performed again.

7. The method according to claim 6, characterized in that The determining a new address to be identified based on the address to be identified and the preset byte size includes: If the preset position is the starting position of the host machine instruction unit, the difference between the address to be identified and the preset byte size is determined as a new address to be identified; If the preset position is the end position of the host machine instruction unit, the sum of the address to be identified and the preset byte size is determined as a new address to be identified.

8. The method according to claim 1, characterized in that The preset mark is a magic number defined by a macro; the preset mark does not belong to the instruction set of the host machine.

9. A binary translation device, characterized in that: The device comprises: A combining module, for combining a preset mark with a basic block pointer of any translated host machine instruction unit to obtain a combination, and inserting the combination into a preset position in the host machine instruction unit; The first acquisition module is used to respond to a search operation on any basic block pointer, based on the search address indicated by the search operation and the preset mark, obtain the assembly corresponding to the search address as a target assembly, and determine the basic block pointer contained in the target assembly as the target basic block pointer corresponding to the search operation.

10. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other through the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 1-8 when executing a program stored in a memory.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

12. A computer program, characterized in that When the computer program is executed by a computer, the method according to any one of claims 1 to 8 is implemented.

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