Memory Scheduling System, Method, Electronic Device, Storage Medium and Program

Abstract

The present application discloses a memory scheduling system, method, electronic device, storage medium and program, relating to the technical field of servers. The memory scheduling system includes multiple servers, a switching device and multiple memory devices. The switching device includes multiple upstream memory interfaces, multiple downstream memory interfaces, a processor and a connector. Among them, the switching device is connected to the multiple servers through the multiple upstream memory interfaces, and the switching device is connected to the multiple memory devices through the multiple downstream memory interfaces. The memory device includes at least one memory logical segment; the processor is used to record the scheduling times corresponding to each memory logical segment, and determine the target memory segment corresponding to at least one server among the multiple memory logical segments corresponding to the multiple memory devices according to the scheduling times corresponding to each memory logical segment. The utilization rate of memory resources can be improved.

Description

Technical Field

[0001] This application relates to the technical field of servers, and particularly to a memory scheduling system, method, electronic device, storage medium, and program. Background Art

[0002] In a data center, there can be multiple servers and a memory device corresponding to each server. When a server processes data through a Central Processing Unit (CPU), the memory device corresponding to the server can provide memory resources for the CPU.

[0003] In related technologies, memory pooling can be performed through Compute Express Link (CXL) switch technology, integrating memory resources scattered in different servers into a resource pool. Each server can obtain memory resources from the memory pool. However, each memory device in the resource pool can only be allocated to one server for use, and the memory resources used by the server for work are much smaller than the memory resources of the allocated memory device, resulting in low memory resource utilization. Summary of the Invention

[0004] This application provides a memory scheduling system, method, electronic device, storage medium, and program to at least solve the problem of low memory resource utilization in related technologies.

[0005] This application provides a memory scheduling system. The memory scheduling system includes multiple servers, a switching device, and multiple memory devices. The switching device includes multiple upstream memory interfaces, multiple downstream memory interfaces, a processor, and a connector. The processor is connected to the connector. Among them,

[0006] The switching device is connected to the multiple servers through the multiple upstream memory interfaces, and the switching device is connected to the multiple memory devices through the multiple downstream memory interfaces. The memory devices include at least one memory logical segment;

[0007] The multiple memory devices are used to provide memory resources for the multiple servers, and the connector is used to connect each upstream memory interface to the downstream memory interface corresponding to the target memory segment;

[0008] The processor is used to record the scheduling times corresponding to each memory logical segment, and determine at least one target memory segment corresponding to a server among the multiple memory logical segments corresponding to the multiple memory devices according to the scheduling times corresponding to each memory logical segment. The target memory segment is used to provide memory resources for its corresponding server.

[0009] This application provides a memory scheduling method, including:

[0010] Obtain the resource requirement of the target server;

[0011] According to the resource requirement, determine the target memory segment corresponding to the target server among multiple memory logical segments. The target memory segment is used to provide memory resources for the target server. The multiple memory logical segments are determined by partitioning the memories of multiple memory devices, and each memory device corresponds to at least one memory logical segment.

[0012] This application provides a memory scheduling device, including: a first acquisition module, a second acquisition module, a first determination module, and a second determination module, where,

[0013] The first acquisition module is used to obtain the resource requirement of the target server;

[0014] The second acquisition module is used to obtain the first memory capacity corresponding to each memory logical segment among the multiple memory logical segments. The multiple memory logical segments are determined by partitioning the memories of multiple memory devices, and each memory device corresponds to at least one memory logical segment;

[0015] The first determination module is used to determine multiple intermediate memory segments among the multiple memory logical segments according to the scheduling times corresponding to each memory logical segment;

[0016] The second determination module is used to determine the target memory segment according to the first memory capacity and the resource requirement corresponding to each intermediate memory segment. The target memory segment is used to provide memory resources for the target server.

[0017] This application also provides an electronic device, including: a memory for storing a computer program; a processor for implementing the steps of any of the above memory scheduling methods when executing the computer program.

[0018] This application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above memory scheduling methods are implemented.

[0019] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, the steps of any of the above memory scheduling methods are implemented.

[0020] Through the memory scheduling system, method, electronic device, storage medium, and program provided by this application, the memory scheduling system may include multiple servers, a switching device, and multiple memory devices. The switching device may include multiple upstream memory interfaces, multiple downstream memory interfaces, a processor, and a connector. The processor may be used to determine, among multiple memory logical segments corresponding to multiple memory devices, the target memory segment corresponding to each server. The memory devices may be divided into at least one memory logical segment. The processor may determine, according to the scheduling times corresponding to each memory logical segment, the target logical segment corresponding to each upstream memory interface among the multiple memory logical segments corresponding to the multiple memory devices. The memory capacity of the memory logical segment is relatively small. After being allocated to the server corresponding to the upstream memory interface, the difference between the memory resources used by the server for work and the memory resources corresponding to the allocated target logical segment can be reduced, thereby improving the utilization rate of memory resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] To more clearly illustrate the embodiments of this application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of this application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 Schematic diagram of an application scenario provided by an embodiment of this application;

[0023] Figure 2 Schematic diagram of the structure of a memory scheduling system provided by an embodiment of this application;

[0024] Figure 3 Schematic diagram of the structure of another memory scheduling system provided by an embodiment of this application;

[0025] Figure 4 Schematic diagram of the structure of a memory resource scheduling provided by an embodiment of this application;

[0026] Figure 5 Schematic diagram of the flow of a memory scheduling method provided by an embodiment of this application;

[0027] Figure 6 Schematic diagram of another memory scheduling method provided by an embodiment of this application;

[0028] Figure 7 Schematic diagram of the structure of a memory scheduling device provided by an embodiment of this application;

[0029] Figure 8 Schematic diagram of the structure of an electronic device provided by this application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present application.

[0031] It should be noted that in the description of the present application, the terms "include", "comprise" or any other variant thereof are intended to cover a non-exclusive inclusion, such that a process, method, article or device including a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0032] Figure 1 It is a schematic diagram of an application scenario provided for the embodiments of the present application. Please refer to Figure 1 , the memory scheduling system 100 includes a host box (Host Box, HB), a Compute Express Link (CXL) switch box (CXLSwitch Box, CSB), and a CXL memory box (CXL Memory Box, CMB). Among them, the host box may include multiple servers 101, the switch box may include a switching device 102, and the memory box may include multiple memory devices 103.

[0033] The switching device 102 may include multiple upstream memory interfaces, multiple downstream memory interfaces, a processor, and a connector. The CPU of the server 101 may be connected to an upstream memory interface of the switching device 102 through CXL. The downstream memory interface of the switching device 102 may be connected to a memory device 103 through CXL. CXL may be a cache coherence protocol based on the PCIe physical bus to release memory resources and can achieve an increase in the memory capacity across multiple CPUs.

[0034] The switching device 102 may perform memory pooling through CXL switch technology, integrating the memory resources of multiple memory devices 103 into a resource pool, and each server 101 may determine its corresponding memory device 103 in the resource pool.

[0035] However, each memory device in the resource pool can only be allocated to one server for use. The memory resources used by the server for work are much smaller than the memory resources of the allocated memory device (for example, the capacity of the memory device allocated to the server is 64 GB, but only 20 GB is actually occupied, and the remaining 44 GB is idle), resulting in low utilization of memory resources.

[0036] In the embodiments of the present application, a memory device can be divided into at least one memory logical segment. The processor can determine the target logical segment corresponding to each upstream memory interface among the multiple memory logical segments corresponding to multiple memory devices according to the scheduling times corresponding to each memory logical segment. The memory capacity of the memory logical segment is small. After being allocated to the server corresponding to the upstream memory interface, the difference between the memory resources used by the server for work and the memory resources corresponding to the allocated target logical segment can be reduced, thereby improving the utilization rate of memory resources.

[0037] Figure 2 It is a schematic structural diagram of a memory scheduling system provided by an embodiment of the present application. Please refer to Figure 2 , the memory scheduling system 100 can include multiple servers, a switching device, and multiple memory devices. The switching device can be connected to multiple servers through multiple upstream memory interfaces, and the switching device can be connected to multiple memory devices through multiple downstream memory interfaces.

[0038] Specifically, the server can be a dual-processor server, which can include two CPUs. The two CPUs can be communicatively connected through Ultra Path Interconnect (UPI). Among them, UPI can be used to achieve high-speed communication between CPUs in a multi-processor system. The upstream memory interface can be communicatively connected to the two CPUs through CXL respectively.

[0039] Please refer to Figure 2 , there are a total of 3 servers. Each server includes two CPUs. The switching device has a total of 3 upstream memory interfaces. The first upstream memory interface is communicatively connected to the two CPUs of the first server through CXL respectively. The second upstream memory interface is communicatively connected to the two CPUs of the second server through CXL respectively. The third upstream memory interface is communicatively connected to the two CPUs of the third server through CXL respectively.

[0040] It should be noted that in the embodiments of the present application, only the connection between the dual-processor server and the upstream memory interface is described, and the server is not limited. For example, the server can also be a single-processor server, a four-processor server, etc.

[0041] Multiple memory devices can be used to provide memory resources to multiple servers. The memory device can include a Memory Expander Controller (MXC), flash chips, and at least one storage module. The downlink memory interface is connected to the memory expander controller, and the memory expander controller is respectively connected to the flash chips and at least one storage module. Among them, the memory device can be a memory module.

[0042] The processor can obtain the memory capacity of at least one memory module in the memory expander controller through the downlink memory interface; the flash chips are used to store the configuration parameters of at least one memory module.

[0043] The storage module can be a Dual-Inline-Memory-Modules (DIMM). The MXC is connected to the DIMM, and the MXC is connected to the Flash through a Serial Peripheral Interface (SPI) bus. The SPI bus is a synchronous serial communication protocol mainly used for short-distance and high-speed inter-chip communication.

[0044] Among them, the MXC can be responsible for managing memory expansion and access optimization. For example, coordinating the work of multiple DIMMs, controlling the bandwidth allocation of memory channels, and optimizing the efficiency of data streams. The Flash can be used to store Serial Presence Detect (SPD) information. The SPD records the configuration parameters of the DIMM (such as timing, capacity, voltage, manufacturer information, etc.) for the system to automatically identify and configure the memory when starting up. The DIMM can integrate multiple Dynamic Random Access Memory (DRAM) chips to provide temporary data storage for the CPU and support high-speed read and write.

[0045] The DIMM can be a fourth-generation Double Data Rate 4 (DDR4) synchronous dynamic random access memory or a fifth-generation Double Data Rate 5 (DDR5) synchronous dynamic random access memory.

[0046] The downlink memory interface can be connected to the MXC of the memory device through a high-speed interconnect bus (i.e., CXL). Please refer to Figure 2 There are 3 downlink memory interfaces and 3 memory devices in total. The first downlink memory interface is connected to the MXC of the first memory device through CXL, the second downlink memory interface is connected to the MXC of the second memory device through a high-speed interconnect bus (i.e., CXL), and the third downlink memory interface is connected to the MXC of the third memory device through CXL.

[0047] Please refer to Figure 2 , the switching device may include multiple upstream memory interfaces, multiple downstream memory interfaces, a processor, and a connector. The processor and the connector are connected, and the connector connects each upstream memory interface to the downstream memory interface corresponding to the target memory segment.

[0048] The processor may divide the memory device into at least one memory logical segment. The processor may record the scheduling times corresponding to each memory logical segment. The processor may determine, based on the scheduling times corresponding to each memory logical segment, at least one target memory segment corresponding to a server among the multiple memory logical segments corresponding to the multiple memory devices. The target memory segment may be used to provide memory resources for its corresponding server.

[0049] After the processor determines the target memory segment, the connector may be used to connect each upstream memory interface to the downstream memory interface corresponding to the target memory segment. The downstream memory interface may include at least one second sub-interface, and the second sub-interface may be used to store the logical address corresponding to a memory logical segment. The number of second sub-interfaces corresponding to each downstream memory interface is the same as the number of memory logical segments of the memory device corresponding to the downstream memory interface.

[0050] Please refer to Figure 2 , each downstream memory interface includes M second sub-interfaces, that is, the memory device is divided into M memory logical segments, where M is an integer greater than or equal to 1. Each downstream memory interface may store the logical address of its corresponding memory logical segment.

[0051] The connector may connect the first upstream memory interface to two second sub-interfaces of the first downstream memory interface, that is, two memory logical segments of the first memory device provide memory resources for the first server; it may connect the second upstream memory node to one second sub-interface of the second downstream memory interface and one second sub-interface of the third downstream memory interface, that is, one memory logical segment of the second memory device and one memory logical segment of the third memory device provide memory resources for the second server; it may connect the third upstream memory interface to one second sub-interface of the third downstream memory interface, that is, one memory logical segment of the third memory device provides memory resources for the third server.

[0052] In the embodiments of the present application, a memory device may include at least one memory logic segment. The processing device may determine a target logic segment corresponding to each upstream memory interface among multiple memory logic segments corresponding to multiple memory devices according to the scheduling times corresponding to each memory logic segment. The memory capacity of the memory logic segment is relatively small. After being allocated to the server corresponding to the upstream memory interface, the difference between the memory resources used by the server for work and the memory resources corresponding to the allocated target logic segment can be reduced, thereby improving the utilization rate of memory resources. In addition, through the scheduling times corresponding to each memory logic segment, the memory logic segment with fewer scheduling times can be determined as the target logic segment, the scheduling times of each memory logic segment can be balanced, the service life of the memory device can be improved, and thus the stability of the system can be improved.

[0053] Figure 3 It is a schematic structural diagram of another memory scheduling system provided by the embodiments of the present application. Please refer to Figure 3 , in Figure 2 Based on the memory scheduling system 100 shown, in the memory scheduling system 100, the processor and the connector are communicatively connected through a UART bus. Among them, the UART bus (Universal Asynchronous Receiver / Transmitter) is an asynchronous serial communication protocol and is widely used for low-speed and reliable data transmission between devices (such as between a microcontroller and a sensor, a processor and a connector, etc.).

[0054] The processor can obtain the resource demand of the target server and determine the target memory segment corresponding to the target server among multiple memory logic segments according to the resource demand and the resource demand.

[0055] In the present application, the target memory segment corresponding to the target server can be determined through the resource demand of the target server, so that the memory resources allocated to the target server can just meet the use of the target server, and thus more memory resources can be released for the server with a larger resource demand, which can improve the effectiveness of memory resource allocation. In addition, the idle of memory resources in the target server can be reduced, and the utilization rate of memory resources can be improved.

[0056] In the present application, through the scheduling times, the memory logic segment with a lower usage frequency can be preferentially scheduled for the target server, the usage rate of each memory logic segment can be balanced, the situation that the usage rate of some memory logic segments is relatively high can be avoided, the service life of the corresponding memory device can be improved, and thus the reliability of the system can be improved.

[0057] In some possible embodiments, the processor further includes an expander, and the processor can be connected to multiple downstream memory interfaces through the expander.

[0058] Specifically, the expander and the processor are communicatively connected via an Inter-Integrated Circuit (I2C) bus. Among them, the expander can be an I2C Expander, which is an electronic device used to enhance or expand the functions of the I2C bus. It can solve the problem of insufficient General Purpose Input / Output (GPIO) pin numbers in system design and simplify circuit design through flexible serial communication.

[0059] The processor can also be used to perform memory partitioning on the memory devices corresponding to each downlink memory interface to determine at least one memory logical segment corresponding to each memory device.

[0060] In this application, the memory device can be divided into at least one memory logical segment, and the memory capacity of each memory logical segment is smaller than that of the memory device. When allocating the memory logical segment to the target server, the idle memory capacity can be reduced, and the utilization rate of memory resources can be improved.

[0061] The connector can be used to connect each uplink memory interface to the downlink memory interface corresponding to the target memory segment.

[0062] The connector can receive instructions from the processor and schedule the memory resources of different downlink memory interfaces to the specified uplink memory interface.

[0063] In some possible embodiments, the uplink memory interface may include at least one first sub-interface, the downlink memory interface may include at least one second sub-interface, the connector is connected to at least one first sub-interface corresponding to each uplink memory interface, and the connector is connected to at least one second sub-interface corresponding to each downlink memory interface, where

[0064] The first sub-interface can be used to store the logical address of the target memory segment corresponding to the target memory interface, and the target memory interface is the uplink memory interface corresponding to the first sub-interface; the second sub-interface can be used to store the logical address corresponding to any one memory logical segment.

[0065] For example, assume that the first memory device is divided into 16 memory logical segments, and the first memory device corresponds to the first downlink memory interface. Then, the first downlink memory interface includes 16 second sub-interfaces, and each second sub-interface can store the logical address corresponding to a memory logical segment.

[0066] It should be noted that the number of memory logic segments corresponding to each memory device may be the same or different. For example, the first memory device includes 16 memory logic segments, the first memory device may include 8 memory logic segments, and the third memory device may include 16 memory logic segments.

[0067] The processor may store the logical address of the target memory segment in the first sub-interface of the target memory interface. For example, please refer to Figure 3 , the first server corresponds to the first uplink memory interface. Assuming that the target memory segments corresponding to the first server are the first and second memory logic segments of the first memory device, then, the logical address of the first memory logic segment of the first memory device may be stored in the first first sub-interface of the first uplink memory interface, and the logical address of the second memory logic segment of the first memory device may be stored in the second first sub-interface of the first uplink memory interface.

[0068] In this application, the logical address of the target memory segment may be stored through the first sub-interface. The server may utilize the memory resources through the logical address, which can improve the efficiency of the server for memory access.

[0069] It should be noted that the maximum number of the first sub-interfaces corresponding to the uplink memory interface is the number of multiple memory logic segments. For example, there are 3 memory devices in total, and each memory device includes 16 memory logic segments, so there are 48 memory logic segments in total. Then, the maximum number of the first sub-interfaces corresponding to the uplink memory interface is 48.

[0070] Generally, not all memory logic segments are allocated to the same server. The number of the first sub-interfaces corresponding to the uplink memory interface may be the number of memory logic segments corresponding to one memory device. For example, the number of the first sub-interfaces corresponding to the uplink memory interface may be 16 or 8, etc.

[0071] Figure 4 It is a schematic structural diagram of a memory resource scheduling provided by an embodiment of this application. Please refer to Figure 4 , for any memory device, this memory device may include 16 memory logic segments. Among them, the full English name of the memory logic segment is Memory Logic Segment, and the English abbreviation is MLS. Figure 4 The 16 memory logic segments are respectively indicated by MLS0-MLS15 in [[ ]]. A processor and a connector are included in the switching device, and the processor and the connector are communicatively connected through UART. Through the switching device, the memory logic segments of the memory device can be scheduled for 4 servers to use. Figure 4Among them, four servers are respectively indicated by HOST0, HOST1, HOST2, and HOST3. The target memory segments corresponding to HOST0 are MLS0 and MLS3, the target memory segments corresponding to HOST1 are MLS5 and MLS8, the target memory segments corresponding to HOST2 are MLS7 and MLS9, and the target memory segments corresponding to HOST3 are MLS12 and MLS15.

[0072] After dividing the memory device into multiple memory logical segments, the memory logical segments can be allocated to different servers for use, which can greatly improve the utilization rate of the memory.

[0073] In some possible embodiments, the memory logical segments of different memory devices can be allocated to the same target server. For example, the memory logical segments of the first memory device and the second memory device are allocated to the first server.

[0074] Based on the above memory scheduling system, below, in combination with Figure 5 and Figure 6 the memory scheduling method provided by the embodiments of the present application will be described.

[0075] Figure 5 It is a schematic flowchart of a memory scheduling method provided by an embodiment of the present application. Please refer to Figure 5 and the method may include:

[0076] S501. Obtain the resource demand of the target server.

[0077] The target server is any one of multiple servers.

[0078] S502. Obtain the first memory capacity corresponding to each memory logical segment among multiple memory logical segments.

[0079] Before determining the target memory segment corresponding to the target server, it further includes performing memory partitioning processing on each memory device. The specific execution process can be referred to the following steps: The memory capacity corresponding to each memory device can be obtained through multiple downstream memory interfaces. For any one memory device, memory partitioning processing is performed according to the second memory capacity of the memory device to obtain at least one memory logical segment corresponding to the memory device, and each memory logical segment is stored in the second sub-interface.

[0080] Multiple memory logic segments may include at least one memory logic segment corresponding to each memory device. For example, assume there are a total of 3 memory devices. The first memory device includes memory logic segments 11 and 12, the second memory device includes memory logic segment 21, and the third memory device includes memory logic segments 31 and 32. Then the multiple memory logic segments include memory logic segments 11, 12, 21, 31, and 32.

[0081] It should be noted that after the memory chassis corresponding to multiple memory devices is powered on, for any one memory device, the MXC can read the Flash to complete initialization, and the MXC can obtain the memory resources of each DIMM. The processor can obtain the second memory capacity of each memory device through the MXC.

[0082] S503. Determine multiple intermediate memory segments among the multiple memory logic segments according to the scheduling times corresponding to each memory logic segment.

[0083] The multiple intermediate memory segments are the memory logic segments with fewer call times among the multiple memory logic segments.

[0084] After the processor schedules the memory logic segment, it can update the scheduling times corresponding to the memory logic segment. When allocating the target memory segment to the target server each time, the memory logic segment with a low call count can be preferentially allocated, which can improve the service life of the memory device and, at the same time, improve the reliability of the system.

[0085] S504. Determine the target memory segment according to the first memory capacity and resource demand corresponding to each intermediate memory segment.

[0086] The target memory segment can be used to provide memory resources for the target server. The multiple memory logic segments are determined by partitioning the memory of multiple memory devices, and each memory device corresponds to at least one memory logic segment.

[0087] The memory scheduling method provided by this application can determine multiple intermediate memory segments according to the resource demand of the target server and the call times corresponding to each memory logic segment. The intermediate memory segments are the memory logic segments with fewer call times, and then determine the target logic segment corresponding to each upstream memory interface among the multiple intermediate memory segments. Multiple intermediate memory segments can be determined through the call times, and the memory logic segments with fewer usage times can be preferentially allocated, which can improve the reliability of the system. In addition, the first memory capacity of the memory logic segment is small. After being allocated to the server corresponding to the upstream memory interface, the difference between the memory resources used by the server for work and the memory resources corresponding to the allocated target logic segment can be reduced, thereby improving the utilization rate of memory resources.

[0088] Figure 6Schematic diagram of another memory scheduling method provided by an embodiment of this application. Please refer to Figure 6 This method may include:

[0089] S601. Obtain the resource requirement of the target server.

[0090] For the execution process of S601, please refer to the execution process of S501 above, which will not be elaborated here.

[0091] S602. Obtain the first memory capacity corresponding to each memory logic segment among multiple memory logic segments.

[0092] The first memory capacity corresponding to each memory logic can be obtained through multiple second sub-interfaces.

[0093] In some possible embodiments, the first memory capacity corresponding to each memory logic segment may be the same. For example, if the second memory capacity of the memory device is 64G and the memory device is divided into 8 memory logic segments, then the first memory capacity corresponding to each memory logic segment is 8G.

[0094] In some possible embodiments, the first memory capacity corresponding to each memory logic may be the same or different. For example, if the second memory capacity of the memory device is 64G and the memory device is divided into 12 memory logic segments, then the first memory capacity of 8 memory logic segments is 5G, and the first memory capacity of 4 memory logic segments is 6G.

[0095] S603. Determine multiple intermediate memory segments among multiple memory logic segments according to the scheduling times corresponding to each memory logic segment.

[0096] In some possible embodiments, sort multiple memory logic segments in ascending order of scheduling times to obtain a sorted memory segment set, obtain a preset number N, and determine the first N memory logic segments in the memory segment set as multiple intermediate memory segments, where N is an integer greater than or equal to 1.

[0097] For example, assume there are 8 memory logic segments, namely memory logic segments 1-8. The scheduling times corresponding to each memory logic segment can be seen below. The memory segment set is {memory logic segment 3, memory logic segment 2, memory logic segment 4, memory logic segment 8, memory logic segment 1, memory logic segment 7, memory logic segment 6, memory logic segment 5}. Assume the preset number N is 4, then the determined multiple intermediate memory segments are: memory logic segment 3, memory logic segment 2, memory logic segment 4, memory logic segment 8.

[0098] Table 1

[0099] Memory logic segment Scheduling times Scheduling ratio Memory capacity Memory logic segment 1 13 13% 1G Memory logic segment 2 7 7% 1G Memory logic segment 3 6 6% 2G Memory logic segment 4 9 9% 4G Memory logic segment 5 20 20% 6G Memory logic segment 6 18 18% 6G Memory logic segment 7 16 16% 8G Memory logic segment 8 11 11% 8G

[0100] In some possible embodiments, according to the number of scheduling times corresponding to each memory logic segment, determine the scheduling ratio corresponding to each memory logic segment, obtain a preset ratio, and determine the memory logic segments with a scheduling ratio less than or equal to the preset ratio as intermediate memory segments, so as to determine multiple intermediate memory segments.

[0101] Specifically, for any memory logic segment, determine the ratio of the number of scheduling times corresponding to this memory logic segment to the total number of scheduling times corresponding to multiple memory logic segments as the scheduling ratio.

[0102] For example, there are a total of 8 memory logic segments, namely memory logic segments 1-8. For the number of scheduling times corresponding to each memory logic segment and the scheduling ratio corresponding to each memory logic segment, please refer to Table 1. Assuming the preset ratio is 10%, then memory logic segments 2, 3, and 4 are intermediate memory segments.

[0103] S604. Determine whether there is an intermediate memory segment in the first memory capacity corresponding to each intermediate memory segment that is greater than the resource demand.

[0104] If so, execute step S605;

[0105] If not, execute step S607.

[0106] S605. According to the first memory capacity and resource demand corresponding to each intermediate memory segment, determine at least one first memory segment and multiple second memory segments.

[0107] Among them, the first memory segment is an intermediate memory segment whose first memory capacity is greater than or equal to the resource demand, and the second memory segment is an intermediate memory segment whose first memory capacity is less than the resource demand.

[0108] S606. Determine the target memory segment according to at least one first memory segment, multiple second memory segments, and the resource demand.

[0109] The target memory segment can be one or more.

[0110] In some possible embodiments, the difference between the first memory capacity corresponding to each first memory segment in at least one first memory segment and the resource demand can be determined as the capacity difference; determine whether there is a first memory segment with a capacity difference less than or equal to the preset difference; if so, determine the first memory segment with a capacity difference less than or equal to the preset difference as the target memory segment, and the target memory segment is one; if not, determine the target memory segment according to the first memory capacity corresponding to the second memory segment, and the target memory segment is multiple.

[0111] The capacity difference is used to indicate the degree to which the first memory capacity corresponding to the first memory segment is larger than the resource demand of the server.

[0112] If the degree to which the first memory capacity of the first memory segment is greater than the resource demand is small, the first memory segment can be determined as the target memory segment. At this time, there is one target memory segment.

[0113] If there is a first memory segment whose capacity difference is less than or equal to the preset difference, that is, the first memory segment not only meets the memory requirements of the target server but also does not cause too much memory resources to be idle, the first memory segment can be determined as the target memory segment.

[0114] In some possible embodiments, there may be multiple first memory segments whose capacity differences are less than or equal to the preset difference, and the first memory segment with the fewest scheduling times can be determined as the target memory segment.

[0115] If the degree to which the first memory capacity of the first memory segment is greater than the resource demand is large, that is, the capacity difference is greater than the preset difference, the first memory segment cannot be determined as the target memory segment of the target server. If a memory logic segment with more allocated memory resources is assigned to the target server, it will cause a lot of memory resources to be idle and reduce the utilization rate of memory resources. At this time, the target memory segment can be determined according to the first memory capacity corresponding to each second memory segment, and there are multiple target memory segments.

[0116] For example, there are a total of 8 memory logic segments. The corresponding scheduling times, scheduling ratios, and memory capacities of each memory logic segment can be seen in Table 1. Suppose the resource demand is 5G, and memory logic segment 3, memory logic segment 2, memory logic segment 4, and memory logic segment 8 are intermediate memory segments. Among them, memory logic segment 8 is the first memory segment, and memory logic segment 3, memory logic segment 2, and memory logic segment 4 are second memory segments. Suppose the preset difference is 1G, then the capacity difference of memory logic segment 8 is greater than the preset difference, and the target memory segment can be determined among memory logic segment 3, memory logic segment 2, and memory logic segment 4.

[0117] The first memory capacity of the second memory segment is less than the resource demand. Then, there are multiple target memory segments determined among the multiple second memory segments. The memory capacities corresponding to the multiple target memory segments should be greater than the resource demand. Multiple memory segment combinations can be determined among the multiple second memory segments to select a suitable one as the target memory segment of the target server from the multiple memory segment combinations.

[0118] Specifically, multiple memory segment combinations can be determined according to the multiple second memory segments. The memory segment combinations can include at least two second memory segments; determine the third memory capacity corresponding to each memory segment combination; determine the memory segment combinations with a third memory capacity greater than the resource demand as intermediate combinations to obtain at least one intermediate combination; determine the intermediate combination with the smallest third memory capacity as the target combination, and determine the second memory segments corresponding to the target combination as the target memory segments.

[0119] For example, assume that the second memory segments are memory logic segment 3, memory logic segment 2, and memory logic segment 4. Four memory segment combinations can be determined, namely memory segment combinations 1 - 4. Assume that the first memory capacity corresponding to each memory logic segment can be referred to in Table 1, and the second memory segments and the third memory capacity corresponding to each memory segment combination can be referred to in Table 2 as shown. Then, the intermediate combinations can be determined as memory segment combination 3 and memory segment combination 4. Since the third memory capacity of memory segment combination 3 is less than that of memory segment combination 4, the memory logic segment 3 and memory logic segment 4 corresponding to memory segment combination 3 can be determined as the target memory segments.

[0120] Table 2

[0121] Memory segment combination Memory segment Memory capacity Memory segment combination 1 Memory logic segment 2 and memory logic segment 3 3G Memory segment combination 2 Memory logic segment 2 and memory logic segment 4 5G Memory segment combination 3 Memory logic segment 3 and memory logic segment 4 6G Memory segment combination 4 Memory logic segment 3, memory logic segment 2 and memory logic segment 4 7G

[0122] In this application, it can be determined whether there is a first memory segment whose capacity difference is less than or equal to a preset difference. If so, the first memory segment with a capacity difference less than or equal to the preset difference is determined as the target memory segment; if not, the target memory segment is determined according to the first memory capacity corresponding to the second memory segment, which can ensure that the memory logic segments allocated to the target server will not be much larger than the resource demand, reduce the waste of memory resources, and increase the utilization rate of memory resources.

[0123] S607. Determine the target memory segment according to the first memory capacity corresponding to each intermediate memory segment.

[0124] In some possible embodiments, the execution process of determining the target memory segment according to the first memory capacity corresponding to each second memory segment in step S606 can be referred to, which will not be elaborated here.

[0125] In some other possible embodiments, multiple intermediate memory segments can be sorted according to the first memory capacity corresponding to each intermediate memory segment to obtain a memory segment queue; the target memory segment is determined in the memory segment queue according to the resource demand.

[0126] Specifically, multiple intermediate memory segments can be sorted from largest to smallest according to the first memory capacity to obtain a memory segment queue.

[0127] There are Q intermediate memory segments in the memory segment queue. The i-th first candidate memory segment is sequentially determined in the memory segment queue, and the j-th second candidate memory segment except the i-th first candidate memory segment is determined until the sum of the i-th first candidate memory segment and the j-th second candidate memory segment is greater than the resource demand. The i-th first candidate memory segment and the j-th second candidate memory segment are determined as the target memory segments. Wherein, Q is an integer greater than or equal to 1, i is 1, 2, ……, Q, and j is 1, 2, ……, Q - 1.

[0128] For example, assume that memory logic segments 3, 2, 4, and 8 are intermediate memory segments. The memory capacity corresponding to each memory logic segment can be referred to in Table 1. Assume that the memory segment queue is {memory logic segment 4, memory logic segment 3, and memory logic segment 2}. Assume that the resource requirement is 5G, and the preset difference is 1G. The first first candidate memory segment is memory logic segment 4, and the first second candidate memory segment is memory logic segment 3. The sum of memory logic segment 4 and memory logic segment 3 is greater than the resource requirement, so it can be determined that memory logic segment 4 and memory logic segment 3 are the target memory segments.

[0129] The memory scheduling method provided by the embodiments of this application can obtain the first memory capacity corresponding to each memory logic segment among multiple memory logic segments, determine multiple intermediate memory segments among the multiple memory logic segments according to the scheduling times corresponding to each memory logic segment, and determine the target memory segment according to the first memory capacity corresponding to each intermediate memory segment and the resource requirement. The memory logic segment with fewer scheduling times can be selected as the target memory segment through the scheduling times, which can improve the service life of the memory device and thus improve the reliability of the system. In addition, after multiple intermediate memory segments are selected, one target memory segment or multiple target memory segments can be selected through the first memory capacity corresponding to each intermediate memory segment, so that the memory resources provided by the target memory segment are suitable for the resource requirement and too much memory resources will not be idle, which can improve the utilization rate of the memory resources.

[0130] Figure 7 It is a schematic structural diagram of a memory scheduling device provided by the embodiments of this application. Please refer to Figure 7 , the memory scheduling device 700 includes a first acquisition module 701, a second acquisition module 702, a first determination module 703, and a second determination module 704, where,

[0131] The first acquisition module 701 is configured to acquire the resource requirement of the target server;

[0132] The second acquisition module 702 is configured to acquire the first memory capacity corresponding to each memory logic segment among multiple memory logic segments. The multiple memory logic segments are determined by partitioning the memories of multiple memory devices, and each memory device corresponds to at least one memory logic segment;

[0133] The first determination module 703 is configured to determine multiple intermediate memory segments among the multiple memory logic segments according to the scheduling times corresponding to each memory logic segment;

[0134] The second determination module 704 is configured to determine the target memory segment according to the first memory capacity corresponding to each intermediate memory segment and the resource requirement. The target memory segment is used to provide memory resources for the target server.

[0135] In a possible embodiment, the second determination module 704 is specifically configured to:

[0136] Determine whether there is an intermediate memory segment among the first memory capacities corresponding to each intermediate memory segment whose value is greater than the resource demand;

[0137] If so, determine at least one first memory segment and multiple second memory segments according to the first memory capacity and the resource demand corresponding to each intermediate memory segment, and determine the target memory segment according to at least one first memory segment, multiple second memory segments and the resource demand, where the first memory segment is an intermediate memory segment whose first memory capacity is greater than or equal to the resource demand, and the second memory segment is an intermediate memory segment whose first memory capacity is less than the resource demand;

[0138] If not, determine the target memory segment according to the first memory capacity corresponding to each intermediate memory segment.

[0139] In a possible embodiment, the second determination module 704 is specifically configured to:

[0140] Determine the difference between the first memory capacity corresponding to each first memory segment in at least one first memory segment and the resource demand as the capacity difference;

[0141] Determine whether there is a first memory segment whose capacity difference is less than or equal to a preset difference;

[0142] If so, determine the first memory segment whose capacity difference is less than or equal to the preset difference as the target memory segment, and the target memory segment is one;

[0143] If not, determine the target memory segment according to the first memory capacity corresponding to the second memory segment, and the target memory segment is multiple.

[0144] In a possible embodiment, the second determination module 704 is specifically configured to:

[0145] Sort the multiple intermediate memory segments according to the first memory capacity corresponding to each intermediate memory segment to obtain a memory segment queue;

[0146] Determine the target memory segment in the memory segment queue according to the resource demand.

[0147] In a possible embodiment, the second determination module 704 is specifically configured to:

[0148] Determine multiple memory segment combinations according to the multiple second memory segments, and the memory segment combination includes at least two second memory segments;

[0149] Determine the third memory capacity corresponding to each memory segment combination;

[0150] Combine the memory segments with a third memory capacity greater than the resource requirement, and determine them as intermediate combinations to obtain at least one intermediate combination;

[0151] Determine the intermediate combination with the smallest third memory capacity as the target combination, and determine the second memory segment corresponding to the target combination as the target memory segment.

[0152] In one possible embodiment, the second determination module 704 is specifically configured to:

[0153] Sort multiple memory logic segments in ascending order of the number of scheduling times to obtain a sorted memory segment set, obtain a preset number N, and determine the first N memory logic segments in the memory segment set as multiple intermediate memory segments, where N is an integer greater than or equal to 1;

[0154] Alternatively, determine the scheduling ratio corresponding to each memory logic segment according to the number of scheduling times corresponding to each memory logic segment, obtain a preset ratio, and determine the memory logic segments with a scheduling ratio less than or equal to the preset ratio as intermediate memory segments to determine multiple intermediate memory segments.

[0155] For the description of the features in the corresponding embodiments of the memory scheduling device, reference can be made to the relevant descriptions in the corresponding embodiments of the memory scheduling method, which will not be elaborated here one by one.

[0156] Figure 8 This is a schematic structural diagram of an electronic device provided by the present application. As Figure 8 shown, the electronic device 800 provided in this embodiment includes: at least one processor 801 and a memory 802. Optionally, the electronic device 800 further includes a communication component 803. Among them, the processor 801, the memory 802, and the communication component 803 are connected through a bus.

[0157] In a specific implementation process, at least one processor 801 executes the computer execution instructions stored in the memory 802, so that at least one processor 801 executes the above-mentioned in-land scheduling method embodiment.

[0158] For the specific implementation process of the processor 801, reference can be made to the above method embodiment, and its implementation principle and technical effects are similar, which will not be elaborated here in this embodiment.

[0159] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or may also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), etc. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in combination with the application can be directly implemented by the execution of the hardware processor, or can be implemented by the combination of the hardware and software modules in the processor.

[0160] The memory may include a random access memory (RAM), and may also include a non-volatile memory (NVM), such as at least one disk memory.

[0161] The bus may be an industry standard architecture (ISA) bus, a peripheral component interconnect (PCI) bus, an extended industry standard architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For the sake of convenience of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.

[0162] The embodiments of the present application also provide a computer-readable storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any one of the embodiments of the above memory scheduling method when running.

[0163] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memories (ROMs), random access memories (RAMs), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0164] The embodiments of the present application also provide a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any one of the embodiments of the above memory scheduling method are implemented.

[0165] Embodiments of the present application further provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the steps in any of the above embodiments of the memory scheduling method.

[0166] Those skilled in the art can further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present application.

[0167] The above has introduced in detail a memory scheduling method provided by the present application. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

Claims

1. A memory scheduling system, characterized in that: The memory scheduling system includes multiple servers, a switching device and multiple memory devices, wherein the switching device includes multiple upstream memory interfaces, multiple downstream memory interfaces, a processor and a connector, wherein the processor is connected to the connector, The switching device is connected to the multiple servers via the multiple upstream memory interfaces, the switching device is connected to the multiple memory devices via the multiple downstream memory interfaces, and the memory device includes at least one memory logic segment; The multiple memory devices are used to provide memory resources to the multiple servers, and the connector is used to connect each upstream memory interface to a downstream memory interface corresponding to a target memory segment; The processor is used to record the scheduling number corresponding to each memory logic segment, and determine, according to the scheduling number corresponding to each memory logic segment, a target memory segment corresponding to at least one server among the multiple memory logic segments corresponding to the multiple memory devices, wherein the target memory segment is used to provide memory resources for the corresponding server; The upstream memory interface includes at least one first sub-interface, the downstream memory interface includes at least one second sub-interface, the connector is connected to at least one first sub-interface corresponding to each upstream memory interface, and the connector is connected to at least one second sub-interface corresponding to each downstream memory interface, wherein: The first sub-interface is used to store a logical address of a target memory segment corresponding to a target memory interface, and the target memory interface is an uplink memory interface corresponding to the first sub-interface; The second sub-interface is used to store the logical address corresponding to any memory logical segment.

2. The memory scheduling system according to claim 1, characterized in that: The processor is specifically used for: Get the resource requirements of the target server; According to the resource demand and the number of scheduling times corresponding to each memory logical segment, a target memory segment corresponding to the target server is determined from the multiple memory logical segments.

3. The memory scheduling system according to claim 2, characterized in that: The processor further includes an expander, and the processor is connected to the multiple downstream memory interfaces via the expander, wherein: The processor is further configured to perform memory partitioning processing on the memory device corresponding to each downstream memory interface, and determine at least one memory logical segment corresponding to each memory device.

4. The memory scheduling system according to claim 3, characterized in that: The memory device includes a memory expansion controller, a flash memory chip and at least one storage module, the downstream memory interface is connected to the memory expansion controller, and the memory expansion controller is respectively connected to the flash memory chip and the at least one storage module, wherein: The processor obtains the memory capacity of the at least one memory module in the memory expansion controller through the downstream memory interface; The flash memory chip is used to store configuration parameters of the at least one memory module.

5. The memory scheduling system according to claim 4, characterized in that: The multiple upstream memory interfaces are communicatively connected to the multiple servers via a high-speed interconnection bus, and the multiple downstream memory interfaces are communicatively connected to the multiple memory devices via a high-speed interconnection bus.

6. A memory scheduling method, the memory scheduling method being applied to the memory scheduling system according to any one of claims 1 to 5, characterized in that: include: Get the resource requirements of the target server; Obtaining a first memory capacity corresponding to each memory logical segment of a plurality of memory logical segments, wherein the plurality of memory logical segments are determined by performing memory division on a plurality of memory devices, and each memory device corresponds to at least one memory logical segment; According to the scheduling number corresponding to each memory logical segment, determining a plurality of intermediate memory segments among the plurality of memory logical segments; A target memory segment is determined according to the first memory capacity corresponding to each intermediate memory segment and the resource demand, and the target memory segment is used to provide memory resources for the target server.

7. The method according to claim 6, characterized in that Determining the target memory segment according to the first memory capacity corresponding to each intermediate memory segment and the resource requirement includes: Determine whether there is an intermediate memory segment greater than the resource requirement in the first memory capacity corresponding to each intermediate memory segment; If so, determining at least one first memory segment and multiple second memory segments according to the first memory capacity corresponding to each intermediate memory segment and the resource requirement, and determining the target memory segment according to the at least one first memory segment, the multiple second memory segments and the resource requirement, wherein the first memory segment is an intermediate memory segment whose first memory capacity is greater than or equal to the resource requirement, and the second memory segment is an intermediate memory segment whose first memory capacity is less than the resource requirement; If not, the target memory segment is determined according to the first memory capacity corresponding to each intermediate memory segment.

8. The method according to claim 7, characterized in that Determining the target memory segment according to the at least one first memory segment, the plurality of second memory segments, and the resource requirement includes: Determine a difference between a first memory capacity corresponding to each first memory segment in the at least one first memory segment and the resource requirement as a capacity difference; Determine whether there is a first memory segment whose capacity difference is less than or equal to a preset difference; If so, the first memory segment whose capacity difference is less than or equal to the preset difference is determined as the target memory segment, and there is one target memory segment; If not, the target memory segment is determined according to the first memory capacity corresponding to the second memory segment, and there are multiple target memory segments.

9. The method according to claim 8, characterized in that Determining the target memory segment according to the first memory capacity corresponding to the second memory segment includes: Determine a plurality of memory segment combinations according to the plurality of second memory segments, wherein the memory segment combinations include at least two second memory segments; Determine the third memory capacity corresponding to each memory segment combination; Determine the memory segment combination whose third memory capacity is greater than the resource requirement as an intermediate combination, so as to obtain at least one intermediate combination; The intermediate combination with the smallest third memory capacity is determined as the target combination, and the second memory segment corresponding to the target combination is determined as the target memory segment.

10. The method according to claim 7, characterized in that Determining the target memory segment according to the first memory capacity corresponding to each intermediate memory segment includes: According to the first memory capacity corresponding to each intermediate memory segment, the plurality of intermediate memory segments are sorted to obtain a memory segment queue; According to the resource demand, the target memory segment is determined in the memory segment queue.

11. The method according to claim 7, characterized in that According to the scheduling times corresponding to each memory logic segment, a plurality of intermediate memory segments are determined in the plurality of memory logic segments, including: Sorting the plurality of memory logical segments according to the order of the scheduling times from small to large to obtain a sorted memory segment set, obtaining a preset number N, and determining the first N memory logical segments in the memory segment set as the plurality of intermediate memory segments, where N is an integer greater than or equal to 1; Alternatively, according to the scheduling number corresponding to each memory logic segment, the scheduling ratio corresponding to each memory logic segment is determined, a preset ratio is obtained, and the memory logic segment whose scheduling ratio is less than or equal to the preset ratio is determined as the intermediate memory segment, so as to determine the multiple intermediate memory segments.

12. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to implement the steps of the memory scheduling method as claimed in any one of claims 6 to 11 when executing the computer program.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the memory scheduling method according to any one of claims 6 to 11.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the memory scheduling method according to any one of claims 6 to 11 are implemented.

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