Health monitoring method and device of logic design system, equipment and storage medium

Abstract

The invention discloses a health monitoring method and device for a logic design system, equipment and a storage medium, and relates to the field of integrated circuits, and the method comprises the steps: operating collected excitation data generated when the system is powered on, and comparing an obtained operation result with a preset simulation result to obtain a corresponding comparison result; if the comparison result represents that the operation result is inconsistent with the preset simulation result, counting operation error data based on the comparison result, and generating an error code corresponding to the operation error data; and sending the operation result and the error code to an upper computer, so that the upper computer determines an error source and a fault level according to the error code and the operation result, and then performs system health monitoring based on the error source and the fault level. In this way, the source part of the error in the chip can be positioned, the fault level of the error can be judged, and then system health monitoring is carried out through the error source and the fault level.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a health monitoring method, device, equipment and storage medium for a logic design system. Background Art

[0002] FPGA (Field Programmable Gate Array) is an integrated circuit with programmable features pre-designed and implemented on silicon wafers. It can be configured into a specified circuit structure according to the needs of designers, so that customers do not have to rely on ASIC (Application Specific Integrated Circuit) chips designed and manufactured by chip manufacturers. It is widely used in prototype verification, communications, automotive electronics, industrial control, aerospace, data centers and other fields.

[0003] Nowadays, the scale of chips is getting bigger and bigger, and the scale of FPGA logic design is getting bigger and bigger. It is not easy to locate the problems on the FPGA board. If the design is very large in logic scale, it will take a lot of time to locate the problem. Therefore, a method for FPGA system health monitoring is needed. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a health monitoring method, device, equipment and storage medium for a logic design system, which can locate the source of errors in the chip and determine the fault level of the errors, and then perform system health monitoring based on the error source and the fault level. The specific scheme is as follows:

[0005] In a first aspect, the present application discloses a health monitoring method for a logic design system, which is applied to a target chip, comprising:

[0006] Run the collected stimulus data generated when the system is powered on, and compare the obtained running results with the preset simulation results to obtain corresponding comparison results;

[0007] If the comparison result indicates that the operation result is inconsistent with the preset simulation result, counting operation error data based on the comparison result, and generating an error code corresponding to the operation error data;

[0008] The operation result and the error code are sent to a host computer so that the host computer can determine the error source and the fault level according to the error code and the operation result, and then perform system health monitoring based on the error source and the fault level.

[0009] Optionally, the running of the collected excitation data generated when the system is powered on, and comparing the obtained running results with preset simulation results to obtain corresponding comparison results, includes:

[0010] Collecting the stimulus data generated when the system is powered on, and packaging the collected stimulus data to obtain a stimulus data packet;

[0011] Sending the stimulus data packet to the main logic component so that the main logic component unpacks the stimulus data packet and runs the unpacked stimulus data to generate corresponding running results;

[0012] The operation result and the preset simulation operation result are compared to determine whether the operation result is completely consistent with the preset simulation operation result, and a corresponding comparison result is generated; the preset simulation operation result is a result of error-free operation.

[0013] Optionally, if the comparison result indicates that the operation result is inconsistent with the preset simulation result, counting operation error data based on the comparison result and generating an error code corresponding to the operation error data includes:

[0014] If the comparison result indicates that the operation result is inconsistent with the preset simulation result, determining target data in the operation result that is inconsistent with the preset simulation result according to the comparison result, and using the target data as error data;

[0015] Power-on errors and operating state errors corresponding to the error data are counted, and error codes corresponding to the error data are generated according to the power-on errors and operating state errors.

[0016] Optionally, determining a fault level according to the error code and the operation result includes:

[0017] Determine whether the running state error causes a system error according to the running state error corresponding to the error code and the running result;

[0018] If the operating status error leads to a system error, the fault level is determined based on a system error type corresponding to the system error; the system error type includes system shutdown, system function error, and warning error.

[0019] Optionally, determining the source of the error according to the error code and the operation result includes:

[0020] Analyze the error code to determine the error type corresponding to the error code, and filter error-inducing data corresponding to the error type from a preset cache; the error-inducing data is preset data that induces a running error;

[0021] The error inducing data is sent to the target chip, so that the target chip runs the error inducing data after receiving the error inducing data, and determines the source of the error based on the obtained target running result.

[0022] Optionally, the running the error-inducing data and determining the source of the error based on the obtained target running result includes:

[0023] Running the error-inducing data to obtain a target running result corresponding to the error-inducing data;

[0024] If the target operation result indicates that error data of the same error type appears, the error source causing the error data locally is determined.

[0025] Optionally, the health monitoring method of the logic design system further includes:

[0026] Timestamp data is added to the error source and the error level based on the current system time to obtain error information to be displayed, and the error information to be displayed is displayed through the system front end.

[0027] In a second aspect, the present application discloses a health monitoring device for a logic design system, which is applied to a target chip, comprising:

[0028] The data comparison module is used to run the collected stimulus data generated when the system is powered on, and compare the obtained running results with the preset simulation results to obtain corresponding comparison results;

[0029] an error code generating module, configured to collect operation error data based on the comparison result and generate an error code corresponding to the operation error data if the comparison result indicates that the operation result is inconsistent with the preset simulation result;

[0030] The health monitoring module is used to send the operation result and the error code to the host computer, so that the host computer can determine the error source and the fault level according to the error code and the operation result, and then perform system health monitoring based on the error source and the fault level.

[0031] In a third aspect, the present application discloses an electronic device, comprising:

[0032] Memory, used to store computer programs;

[0033] The processor is used to execute the computer program to implement the health monitoring method of the logic design system as described above.

[0034] In a fourth aspect, the present application discloses a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the health monitoring method of a logic design system as described above.

[0035] In this application, the collected excitation data generated when the system is powered on can be run, and the obtained operation results can be compared with the preset simulation results to obtain the corresponding comparison results; if the comparison results indicate that the operation results are inconsistent with the preset simulation results, the operation error data is statistically analyzed based on the comparison results, and an error code corresponding to the operation error data is generated; the operation results and the error code are sent to the host computer, so that the host computer determines the error source and the fault level according to the error code and the operation results, and then performs system health monitoring based on the error source and the fault level. In this way, the source of the error in the chip can be located and the fault level of the error can be determined, and then the system health monitoring can be performed through the error source and the fault level.

[0036] It can be seen that through the method of the present application, the excitation data when the system is powered on can be collected, and then the excitation data can be run and the obtained operation result can be compared with the preset simulation result. If the obtained comparison result is inconsistent with the preset simulation result, it indicates that there is an operation error at present, and it is necessary to count the operation error data and generate the corresponding error code, and then send the operation result and the error code to the host computer so that the host computer can determine the error source and fault level based on the received information, and then perform system health monitoring based on the error source and the fault level. In this way, the source of the error in the chip can be located and the fault level of the error can be determined, and then the system health monitoring can be performed through the error source and the fault level. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0038] Figure 1 A flow chart of a health monitoring method for a logic design system disclosed in this application;

[0039] Figure 2 A health monitoring interaction logic diagram of a logic design system disclosed in this application;

[0040] Figure 3A schematic diagram of the structure of a health monitoring device of a logic design system disclosed in this application;

[0041] Figure 4 This is a structural diagram of an electronic device disclosed in this application. DETAILED DESCRIPTION

[0042] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0043] In the prior art, as the scale of FPGA logic design becomes larger and larger, it is difficult to locate problems on the FPGA board. If the design is very large in logic scale, it will take a lot of time to locate the problem. Therefore, a method for processing FPGA system health monitoring is needed.

[0044] In order to solve the above technical problems, the present application discloses a health monitoring method, device, equipment and storage medium for a logic design system, which can locate the source of errors in the chip and determine the fault level of the errors, and then perform system health monitoring based on the error source and the fault level.

[0045] See also Figure 1 As shown, an embodiment of the present invention discloses a health monitoring method for a logic design system, which is applied to a target chip, and includes:

[0046] Step S11 , running the collected excitation data generated when the system is powered on, and comparing the obtained running results with the preset simulation results to obtain corresponding comparison results.

[0047] In this embodiment, it is necessary to run the collected excitation data generated when the system is powered on, and compare the obtained operation results with the preset simulation results. Specifically, it is necessary to collect the excitation data generated when the system is powered on, and then package the generated excitation data to obtain an excitation data packet corresponding to the excitation data, and then send the excitation data packet to the main logic component, that is, the main logic module. After receiving the excitation data packet, the logic component unpacks the excitation data packet and runs the unpacked excitation data to obtain the operation results generated by running the excitation data. It should be noted that the purpose of running the excitation data is to perform a power-on self-test. After the operation is completed, the error data can be determined by comparing the operation results with the preset simulation results.

[0048] Furthermore, it is necessary to compare the running results generated by the running excitation data with the preset simulation running results. It should be noted that the simulation running results are the correct results of the excitation data obtained by simulating the external algorithm. The preset simulation results need to be stored in the local preset cache. After obtaining the running results of the excitation data, it is necessary to compare the running results and the simulation running results.

[0049] Step S12: If the comparison result indicates that the operation result is inconsistent with the preset simulation result, operation error data is counted based on the comparison result, and an error code corresponding to the operation error data is generated.

[0050] In this embodiment, if the comparison result between the running result and the preset simulation running result indicates that the running result is inconsistent with the preset simulation result, it is necessary to determine the target data in the running result that is inconsistent with the preset simulation result based on the comparison result, and use the target data as error data. It should be noted that when the running result is compared with the preset simulation running result, a flag can be generated to indicate whether the running result is completely consistent with the preset simulation running result, that is, whether the power-on operation of the current target chip is correct. Therefore, the generated flag can be used as the comparison result, and whether the power-on operation of the current target chip is abnormal can be directly determined based on the comparison result.

[0051] Furthermore, if the comparison result obtained indicates that the running result is inconsistent with the preset simulation result, it is necessary to count the target data in the running result that is inconsistent with the preset simulation result, and then use the counted target data as error data. Furthermore, it is necessary to generate a corresponding error code based on the error data, where the error code is an 8-bit hexadecimal number, including power-on self-test errors, some state errors in operation, such as message count errors for each module input and output, state machine errors, etc.

[0052] Step S13: Send the operation result and the error code to a host computer, so that the host computer determines the error source and the fault level according to the error code and the operation result, and then performs system health monitoring based on the error source and the fault level.

[0053] In this embodiment, the operation result and the error code need to be sent to the host computer so that the host computer can determine the fault level according to the error code and the operation result. Specifically, after the host computer receives the operation result and the error code, it can determine whether the operation status error causes a system error according to the operation status error corresponding to the error code and the operation result. It should be noted that the error level is divided according to the system's tolerance for errors, including fatal errors, serious errors, and general errors. Fatal errors are the most serious error level, that is, system shutdown errors. Such errors will cause the system to stop running immediately. Serious errors will seriously affect the key functions of the system, that is, system function errors. Such errors will affect the normal operation of the system, but will not cause the complete loss of the key functions of the system. General errors indicate that the system has detected some potential problems or abnormal conditions, that is, warning errors. Such errors do not have a substantial impact on the normal operation of the system.

[0054] Further, the host computer can determine the source of the error according to the error code and the operation result. Specifically, after the host computer receives the operation result and the error code, it can analyze the error code to determine the error type corresponding to the error code, and filter the error-inducing data corresponding to the error type from the preset cache. It should be noted that the error-inducing data is the preset data that induces the operation error. And the error-inducing data is a pre-set code that induces common errors based on the common error types of the chip. The error-inducing data can be sent to the target chip so that the target chip runs the error-inducing data after receiving the error-inducing data, and determines the source of the error based on the target operation result obtained. And after running the error-inducing data, if the target operation result characterizes the occurrence of error data of the same error type, it characterizes that the error-inducing data causes the same error as the error type. Since the error source corresponding to the error-inducing data is clear, the error source of the local error data can be determined according to the error-inducing data. Finally, the system health monitoring can be performed according to the error source and the fault level, so that the relevant personnel can make corresponding health adjustments to the target chip according to the error source and the fault level.

[0055] Furthermore, timestamp data can be added to the error source and error level based on the current system time to obtain the error information to be displayed, and the error information to be displayed can be displayed through the system front end. In this way, the error information can be displayed intuitively so that the user can directly understand the error information, which effectively improves the user's experience.

[0056] It can be seen that in this embodiment, the excitation data when the system is powered on can be collected, and then the excitation data can be run and the obtained operation results can be compared with the preset simulation results. If the obtained comparison results are inconsistent with the preset simulation results, it indicates that there is an operation error at present, and it is necessary to count the operation error data and generate the corresponding error code, and then send the operation results and error codes to the host computer so that the host computer can determine the error source and fault level based on the received information, and then perform system health monitoring based on the error source and the fault level. In this way, the source of the error in the chip can be located and the fault level of the error can be determined, and then the system health monitoring can be performed through the error source and the fault level.

[0057] See also Figure 2 As shown, an embodiment of the present invention discloses a health monitoring interaction logic of a logic design system, including:

[0058] like Figure 2 As shown, the target chip includes a main logic module and a system health detection module, and the system health detection module includes a data packaging module, a timestamp module, a state monitoring module, an excitation module, an error injection module, a data packet parsing module, a self-test module, an error statistics module, and an error isolation module. Among them, the logic of health detection is as follows: when the system is powered on, the excitation module generates power-on excitation data, and packages it through the data packaging module and sends it to the main logic module. The main logic module receives the excitation data, unpacks it, and runs it, and then sends the running result to the self-test module. The self-test module compares the running result with the preset simulation result saved in the excitation module. If the result is the same, the result and data are packaged and sent to the host computer. If the result is wrong, the running result and the comparison result are sent to the error statistics module. The error statistics module counts the errors and gives the corresponding error code. At the same time, the error isolation module is turned on, the main logic module is reset according to the error code, and the error code is packaged and sent to the host computer. Fault diagnosis is performed on the host computer according to the error code. The fault diagnosis module further sends a command to the error injection module, which injects error-inducing data corresponding to the error code according to the error code to determine which specific module the error of the main logic module comes from, and feeds back the final result to the host computer.

[0059] Furthermore, after the system is powered on, the main logic module will package the status data of each module and send it to the system health monitoring module. The status monitoring module in the system health monitoring module will classify these status data, add timestamps, and send them to the real-time monitoring module of the host computer through the network port for display. If an error occurs, the error statistics module will count the errors and analyze the error level. If the level is a fatal error or a serious error, the main logic module will be reset and stopped. If the error level is a general error, the module with the error source will be isolated. All data from the system health monitoring will be sent to the host computer in real time for fault diagnosis and health prediction assessment.

[0060] See also Figure 3 As shown, an embodiment of the present invention discloses a health monitoring device for a logic design system, which is applied to a target chip, and includes:

[0061] The data comparison module 11 is used to run the collected excitation data generated when the system is powered on, and compare the obtained running results with the preset simulation results to obtain corresponding comparison results;

[0062] an error code generating module 12, configured to collect operation error data based on the comparison result and generate an error code corresponding to the operation error data if the comparison result indicates that the operation result is inconsistent with the preset simulation result;

[0063] The health monitoring module 13 is used to send the operation result and the error code to the host computer, so that the host computer determines the error source and the fault level according to the error code and the operation result, and then performs system health monitoring based on the error source and the fault level.

[0064] In some embodiments, the data comparison module 11 may specifically include:

[0065] A data packaging unit is used to collect the excitation data generated when the system is powered on, and to package the collected excitation data to obtain an excitation data packet;

[0066] A first data operation unit, used for sending the stimulus data packet to the main logic component, so that the main logic component unpacks the stimulus data packet and runs the unpacked stimulus data to generate a corresponding operation result;

[0067] The data comparison unit is used to compare the operation result and the preset simulation operation result to determine whether the operation result is completely consistent with the preset simulation operation result, and generate a corresponding comparison result; the preset simulation operation result is an error-free operation result.

[0068] In some embodiments, the error code generating module 12 may specifically include:

[0069] an error data determining unit, configured to determine target data in the operation result that is inconsistent with the preset simulation result according to the comparison result if the comparison result indicates that the operation result is inconsistent with the preset simulation result, and use the target data as error data;

[0070] The error code generating unit is used to count the power-on errors and running state errors corresponding to the error data, and generate error codes corresponding to the error data according to the power-on errors and running state errors.

[0071] In some embodiments, the health monitoring module 13 may specifically include:

[0072] an error type determination unit, configured to determine whether the operation state error causes a system error according to the operation state error corresponding to the error code and the operation result;

[0073] A fault level determination unit is used to determine the fault level based on a system error type corresponding to the system error if the operating state error leads to a system error; the system error type includes system shutdown, system function error and warning error.

[0074] In some embodiments, the health monitoring module 13 may specifically include:

[0075] A data screening submodule, used for analyzing the error code to determine the error type corresponding to the error code, and screening the error-inducing data corresponding to the error type from a preset cache; the error-inducing data is preset data for inducing a running error;

[0076] The error source determination submodule is used to send the error inducing data to the target chip, so that the target chip runs the error inducing data after receiving the error inducing data, and determines the error source based on the obtained target running result.

[0077] In some embodiments, the error source determination submodule may further include:

[0078] A second data operation unit, used for operating the error-inducing data to obtain a target operation result corresponding to the error-inducing data;

[0079] The error source determination unit is used to determine the error source that locally triggers the error data if the target operation result characterizes the occurrence of error data of the same error type.

[0080] In some embodiments, the health monitoring device of the logic design system may further include:

[0081] The information display unit is used to add timestamp data to the error source and the error level based on the current system time to obtain the error information to be displayed, and display the error information to be displayed through the system front end.

[0082] Furthermore, the present application also discloses an electronic device. Figure 4 This is a structural diagram of an electronic device 20 according to an exemplary embodiment. The content in the diagram cannot be regarded as any limitation on the scope of use of the present application.

[0083] Figure 4 A schematic diagram of the structure of an electronic device 20 provided in an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the health monitoring method of the logic design system disclosed in any of the aforementioned embodiments. In addition, the electronic device 20 in this embodiment may specifically be an electronic computer.

[0084] In this embodiment, the power supply 23 is used to provide working voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and the external device, and the communication protocol it follows is any communication protocol that can be applied to the technical solution of the present application, and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0085] In addition, the memory 22 as a carrier for resource storage may be a read-only memory, a random access memory, a disk or an optical disk, etc. The resources stored thereon may include an operating system 221, a computer program 222, etc., and the storage method may be temporary storage or permanent storage.

[0086] The operating system 221 is used to manage and control the hardware devices on the electronic device 20 and the computer program 222, which can be Windows Server, Netware, Unix, Linux, etc. In addition to including a computer program that can be used to complete the health monitoring method of the logic design system executed by the electronic device 20 disclosed in any of the aforementioned embodiments, the computer program 222 can further include a computer program that can be used to complete other specific tasks.

[0087] Furthermore, the present application also discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, the aforementioned disclosed logic design system health monitoring method is implemented. For the specific steps of the method, reference may be made to the corresponding contents disclosed in the aforementioned embodiments, and no further description will be given here.

[0088] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0089] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0090] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0091] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0092] The technical solution provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technicians in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A health monitoring method for a logic design system, characterized in that: Applied to target chips, including: Run the collected stimulus data generated when the system is powered on, and compare the obtained running results with the preset simulation results to obtain corresponding comparison results; If the comparison result indicates that the operation result is inconsistent with the preset simulation result, counting operation error data based on the comparison result, and generating an error code corresponding to the operation error data; The operation result and the error code are sent to a host computer so that the host computer can determine the error source and the fault level according to the error code and the operation result, and then perform system health monitoring based on the error source and the fault level.

2. The health monitoring method of a logic design system according to claim 1, characterized in that: The operation collects the excitation data generated when the system is powered on, and compares the obtained operation result with the preset simulation result to obtain a corresponding comparison result, including: Collecting the stimulus data generated when the system is powered on, and packaging the collected stimulus data to obtain a stimulus data packet; Sending the stimulus data packet to the main logic component so that the main logic component unpacks the stimulus data packet and runs the unpacked stimulus data to generate corresponding running results; The operation result and the preset simulation operation result are compared to determine whether the operation result is completely consistent with the preset simulation operation result, and a corresponding comparison result is generated; the preset simulation operation result is a result of error-free operation.

3. The health monitoring method of a logic design system according to claim 1, characterized in that: If the comparison result indicates that the operation result is inconsistent with the preset simulation result, counting operation error data based on the comparison result and generating an error code corresponding to the operation error data include: If the comparison result indicates that the operation result is inconsistent with the preset simulation result, determining target data in the operation result that is inconsistent with the preset simulation result according to the comparison result, and using the target data as error data; Power-on errors and operating state errors corresponding to the error data are counted, and error codes corresponding to the error data are generated according to the power-on errors and operating state errors.

4. The health monitoring method of a logic design system according to claim 3, characterized in that: Determining the fault level according to the error code and the operation result includes: Determine whether the running state error causes a system error according to the running state error corresponding to the error code and the running result; If the operating status error leads to a system error, the fault level is determined based on a system error type corresponding to the system error; the system error type includes system shutdown, system function error, and warning error.

5. The health monitoring method of a logic design system according to claim 1, characterized in that: Determining the source of the error according to the error code and the operation result includes: Analyze the error code to determine the error type corresponding to the error code, and filter error-inducing data corresponding to the error type from a preset cache; the error-inducing data is preset data that induces a running error; The error inducing data is sent to the target chip, so that the target chip runs the error inducing data after receiving the error inducing data, and determines the source of the error based on the obtained target running result.

6. The health monitoring method of a logic design system according to claim 5, characterized in that: The running the error-inducing data and determining the source of the error based on the obtained target running result includes: Running the error-inducing data to obtain a target running result corresponding to the error-inducing data; If the target operation result indicates that error data of the same error type appears, the error source causing the error data locally is determined.

7. The health monitoring method of a logic design system according to any one of claims 1 to 6, characterized in that: Also includes: Timestamp data is added to the error source and the error level based on the current system time to obtain error information to be displayed, and the error information to be displayed is displayed through the system front end.

8. A health monitoring device for a logic design system, characterized in that: Applied to target chips, including: The data comparison module is used to run the collected stimulus data generated when the system is powered on, and compare the obtained running results with the preset simulation results to obtain corresponding comparison results; an error code generating module, configured to collect operation error data based on the comparison result and generate an error code corresponding to the operation error data if the comparison result indicates that the operation result is inconsistent with the preset simulation result; The health monitoring module is used to send the operation result and the error code to the host computer, so that the host computer can determine the error source and the fault level according to the error code and the operation result, and then perform system health monitoring based on the error source and the fault level.

9. An electronic device, characterized in that: include: Memory, used to store computer programs; A processor, configured to execute the computer program to implement the health monitoring method for a logic design system as claimed in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: Used to store a computer program, wherein when the computer program is executed by a processor, the health monitoring method for a logic design system according to any one of claims 1 to 7 is implemented.

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