Time sequence detection circuit, chip, electronic equipment and time sequence detection method

Abstract

The invention relates to a time sequence detection circuit, a chip, electronic equipment and a time sequence detection method, and the circuit comprises a signal generation module which is used for generating an excitation signal and a frequency division clock signal; the time delay module is used for performing time delay processing on the excitation signal to generate a time delay signal; and the signal detection module is used for taking the frequency division clock signal as a sampling reference, performing periodic detection on the delay signal, and generating a state signal for representing a time sequence state of the delay signal according to a detection result so as to realize real-time monitoring of the time sequence margin in the chip, thereby being capable of giving an alarm in time before a time sequence risk occurs, and improving the reliability of the chip. And the safety of the chip is ensured.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a timing detection circuit, a chip, an electronic device and a timing detection method. Background Art

[0002] In electronic devices, System On Chip (SOC) is a core component responsible for handling various complex tasks to ensure the normal operation of electronic devices. However, these chips may also become targets of malicious attackers. Attackers may increase the operating frequency by manipulating the chip's clock path registers, or reduce the operating voltage by adjusting the power path registers. These operations will cause the chip's internal logic circuits to deviate from their normal operating characteristics, increase timing risks, and thus may trigger error injection attacks, posing a threat to the chip's security. Summary of the invention

[0003] The present application provides a timing detection circuit, chip, electronic device and timing detection method. The present application generates an excitation signal and a frequency-divided clock signal through a signal generation module, delays the excitation signal through a delay module, generates a delay signal, uses the frequency-divided clock signal as a sampling reference through a signal detection module, periodically detects the delay signal, and generates a status signal for characterizing the timing state of the delay signal according to the detection result, so as to realize real-time monitoring of the timing margin inside the chip, so as to be able to issue an alarm in time before the timing risk occurs, and ensure the safety of the chip. The technical solution of the present application is as follows:

[0004] The first embodiment of the present application provides a timing detection circuit, including:

[0005] A signal generating module, used for generating an excitation signal and a frequency-divided clock signal;

[0006] A delay module, used for performing delay processing on the excitation signal to generate a delay signal;

[0007] The signal detection module is used to use the divided clock signal as a sampling reference, perform periodic detection on the delayed signal, and generate a status signal according to the detection result; wherein the status signal is used to characterize the timing state of the delayed signal.

[0008] A second embodiment of the present application provides a chip, comprising: a timing detection circuit as described above.

[0009] A third aspect of the present application provides an electronic device, including: the timing detection circuit as described above.

[0010] A fourth aspect of the present application provides a timing detection method, including:

[0011] Generate an excitation signal and a frequency-divided clock signal;

[0012] Performing delay processing on the excitation signal to generate a delay signal;

[0013] The frequency-divided clock signal is used as a sampling reference to periodically detect the delay signal, and a state signal is generated according to the detection result; wherein the state signal is used to characterize the timing state of the delay signal.

[0014] The fifth aspect embodiment of the present application proposes a non-temporary computer-readable storage medium, on which computer program instructions are stored. When the computer program instructions are executed by a processor, the steps of the above-mentioned timing detection method are implemented.

[0015] The sixth aspect of the present application provides a computer program product, including a computer program, which implements the steps of the above-mentioned timing detection method when executed by a processor.

[0016] The technical solution provided by the embodiments of the present application brings at least the following beneficial effects:

[0017] The timing detection circuit of the embodiment of the present application includes a signal generating module, a delay module and a signal detection module, wherein the signal generating module is used to generate an excitation signal and a divided clock signal, the delay module is used to perform delay processing on the excitation signal to generate a delay signal, and the signal detection module is used to use the divided clock signal as a sampling reference, perform periodic detection on the delay signal, and generate a status signal for characterizing the timing state of the delay signal based on the detection result, so as to realize real-time monitoring of the internal timing margin of the chip, and can issue an alarm in time before the timing risk occurs to ensure the safety of the chip.

[0018] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application, and do not constitute an improper limitation on the present application.

[0020] Figure 1 is a schematic diagram of a timing detection circuit according to an embodiment of the present application;

[0021] Figure 2 is a circuit diagram of a timing detection circuit according to an embodiment of the present application;

[0022] Figure 3 is a timing diagram of a timing detection circuit according to an embodiment of the present application when the operating frequency changes;

[0023] Figure 4 is a timing diagram of a timing detection circuit according to an embodiment of the present application when the operating voltage changes;

[0024] Figure 5 It is a flowchart of a timing detection method according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to enable ordinary persons in the art to better understand the technical solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0026] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims.

[0027] The following describes a timing detection circuit, a chip, an electronic device, and a timing detection method according to embodiments of the present application with reference to the accompanying drawings.

[0028] The critical timing paths within the chip are affected by many factors, including process fluctuations, voltage changes, frequency adjustments, and aging effects. During the design phase, it is very difficult to find the most critical path because these factors may be different in the actual working environment. Traditional direct measurement methods require precise modeling and verification of each possible critical path, which not only increases the complexity of the design, but may also extend the design cycle.

[0029] To this end, the present application proposes an indirect measurement method, which simulates the critical path in the actual circuit by constructing an adjustable delay path. The delay of this delay path is close to a normal working cycle and is used for safety timing detection, which can avoid the selection of the critical path in the design stage.

[0030] Figure 1 is a schematic diagram of a timing detection circuit according to an embodiment of the present application.

[0031] like Figure 1 As shown, the timing detection circuit 100 of the embodiment of the present application includes: a signal generating module 101, a delay module 103 and a signal detection module 104.

[0032] The signal generating module 101 is used to generate the excitation signal st and the frequency-divided clock signal clk_div. The delay module 103 is used to perform delay processing on the excitation signal st to generate the delay signal delay. The signal detecting module 104 is used to use the frequency-divided clock signal clk_div as a sampling reference, perform periodic detection on the delay signal delay, and generate a state signal s0 according to the detection result; wherein the state signal s0 is used to characterize the timing state of the delay signal delay.

[0033] Exemplarily, in the present application, the divided clock signal clk_div includes a divided-frequency clock signal.

[0034] Exemplarily, the periodic detection of the delay signal delay may be performed in an edge-triggered manner.

[0035] In this embodiment, the clock signal input end of the signal generating module 101 is used to receive the reference clock signal clk, the first output end of the signal generating module 101 is connected to the input end of the delay module 103, the second output end of the signal generating module 101 is connected to the first input end of the signal detection module 104, the output end of the delay module 103 is connected to the second input end of the signal detection module 104, and the output end of the signal detection module 104 is used to output the state signal s0.

[0036] After receiving the reference clock signal clk, the signal generating module 101 generates an excitation signal st and a divided clock signal clk_div according to the received reference clock signal clk, wherein the excitation signal st is output to the input end of the delay module 103, and the divided clock signal clk_div is output to the first input end of the signal detecting module 104.

[0037] The delay module 103 performs logic delay on the excitation signal st to generate a delay signal delay, the delay of which can cover the maximum logic delay of the detection area to ensure the effectiveness of the detection. The delay signal delay is output to the second input terminal of the signal detection module 104.

[0038] The signal detection module 104 uses the divided clock signal clk_div as a sampling reference, performs periodic detection on the delay signal delay by edge triggering, and outputs a state signal s0 according to the detection result. If the delay time of the delay signal delay can meet the expected value (i.e., the preset setup time requirement), the signal detection module 104 outputs a low-level state signal S0, indicating that no timing risk is detected; if the delay time of the delay signal delay does not meet the expected value, the signal detection module 104 outputs a high-level state signal S0, indicating that a timing risk is detected.

[0039] Therefore, the present application deploys a timing detection circuit 100 in the chip, and the timing detection circuit 100 is composed of a signal generation module 101, a delay module 103 and a signal detection module 104 working together, which significantly reduces the area overhead of the chip; by delaying the processing of the excitation signal, it can ensure that the timing detection circuit 100 can cover all critical paths, thereby realizing real-time monitoring of the timing margin inside the chip; by periodically detecting the delay signal, an alarm can be issued in time before the timing risk occurs, thereby ensuring the safety of the chip. Therefore, the timing detection circuit 100 of the present application is suitable for various complex SOC designs.

[0040] In order to enable those skilled in the art to more clearly understand the timing detection circuit 100 of the embodiment of the present application. Figure 2 The circuit diagram of the timing detection circuit 100 is shown in FIG.

[0041] like Figure 2 As shown, the signal generating module 101 of the embodiment of the present application includes: a clock gating unit ICG and a frequency dividing unit 102.

[0042] Among them, the clock input terminal clk_in of the clock gating unit ICG serves as the clock signal input terminal of the signal generating module 101, and is used to receive the reference clock signal clk; the enable terminal en of the clock gating unit ICG is used to receive the control signal ctl; the clock gating unit ICG is used to perform gating processing on the reference clock signal clk according to the received control signal ctl, and generate a reference clock signal after gated processing; the output terminal clk_out of the clock gating unit ICG is used to output the gated reference clock signal.

[0043] The input end of the frequency dividing unit 102 is connected to the output end of the clock gating unit ICG, and is used to receive the reference clock signal after gated processing; the frequency dividing unit 102 is used to generate an excitation signal st and a divided clock signal clk_div according to the reference clock signal after gated processing; the first output end of the frequency dividing unit 102 serves as the first output end of the signal generating module 101, and is used to output the excitation signal st; the second output end of the frequency dividing unit 102 serves as the second output end of the signal generating module 101, and is used to output the divided clock signal clk_div.

[0044] In this embodiment, the frequency division unit 102 includes: a counter (not shown in the figure). The counter is used to count the reference clock signal after the gate control process, and to clear the count value when it reaches a preset value such as 2, and to synchronously generate an excitation signal st when the 0th bit of the count value is flipped; wherein the frequency division clock signal clk_div is generated under the triggering of the excitation signal st.

[0045] like Figure 2As shown, the signal generating module 101 further includes: an AND gate unit 107 .

[0046] Among them, the first input end of the AND gate unit 107 is used to receive the enable signal en; the second input end of the AND gate unit 107 is used to receive the state signal s0' after inversion processing; the AND gate unit 107 is used to generate the control signal ctl according to the received enable signal en and the state signal s0' after inversion processing; the output end of the AND gate unit 107 is connected to the enable end en of the clock gating unit ICG, and is used to output the control signal ctl.

[0047] like Figure 2 As shown, the timing detection circuit 100 further includes: a first inverter 108 .

[0048] Among them, the input end of the first inverter 108 is connected to the output end of the signal detection module 104, and is used to receive the state signal s0 output by the signal detection module 104; the first inverter 108 is used to invert the state signal s0 to generate the inverted state signal s0'; the output end of the first inverter 108 is connected to the second input end of the AND gate unit 107, and is used to output the inverted state signal s0'.

[0049] like Figure 2 As shown, the delay module 103 of the embodiment of the present application includes: a delay chain and a selector 106.

[0050] The delay chain includes a plurality of delay units 105 connected in series.

[0051] The input end of the first delay unit 105 is connected to the first output end of the frequency division unit 102, and is used to receive the excitation signal st; the first delay unit 105 is used to perform a first delay processing on the excitation signal st to generate an excitation signal after the first delay processing; the output end of the first delay unit 105 is respectively connected to the input end of the second delay unit 105 and the first input end of the selector 106, and is used to output the excitation signal after the first delay processing.

[0052] The input end of the second delay unit 105 is connected to the output end of the first delay unit 105, and is used to receive the excitation signal after the first delay processing; the second delay unit 105 is used to perform another delay processing on the excitation signal after the first delay processing, that is, to perform a second delay processing on the excitation signal to generate an excitation signal after the second delay processing; the output end of the second delay unit 105 is respectively connected to the input end of the second delay unit 105 and the second input end of the selector 106, and is used to output the excitation signal after the second delay processing.

[0053] The same goes for the third delay unit 105 , . . . , and the Nth delay unit 105 .

[0054] The selection end of the selector 106 is used to receive the selection signal sel; the selector 106 is used to select an excitation signal after delay processing output by a delay unit 105 from the delay chain according to the received selection signal sel as the delay signal delay; the output end of the selector 106 outputs the delay signal delay.

[0055] like Figure 2 As shown, the signal detection module 104 includes: a second inverter 109 and a trigger DFF.

[0056] The input end of the second inverter 109 is used to receive the delay signal delay; the second inverter 109 is used to invert the delay signal delay to generate an inverted delay signal; the output end of the second inverter 109 is used to output the inverted delay signal.

[0057] The D input terminal of the trigger DFF is used to receive the delayed signal after inversion processing; the clock input terminal of the trigger DFF is used to receive the divided clock signal clk_div; the trigger DFF is used to capture the rising edge of the delayed signal after inversion processing at each rising edge moment of the divided clock signal clk_div, and generate a state signal s0 according to the relative timing relationship between the captured rising edge of the delayed signal after inversion processing and the rising edge of the divided clock signal; the Q output terminal of the trigger DFF is used to output the state signal s0.

[0058] The generation logic of the state signal s0 is as follows:

[0059] If the rising edge of the captured delayed signal after inversion processing appears before the rising edge of the divided clock signal clk_div, a low-level status signal is generated. In other words, if the delay time of the delay signal delay meets the expected value, it indicates that the chip is not attacked by DVFS (Dynamic Voltage and Frequency Scaling), and a low-level status signal s0 is output at this time, indicating that no timing risk is detected.

[0060] If the rising edge of the captured delayed signal after inversion processing appears after the rising edge of the divided clock signal clk_div, a high-level status signal is generated. In other words, if the delay time of the delay signal delay does not meet the expected value, it indicates that the chip may be attacked by DVFS. At this time, the output status signal s0 is pulled high, indicating that a timing risk is detected.

[0061] Therefore, the timing detection circuit 100 of the embodiment of the present application can reserve sufficient margin for detection by using the divided clock signal clk_div as the sampling reference, avoiding false detection caused by the imbalance of the rising edge and the falling edge of the delay chain, and periodically detects the delayed signal after inversion processing through edge triggering to determine whether the delay time of the delayed signal meets the expected value, so as to detect whether the chip is attacked by DVFS. Therefore, the timing detection circuit 100 of the embodiment of the present application can ensure that the detection result is still accurate and reliable even under different process conditions and working environments.

[0062] Figure 3 1 is a timing diagram of a timing detection circuit according to an embodiment of the present application when the operating frequency changes. Figure 3 In the timing diagram of the timing detection circuit 100 shown in FIG. 1 , the reset signal reset_n is used to initialize the state of the timing detection circuit 100. When reset_n is at a high level, the timing detection circuit 100 starts to work and performs timing detection.

[0063] Figure 4 1 is a timing diagram of a timing detection circuit according to an embodiment of the present application when the operating voltage changes. Figure 4 In the timing diagram of the timing detection circuit 100 shown in FIG. 1 , the reset signal reset_n is used to initialize the state of the timing detection circuit 100. When reset_n is at a high level, the timing detection circuit 100 starts to work and performs timing detection.

[0064] like Figure 3 and Figure 4 As shown, the divided clock signal clk_div is explained by taking the three-frequency clock signal as an example. The timing detection circuit 100 of the embodiment of the present application completes a safety detection every 3 clock cycles to ensure that the detection frequency is high enough to detect potential problems before the timing risk occurs. The high-level pulse width used for timing detection each time is 1 clock cycle, and the low-level pulse width is 2 clock cycles; wherein, the clock cycle of 1 high-level pulse width ensures that the detection window meets the requirements of the timing detection circuit, and no leakage detection caused by too small pulse width will occur; the clock cycle of 2 low-level pulse widths provides sufficient recovery time to ensure the accuracy of detection; the timing margin of 1 low-level pulse width clock cycle between the high-level and low-level pulses ensures sufficient delay difference compensation to avoid false detection caused by the rise and fall delay differences caused by the differences between PMOS (P-channel Metal-Oxide-Semiconductor, P-channel Metal-Oxide Semiconductor Field Effect Transistor) and NMOS (N-channel Metal-Oxide-Semiconductor, N-channel Metal-Oxide Semiconductor Field Effect Transistor) devices.

[0065] Continue to refer Figure 3 , when the operating frequency increases, the delay time of the excitation signal st through the delay module 103 remains unchanged, but becomes shorter relative to the period of the divided clock signal clk_div, resulting in a delay in the delay signal delay output by the delay module 103 relative to the rising edge of the divided clock signal clk_div. That is, the rising edge of the delay signal delay is later than the rising edge of the divided clock signal clk_div. At this time, since the delay signal delay cannot be sampled as a high level at the rising edge of the divided clock signal clk_div, the output state signal s0 is pulled high, indicating that a timing risk is detected.

[0066] Continue to refer Figure 4 , when the working voltage decreases, the delay time of the excitation signal st through the delay module 103 will increase and exceed a normal working clock cycle. That is, the delay of the delay signal delay is greater than a normal working clock cycle. At this time, since the rising edge of the divided clock signal clk_div cannot sample the delay signal delay as a high level, the output state signal s0 is pulled high, indicating that a timing risk is detected.

[0067] When a timing risk is detected and a status signal is issued (i.e. used as an alarm signal), the clock gating unit ICG will gate the received reference clock signal clk and temporarily stop the transmission of the reference clock signal clk. This mechanism can not only reduce power consumption, but also reduce unnecessary clock activities when potential timing problems are detected, ensuring the safety of the system.

[0068] Therefore, the timing detection circuit of the embodiment of the present application is responsible for monitoring the timing margin of the timing path, and issuing an alarm or taking corresponding measures (such as reducing the operating frequency, increasing the operating voltage, shutting down some functions, etc.) when the timing margin is insufficient. It can cope with the timing risks brought about by frequency changes and voltage reductions, and ensure chip safety.

[0069] To summarize, the timing detection circuit of the embodiment of the present application includes a signal generating module, a delay module and a signal detection module, wherein the signal generating module is used to generate an excitation signal and a divided clock signal, the delay module is used to perform delay processing on the excitation signal to generate a delay signal, and the signal detection module is used to use the divided clock signal as a sampling reference, perform periodic detection on the delay signal, and generate a status signal for characterizing the timing state of the delay signal according to the detection result, so as to realize real-time monitoring of the internal timing margin of the chip, and be able to issue an alarm in time before the timing risk occurs to ensure the safety of the chip.

[0070] Based on the above embodiments, the present application also proposes a chip, which includes the above timing detection circuit.

[0071] In the embodiments of the present application, the chip may be an application-specific integrated circuit (ASIC) or a field programmable gate array (FPGA).

[0072] It should be noted that for details not disclosed in the chip of the embodiment of the present application, please refer to the details disclosed in the timing detection circuit of the embodiment of the present application, and the details will not be repeated here.

[0073] The chip of the embodiment of the present application, by using the above-mentioned timing detection circuit, can realize real-time monitoring of the internal timing margin of the chip and issue an alarm in time before the timing risk occurs, thereby ensuring the safety of the chip.

[0074] Based on the above embodiments, the present application also proposes an electronic device, which includes the above timing detection circuit.

[0075] In the embodiments of the present application, the electronic device may be a vehicle, a mobile phone, a computer, a digital broadcast terminal, a messaging device, a game console, a tablet device, a medical device, a fitness device, a personal digital assistant, etc.

[0076] It should be noted that for details not disclosed in the electronic device of the embodiment of the present application, please refer to the details disclosed in the timing detection circuit of the embodiment of the present application, and the details will not be repeated here.

[0077] The electronic device of the embodiment of the present application, by using the above-mentioned timing detection circuit, can realize real-time monitoring of the internal timing margin of the chip and issue an alarm in time before the timing risk occurs, thereby ensuring the safety of the chip.

[0078] Figure 5 is a flowchart of a timing detection method according to an embodiment of the present application.

[0079] like Figure 5 As shown, the timing detection method of the embodiment of the present application includes:

[0080] S1 generates an excitation signal and a divided clock signal.

[0081] S2, delay processing is performed on the excitation signal to generate a delayed signal.

[0082] S3, using the divided clock signal as a sampling reference, periodically detecting the delayed signal, and generating a state signal according to the detection result; wherein the state signal is used to characterize the timing state of the delayed signal.

[0083] In one embodiment of the present application, generating an excitation signal and a frequency-divided clock signal includes:

[0084] Performing gate control on the reference clock signal according to the received control signal to generate a gated reference clock signal;

[0085] An excitation signal and a frequency-divided clock signal are generated according to the reference clock signal after gate control processing.

[0086] In one embodiment of the present application, the steps of generating the excitation signal are as follows:

[0087] Counting the reference clock signal after gate control, clearing the count value when it reaches a preset value, and synchronously generating an excitation signal when the 0th bit of the counter count value flips;

[0088] The frequency-divided clock signal is generated under the triggering of the excitation signal.

[0089] In one embodiment of the present application, the steps of generating the control signal are as follows:

[0090] A control signal is generated according to the received enable signal and the inverted state signal.

[0091] In one embodiment of the present application, delay processing is performed on the excitation signal to generate a delay signal, including:

[0092] According to the received selection signal, an excitation signal after delay processing output by a delay unit is selected from the delay chain as a delay signal.

[0093] In one embodiment of the present application, the frequency-divided clock signal is used as a sampling reference, the delay signal is periodically detected, and a status signal is generated according to the detection result, including:

[0094] Performing inversion processing on the delayed signal to generate an inverted delayed signal;

[0095] At each rising edge of the frequency-divided clock signal, the rising edge of the delayed signal after the inversion process is captured;

[0096] A state signal is generated according to the relative timing relationship between the rising edge of the delayed signal after the inversion processing and the rising edge of the divided clock signal.

[0097] In one embodiment of the present application, a state signal is generated according to the relative timing relationship between the rising edge of the delayed signal after the inversion processing and the rising edge of the divided clock signal, including:

[0098] In response to the rising edge of the captured delayed signal after inversion processing occurring before the rising edge of the divided clock signal, a low-level state signal is generated;

[0099] In response to the captured rising edge of the delayed signal after the inversion process occurring after the rising edge of the divided clock signal, a high level state signal is generated.

[0100] It should be noted that for details not disclosed in the timing detection method of the embodiment of the present application, please refer to the details disclosed in the timing detection circuit of the embodiment of the present application, and the details will not be repeated here.

[0101] The timing detection method of the embodiment of the present application first generates an excitation signal and a frequency-divided clock signal, then performs delay processing on the excitation signal to generate a delay signal, then uses the frequency-divided clock signal as a sampling reference, performs periodic detection on the delay signal, and generates a state signal for characterizing the timing state of the delay signal based on the detection result. As a result, the method can realize real-time monitoring of the internal timing margin of the chip, and issue an alarm before the timing risk occurs, thereby ensuring the safety of the chip.

[0102] Based on the above embodiments, the present application proposes a non-transitory computer-readable storage medium.

[0103] The non-temporary computer-readable storage medium of the embodiment of the present application stores computer program instructions, and when the computer program instructions are executed by a processor, the steps of the timing detection method as described above are implemented.

[0104] Based on the above embodiments, the present application proposes a computer program product.

[0105] The computer program product of the embodiment of the present application includes a computer program, and when the computer program is executed by a processor, the steps of the timing detection method as described above are implemented.

[0106] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0107] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of this application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0108] Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, fragment or portion of code comprising one or more executable instructions for implementing the steps of a custom logical function or process, and the scope of the preferred embodiments of the present application includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in the reverse order depending on the functions involved, which should be understood by technicians in the technical field to which the embodiments of the present application belong.

[0109] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as an ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For the purposes of this specification, "computer-readable medium" can be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses. More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wirings (electronic devices), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and editable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0110] It should be understood that the various parts of the present application can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, a plurality of steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA for short), a field programmable gate array (FPGA for short), etc.

[0111] A person skilled in the art may understand that all or part of the steps in the method for implementing the above-mentioned embodiment may be completed by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, which, when executed, includes one or a combination of the steps of the method embodiment.

[0112] In addition, each functional unit in each embodiment of the present application may be integrated into a processing module, or each unit may exist physically separately, or two or more units may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of a software functional module. If the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0113] The storage medium mentioned above may be a read-only memory, a magnetic disk or an optical disk, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limiting the present application. A person of ordinary skill in the art may change, modify, replace and modify the above embodiments within the scope of the present application.

[0114] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the appended claims.

[0115] It should be understood that the present application is not limited to the precise structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A timing detection circuit, characterized in that: include: A signal generating module, used for generating an excitation signal and a frequency-divided clock signal; A delay module, used for performing delay processing on the excitation signal to generate a delay signal; The signal detection module is used to use the divided clock signal as a sampling reference, perform periodic detection on the delayed signal, and generate a status signal according to the detection result; wherein the status signal is used to characterize the timing state of the delayed signal.

2. The timing detection circuit according to claim 1, characterized in that: The signal generating module comprises: A clock gating unit, used to perform gating processing on the reference clock signal according to the received control signal, and generate a reference clock signal after the gating processing; The frequency division unit is used to generate the excitation signal and the frequency-divided clock signal according to the reference clock signal after gate control processing.

3. The timing detection circuit according to claim 2, characterized in that: The frequency division unit comprises: A counter, used for counting the reference clock signal after the gate control process, clearing the count value when it reaches a preset value, and synchronously generating the excitation signal when the 0th bit of the count value is flipped; The frequency-divided clock signal is generated under the triggering of the excitation signal.

4. The timing detection circuit according to claim 2 or 3, characterized in that: The signal generating module further includes: The AND gate unit is used to generate the control signal according to the received enable signal and the inverted state signal.

5. The timing detection circuit according to claim 4, characterized in that: The timing detection circuit further includes: The first inverter is used to perform inversion processing on the state signal to generate the inverted state signal.

6. The timing detection circuit according to claim 1, characterized in that: The delay module comprises: A delay chain, the delay chain comprising a plurality of delay units connected in series, each of the delay units being used to perform delay processing on the excitation signal; The selector is used to select an excitation signal after delay processing output by the delay unit from the delay chain according to a received selection signal as the delay signal.

7. The timing detection circuit according to claim 1, characterized in that: The signal detection module comprises: A second inverter is used to perform inversion processing on the delayed signal to generate an inverted delayed signal; A trigger is used to capture the rising edge of the delayed signal after inversion processing at each rising edge of the divided clock signal, and generate the status signal according to the relative timing relationship between the captured rising edge of the delayed signal after inversion processing and the rising edge of the divided clock signal.

8. The timing detection circuit according to claim 7, characterized in that: The trigger is used to capture the relative timing relationship between the rising edge of the delayed signal after the inversion process and the rising edge of the divided clock signal, including: In response to the captured rising edge of the delayed signal after inversion processing occurring before the rising edge of the divided clock signal, generating the state signal of low level; In response to the captured rising edge of the delayed signal after the inversion process occurring after the rising edge of the divided clock signal, the state signal of a high level is generated.

9. A chip, characterized in that: include: A timing detection circuit as claimed in any one of claims 1 to 8.

10. An electronic device, characterized in that: include: A timing detection circuit as claimed in any one of claims 1 to 8.

11. A timing detection method, characterized in that: include: Generate an excitation signal and a frequency-divided clock signal; Performing delay processing on the excitation signal to generate a delay signal; The frequency-divided clock signal is used as a sampling reference to periodically detect the delay signal, and a state signal is generated according to the detection result; wherein the state signal is used to characterize the timing state of the delay signal.

12. A non-transitory computer-readable storage medium having computer program instructions stored thereon, characterized in that: When the computer program instructions are executed by a processor, the steps of the timing detection method according to claim 11 are implemented.

13. A computer program product, characterized in that The method comprises a computer program, and when the computer program is executed by a processor, the steps of the timing detection method according to claim 11 are implemented.

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