Multi-device multi-channel power data synthesis method and storage medium
Through the multi-device and multi-channel power data synthesis method, the power data during separate operation is synthesized into the power data during the simultaneous operation of multiple electrical appliances, which solves the problem that the prior art cannot accurately predict the power consumption during the simultaneous operation of multiple electrical appliances, and achieves higher load prediction accuracy and reduced electricity consumption costs.
Patent Information
- Application Number
- CN202510127099.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-30
- Publication Date
- 2025-05-09
AI Technical Summary
The prior art cannot effectively utilize power data during separate operation to accurately predict power consumption during simultaneous operation of multiple appliances, especially in power monitoring and optimization systems.
A multi-device multi-channel power data synthesis method is proposed, including steps such as data acquisition, voltage data cleaning, upsampling, full-period extraction, resampling, judgment, downsampling, data correction, data synthesis and synthetic data downsampling. Through these steps, the power data during separate operation is synthesized into the power data during the operation of multiple electrical appliances at the same time.
This method can more accurately estimate the power consumption of electrical appliances when they are running simultaneously, improve the accuracy of load prediction and optimization control of the power system, and reduce the power consumption cost of the power system.
Smart Images
Figure CN119961575A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of electrical technology, and in particular to a multi-device multi-channel power data synthesis method and a storage medium. Background Art
[0002] In modern power systems, the operation of multiple electrical appliances often leads to interactive effects on power consumption. Generally, it is easier to obtain power data when an appliance is operating alone, but when multiple appliances are operating at the same time, the changes in power data become more complicated.
[0003] Existing technologies mainly focus on how to process these complex data, but lack a method that can synthesize the power data of multiple appliances when they are running simultaneously from the power data of individual appliances when they are running separately. Especially in power monitoring and optimization systems, how to use the data of individual appliances to accurately predict the power consumption of multiple appliances when they are running simultaneously is still a challenge. Summary of the invention
[0004] The present application provides a multi-device multi-channel power data synthesis method and storage medium to solve the problem that the prior art cannot use data from individual operations to accurately predict the power consumption of multiple electrical appliances when they are running simultaneously.
[0005] The present application proposes a multi-device multi-channel power data synthesis method, which specifically includes a data acquisition step, a voltage data cleaning step, an upsampling step, a complete cycle extraction step, a resampling step, a judgment step, a downsampling step, a data correction step, a data synthesis step and a synthesized data downsampling step.
[0006] The data acquisition step is used to acquire more than two groups of data, each group of data comes from different devices, the devices include a first device and a second device, and the current data and voltage data in each group of data come from different channels; the voltage data cleaning step is to clean the voltage data, and use the median filtering method to find and replace the abnormal values of the voltage data; the upsampling step is based on Fourier transform, upsampling the current data and the voltage data to obtain upsampled current data and upsampled voltage data; the complete cycle extraction step is to perform zero crossing point detection on the upsampled current data and the upsampled voltage data, and calculate the sign change of the sampling points adjacent to the zero crossing point. If the sign change meets the preset condition, the zero crossing point is a zero crossing point, and the data between two adjacent zero crossing points is a set of complete cycle data to obtain a complete cycle; the resampling step is used to set a preset offset, the first device includes first cycle data, the second device includes second cycle data, the number of cycle offsets of the second cycle data relative to the first cycle data is the preset offset, and the second cycle data is resampled with the length of the target length threshold to obtain to the resampled voltage data and the resampled current data; the judging step is used to judge the size relationship between the target length threshold and the length of the second cycle data, if the target length threshold is equal to the length of the second cycle data, then the data correction step is performed; if the target length threshold is greater than the length of the second cycle data, then the up-sampling step is returned; if the target length threshold is less than the length of the second cycle data, then the next step is performed; the down-sampling step is to down-sample the resampled voltage data and the resampled current data so that the target length threshold of the resampled voltage data and the resampled current data is equal to the length of the second cycle data; the data correction step is to correct the obtained resampled current data to obtain the corrected current data; the data synthesis step is to add the corrected current data to the current cycle data in the first cycle data to obtain the initial synthesized current data, and the voltage cycle data in the first cycle data is the initial synthesized voltage data; the synthesized data down-sampling step is to down-sample the initial synthesized current data and the initial synthesized voltage data to obtain the final synthesized voltage data and the final synthesized current data.
[0007] Furthermore, the voltage data cleaning step specifically includes a window forming step, a median calculating step, a residual calculating step and an abnormality judging step.
[0008] The window forming step is used to traverse the voltage data sequence and for each sampling point v i , take the (f-1) / 2 sampling points before and after to form a window, and the formula is
[0009] W i = {vi-(f-1) / 2 ,…,v i ,…,v i+(f-1) / 2}
[0010] Where i represents the sampling point number, i∈[1,L], L represents the length of the voltage data, W i represents the window, v i represents the sampling point, that is, the original signal, and f represents the window size.
[0011] The median calculation step is used to calculate the obtained window W i The median value of is given by
[0012] M i =Median(W i )
[0013] Among them, M i Represents window W i The median value of .
[0014] The residual calculation step is to use the median M i Instead of the original signal v i After that, the filtered signal sequence V′ is formed, and the residual between the filtered signal sequence V′ and the original signal is calculated. The formula is:
[0015] d i =|v i -M i |
[0016] Among them, d i Represents the residual.
[0017] The abnormality judgment step is to set an abnormality threshold T. If d i >T, then determine v i is an abnormal signal, and the abnormal signal v i Replace with the median value M i .
[0018] Furthermore, the upsampling step specifically includes a first frequency domain calculation step, a frequency domain interpolation step and an upsampling signal acquisition step.
[0019] The first frequency domain calculation step is to perform discrete Fourier transform on the current data and the voltage data to obtain the frequency domain, and the formula is:
[0020]
[0021] Where N represents the original signal and X[k] represents the frequency domain signal.
[0022] The frequency domain interpolation step is to increase the number of sampling points according to the need, increase the sample points in the frequency domain, and implement upsampling by inserting zero values in the high-frequency part of the frequency domain. The formula is:
[0023]
[0024] Among them, X new [k] represents the frequency domain after interpolation, MN represents the number of zero values inserted in the frequency domain, M represents the number of up-sampled points, and the length of the frequency domain after interpolation is M, M=A*L, and A is a constant.
[0025] The up-sampling signal acquisition step is to use inverse Fourier transform to interpolate the frequency domain X new [k] is converted back to the time domain to obtain the upsampled signal, whose formula is
[0026]
[0027] Among them, V up Represents the up-sampled voltage data, I up Represents the upsampled current data.
[0028] Furthermore, the complete cycle extraction step specifically includes a voltage cycle acquisition step and a current cycle acquisition step.
[0029] The voltage cycle acquisition step is to sample the voltage data V up Perform zero-crossing detection and calculate the sign change of adjacent voltage sampling points. If the voltage data V is sampled up There is v i <0 and v i+1 >0, then i is the zero crossing point from negative to positive, recorded as Z m , the data between two adjacent zero-crossing points is a complete set of waveform data, so the voltage waveform data V up Can be divided into multiple complete cycle data, Among them DV i Indicates voltage data V up The current cycle acquisition step is based on the voltage cycle to the current data C up Similarly, grouping is performed to obtain DC i Indicates current data C up The ith complete cycle of .
[0030] Furthermore, the downsampling step specifically includes a second frequency domain calculation step, a filter application step, a frequency domain clipping step and a time domain acquisition step.
[0031] The second frequency domain calculation step is to perform discrete Fourier transform on the current data and the voltage data to obtain the frequency domain, and the formula is:
[0032]
[0033] Where N represents the original signal and X[k] represents the frequency domain signal.
[0034] The filter application step is to apply a low-pass filter in the frequency domain, retain the low-frequency part, and set the high-frequency component to zero. The low-pass filter is defined as
[0035]
[0036] Among them, X filtered [k] represents the definition of the low-pass filter, p1 represents the target length threshold, and p2 represents the length of the second frequency data.
[0037] The frequency domain trimming step first takes the first p1 / 2 low-frequency points and copies their conjugate symmetric parts to make the new frequency domain signal length p1, and then discards the high-frequency part to reduce the data length. The trimmed frequency domain signal is
[0038] X down [k] = X filtered [k], k = 0, 1, 2…, p1-1
[0039] Among them, X down [k] represents the cropped frequency domain signal.
[0040] The time domain acquisition step is to obtain the downsampled frequency domain signal X down [k] is converted back to the time domain to obtain a new time domain signal, whose formula is
[0041]
[0042] Among them, x down [n] represents a time domain signal, the number of data points of which is p1. At this time, the target length threshold is equal to the length of the second frequency data.
[0043] Furthermore, the calculation formula of the data correction step is:
[0044] PC2adjust i =PC2 i *PC1 i / PC2 i
[0045] Among them, PC2adjust i Represents the corrected current data of the second device, PC2 iRepresents the resampled current data of the second device, PC1 i Represents the current cycle data of the first device, PC2 i The current cycle data of the second device is represented.
[0046] Furthermore, in the data synthesis step, the calculation formula of the initial synthesized voltage data is:
[0047] VSD i =PV1 i
[0048] Among them, VSD i Indicates the initial composite voltage data, PV1 i representing voltage cycle data of the first device;
[0049] The calculation formula of the initial synthetic current data is:
[0050] CSD i =PC1 i +PC2adjust i
[0051] Among them, CSD i represents the initial synthetic current data, PC1 i Represents the current frequency data of the first device, PC2adjust i The device is indicative of corrected current data for the second device.
[0052] Furthermore, in the synthetic data downsampling step, the calculation formula of the final synthetic voltage data is:
[0053] VR i =VSD i*A
[0054] Among them, VR i Represents the final composite voltage data, VSD i represents the initial synthetic voltage data, A is a constant;
[0055] The calculation formula of the final synthetic current data is:
[0056] CR i =CSD i*A
[0057] Among them, CR i represents the final composite current data, CSD i represents the initial synthetic current data.
[0058] The present application also proposes a storage medium storing computer-readable instructions. When the computer-readable instructions are read by at least one processor, the at least one processor executes at least one step in the multi-device multi-channel power data synthesis method.
[0059] The present application provides a method and storage medium for synthesizing multi-device multi-channel power data, which utilizes multi-channel power data collected when multiple electrical appliances are running individually to synthesize power data of multiple electrical appliances running simultaneously. The present invention can more accurately estimate the power consumption of electrical appliances when they are running simultaneously through the power data of a single electrical appliance when running, thereby improving the accuracy of load prediction and optimal control of the power system and reducing the electricity cost of the power system. BRIEF DESCRIPTION OF THE DRAWINGS
[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.
[0061] Figure 1 is a flow chart of a method for synthesizing multi-device multi-channel power data according to an embodiment of the present application;
[0062] Figure 2 is a flow chart of the voltage data cleaning steps described in an embodiment of the present application;
[0063] Figure 3 is a flow chart of the upsampling step method described in an embodiment of the present application;
[0064] Figure 4 is a flow chart of the complete cycle extraction steps described in the embodiments of the present application;
[0065] Figure 5 is a flow chart of the downsampling steps described in the embodiment of the present application;
[0066] Figure 6 It is a schematic diagram of the storage medium described in an embodiment of the present application.
[0067] Description of reference numerals:
[0068] 100 storage medium, 110 processor, 120 memory. DETAILED DESCRIPTION
[0069] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.
[0070] like Figure 1 As shown, the present application provides a multi-device multi-channel power data synthesis method, which specifically includes step S1) a data acquisition step, step S2) a voltage data cleaning step, step S3) an upsampling step, step S4) a complete cycle extraction step, step S5) a resampling step, step S6) a judgment step, step S7) a downsampling step, step S8) a data correction step, step S9) a data synthesis step and step S10) a synthesized data downsampling step.
[0071] Step S1) data acquisition step, acquiring more than two groups of data, each group of data comes from a different device, the device includes a first device and a second device, and the current data and voltage data in each group of data come from different channels.
[0072] In this embodiment, there are two single-phase electrical devices, namely the first device and the second device. The first device has two channels of data, namely the voltage V1 and the current C1, and V1 and C1 are of equal length L1; the second device has two channels of data, namely the voltage V2 and the current C2, and V2 and C2 are of equal length L2; the voltage and current data of each electrical appliance are collected independently, using a synchronous sampling method, the sampling frequency is not less than 1600Hz, and the sampling accuracy is not less than 16 bits.
[0073] Step S2) A voltage data cleaning step is to clean the voltage data and use a median filtering method to find abnormal values of the voltage data and replace them.
[0074] The voltage data V1 of the first device and the voltage data V2 of the second device are cleaned respectively. The general expression of the voltage data V1 and the voltage data V2 is V={v1,v2,v3,…,v L}, the voltage data length is l.
[0075] like Figure 2 As shown, step S2) the voltage data cleaning step specifically includes step S21) a window forming step, step S22) a median calculating step, step S23) a residual calculating step and step S24) an abnormality judging step.
[0076] Step S21) Window formation step, traversing the voltage data sequence, for each sampling point v i, take the (f-1) / 2 sampling points before and after to form a window, and the formula is
[0077] W i = {v i-(f-1) / 2 ,…,v i ,…,v i+(f-1) / 2}
[0078] Where i represents the sampling point number, i∈[1,L], L represents the length of the voltage data, W i represents the window, v i represents the sampling point, that is, the original signal, and f represents the window size.
[0079] In this embodiment, the window size is usually an odd number, and 3 is used in this embodiment.
[0080] Step S22) median calculation step, calculate the obtained window W i The median value of is given by
[0081] M i =Median(W i )
[0082] Among them, M i Represents window W i The median value of .
[0083] Step S23) Residual calculation step, using the median M i Instead of the original signal v i After that, the filtered signal sequence V′ is formed, and the residual between the filtered signal sequence V′ and the original signal is calculated. The formula is:
[0084] d i =|v i -M i |
[0085] Among them, d i Represents the residual.
[0086] Step S24) abnormality judgment step, by setting the abnormality threshold T, if d i >T, then determine v i is an abnormal signal, and the abnormal signal v i Replace with the median value M i .
[0087] Step S3) upsampling step: based on Fourier transform, upsampling the current data and the voltage data to obtain upsampled current data and upsampled voltage data.
[0088] In this embodiment, four channels are up-sampled, namely, the voltage channel V1 of the first device, the current channel C1 of the first device, the voltage channel V2 of the second device, and the current channel C2 of the second device. The up-sampling target length is 100 times the original length. The up-sampling method is Fourier transform up-sampling. Taking the voltage data V1 of the first device as an example, the original data length is L1, and the target length after up-sampling is 100*L1.
[0089] like Figure 3 As shown, step S3) the upsampling step specifically includes step S31) a first frequency domain calculation step, step S32) a frequency domain interpolation step and step S33) an upsampling signal acquisition step.
[0090] Step S31) The first frequency domain calculation step is to perform discrete Fourier transform on the current data and the voltage data to obtain the frequency domain, and the formula is:
[0091]
[0092] Where N represents the original signal and X[k] represents the frequency domain signal.
[0093] Step S32) frequency domain interpolation step, according to the need to increase the number of sampling points, increase the sample points in the frequency domain, and implement upsampling by inserting zero values in the high-frequency part of the frequency domain. The formula is:
[0094]
[0095] Among them, X new [k] represents the frequency domain after interpolation, MN represents the number of zero values inserted in the frequency domain, M represents the number of up-sampled points, and the length of the frequency domain after interpolation is M, M=A*L, A is a constant, which is 100 in this embodiment.
[0096] Step S33) upsampling signal acquisition step, using inverse Fourier transform to interpolate the frequency domain X new [k] is converted back to the time domain to obtain the upsampled signal, whose formula is
[0097]
[0098] Among them, V up Represents the up-sampled voltage data, I up Represents the upsampled current data.
[0099] In this embodiment, the voltage channel V1 of the first device is upsampled to obtain V1 up [n], after upsampling the current channel C1 of the first device, C1 is obtained up [n], upsample the voltage channel V2 of the second device to obtain V2 up[n], after upsampling the current channel C2 of the second device, C2 is obtained up [n]
[0100] Step S4) is a complete cycle extraction step, in which the upsampled current data and the upsampled voltage data are subjected to zero-crossing point detection, and the sign change of the sampling points adjacent to the zero-crossing point is calculated. If the sign change satisfies a preset condition, the zero-crossing point is a zero-crossing point, and the data between two adjacent zero-crossing points is a set of complete cycle data, thereby obtaining a complete cycle.
[0101] like Figure 4 As shown, step S4) the complete cycle extraction step specifically includes step S41) the voltage cycle acquisition step and step S42) the current cycle acquisition step.
[0102] Step S41) Voltage cycle acquisition step, sampling voltage data V up Perform zero-crossing detection and calculate the sign change of adjacent voltage sampling points. If the voltage data V is sampled up There is v i <0 and v i+1 >0, then i is the zero crossing point from negative to positive, recorded as Z m , the data between two adjacent zero-crossing points is a complete set of waveform data, so the voltage waveform data V up Can be divided into multiple complete cycle data, Among them DV i Indicates voltage data V up The ith complete cycle of .
[0103] Step S42) Current cycle acquisition step, based on the voltage cycle current data C up Similarly, grouping is performed to obtain DC i Indicates current data C up The ith complete cycle of .
[0104] In this embodiment, the up-sampled voltage data V1 up The complete cycle obtained is DV1, and the up-sampled current data is C1 up The complete cycle obtained is DC1, and the up-sampled voltage data is V2 up The complete cycle obtained is DV2, and the up-sampled voltage data is C2 up The resulting complete cycle is DC2.
[0105] Step S5) A resampling step is performed, wherein a preset offset is set. The first device includes first frequency data, and the second device includes second frequency data. The number of frequency offsets of the second frequency data relative to the first frequency data is the preset offset. The second frequency data is resampled with a length of a target length threshold to obtain resampled voltage data and resampled current data.
[0106] In this embodiment, an offset is set to represent the number of cycles of the second device offset relative to the first device, so that the first device and the second device correspond to each other according to the cycles, that is, the i-th cycle of the first device corresponds to the i-offset-th cycle of the second device; each group of corresponding cycle data is resampled, and the i-th voltage cycle of the first device is DV1 i , the i-th current cycle is DC1 i , the length is p1, which is the length of the first frequency data, and the voltage frequency corresponding to the second device is DV2 i-offset , the corresponding current frequency is DC2 i-offset , the length is p2, which is the length of the second frequency data; the voltage frequency data DV2 of the second device i-offset And current cycle data DC2 i-offset Resampling is performed respectively, and the target length of resampling is p1, and the target length threshold is the length p1 of the first frequency data.
[0107] Step S6) The judgment step is used to judge the size relationship between the target length threshold and the length of the second frequency data. If the target length threshold is equal to the length of the second frequency data, that is, p1 is equal to p2, then the data correction step is executed; if the target length threshold is greater than the length of the second frequency data, that is, p1 is greater than p2, then the upsampling step is returned; if the target length threshold is less than the length of the second frequency data, that is, p1 is less than p2, then the next step is executed.
[0108] Step S7) downsampling step, downsampling the resampled voltage data and the resampled current data so that the target length threshold of the resampled voltage data and the resampled current data is equal to the length of the second frequency data.
[0109] like Figure 5 As shown, step S7) the downsampling step specifically includes step S71) a second frequency domain calculation step, step S72) a filter application step, step S73) a frequency domain clipping step and step S74) a time domain acquisition step.
[0110] Step S71) A second frequency domain calculation step is to perform discrete Fourier transform on the current data and the voltage data to obtain a frequency domain, and the formula is:
[0111]
[0112] Where N represents the original signal and X[k] represents the frequency domain signal.
[0113] Step S72) filter application step, applying a low-pass filter in the frequency domain, retaining the low-frequency part and setting the high-frequency component to zero, the low-pass filter is defined as
[0114]
[0115] Among them, X filtered [k] represents the definition of the low-pass filter, p1 represents the target length threshold, and p2 represents the length of the second frequency data.
[0116] Step S73) Frequency domain clipping step: Since the target length p1 is less than p2, the number of frequency domain points needs to be reduced. First, the first p1 / 2 low-frequency points are taken and their conjugate symmetric parts are copied to make the new frequency domain signal length p1. Then the high-frequency part is discarded to reduce the data length. The clipped frequency domain signal is
[0117] X down [k] = X filtered [k], k = 0, 1, 2…, p1-1
[0118] Among them, X down [k] represents the cropped frequency domain signal.
[0119] Step S74) Time domain acquisition step, the downsampled frequency domain signal X down [k] is converted back to the time domain to obtain a new time domain signal, whose formula is
[0120]
[0121] Among them, x down [n] represents the time domain signal, and its data point number is p1. At this time, the target length threshold is equal to the length of the second frequency data. At this time, the length of the resampled voltage data and the resampled current data meets the requirements, and step S8) data correction step can be executed.
[0122] Step S8) Data correction step, correcting the resampled current data to obtain corrected current data. The frequency length of the second device after resampling is the same as the frequency length of the first device, both of which are p1. It is necessary to correct the current data of the second device. According to the circuit principle, when the resistance remains unchanged, the current data should be proportional to the voltage data. The calculation formula of the data correction step is:
[0123] PC2adjust i=PC2 i *PC1 i / PC2 i
[0124] Among them, PC2adjust i Represents the corrected current data of the second device, PC2 i Represents the resampled current data of the second device, PC1 i Represents the current cycle data of the first device, PC2 i The current cycle data of the second device is represented.
[0125] Step S9) The data synthesis step is to add the corrected current data to the current cycle data in the first cycle data to obtain the initial synthesized current data. The voltage cycle data in the first cycle data is the initial synthesized voltage data. The calculation formula of the initial synthesized voltage data is:
[0126] VSD i =PV1 i
[0127] Among them, VSD i Indicates the initial composite voltage data, PV1 i representing voltage cycle data of the first device;
[0128] The calculation formula of the initial synthetic current data is:
[0129] CSD i =PC1 i +PC2adjust i
[0130] Among them, CSD i represents the initial synthetic current data, PC1 i Represents the current frequency data of the first device, PC2adjust i The device is indicative of corrected current data for the second device.
[0131] Step S10) Synthesized data downsampling step, downsampling the initial synthesized current data and the initial synthesized voltage data to obtain final synthesized voltage data and final synthesized current data, downsampling the synthesized data to reduce its sampling rate to the original sampling value. Since the upsampling is performed according to a fixed ratio A=100, the downsampling process only needs to select a value every 100 points. The calculation formula of the final synthesized voltage data is:
[0132] VR i =VSD i*A
[0133] Among them, VRi represents the final synthesized voltage data, VSDi represents the initial synthesized voltage data, and A is a constant;
[0134] The calculation formula of the final synthetic current data is:
[0135] CR i =CSD i*A
[0136] Among them, CR i represents the final composite current data, CSD i Represents initial synthetic current data, which is obtained by obtaining voltage data and current data of a first device in an electric power system, voltage data and current data of a second device to synthesize final synthetic current data and final synthetic voltage data to obtain the total power consumption of all electrical appliances in the electric power system when they are running simultaneously.
[0137] like Figure 6 As shown, the present application also proposes a storage medium 100 storing computer-readable instructions. When the computer-readable instructions are read by at least one processor 110, at least one processor 120 executes at least one step in the multi-device multi-channel power data synthesis method.
[0138] The present application provides a method and storage medium for synthesizing multi-device multi-channel power data, which utilizes multi-channel power data collected when multiple electrical appliances are running individually to synthesize power data of multiple electrical appliances running simultaneously. The present invention can more accurately estimate the power consumption of electrical appliances when they are running simultaneously through the power data of a single electrical appliance when running, thereby improving the accuracy of load prediction and optimal control of the power system and reducing the electricity cost of the power system.
[0139] The above is a detailed introduction to the multi-device multi-channel power data synthesis method and storage medium provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea; at the same time, for general technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.
Claims
1. A method for synthesizing multi-device multi-channel power data, characterized in that: The specific steps include: a data acquisition step of acquiring two or more sets of data, each set of data being from a different device, the device including a first device and a second device, and the current data and the voltage data in each set of data being from different channels; A voltage data cleaning step, cleaning the voltage data, using a median filtering method to find abnormal values of the voltage data and replace them; An upsampling step, based on Fourier transform, upsampling the current data and the voltage data to obtain upsampled current data and upsampled voltage data; In the complete cycle extraction step, the up-sampled current data and the up-sampled voltage data are subjected to zero-crossing point detection, and the sign change of the sampling points adjacent to the zero-crossing point is calculated. If the sign change meets the preset conditions, the zero-crossing point is a zero-crossing point, and the data between two adjacent zero-crossing points is a set of complete cycle data, thereby obtaining a complete cycle; The resampling step includes setting a preset offset, wherein the first device includes first frequency data, the second device includes second frequency data, the frequency offset number of the second frequency data relative to the first frequency data is the preset offset, and the second frequency data is resampled with a length of a target length threshold to obtain resampled voltage data and resampled current data; A judging step, judging the size relationship between the target length threshold and the length of the second frequency data, if the target length threshold is equal to the length of the second frequency data, executing a data correction step; if the target length threshold is greater than the length of the second frequency data, returning to the up-sampling step; if the target length threshold is less than the length of the second frequency data, executing the next step; A downsampling step of downsampling the resampled voltage data and the resampled current data so that a target length threshold of the resampled voltage data and the resampled current data is equal to the length of the second cycle data; A data correction step, correcting the resampled current data to obtain corrected current data; a data synthesis step, adding the corrected current data to the current cycle data in the first cycle data to obtain initial synthesized current data, wherein the voltage cycle data in the first cycle data is the initial synthesized voltage data; and The synthetic data downsampling step downsamples the initial synthetic current data and the initial synthetic voltage data to obtain final synthetic voltage data and final synthetic current data.
2. The method for synthesizing multi-device multi-channel power data according to claim 1, characterized in that: The voltage data cleaning step specifically includes the following steps: The window forming step traverses the voltage data sequence, and for each sampling point vi, takes the (f-1) / 2 sampling points before and after it to form a window, and its formula is: Wi={vi-(f-1) / 2,…,you,…,you +( f- 1) / 2 } Wherein, i represents the sampling point number, i∈[1,L], L represents the length of the voltage data, Wi represents the window, vi represents the sampling point, that is, the original signal, and f represents the window size; The median calculation step is to calculate the median of the obtained window Wi, and its formula is: Mi=Median(Wi) Among them, Mi represents the median value of window Wi; The residual calculation step is to replace the original signal vi with the median Mi to form the filtered signal sequence V′, and calculate the residual between the filtered signal sequence V′ and the original signal. The formula is: di=|vi-Mi| where di represents the residual; and In the abnormality judgment step, an abnormal threshold T is set. If di>T, vi is determined to be an abnormal signal, and the abnormal signal vi is replaced by the median Mi.
3. The method for synthesizing multi-device multi-channel power data according to claim 1, characterized in that: The upsampling step specifically includes the following steps: The first frequency domain calculation step is to perform discrete Fourier transform on the current data and the voltage data to obtain the frequency domain, and the formula is: Where N represents the original signal, and X[k] represents the frequency domain signal; The frequency domain interpolation step increases the number of sampling points in the frequency domain according to the need, and upsampling is achieved by inserting zero values in the high-frequency part of the frequency domain. The formula is: Wherein, Xnew[k] represents the frequency domain after interpolation, MN represents the number of zero values inserted in the frequency domain, M represents the number of up-sampled points, the length of the frequency domain after interpolation is M, M=A*L, and A is a constant; and The up-sampled signal acquisition step uses the inverse Fourier transform to convert the interpolated frequency domain Xnew[k] back to the time domain to obtain the up-sampled signal, which is expressed as follows: Wherein, Vup represents the up-sampled voltage data, and Cup represents the up-sampled current data.
4. The method for synthesizing multi-device multi-channel power data according to claim 1, characterized in that: The complete cycle extraction step specifically includes the following steps: The voltage cycle acquisition step is to perform zero-crossing detection on the up-sampled voltage data Vup and calculate the sign change of adjacent voltage sampling points. If vi<0 and vi +1 >0, i is the zero crossing point from negative to positive, recorded as Zm, and the data between two adjacent zero crossing points is a set of complete waveform data. Therefore, the voltage waveform data Vup can be divided into multiple complete cycle data. Wherein DVi represents the i-th complete cycle of the voltage data Vup; as well as The current cycle acquisition step is to group the current data Cup based on the voltage cycle to obtain DCi represents the i-th complete cycle of the current data Cup.
5. The method for synthesizing multi-device multi-channel power data according to claim 1, characterized in that: The downsampling step specifically includes the following steps: The second frequency domain calculation step is to perform discrete Fourier transform on the current data and the voltage data to obtain the frequency domain, and the formula is: Where N represents the original signal, and X[k] represents the frequency domain signal; The filter application step is to apply a low-pass filter in the frequency domain to retain the low-frequency part and set the high-frequency component to zero. The low-pass filter is defined as Wherein, Xfiltered[k] represents the definition of the low-pass filter, p1 represents the target length threshold, and p2 represents the length of the second frequency data; In the frequency domain clipping step, first take the first p1 / 2 low-frequency points and copy their conjugate symmetric parts to make the new frequency domain signal length p1, then discard the high-frequency part to reduce the data length. The clipped frequency domain signal is Xdown[k]=Xfiltered[k],k=0,1,2…,p1-1 Where Xdown[k] represents the frequency domain signal after clipping; In the time domain acquisition step, the downsampled frequency domain signal Xdown[k] is converted back to the time domain to obtain a new time domain signal, which is expressed as follows: Wherein, xdown[n] represents a time domain signal, the number of data points of which is p1, and at this time, the target length threshold is equal to the length of the second frequency data.
6. The multi-channel power data synthesis method according to claim 1, characterized in that: The calculation formula of the data correction step is: PC2adjusti=PC2i*PC1i / PC2i Among them, PC2adjusti represents the corrected current data of the second device, PC2i represents the resampled current data of the second device, PC1i represents the current cycle data of the first device, and PC2i represents the current cycle data of the second device.
7. The method for synthesizing multi-device multi-channel power data according to claim 1, characterized in that: In the data synthesis step, the calculation formula of the initial synthesis voltage data is: VSDi=PV1i Wherein, VSDi represents the initial synthetic voltage data, and PV1i represents the voltage cycle data of the first device; The calculation formula of the initial synthetic current data is: CSDi=PC1i+PC2adjusti Among them, CSDi represents the initial synthetic current data, PC1i represents the current cycle data of the first device, and PC2adjusti represents the correction current data of the second device.
8. The method for synthesizing multi-device multi-channel power data according to claim 1, characterized in that: In the synthetic data downsampling step, the calculation formula of the final synthetic voltage data is: VRi=VSDi* A Wherein, VRi represents the final synthesized voltage data, VSDi represents the initial synthesized voltage data, and A is a constant; The calculation formula of the final synthetic current data is: CRi=CSDi* A Wherein, CRi represents the final synthetic current data, and CSDi represents the initial synthetic current data.
9. A storage medium storing computer-readable instructions, which, when read by at least one processor, enables at least one processor to execute at least one step of the multi-device multi-channel power data synthesis method according to any one of claims 1 to 8.