Display panel and display device

Abstract

The application discloses a display panel and a display device, which comprise a substrate, a first conductor layer, a first insulating layer and a second conductor layer; the first conductor layer is located on one side of the substrate, and the first conductor layer comprises a first trace; the first insulating layer is located on a side, away from the substrate, of the first conductor layer; the second conductor layer is located on a side, away from the substrate, of the first insulating layer, and the second conductor layer comprises a second trace; the orthographic projections of the first trace and the second trace on the substrate are arranged at intervals; wherein a shielding part is further formed in the first conductor layer and / or the second conductor layer; the orthographic projection of at least part of the shielding part on the substrate is located between the orthographic projection of the first trace on the substrate and the orthographic projection of the second trace on the substrate; and the shielding part has a fixed potential. In the above manner, the application can reduce the parasitic capacitance of the FIAA trace and optimize the display effect.

Description

Technical Field

[0001] This application belongs to the field of display technology, specifically relating to a display panel and a display device. Background Technology

[0002] With the continuous development of display technology, display panels are increasingly moving towards narrower bezels. Currently, in order to better achieve a narrow bottom bezel on display panels, related technologies employ a technique of placing some fanout lines in the display area (Fanout in AA, or FIAA for short). However, this technique increases the parasitic capacitance of the FIAA traces, causing bright lines to appear on the display panel in the FIAA area. Summary of the Invention

[0003] This application provides a display panel and display device that can reduce the parasitic capacitance of FIAA traces and optimize the display effect.

[0004] To solve the above-mentioned technical problems, one technical solution adopted in this application is: providing a display panel, including a substrate, a first conductor layer, a first insulating layer, and a second conductor layer; the first conductor layer is located on one side of the substrate and includes a first trace; the first insulating layer is located on the side of the first conductor layer opposite to the substrate; the second conductor layer is located on the side of the first insulating layer opposite to the substrate and includes a second trace, the orthographic projections of the first trace and the second trace on the substrate being spaced apart; wherein, a shielding portion is further formed in the first conductor layer and / or the second conductor layer, at least a portion of the orthographic projection of the shielding portion on the substrate being located between the orthographic projections of the first trace and the second trace on the substrate, and the shielding portion having a fixed potential.

[0005] Preferably, the first trace includes a first line segment, the second trace includes a second line segment, the first line segment and the second line segment extend in the same direction, and the orthographic projection of the shielding portion on the substrate is located between the orthographic projections of the first line segment and the second line segment on the substrate.

[0006] Preferably, the first line segment, the second line segment, and the shielding portion extend in the same direction.

[0007] Preferably, the shielding portion includes a first shielding sub-portion located in the first conductor layer, and the first conductor layer further includes a third trace, wherein the third trace has a fixed potential, and the first shielding sub-portion is electrically connected to the third trace.

[0008] Preferably, the third trace, the second trace, and the orthographic projection of the first trace on the substrate are arranged sequentially at intervals.

[0009] Preferably, the third trace is a first reference voltage line.

[0010] Preferably, the first conductor layer further includes a first connecting line that electrically connects the first shielding sub-part to the third trace.

[0011] Preferably, the number of the first connecting lines is one, and the first connecting line connects the middle part of the first shielding sub-part to the third wiring; or, the number of the first connecting lines is at least two, wherein one of the first connecting lines connects one end of the first shielding sub-part to the third wiring, and the other of the first connecting lines connects the other end of the first shielding sub-part to the third wiring.

[0012] Preferably, the shielding portion includes a second shielding sub-portion located in the second conductor layer, and the second conductor layer further includes a fourth trace having a fixed potential, and the second shielding sub-portion is electrically connected to the fourth trace.

[0013] Preferably, the fourth trace is a second reference voltage line.

[0014] Preferably, the second conductor layer further includes a second connecting line that electrically connects the second shielding sub-part to the fourth trace.

[0015] Preferably, there is one second connecting line, which connects the middle part of the second shielding sub-part to the fourth trace; or, there are at least two second connecting lines, one of which connects one end of the second shielding sub-part to the fourth trace, and the other connects the other end of the second shielding sub-part to the fourth trace.

[0016] Preferably, the material of the first insulating layer includes inorganic materials; the potential of the first trace is not fixed, and the potential of the second trace is not fixed.

[0017] Preferably, the first trace is a scan line.

[0018] Preferably, the display panel includes a display area and a non-display area. The display area includes a first display area and a second display area, with the second display area located on the side of the first display area closer to the non-display area. The display panel further includes a second insulating layer and a third conductor layer. The second insulating layer is located on the side of the second conductor layer facing away from the substrate. The third conductor layer is located on the side of the second insulating layer facing away from the substrate. The third conductor layer includes a data line and a fan-out line. The data line is located in the second display area, and the fan-out line is located in the first display area. The second trace electrically connects the data line and the fan-out line.

[0019] Preferably, the material of the first conductor layer includes a molybdenum layer and a titanium layer stacked together; the materials of the second conductor layer and the third conductor both include a first titanium layer, an aluminum layer and a second titanium layer stacked together.

[0020] Based on the same inventive concept, this application also provides a display device, including a display panel as described in the above embodiments.

[0021] Unlike existing technologies, the beneficial effects of this application are: the display panel provided by this application forms a shield between the first and second traces. The shield reduces the electric field generated between the first and second traces and reduces the parasitic capacitance between them. Since the shield has a fixed potential, the potential of the first and second traces is not easily shifted. That is, the potential on the scan line and the adapter line always remains at the original set potential, thereby reducing the probability of bright lines appearing on the display interface. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort, wherein:

[0023] Figure 1 This is a structural diagram of a display panel that utilizes FIAA technology;

[0024] Figure 2 This is a schematic diagram of the pixel driving circuit in a display panel that uses FIAA technology;

[0025] Figure 3 This is a schematic diagram of the structure of one embodiment of the display panel of this application;

[0026] Figure 4 for Figure 3 Top view of the central section of the wiring;

[0027] Figure 5 This is a top view of another embodiment of the wiring in the display panel of this application;

[0028] Figure 6 This is a schematic diagram of another embodiment of the display panel of this application;

[0029] Figure 7 for Figure 6 Top view of the central section of the wiring;

[0030] Figure 8 This is a top view of another embodiment of the wiring in the display panel of this application;

[0031] Figure 9 This is a top view of another embodiment of the wiring in the display panel of this application. Detailed Implementation

[0032] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0033] Before introducing the solution of this application, we will first explain the reason why bright lines exist in display panels using FIAA technology in the prior art:

[0034] See Figure 1 The display panel 10 includes a display area AA and a non-display area NA surrounding the display area AA. The display area AA includes a first display area AA1 in the middle and second display areas AA2 located on both sides of the first display area AA1. The second display areas AA2 correspond to the areas of the display panel 10 with rounded corners. To achieve a narrow bezel, in the display panel 10 using FIAA technology, the data line 21 located in the second display area AA2 is switched to a fan-out line 22 located in the first display area AA1 via an adapter cable F, and then connected to the driver chip IC through the fan-out line 22, thus eliminating the need to set a fan-out line 22 for the non-display area NA of the second display area AA2. Both the data line 21 and the fan-out line 22 extend along the second direction Y and are spaced apart along the first direction X. At least a portion of the adapter cable F extends along the first direction X.

[0035] See Figure 2 The display panel 10 also includes scan lines S, at least a portion of which extend along the first direction X. The scan lines S are electrically connected to the gates in the same row of the display. The scan lines S are used to transmit gate signals and have a switching potential. The adapter line F is connected to the data line 21 and also has a switching potential. Figure 2 As shown, due to the close distance between the adapter line F and the scan line S, the parasitic capacitance between them is large, which makes it easy for the jumping potentials on the two lines to couple. The voltages on the two lines affect each other, causing the voltage at the first connection point D of the data line 21 and the adapter line F to deviate from the voltage required for light emission. This ultimately leads to a display abnormality at the first connection point D, and multiple obliquely arranged first connection points D with display abnormalities combine to form an oblique bright line.

[0036] In view of this, this application provides a display panel 10, please refer to... Figure 3 and Figure 4The display panel 10 includes a substrate 101, a first conductor layer 102, a first insulating layer 103, and a second conductor layer 104. The first conductor layer 102 is located on one side of the substrate 101 and includes a first trace 11. Specifically, the first trace 11 can be a scan line S. It should be noted that the scan line S can also be located in a fourth conductor layer 107 below the first conductor layer 102. The orthogonal projections of the scan line S in the fourth conductor layer 107 and the first trace 11 onto the substrate 101 can partially overlap. Specifically, the first conductor layer 102 can be a gate oxide layer, whose material includes a stacked molybdenum layer and a titanium layer. The first insulating layer 103 is located on the side of the first conductor layer 102 facing away from the substrate 101. Specifically, the material of the first insulating layer 103 includes inorganic materials, such as silicon oxide or silicon nitride. The second conductor layer 104 is located on the side of the first insulating layer 103 facing away from the substrate 101. The second conductor layer 104 includes a second trace 12. The orthographic projections of the first trace 11 and the second trace 12 on the substrate 101 are spaced apart. Specifically, the second trace 12 can be a transition line F. A shielding portion P is also formed in the first conductor layer 102 and / or the second conductor layer 104. At least a portion of the orthographic projection of the shielding portion P on the substrate 101 is located between the orthographic projections of the first trace 11 and the second trace 12 on the substrate 101. The shielding portion P has a fixed potential. The display panel 10 also includes a second insulating layer 105 and a third conductor layer 106. The second insulating layer 105 is located on the side of the second conductor layer 104 facing away from the substrate 101; the third conductor layer 106 is located on the side of the second insulating layer 105 facing away from the substrate 101. The data line 21 and the fan-out line 22 are located on the third conductor layer 106. The data line 21 is located in the second display area AA2, and the fan-out line 22 is located in the first display area AA1. The second trace 12 electrically connects the data line 21 and the fan-out line 22. Specifically, the second conductor layer 104 and the third conductor layer 106 are both metal layers, and their materials both include a first titanium layer, an aluminum layer, and a second titanium layer stacked together. The second insulating layer 105 can be a planarization layer, and its material can be an organic adhesive.

[0037] Since the material of the first insulating layer 103 is usually inorganic, its thickness is relatively small, resulting in a close distance between the first conductor layer 102 and the second conductor layer 104. This leads to a larger parasitic capacitance between the first trace 11 located in the first conductor layer 102 and the second trace 12 located in the second conductor layer 104, thus affecting the display effect at the corresponding position of the second trace 12. This application forms a shielding portion P between the first trace 11 and the second trace 12. The shielding portion P reduces the electric field generated between the first trace 11 and the second trace 12, lowering the parasitic capacitance between them. Because the shielding portion P has a fixed potential, the potentials of the first trace 11 and the second trace 12 are less likely to shift; that is, the potentials on the scan line S and the adapter line F always remain at their originally set potentials, thereby reducing the probability of bright lines appearing on the display interface.

[0038] Optionally, please continue reading Figure 4 The first trace 11 includes a first segment 111, and the second trace 12 includes a second segment 121. The first segment 111 and the second segment 121 extend in the same direction. The orthographic projection of the shielding portion P onto the substrate 101 lies between the orthographic projections of the first segment 111 and the second segment 121 onto the substrate 101. Optionally, the first segment 111, the second segment 121, and the shielding portion P extend in the same direction. The shielding portion P can shield only a portion of the first trace 11 and the second trace 12, which reduces the fabrication difficulty of the shielding portion P and reduces its impact on transmittance. It should be noted that a first trace 11 may include multiple first segments 111, a second trace 12 may include multiple second segments 121, and the shielding portion P may be one or more.

[0039] Continue reading Figure 4 and Figure 5In one specific embodiment, the shielding portion P may be partially formed in the first conductor layer 102. The shielding portion P includes a first shielding sub-portion P1 located in the first conductor layer 102. The first conductor layer 102 further includes a third trace 13, wherein the third trace 13 has a fixed potential. The first shielding sub-portion P1 is electrically connected to the third trace 13. Specifically, the third trace 13 is a first reference voltage line used to provide a Vref (reference voltage) signal, and it always has a constant potential. In this embodiment, the third trace 13, the first shielding sub-portion P1, and the first trace 11 are all located in the first conductor layer 102, and the orthogonal projections of the first trace 11, the first shielding sub-portion P1, and the second trace 12 on the substrate 101 are arranged sequentially at intervals. That is, compared with the second trace 12, the first shielding sub-portion P1 is closer to the first trace 11, and the two are arranged in the same layer, which makes the electric field between them stronger, which can significantly reduce the electric field between the first trace 11 and the second trace 12 and reduce the voltage coupling between them. Optionally, the orthographic projections of the third trace 13, the second trace 12, and the first trace 11 on the substrate 101 are arranged sequentially at intervals. This arrangement allows the first shielding sub-part P1 to be formed by extending from the third trace 13 toward the first trace 11, making the fabrication more convenient.

[0040] Optionally, the first conductor layer 102 further includes a first connecting line L1, electrically connecting the first shielding sub-part P1 and the third trace 13. The first connecting line L1 connects the first shielding sub-part P1 and the third trace 13, so that the first shielding sub-part P1 has the same fixed potential as the third trace 13. In this embodiment, the first connecting line L1 is located in the same film layer as the first shielding sub-part P1 and the third trace 13, which facilitates fabrication. In other embodiments, the first connecting line L1 may also be located in other film layers and connected to the first shielding sub-part P1 and the third trace 13 through vias.

[0041] Optionally, please continue reading Figure 5 There is one first connecting line L1, which connects the middle of the first shielding sub-part P1 to the third trace 13. In this embodiment, each first shielding sub-part P1 corresponds to one first connecting line L1. The first shielding sub-part P1, the first connecting line L1, and the third trace 13 form an "I"-shaped structure. The first connecting line L1 occupies a small area, which has a smaller impact on the light-emitting element and helps to ensure a high transmittance. Optionally, the first connecting line L1 is arranged perpendicular to the first shielding sub-part P1 and the third trace 13. In this case, the length of the first connecting line L1 is the shortest, so that the area occupied by the first connecting line L1 is minimized, ensuring a high transmittance. In other embodiments, the first connecting line L1 may also intersect the first shielding sub-part P1 or the third trace 13 at an angle.

[0042] Alternatively, see [link to relevant documentation] Figure 6There are two first connecting lines L1. One first connecting line L1 connects one end of the first shielding sub-part P1 to the third trace 13, and the other first connecting line L1 connects the other end of the first shielding sub-part P1 to the third trace 13. In this embodiment, the first shielding sub-part P1, the two first connecting lines L1, and the third trace 13 form a closed loop, making the first shielding sub-part P1 and the third trace 13 connected in parallel. This reduces the resistance of the third trace 13, i.e., reduces the voltage drop between the near and far ends of the trace, ensuring the uniformity of the display effect. Optionally, in this embodiment, the included angle between the first connecting line L1 and the first shielding sub-part P1 is an obtuse angle, i.e., the first shielding sub-part P1, the two first connecting lines L1, and the third trace 13 together form an isosceles trapezoid, which can reduce the tip effect at the connection point of the first connecting line L1 and the first shielding sub-part P1 and ensure the trace yield. In other embodiments, the included angle between the first connecting line L1 and the first shielding sub-part P1 can also be a right angle or an acute angle. The number of first connecting lines L1 can also be more.

[0043] See Figure 7 and Figure 8 In another specific embodiment, the shielding portion P may also be partially formed in the second conductor layer 104. The shielding portion P includes a second shielding sub-portion P2 located in the second conductor layer 104. The second conductor layer 104 further includes a fourth trace 14, wherein the fourth trace 14 has a fixed potential, and the second shielding sub-portion P2 is electrically connected to the fourth trace 14. Specifically, the fourth trace 14 is a second reference voltage line used to provide a Vref (reference voltage) signal, which always has a constant potential. This potential is different from the potential provided by the first reference voltage line, and different reference voltages can be provided to the light-emitting element simultaneously, improving the precision of display brightness control. In this embodiment, the fourth trace 14, the second shielding sub-part P2, and the second trace 12 are all located in the second conductor layer 104. The orthographic projections of the first trace 11, the second shielding sub-part P2, and the second trace 12 on the substrate 101 are arranged alternately. That is, compared with the first trace 11, the second shielding sub-part P2 is closer to the second trace 12, and the two are arranged in the same layer, which makes the electric field between them stronger. This can significantly reduce the electric field between the first trace 11 and the second trace 12 and reduce the voltage coupling between them.

[0044] Optionally, the second conductor layer 104 further includes a second connecting line L2, electrically connecting the second shielding sub-part P2 and the fourth trace 14. In this embodiment, the second connecting line L2, the second shielding sub-part P2, and the fourth trace 14 are located in the same film layer, which facilitates fabrication. In other embodiments, the second connecting line L2 may also be located in other film layers and connected to the second shielding sub-part P2 and the fourth trace 14 through vias.

[0045] Optionally, please continue reading Figure 7There is one second connecting line L2, which connects the middle of the second shielding sub-part P2 to the fourth trace 14. In this embodiment, each second shielding sub-part P2 corresponds to one second connecting line L2. The second shielding sub-part P2, the second connecting line L2, and the fourth trace 14 form an "I"-shaped structure. The second connecting line L2 occupies a small area, which has a smaller impact on the light-emitting element and helps to ensure a high transmittance. Optionally, the second connecting line L2 is arranged perpendicular to the second shielding sub-part P2 and the fourth trace 14. In this case, the length of the second connecting line L2 is the shortest, so that the area occupied by the second connecting line L2 is minimized, ensuring a high transmittance. In other embodiments, the second connecting line L2 may also intersect the second shielding sub-part P2 or the fourth trace 14 at an angle.

[0046] Alternatively, see [link to relevant documentation] Figure 8 There are two second connecting lines L2. One second connecting line L2 connects one end of the second shielding sub-part P2 to the fourth trace 14, and the other second connecting line L2 connects the other end of the second shielding sub-part P2 to the fourth trace 14. In this embodiment, the second shielding sub-part P2, the two second connecting lines L2, and the fourth trace 14 form a closed loop, making the second shielding sub-part P2 and the fourth trace 14 connected in parallel. This reduces the resistance of the fourth trace 14, i.e., reduces the voltage drop between the near and far ends of the trace, ensuring the uniformity of the display effect. Optionally, in this embodiment, the angle between the second connecting line L2 and the second shielding sub-part P2 is an obtuse angle, i.e., the second shielding sub-part P2, the two second connecting lines L2, and the fourth trace 14 together form an isosceles trapezoid, which can reduce the tip effect at the connection point of the second connecting line L2 and the second shielding sub-part P2 and ensure the trace yield. In other embodiments, the angle between the second connecting line L2 and the second shielding sub-part P2 can also be a right angle or an acute angle. The number of second connecting lines L2 can also be more.

[0047] Optionally, see Figure 9In one specific embodiment, the shielding portion P can be partially formed in the first conductor layer 102 and partially formed in the second conductor layer 104. That is, the shielding portion P simultaneously includes a first shielding sub-part P1 and a second shielding sub-part P2, as well as a first connecting line L1 and a second connecting line L2. Since there are two shielding sub-parts simultaneously between the first trace 11 and the second trace 12, the shielding capability can be further improved, and the display effect can be enhanced. In this embodiment, there is one first connecting line L1 and one second connecting line L2. The first shielding sub-part P1, the first connecting line L1, and the third trace 13 form an "I"-shaped structure, and the second shielding sub-part P2, the second connecting line L2, and the fourth trace 14 form an "I"-shaped structure. Compared with the embodiment where the shielding portion P is set in only one conductor layer, the shielding portion P in this embodiment has more traces. Since the area occupied by the first connecting line L1 and the second connecting line L2 is the smallest in this embodiment, the impact on the transmittance of the display panel can be reduced. In order to further reduce the impact of the shielding portion P on the transmittance, the first shielding sub-part P1 and the second shielding sub-part P2 can be set to partially overlap. In other embodiments, the shielding portion P in the first conductor layer 102 and the shielding portion P in the second conductor layer 104 may also be other shapes, such as an isosceles trapezoid, and their shapes may be the same or different.

[0048] Based on the same inventive concept, this application also provides a display device, which includes the display panel provided in this application embodiment. Therefore, this display device possesses the technical features of the display panel provided in this application embodiment and can achieve the beneficial effects of the display panel provided in this application embodiment. Similarities can be found in the above description of the display panel provided in this application embodiment, and will not be repeated here.

[0049] The above are merely embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A display panel, characterized in that, include: Substrate; A first conductor layer is located on one side of the substrate, and the first conductor layer includes a first trace; A first insulating layer is located on the side of the first conductor layer opposite to the substrate; The second conductor layer is located on the side of the first insulating layer away from the substrate. The second conductor layer includes a second trace, and the first trace and the second trace are spaced apart by their orthogonal projections on the substrate. Wherein, a shielding portion is further formed in the first conductor layer and / or the second conductor layer, and at least a portion of the orthogonal projection of the shielding portion on the substrate is located between the orthogonal projection of the first trace on the substrate and the orthogonal projection of the second trace on the substrate, and the shielding portion has a fixed potential; The shielding portion includes a first shielding sub-portion located in the first conductor layer. The first conductor layer further includes a third trace having a fixed potential. The first shielding sub-portion is electrically connected to the third trace. The first conductor layer also includes a first connecting line electrically connecting the first shielding sub-portion and the third trace. The number of first connecting lines is at least two, one of which connects one end of the first shielding sub-portion to the third trace, and the other connects the other end of the first shielding sub-portion to the third trace. The angle between the first connecting line and the first shielding sub-portion is an obtuse angle. Alternatively... The shielding portion includes a second shielding sub-portion located in the second conductor layer. The second conductor layer further includes a fourth trace having a fixed potential. The second shielding sub-portion is electrically connected to the fourth trace. The second conductor layer also includes a second connecting line electrically connecting the second shielding sub-portion and the fourth trace. The number of second connecting lines is at least two, one of which connects one end of the second shielding sub-portion to the fourth trace, and the other connects the other end of the second shielding sub-portion to the fourth trace. The angle between the second connecting line and the second shielding sub-portion is an obtuse angle.

2. The display panel according to claim 1, characterized in that, The first trace includes a first line segment, and the second trace includes a second line segment. The first line segment and the second line segment extend in the same direction, and the orthographic projection of the shielding portion on the substrate is located between the orthographic projections of the first line segment and the second line segment on the substrate.

3. The display panel according to claim 2, characterized in that, The first line segment, the second line segment, and the shielding part extend in the same direction.

4. The display panel according to claim 1, characterized in that, The third trace, the second trace, and the first trace are arranged at intervals on the substrate by their orthogonal projections.

5. The display panel according to claim 4, characterized in that, The third trace is the first reference voltage line.

6. The display panel according to claim 1, characterized in that, The fourth trace is the second reference voltage line.

7. The display panel according to claim 6, characterized in that, The material of the first insulating layer includes inorganic materials; The potential of the first trace is not fixed, and the potential of the second trace is not fixed.

8. The display panel according to claim 1, characterized in that, The first trace is a scan line.

9. The display panel according to claim 8, characterized in that, The display panel includes a display area and a non-display area. The display area includes a first display area and a second display area. The second display area is located on the side of the first display area close to the non-display area. The display panel also includes a second insulating layer located on the side of the second conductor layer away from the substrate. A third conductor layer is located on the side of the second insulating layer away from the substrate. The third conductor layer includes a data line and a fan-out line. The data line is located in the second display area, and the fan-out line is located in the first display area. The second trace electrically connects the data line and the fan-out line.

10. The display panel according to claim 9, characterized in that, The material of the first conductor layer includes a molybdenum layer and a titanium layer stacked together; The materials of the second conductor layer and the third conductor both include a first titanium layer, an aluminum layer and a second titanium layer stacked together.

11. A display device, characterized in that, The display device includes the display panel as described in any one of claims 1-10.

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