Low-power-consumption display module system based on refresh rate dynamic switching

Abstract

The invention provides a low-power-consumption display module system based on refresh rate dynamic switching. The low-power-consumption display module system comprises a driving integrated circuit, a storage module and a frame rate control module. Wherein when the high frame rate mode and the low frame rate mode are switched, the driving integrated circuit does not need to burn driving codes again, frame rate switching is achieved by switching a parameter table in real time and synchronously updating the MI PI clock frequency, the switching delay is smaller than or equal to 20 ms, and the Gamma voltage curve deviation corresponding to the high frame rate and the low frame rate is smaller than or equal to 0.1 V. Through the combined design of pre-burning full codes and dynamic parameter switching, remarkable technical advantages are formed in the aspects of frame rate switching speed (smaller than or equal to 20 ms), power consumption control (amplification is smaller than or equal to 35%) and display stability (brightness fluctuation is smaller than or equal to 5%), and the industrial application value is achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of display modules, and in particular to a low-power display module system based on dynamic switching of refresh rates. Background Art

[0002] In order to pursue the ultimate picture display effect, current mobile phones usually use high frame rates (120HZ / 144HZ) in special application scenarios such as games. Although high frame rates can make the picture display smooth and reduce lag and delay, high frame rates will increase the power consumption of the display module and increase the heat. Therefore, not all scenarios require the use of high frame rates. In most normal scenarios, low frame rates (60HZ) are used. Currently, the commonly used high and low frame rate switching is usually to set the GIP timing of the display module according to the highest frame rate. The low frame rate is achieved by changing the VFP (non-display area). However, changing the VFP (increasing) is not a true low frame rate, and the GIP Timing used is still a high frame rate. This high frame rate GIP timing display has certain difficulties in display effect debugging or power consumption. Summary of the invention

[0003] The purpose of the present invention is to provide a low-power display module system based on dynamic switching of refresh rate, rather than achieving true frame rate switching by changing VFP.

[0004] Specifically, the technical solution of the present invention is: a low-power display module system based on dynamic switching of refresh rate, comprising:

[0005] Driver integrated circuit, pre-burned with complete driver code for high frame rate mode and low frame rate mode, the driver code framework includes GIP timing configuration unit, VGH / VGL charge pump configuration unit, Gamma voltage adjustment unit, ID VCOM configuration unit;

[0006] A storage module stores a high frame rate parameter table (Table A) and a low frame rate parameter table (Table B), wherein the parameter table includes vertical synchronization leading edge / trailing edge (VFP / VBP), horizontal synchronization leading edge / trailing edge (HFP / HBP) and MIPI clock frequency parameters corresponding to the frame rate;

[0007] The frame rate control module sends a first switching instruction to call Table B or a second switching instruction to call Table A to the driver integrated circuit through the MIPI interface after the display module exits the sleep mode (Sleep Out), and dynamically adjusts the MIPI clock frequency to a CLK value corresponding to the target frame rate;

[0008] Among them, when switching between high frame rate mode and low frame rate mode, the driver integrated circuit does not need to re-burn the driver code. The frame rate switching is achieved by real-time switching of the parameter table and synchronous updating of the MIPI clock frequency. The switching delay is ≤20ms, and the Gamma voltage curve deviation corresponding to the high and low frame rates is ≤0.1V.

[0009] As a preferred technical solution, the total vertical synchronization time VTotal stored in the high frame rate parameter table Table A and the low frame rate parameter table Table B satisfies the relationship:

[0010]

[0011] Among them, the VTotal value of the high frame rate mode is reduced by 15%-40% compared with the low frame rate mode, and the adjustment amount of HFP / HBP accounts for 5%-20% of the single frame time; the proportional relationship between the MIPI clock frequency and the target frame rate is:

[0012]

[0013] Among them, CLK A With CLK B The ratio ranges from 1.5:1 to 4:1.

[0014] As a preferred technical solution, the clock frequency dynamic adjustment module of the MIPI interface includes: a clock divider, which supports 8-level division coefficients and a division step of 1 / 2^n (where n=1 to 8); a frequency locking unit, which compares the phase difference between the reference clock and the output clock through a phase detector, and controls the voltage-controlled oscillator to output the target frequency; wherein the frequency switching response time is ≤5μs and the frequency error is ≤±2%.

[0015] As a preferred technical solution, the adjustment of the vertical synchronization front / back edge, namely VFP / VBP, adopts a nonlinear compensation algorithm, specifically including: when switching from a low frame rate to a high frame rate, the VFP reduction amount ΔVFP satisfies:

[0016]

[0017] Wherein, k1=0.15-0.3, k2=0.05-0.12; the product of the adjustment amount of the horizontal synchronization front / back edge, ie, HFP / HBP, and the pixel clock period (t_pixel) accounts for 8%-15% of the single line time.

[0018] As a preferred technical solution, the pre-burning process of the driver integrated circuit includes:

[0019] Step S1: When the display module is powered on, 2 C bus loads the complete driver code into the register bank;

[0020] Step S2: Verify that the rising edge / falling edge time difference of the GIP timing configuration unit is ≤ 100ns;

[0021] Step S3: calibrate the VGH voltage to 15-18V, the VGL voltage to -5--8V, and the charge pump efficiency ≥ 85%;

[0022] Step S4: writing the Gamma voltage curve into the lookup table, including 256 grayscale voltage values, and the voltage difference between adjacent grayscales is ≤8mV.

[0023] As a preferred technical solution, the frame rate control module also includes an environmental perception unit, which triggers frame rate switching according to at least one of the following conditions: the temperature sensor detects that the display module temperature is ≥45°C and forces switching to a low frame rate; the power detection unit enables the low frame rate mode when the battery capacity is ≤20%; the touch sampling rate detection unit associates the switching frame rate when the touch interruption interval is ≥200ms; wherein the decision delay of the environmental perception unit is ≤10ms, and the high and low frame rate switching process does not cause screen flickering, that is, the brightness fluctuation is ≤5%.

[0024] As a preferred technical solution, the Gamma voltage adjustment unit performs dynamic compensation when the frame rate is switched: when switching to the low frame rate mode, the intermediate grayscale voltage is increased according to the following formula:

[0025] V γ，log [n] = V γ，high [n]+α×(n / 255) β

[0026] Wherein, α=0.02-0.05V, β=1.2-1.8, n is the grayscale value;

[0027] The ID VCOM configuration unit adjusts the common electrode voltage according to the frame rate to meet the following requirements:

[0028] |V COM，high -V COM，low |≤0.3.

[0029] As a preferred technical solution, the GIP timing configuration unit includes a multi-stage shift register, which configures different clock overlap times in high and low frame rate modes:

[0030] High frame rate mode: CLK Overlap = 2-4 Gate pulse widths;

[0031] Low frame rate mode: CLK Overlap = 5-8 Gate pulse widths;

[0032] Among them, the delay difference between stages of the shift register is ≤3%.

[0033] As a preferred technical solution, the display module also includes a touch synchronization module, which executes the following when the frame rate is switched:

[0034] Step T1: Freeze the touch signal sampling until the display refresh is stable;

[0035] Step T2: adjusting the touch scan frequency according to the target frame rate to make it an integer multiple of the display refresh rate;

[0036] Step T3: recalibrate the touch reference capacitance value to compensate for the noise offset caused by the refresh rate change;

[0037] Among them, the touch response recovery time is ≤30ms, and the coordinate reporting rate error is ≤±5%.

[0038] As a preferred technical solution, the low frame rate mode is 30-45Hz, and the high frame rate mode is 90-120Hz; in the low frame rate mode, the overall power consumption of the display module is ≤80mW, and the power consumption increase after switching to the high frame rate is ≤35%; during the frame rate switching process, the proportion of the entire code that has not been re-burned is ≥85%, and the code execution time is shortened by 40-60%.

[0039] The beneficial effects of the technology of the present invention are: after actual measurement and verification, this solution has significant advantages over the existing technology:

[0040] (1) Improved switching speed: The frame rate switching delay is shortened from the traditional solution of >100ms to ≤20ms.

[0041] (2) Power consumption control optimization: The power consumption in low frame mode is reduced by 62% (from 210mW to 80mW), and the power consumption increase after switching is less than 35%.

[0042] (3) Display quality assurance: Gamma voltage deviation ≤ 0.1V (traditional solution 0.3-0.5V), brightness fluctuation < 5% (ISO 9241-307 standard requires ≤ 10%).

[0043] (4) Enhanced system compatibility: The code reuse rate reaches over 85%, reducing the risk of code merge conflicts by 70%.

[0044] The present invention forms significant technical advantages in frame rate switching speed (≤20ms), power consumption control (increase ≤35%) and display stability (brightness fluctuation ≤5%) through the combined design of pre-burning full code and dynamic parameter switching, and has industrial application value. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 A schematic diagram of a low-power display module system framework based on dynamic switching of refresh rates proposed in Embodiment 1 of the present invention;

[0047] Figure 2 A schematic diagram of the pre-burning process of the Driver IC proposed in Embodiment 1 of the present invention;

[0048] Figure 3 This is a schematic diagram of the frame rate switching algorithm flow proposed in Example 1 of the present invention.

[0049] Description of reference numerals: driving integrated circuit 10 ; storage module 20 ; frame rate control module 30 . DETAILED DESCRIPTION

[0050] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0051] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically shown, or only one of them is marked. In this article, "one" not only means "only one", but also means "more than one", and "several" includes "two" and "more than two".

[0052] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0053] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0054] The core of the present invention is to solve the following technical problems:

[0055] (1) Eliminate the need to reload driver code when switching frame rates;

[0056] (2) Realize sub-millisecond dynamic compensation of Gamma / VCOM voltage;

[0057] (3) Build an adaptive synchronization mechanism for touch and display refresh rate.

[0058] Based on the above, the display module system of the present invention includes three major innovative modules:

[0059] 1. Pre-burned full code driver architecture

[0060] During the Driver IC power-up phase, burn the complete code including all the configuration parameters of high and low frame rates at one time (see Figure 2 Flowchart) Code partitions are stored in register banks, including:

[0061] GIP timing configuration unit: preset CLK Overlap time corresponding to high and low frame rates (2-4 Gate cycles for high frame rate, 5-8 Gate cycles for low frame rate)

[0062] Charge pump dynamic adjustment unit: VGH / VGL voltage generation circuit adopts dual loop control (voltage accuracy ±0.5V)

[0063] Code verification mechanism: through I 2 C bus readback check (Checksum Error ≤ 0.01%)

[0064] 2. Dynamic switching mechanism of parameter table

[0065] Establish the high and low frame rate parameter mapping relationship (see Table 1):

[0066]

[0067] Frame rate switching algorithm flow (see Figure 3 ):

[0068] a. Complete parameter table switching within 10ms after receiving the Sleep Out signal

[0069] b. Use nonlinear interpolation to adjust VFP / VBP:

[0070]

[0071] c. Synchronously start the Gamma voltage compensation engine.

[0072] 3. Environmental Adaptive Control System

[0073] Multi-dimensional perception decision logic:

[0074] Temperature protection: When T≥45℃, the frequency is forced to be reduced, and the CLK is reduced by 2% for every 1℃ increase

[0075] Power management: Lock low frame rate mode when remaining power is less than 20%

[0076] Touch linkage: Automatically switch to low frame rate when the touch sampling interval is greater than 200ms.

[0077] Example

[0078] Reference Figure 1 As shown, a low-power display module system based on dynamic refresh rate switching proposed by an embodiment of the present invention includes: a driver integrated circuit, pre-burned with complete driver codes including high frame rate mode and low frame rate mode, and the driver code framework includes a GIP timing configuration unit, a VGH / VGL charge pump configuration unit, a Gamma voltage adjustment unit, and an ID VCOM configuration unit;

[0079] A storage module, storing a high frame rate parameter table (Table A, 210) and a low frame rate parameter table (Table B, 220), wherein the parameter table includes vertical synchronization leading / trailing edges (VFP / VBP), horizontal synchronization leading / trailing edges (HFP / HBP) and MIPI clock frequency parameters corresponding to the frame rate;

[0080] The frame rate control module sends a first switching instruction to call Table B or a second switching instruction to call Table A to the driver integrated circuit through the MIPI interface after the display module exits the sleep mode (Sleep Out), and dynamically adjusts the MIPI clock frequency to a CLK value corresponding to the target frame rate;

[0081] Among them, when switching between high frame rate mode and low frame rate mode, the driver integrated circuit does not need to re-burn the driver code. The frame rate switching is achieved by real-time switching of the parameter table and synchronous updating of the MIPI clock frequency. The switching delay is ≤20ms, and the Gamma voltage curve deviation corresponding to the high and low frame rates is ≤0.1V.

[0082] Preferably, the total vertical synchronization time VTotal stored in the high frame rate parameter table Table A and the low frame rate parameter table Table B satisfies the relationship:

[0083]

[0084] Among them, the VTotal value of the high frame rate mode is reduced by 15%-40% compared with the low frame rate mode, and the adjustment amount of HFP / HBP accounts for 5%-20% of the single frame time; the proportional relationship between the MIPI clock frequency and the target frame rate is:

[0085]

[0086] Among them, CLK A With CLK B The ratio ranges from 1.5:1 to 4:1.

[0087] Preferably, the clock frequency dynamic adjustment module of the MIPI interface includes: a clock divider, supporting 8-level frequency division coefficients, and the frequency division step is 1 / 2^n (where n=1 to 8);

[0088] The frequency locking unit compares the phase difference between the reference clock and the output clock through a phase detector, and controls the voltage-controlled oscillator to output the target frequency; wherein the frequency switching response time is ≤5μs, and the frequency error is ≤±2%.

[0089] Preferably, the adjustment of the vertical synchronization front / back edge, namely VFP / VBP, adopts a nonlinear compensation algorithm, specifically including: when switching from a low frame rate to a high frame rate, the VFP reduction amount ΔVFP satisfies:

[0090]

[0091] Wherein, k1=0.15-0.3, k2=0.05-0.12; the product of the adjustment amount of the horizontal synchronization front / back edge, ie, HFP / HBP, and the pixel clock period (t_pixel) accounts for 8%-15% of the single line time.

[0092] like Figure 2 As shown, preferably, the pre-burning process of the driver integrated circuit includes:

[0093] Step S1: When the display module is powered on, 2 C bus loads the complete driver code into the register bank;

[0094] Step S2: Verify that the rising edge / falling edge time difference of the GIP timing configuration unit is ≤ 100ns;

[0095] Step S3: calibrate the VGH voltage to 15-18V, the VGL voltage to -5--8V, and the charge pump efficiency ≥ 85%;

[0096] Step S4: writing the Gamma voltage curve into the lookup table, including 256 grayscale voltage values, and the voltage difference between adjacent grayscales is ≤8mV.

[0097] Preferably, the frame rate control module also includes an environmental perception unit, which triggers frame rate switching according to at least one of the following conditions: the temperature sensor forces switching to a low frame rate when it detects that the display module temperature is ≥45°C; the power detection unit enables the low frame rate mode when the battery capacity is ≤20%; the touch sampling rate detection unit associates the switching frame rate when the touch interruption interval is ≥200ms; wherein the decision delay of the environmental perception unit is ≤10ms, and the high and low frame rate switching process does not cause screen flickering, that is, the brightness fluctuation is ≤5%.

[0098] Preferably, the Gamma voltage adjustment unit performs dynamic compensation when the frame rate is switched: when switching to the low frame rate mode, the intermediate grayscale voltage is increased according to the following formula:

[0099] V γ，low [n] = V γ，high [n]+α×(n / 255) β

[0100] Wherein, α=0.02-0.05V, β=1.2-1.8, n is the grayscale value;

[0101] The ID VCOM configuration unit adjusts the common electrode voltage according to the frame rate to meet the following requirements:

[0102] |V COM，high -V COM，low |≤0.3V.

[0103] Preferably, the GIP timing configuration unit includes a multi-stage shift register, which configures different clock overlap times in high and low frame rate modes:

[0104] High frame rate mode: CLK Overlap = 2-4 Gate pulse widths;

[0105] Low frame rate mode: CLK Overlap = 5-8 Gate pulse widths;

[0106] Among them, the delay difference between stages of the shift register is ≤3%.

[0107] like Figure 3 As shown, preferably, the display module further includes a touch synchronization module, which executes the following when the frame rate is switched:

[0108] Step T1: Freeze the touch signal sampling until the display refresh is stable;

[0109] Step T2: adjusting the touch scan frequency according to the target frame rate to make it an integer multiple of the display refresh rate;

[0110] Step T3: recalibrate the touch reference capacitance value to compensate for the noise offset caused by the refresh rate change;

[0111] Among them, the touch response recovery time is ≤30ms, and the coordinate reporting rate error is ≤±5%.

[0112] Preferably, the low frame rate mode is 30-45Hz, and the high frame rate mode is 90-120Hz; in the low frame rate mode, the overall power consumption of the display module is ≤80mW, and the power consumption increase after switching to the high frame rate is ≤35%; during the frame rate switching process, the proportion of the entire code that has not been re-burned is ≥85%, and the code execution time is shortened by 40-60%.

[0113] Example 2

[0114] This embodiment conducts basic verification of the effect, selects Novatek NT36672A Driver IC, pre-burns the driver code containing 120Hz / 45Hz dual mode, uses SPI Flash MX25U25635F as the storage module, and partitions the storage of Table A / B parameter tables. The MIPI clock generator uses Samsung S2DOS14, which supports 1.2GHz / 450MHz dual frequency switching.

[0115] The measured data show:

[0116] The switching time from 120Hz to 45Hz is 18.7ms, the power consumption is reduced from 215mW to 79mW, and the maximum offset of the Gamma voltage is 0.08V.

[0117] Example 3

[0118] This embodiment is used to further verify the effect.

[0119] Integrated temperature-frequency linkage algorithm:

[0120] CLK adj =CLK0×[1-0.02×(T-T0)]

[0121] When T increases from 25℃ to 50℃, CLK automatically decreases by 50%.

[0122] Touch synchronization solution: The touch scanning frequency and refresh rate maintain a 4:1 integer ratio (120Hz corresponds to 480Hz touch sampling), and a capacitance reference value dynamic calibration algorithm is used:

[0123] C ref，new =C ref+k×ΔCLK (k=0.05pF / MHz) The specific implementation manner described above further explains in detail the purpose, technical scheme and beneficial effects of the present invention. It should be understood that the above description is only a specific implementation manner of the present invention and is not intended to limit the protection scope of the present invention. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A low-power display module system based on dynamic switching of refresh rate, characterized in that: include: A driver integrated circuit, pre-burned with complete driver codes including a high frame rate mode and a low frame rate mode, wherein the driver code framework includes a GIP timing configuration unit, a VGH / VGL charge pump configuration unit, a Gamma voltage adjustment unit, and an ID VCOM configuration unit; A storage module stores a high frame rate parameter table and a low frame rate parameter table, wherein the parameter table includes vertical synchronization leading / trailing edges (VFP / VBP), horizontal synchronization leading / trailing edges (HFP / HBP) and MIPI clock frequency parameters corresponding to the frame rate; The frame rate control module sends a first switching instruction to call a low frame rate parameter table or a second switching instruction to call a high frame rate parameter table to the driver integrated circuit through the MIPI interface after the display module exits the sleep mode, and dynamically adjusts the MIPI clock frequency to a CLK value corresponding to the target frame rate; Among them, when the high frame rate mode and the low frame rate mode are switched, the driver integrated circuit does not need to re-burn the driver code, and the frame rate switching is achieved by real-time switching of the parameter table and synchronous updating of the MIPI clock frequency. The switching delay is ≤20ms, and the Gamma voltage curve deviation corresponding to the high and low frame rates is ≤0.1V.

2. The display module system according to claim 1, characterized in that: The total vertical synchronization time VTotal stored in the high frame rate parameter table Table A and the low frame rate parameter table Table B satisfies the relationship: The VTotal value of the high frame rate mode is reduced by 15%-40% compared with the low frame rate mode, and the adjustment amount of HFP / HBP accounts for 5%-20% of the single frame time; the proportional relationship between the MIPI clock frequency and the target frame rate is: Among them, CLK A With CLK B The ratio ranges from 1.5:1 to 4:

1.

3. The display module system according to claim 2, characterized in that: The clock frequency dynamic adjustment module of the MIPI interface includes: a clock divider, supporting 8-level frequency division coefficients, and the frequency division step is 1 / 2^n (where n=1 to 8); The frequency locking unit compares the phase difference between the reference clock and the output clock through a phase detector, and controls the voltage-controlled oscillator to output the target frequency; wherein the frequency switching response time is ≤5μs, and the frequency error is ≤±2%.

4. The display module system according to claim 3, characterized in that: The adjustment of the vertical synchronization front / back edge, i.e., VFP / VBP, adopts a nonlinear compensation algorithm, specifically including: when switching from a low frame rate to a high frame rate, the VFP reduction amount ΔVFP satisfies: Wherein, k1=0.15-0.3, k2=0.05-0.12; the product of the adjustment amount of the horizontal synchronization front / back edge, ie, HFP / HBP, and the pixel clock cycle accounts for 8%-15% of the single line time.

5. The display module system according to claim 4, characterized in that: The pre-burning process of the driver integrated circuit includes: Step S1: When the display module is powered on, 2 C bus loads the complete driver code into the register bank; Step S2: Verify that the rising edge / falling edge time difference of the GIP timing configuration unit is ≤ 100ns; Step S3: calibrate the VGH voltage to 15-18V, the VGL voltage to -5--8V, and the charge pump efficiency ≥ 85%; Step S4: writing the Gamma voltage curve into the lookup table, including 256 grayscale voltage values, and the voltage difference between adjacent grayscales is ≤8mV.

6. The display module system according to claim 1, characterized in that: The frame rate control module also includes an environmental perception unit, which triggers frame rate switching according to at least one of the following conditions: the temperature sensor detects that the display module temperature is ≥45°C and forces switching to a low frame rate; the power detection unit enables the low frame rate mode when the battery capacity is ≤20%; the touch sampling rate detection unit associates the switching frame rate when the touch interruption interval is ≥200ms; wherein the decision delay of the environmental perception unit is ≤10ms, and the high and low frame rate switching process does not cause screen flickering, that is, the brightness fluctuation is ≤5%.

7. The display module system according to claim 1, characterized in that: The Gamma voltage adjustment unit performs dynamic compensation when the frame rate is switched: when switching to the low frame rate mode, the intermediate grayscale voltage is increased according to the following formula: V γ,low [n]=V γ,high [n]+α×(n / 255) β Wherein, α=0.02-0.05V, β=1.2-1.8, n is the grayscale value; The ID VCOM configuration unit adjusts the common electrode voltage according to the frame rate to meet the following requirements: |V COM,high -V COM,low |≤0.3V。 8. The display module system according to claim 1, characterized in that: The GIP timing configuration unit includes a multi-stage shift register, which configures different clock overlap times in high and low frame rate modes: High frame rate mode: CLK Overlap = 2-4 Gate pulse widths; Low frame rate mode: CLK Overlap = 5-8 Gate pulse widths; Wherein, the delay difference between stages of the shift register is ≤3%.

9. The display module system according to any one of claims 1 to 8, characterized in that: The display module also includes a touch synchronization module, which executes the following when the frame rate is switched: Step T1: Freeze the touch signal sampling until the display refresh is stable; Step T2: adjusting the touch scan frequency according to the target frame rate to make it an integer multiple of the display refresh rate; Step T3: recalibrate the touch reference capacitance value to compensate for the noise offset caused by the refresh rate change; Among them, the touch response recovery time is ≤30ms, and the coordinate reporting rate error is ≤±5%.

10. The display module system according to claim 9, characterized in that: The low frame rate mode is 30-45Hz, and the high frame rate mode is 90-120Hz; in the low frame rate mode, the overall power consumption of the display module is ≤80mW, and the power consumption increase after switching to the high frame rate is ≤35%; during the frame rate switching process, the proportion of the entire code that has not been re-burned is ≥85%, and the code execution time is shortened by 40-60%.

Images