Display device

Abstract

The invention provides a display device. The plurality of display devices includes a plurality of pixels, and each of the plurality of pixels includes: a light emitting element; a first transistor controlling a current supplied to the light emitting element; a second transistor connected to the data line; a third transistor connected between a second terminal of the first transistor and a gate of the first transistor; a fifth transistor connected between a first terminal of the first transistor and a driving voltage line; and a sixth transistor connected between a second terminal of the first transistor and the light emitting element, in which a first gate of the fifth transistor and a gate of the sixth transistor are connected with a fourth gate line supplying a fourth gate signal, a gate of the third transistor and a second gate of the fifth transistor are connected with a third gate line supplying a third gate signal.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] In recent years, the use of display devices has been diversified. In addition, as the thickness of display devices has become thinner and lighter, the range of their use has tended to be wider.

[0003] As display devices are used in various ways, there are various methods for designing the form of the display devices, and the functions that can be combined or connected with the display devices are also increasing. Summary of the invention

[0004] The present invention provides a display device, which can reduce the area of ​​a frame region by reducing the number of gate drivers, thereby reducing costs.

[0005] The present invention provides a display device capable of reducing power consumption by reducing the number of data drivers.

[0006] The technical problems to be solved by the present disclosure are not limited to the technical problems mentioned above, and ordinary technicians can clearly understand other technical problems not mentioned from the following records.

[0007] In a display device including a plurality of pixels according to a preferred embodiment of the present invention, each of the plurality of pixels may include: a light-emitting element; a first transistor controlling a current supplied to the light-emitting element; a second transistor connected to a data line; a third transistor connected between a second terminal of the first transistor and a gate of the first transistor; a fifth transistor connected between a first terminal of the first transistor and a driving voltage line; and a sixth transistor connected between a second terminal of the first transistor and the light-emitting element, wherein a first gate of the fifth transistor and a gate of the sixth transistor may be connected to a fourth gate line supplying a fourth gate signal, and a gate of the third transistor and a second gate of the fifth transistor may be connected to a third gate line supplying a third gate signal.

[0008] In one embodiment, each of the plurality of pixels may further include: a first capacitor connected between the gate of the first transistor and the second terminal of the second transistor; a second capacitor connected between the second terminal of the second transistor and the driving voltage line; a fourth transistor connected between the gate of the first transistor and the first voltage line; a seventh transistor connected between the light emitting element and the second voltage line; an eighth transistor connected between the second terminal of the second transistor and the third voltage line; and a ninth transistor supplying a bias voltage to the first terminal of the first transistor.

[0009] In one embodiment, the display device may further include a data driving circuit for supplying multiple data signals to the multiple pixels. The data driving circuit may include a demultiplexer. The demultiplexer may supply a data signal to a first data line based on a first control signal, and supply the data signal to a second data line based on a second control signal, and alternately supply the data signal to the first data line and the data signal to the second data line.

[0010] In one embodiment, the demultiplexer may include: a first switching transistor connected to the first data line; and a second switching transistor connected to the second data line, wherein after the first control signal is supplied to the gate of the first switching transistor, the second control signal may be supplied to the gate of the second switching transistor.

[0011] In one embodiment, each of the multiple pixels may be one of a first pixel emitting red light, a second pixel emitting green light, and a third pixel emitting blue light, the first pixel and the third pixel may be connected to the first data line, and the second pixel may be connected to the second data line.

[0012] In one embodiment, the data driving circuit may include a data driving section that outputs the data signal; and a data distribution section that supplies the data signal alternately to the first data line and the second data line based on the first control signal and the second control signal, respectively.

[0013] In one embodiment, the gate of the eighth transistor may be connected to the third gate line, the gate of the second transistor may be connected to the first gate line supplying a first gate signal, the gate of the fourth transistor may be connected to the second gate line supplying a second gate signal, and the gate of the seventh transistor and the gate of the ninth transistor may be connected to the fifth gate line supplying a fifth gate signal.

[0014] In one embodiment, the display device may further include a gate driving circuit that supplies multiple gate signals to the multiple pixels, each of the multiple pixels operates with a non-luminous period and a luminous period within a frame interval, and the gate driving circuit can supply a fourth gate signal of a gate-off voltage to the fourth gate line during the non-luminous period, can supply a second gate signal of a gate-on voltage to the second gate line during a first interval of the non-luminous period, and can supply a third gate signal of a gate-on voltage to the third gate line during a second interval after the first interval of the non-luminous period.

[0015] In one embodiment, the gate driving circuit may supply a first gate signal of a gate-on voltage to the first gate line in a writing interval after the second interval in the non-light-emitting period.

[0016] In one embodiment, the gate driving circuit may supply a fifth gate signal of a gate-on voltage to the fifth gate line in a third interval between the writing interval and the light-emitting period in the non-light-emitting period.

[0017] In one embodiment, the gate driving circuit may supply a fourth gate signal of a gate-on voltage to the fourth gate line during the light emitting period.

[0018] In one embodiment, a first on-time during which the gate driving circuit supplies the gate-on voltage in the first interval and the second interval may be longer than a second on-time during which the gate driving circuit supplies the gate-on voltage in the writing interval and the third interval.

[0019] According to the technical solution of the present disclosure, a display device can be provided which can reduce costs and power consumption by reducing the area of ​​the frame region.

[0020] The effects of the present disclosure are not limited to the effects mentioned above, and a person skilled in the art can clearly understand other effects not mentioned through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1a and Figure 1b is a diagram schematically showing a display device according to an embodiment.

[0022] Figure 2 is a diagram schematically showing a display device according to an embodiment.

[0023] Figure 3 is a diagram schematically showing a display device according to an embodiment.

[0024] Figure 4a and Figure 4b is a diagram showing a method according to an embodiment Figure 3 Equivalent circuit diagram of a pixel.

[0025] Figure 5 It is shown that the supply to Figure 3 Graph of the pixel signal.

[0026] Figure 6a and Figure 6b is a diagram illustrating a demultiplexer according to an embodiment.

[0027] Figure 7 is a timing diagram illustrating the switching operation of the demultiplexer shown in FIG. 6 .

[0028] Figures 8a to 8c is a diagram for explaining the structure and operation of a transistor including a multi-gate.

[0029] Fig. 9 It is a figure which shows the experimental result for demonstrating the effect of this invention.

[0030] Description of Reference Numerals 10A: Display device 11A: Pixel portion 12A: Gate drive circuit 13A: Data drive circuit 14A: Controller 15A: Power supply circuit 150: Data driving unit 170: Data distribution unit GWL: first gate line GIL: second gate line GCL: third gate line EML: fourth gate line GBL: fifth gate line DL: data line OL: Output Line DMX: Demultiplexer Vdata: data signal GCS1 to GCS4: gate control signal DCS: Data Control Signal CCS: Data Distribution Control Signal PCS: Power supply control signal VREF: Reference voltage ELVDD: first driving voltage ELVSS: second driving voltage VINT: first initialization voltage AINT: second initialization voltage DETAILED DESCRIPTION

[0031] The present invention can be subjected to various transformations and has various embodiments, and specific embodiments are listed in the drawings and described in detail in the detailed description. The effects and features of the present invention and methods for achieving them will become clear with reference to the embodiments described in detail below in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in various forms.

[0032] In the following embodiments, terms such as “first” and “second” are used to distinguish one component from other components and are not used in a limiting sense.

[0033] In the following embodiments, unless the context clearly means otherwise, an expression in the singular includes an expression in the plural.

[0034] In the following embodiments, terms such as including or having refer to the presence of features or constituent elements described in the specification, and do not preclude the possibility of adding one or more other features or constituent elements.

[0035] In this specification, "A and / or B" means the case of A, or the case of B, or the case of A and B. In addition, in this specification, "at least one of A and B" means the case of A, or the case of B, or the case of A and B.

[0036] In the following embodiments, when it is mentioned that X and Y are connected, it can include the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Here, X and Y can be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the drawings or detailed description, and also includes connection relationships other than the connection relationships shown in the drawings or detailed description.

[0037] For example, the case where X and Y are electrically connected may include the case where one or more elements (eg, switches, transistors, capacitors, inductors, resistors, diodes, etc.) capable of electrically connecting X and Y are connected between X and Y.

[0038] In the following embodiments, "ON" used in association with the state of an element may refer to the activated state of the element, and "OFF" may refer to the inactivated state of the element. "ON" used in association with a signal received by an element may refer to a signal that activates the element, and "OFF" may refer to a signal that deactivates the element. An element may be activated by a high level voltage or a low level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low level voltage, and an N-channel transistor (N-type transistor) is activated by a high level voltage. Therefore, the "ON" voltage for a P-type transistor and an N-type transistor should be understood as opposite (high to low) voltage levels.

[0039] In the following embodiments, the x direction, y direction and z direction are not limited to directions along three axes on an orthogonal coordinate system, but can be interpreted as including the broad sense thereof. For example, the x direction, y direction and z direction can be orthogonal to each other, but can also refer to different directions that are not orthogonal to each other.

[0040] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals and repeated description thereof will be omitted.

[0041] Figure 1a and Figure 1b is a diagram schematically showing a display device according to an embodiment, Figure 2 is a diagram schematically showing a display device according to an embodiment.

[0042] Reference Figure 1a and Figure 1b, the display device 10 may include a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display area DA may be entirely surrounded by the peripheral area PA.

[0043] When the display area DA is viewed in a planar shape, the display area DA may be in a rectangular shape. As another embodiment, the display area DA may be in a polygonal shape such as a triangle, a pentagon, a hexagon, or a circular shape, an elliptical shape, an amorphous shape, etc. The corners of the edges of the display area DA may have a rounded shape. In one embodiment, as shown in FIG. Figure 1a As shown, the display device 10 may have a display area DA having a shape in which the length in the x direction is longer than the length in the y direction. Figure 1b As shown, the display device 10 may have a display area DA having a shape in which the length in the y direction is longer than the length in the x direction.

[0044] Reference Figure 2 According to an embodiment, a display device 10 may include a pixel portion 11 , a gate driving circuit 12 , a data driving circuit 13 , a controller 14 , and a power supply circuit 15 .

[0045] The pixel portion 11 may be provided in the display area DA. A plurality of conductive lines for transmitting electrical signals to be applied to the display area DA, an outer contour circuit electrically connected to the pixel circuit, and a pad to which a printed circuit substrate or a driver IC chip is attached may be provided in the peripheral area PA. For example, a gate drive circuit 12, a data drive circuit 13, a controller 14, and a power supply circuit 15 may be provided in the peripheral area PA. The peripheral area PA may be a frame area.

[0046] like Figure 2 As shown, a plurality of gate lines GL, a plurality of data lines DL, and a plurality of pixels PX connected thereto may be arranged in the display area DA. The plurality of pixels PX may be arranged in a stripe arrangement, a prism arrangement (diamond arrangement), a mosaic arrangement, and other forms to realize an image. Each pixel PX may include an organic light-emitting diode (OLED) as a display element (light-emitting element). The organic light-emitting diode OLED (refer to Figure 4a ) can be connected to the pixel circuit. The pixel circuit may include a plurality of transistors and at least one capacitor. The pixel PX may be connected to the pixel circuit by an organic light emitting diode OLED (refer to Figure 4a ) emits, for example, red, green, blue or white light. Each pixel PX may be connected to a corresponding at least one gate line among a plurality of gate lines GL and a corresponding data line among a plurality of data lines DL.

[0047] The gate lines GL may extend along the x direction (row direction) and be connected to the pixels PX in the same row. The gate lines GL may transmit gate signals to the pixels PX in the same row. The data lines DL may extend along the y direction (column direction) and be connected to the pixels PX in the same column. The data lines DL may transmit data signals to each of the pixels PX in the same column in synchronization with the gate signals.

[0048] In one embodiment, the peripheral area PA may be a non-display area where no pixels PX are arranged. In another embodiment, a plurality of pixels PX may be arranged in a portion of the peripheral area PA. For example, a plurality of pixels PX may be arranged to overlap the gate drive circuit 12 at least one corner of the peripheral area PA. Thus, the frame area may be reduced and the display area DA may be expanded.

[0049] The gate driving circuit 12 may be connected to a plurality of gate lines GL, generate a gate signal in response to a control signal GCS from the controller 14, and sequentially supply the generated gate signal to the gate lines GL. The gate lines GL may be connected to the gates of transistors included in the pixels PX. The gate signal may be a gate control signal that controls the on and off of the transistors whose gates are connected to the gate lines GL. The gate signal may be a signal including a gate-on voltage that enables the transistor to be turned on and a gate-off voltage that enables the transistor to be turned off.

[0050] exist Figure 2 The figure shows a situation where the pixel PX is connected to one gate line GL, but this is exemplary, and the pixel PX can be connected to more than two gate lines, and the gate driving circuit 12 can supply more than two gate signals with different timings for applying the gate-on voltage to the corresponding gate lines.

[0051] The data driving circuit 13 can convert the grayscale input image data DATA input from the controller 14 into a voltage data signal Vdata. Obviously, the data driving circuit 13 can also convert the grayscale input image data DATA input from the controller 14 into a current data signal.

[0052] The output line outputting the data signal Vdata from the data driving circuit 13 may be connected to the plurality of data lines DL. The data driving circuit 13 may supply the data signal Vdata to the plurality of output lines in response to the control signal DCS from the controller 14, and may selectively connect the plurality of output lines and the data lines DL corresponding to the plurality of output lines in response to the distribution control signal CCS from the controller 14. The data signal Vdata supplied to the data line DL may be supplied to the pixel PX supplied with the gate signal GS.

[0053] The controller 14 may generate control signals GCS, DCS, CCS, and PCS based on signals input from the outside, and supply them to the gate drive circuit 12, the data drive circuit 13, and the power supply circuit 15. The control signal GCS output to the gate drive circuit 12 may include a plurality of clock signals and a gate start signal. The control signal DCS output to the data drive circuit 13 may include a data start signal and a clock signal.

[0054] The power supply circuit 15 may generate a voltage required to drive the pixel PX in response to a control signal PCS from the controller 14. The power supply circuit 15 may generate a first driving voltage ELVDD and a second driving voltage ELVSS and supply them to the pixel PX. The first driving voltage ELVDD may be a high level voltage supplied to a terminal of a driving transistor connected to a first electrode (pixel electrode or anode) of a display element included in the pixel PX. The second driving voltage ELVSS may be a low level voltage supplied to a second electrode (counter electrode or cathode) of a display element included in the pixel PX.

[0055] The display device 10 may include a display panel, and the display panel may include a substrate. The pixel PX may be arranged in a display area DA of the substrate. A portion or all of the gate drive circuit 12 may be directly formed in the peripheral area PA of the substrate in the process of forming transistors constituting the pixel circuit in the display area DA of the substrate. The data drive circuit 13, the controller 14, and the power supply circuit 15 may be formed in the form of separate integrated circuit chips or one integrated circuit chip, respectively, and arranged on a flexible printed circuit board (FPCB: flexible Printed circuit board) electrically connected to a pad arranged on one side of the substrate. In another embodiment, the data drive circuit 13, the controller 14, and the power supply circuit 15 may be directly arranged on the substrate in a chip on glass (COG: Chip On Glass) or a chip on plastic (COP: Chip On Plastic) manner.

[0056] Figure 3 is a diagram schematically showing a display device according to an embodiment.

[0057] Reference Figure 3 The display device 10A may include a pixel portion 11A, a gate driving circuit 12A, a data driving circuit 13A, a controller 14A, and a power supply circuit 15A. The display device 10A may be Figure 2 An embodiment of the display device 10 shown in FIG. Figure 2 The display device 10 shown in FIG. 1 has the same configuration and description as that shown in FIG. 1 .

[0058] The pixel unit 11A may include a plurality of pixels PX. Each pixel PX may be connected to a gate signal GW (refer to Figure 4a and Figure 4b ) of the first gate line GWL, transmitting the second gate signal GI (refer to Figure 4a and Figure 4b ) of the second gate line GIL, transmitting the third gate signal GC (refer to Figure 4a and Figure 4b ) of the third gate line GCL, transmitting the fourth gate signal EM (refer to Figure 4a and Figure 4b ) of the fourth gate line EML, transmitting the fifth gate signal GB (refer to Figure 4a and Figure 4b ) and the data line DL transmitting the data signal Vdata. The light emission of the pixel PX is controlled by the fourth gate signal EM, so the fourth gate signal EM can also be called a light emission control signal, and the fourth gate line EML can also be called a light emission control line.

[0059] In addition, the pixel PX may receive a first driving voltage ELVDD (or first voltage), a second driving voltage ELVSS (or second voltage), a reference voltage VREF (or third voltage), a first initialization voltage VINT (or fourth voltage), and a second initialization voltage AINT (or fifth voltage).

[0060] The gate driving circuit 12A may be connected to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML, and the fifth gate line GBL, and may sequentially supply the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM, and the fifth gate signal GB to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML, and the fifth gate line GBL, respectively. The gate driving circuit 12A may be equipped with the first gate driving circuit to the fourth gate driving circuit. Each of the first gate driving circuit to the fourth gate driving circuit may include a plurality of stages.

[0061] The first gate driving circuit may be connected to a plurality of first gate lines GWL, and may sequentially supply a first gate signal GW to the first gate lines GWL. The second gate driving circuit may be connected to a plurality of second gate lines GIL and a plurality of third gate lines GCL, and may sequentially supply a second gate signal GI to the second gate lines GIL, and sequentially supply a third gate signal GC to the third gate lines GCL. The third gate driving circuit may be connected to a plurality of fourth gate lines EML, and may sequentially supply a fourth gate signal EM to the fourth gate lines EML. The fourth gate driving circuit may be connected to a plurality of fifth gate lines GBL, and may sequentially supply a fifth gate signal GB to the fifth gate line GBL.

[0062] In one embodiment, the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB may be supplied to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML and the fifth gate line GBL of each pixel row at a predetermined timing, respectively. In another embodiment, the first gate signal GW may be supplied to the first gate line GWL of each pixel row in sequence at a predetermined timing, and the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB may be supplied to the second gate line GIL, the third gate line GCL, the fourth gate line EML and the fifth gate line GBL of the two pixel rows at the same time, and may be supplied in sequence in units of two pixel rows. For example, the third gate driving circuit may supply the fourth gate signal EM to the fourth gate line EML of each of the two pixel rows at the same time, and may be supplied in sequence in units of two pixel rows.

[0063] The data driving circuit 13A may include a data driving section 150 and a data distribution section 170. The data driving section 150 may be connected to a plurality of output lines OL1 to OLk, and the plurality of output lines OL1 to OLk may be connected to a plurality of data lines DL through the data distribution section 170. The data driving section 150 may supply a data signal Vdata to the data distribution section 170 through the output lines OL1 to OLk.

[0064] The data distribution section 170 may be connected between a plurality of output lines OL1 to OLk and a plurality of data lines. The data distribution section 170 may include k (k is a natural number greater than 2) demultiplexers DMX having a plurality of switches. That is, the data distribution section 170 may be equipped with the same number of demultiplexers DMX as the number of output lines. One end of the demultiplexer DMX may be connected to a corresponding output line among the plurality of output lines OL1 to OLk. And, the other end of the demultiplexer DMX may be connected to m data lines. The demultiplexer DMX may supply the data signal Vdata supplied from the corresponding output line to the m data lines. The number of demultiplexers DMX included in the data distribution section 170 may be k, and each demultiplexer DMX may be connected to m data lines. In this case, the total number of data lines included in the data driving circuit 13A may be (k). By using the demultiplexer DMX, the number of required output lines is smaller than the number of data lines, so the number of output lines connected to the data driving unit 150 is reduced, thereby reducing the manufacturing cost. In addition, by using the demultiplexer DMX, the number of data driving circuits 13A used for driving at a frequency required by the display device 10 is reduced, thereby reducing power consumption. The demultiplexer DMX may include a plurality of switches (m switches) respectively connected to the corresponding output lines and the m data lines.

[0065] The power supply circuit 15A may supply the first driving voltage ELVDD and the second driving voltage ELVSS to the pixel PX of the pixel section 11A. The power supply circuit 15A may generate a reference voltage VREF, a first initialization voltage VINT, and a second initialization voltage AINT and supply them to the pixel PX of the pixel section 11A.

[0066] The controller 14A can generate control signals GCS1 to GCS4, CCS, DCS, PCS based on signals input from the outside, and supply them to the gate drive circuit 12A, the data drive circuit 13A, and the power supply circuit 15A. The controller 14A can supply corresponding control signals of the control signals GCS1 to GCS4 to each of the first gate drive circuit to the fourth gate drive circuit of the gate drive circuit 12A. The controller 14A can output the distribution control signal CCS to the data distribution unit 170, and the data distribution unit 170 can selectively connect the output lines OL1 to OLk with the data lines corresponding to the distribution control signal CCS. The controller 14A can output m distribution control signals CCS to each of the demultiplexers DMX, so that the m data signals supplied to one output line are supplied to the m data lines in time division. The m distribution control signals CCS can be output sequentially in a manner that does not overlap each other.

[0067] Figure 4a and Figure 4b is a diagram showing a method according to an embodiment Figure 3 Equivalent circuit diagram of a pixel.

[0068] Reference Figure 4a The pixel PX may include a pixel circuit PC and an organic light emitting diode OLED as a display element connected to the pixel circuit PC.

[0069] The pixel circuit PC of the pixel PX may include first to ninth transistors T1 to T9, a first capacitor C1, a second capacitor C2, and signal lines connected thereto. The signal lines may include a data line DL, a first gate line GWL, a second gate line GIL, a third gate line GCL, a fourth gate line EML, a fifth gate line GBL, a driving voltage line VDL, a reference voltage line VRL, a first initialization voltage line VIL1, and a second initialization voltage line VIL2.

[0070] The first transistor T1 may be a transistor having a gate-source voltage Vgs (refer to Fig. 9) determines the size of the source-drain current of the driving transistor, the second transistor T2 to the ninth transistor T9 can be a switching transistor that is turned on / off according to the gate-source voltage (substantially, the gate voltage). The first transistor T1 to the ninth transistor T9 can be implemented as a thin film transistor. Depending on the type of transistor (p-type or n-type) and / or operating conditions, the first terminal of each of the first transistor T1 to the ninth transistor T9 can be a source or a drain, and the second terminal can be the other of the source and the drain. For example, in the case where the first terminal is a source, the second terminal can be a drain.

[0071] The first transistor T1 to the ninth transistor T9 may be P-type silicon thin film transistors. The gate-on voltage of the gate signal that turns on the first transistor T1 to the ninth transistor T9 may be a low-level voltage (second-level voltage), and the gate-off voltage of the gate signal that turns off the first transistor T1 to the ninth transistor T9 may be a high-level voltage (first-level voltage).

[0072] The first transistor T1 may be connected between the driving voltage line VDL and the organic light emitting diode OLED. The first transistor T1 may be connected to the driving voltage line VDL via the fifth transistor T5, and may be electrically connected to the organic light emitting diode OLED via the sixth transistor T6. The first transistor T1 includes a gate connected to the first node N1, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first transistor T1 may supply a driving current corresponding to a voltage applied to the first node N1 according to a switching operation of the second transistor T2 to the organic light emitting diode OLED.

[0073] The second transistor T2 may be connected between the data line DL and the fourth node N4. The second transistor T2 may include a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the fourth node N4. The second transistor T2 may be turned on according to the first gate signal GW received through the first gate line GWL, thereby transmitting the data signal Vdata transmitted through the data line DL to the fourth node N4.

[0074] The third transistor T3 may be connected between the first node N1 and the third node N3. The third transistor T3 may be connected to the organic light emitting diode OLED via the sixth transistor T6. The third transistor T3 may include a gate connected to the third gate line GCL, a first terminal connected to the third node N3, and a second terminal connected to the first node N1. The third transistor T3 may be turned on according to the third gate signal GC received through the third gate line GCL, so that the first transistor T1 may have a diode connection form. In the case where the first transistor T1 has a diode connection form, the threshold voltage of the first transistor T1 may be compensated.

[0075] The fourth transistor T4 may be connected between the first node N1 and the first initialization voltage line VIL1. The fourth transistor T4 may include a gate connected to the second gate line GIL, a first terminal connected to the first node N1, and a second terminal connected to the first initialization voltage line VIL1. The fourth transistor T4 may be turned on according to the second gate signal GI received through the second gate line GIL, transmit the first initialization voltage VINT to the first node N1, and thereby initialize the first node N1 (i.e., the gate of the first transistor T1).

[0076] The fifth transistor T5 may be connected between the driving voltage line VDL and the second node N2. The fifth transistor T5 may include a first gate and a second gate. The fifth transistor T5 may be a double-gate transistor including a first gate as a top gate arranged at an upper portion of the semiconductor and a second gate as a bottom gate arranged at a lower portion of the semiconductor. In one embodiment, referring to Figure 4a , the fifth transistor T5 may include a first gate connected to the fourth gate line EML, a second gate connected to the third gate line GCL, a first terminal connected to the driving voltage line VDL, and a second terminal connected to the second node N2. In another embodiment, referring to Figure 4b The fifth transistor T5 may include a first gate connected to the third gate line GCL, a second gate connected to the fourth gate line EML, a first terminal connected to the driving voltage line VDL, and a second terminal connected to the second node N2.

[0077] The sixth transistor T6 may be connected between the third node N3 and the organic light emitting diode OLED. The sixth transistor T6 may include a gate connected to the fourth gate line EML, a first terminal connected to the third node N3, and a second terminal connected to the pixel electrode of the organic light emitting diode OLED.

[0078] If the fifth transistor T5 and the sixth transistor T6 are simultaneously turned on according to the fourth gate signal EM received through the fourth gate line EML, a driving current may flow in the organic light emitting diode OLED.

[0079] The seventh transistor T7 may be connected between the organic light emitting diode OLED and the second initialization voltage line VIL2. The seventh transistor T7 may include a gate connected to the fifth gate line GBL, a first terminal connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light emitting diode OLED, and a second terminal connected to the second initialization voltage line VIL2. The seventh transistor T7 may be turned on according to the fifth gate signal GB received through the fifth gate line GBL, and transmit the second initialization voltage AINT to the pixel electrode of the organic light emitting diode OLED, thereby initializing the pixel electrode of the organic light emitting diode OLED.

[0080] The eighth transistor T8 may be connected between the fourth node N4 and the reference voltage line VRL. The eighth transistor T8 may include a gate connected to the third gate line GCL, a first terminal connected to the fourth node N4, and a second terminal connected to the reference voltage line VRL. The gate of the eighth transistor T8 may be connected to the gate of the third transistor T3. The eighth transistor T8 may be turned on according to the third gate signal GC received through the third gate line GCL, and transmit the reference voltage VREF to the fourth node N4, thereby initializing the fourth node N4.

[0081] The ninth transistor T9 may be connected to the second node N2 and may supply a bias voltage Vbias to the first terminal of the first transistor T1. The ninth transistor T9 may include a gate connected to the fifth gate line GBL, a first terminal connected to the bias voltage line VBL supplying the bias voltage Vbias, and a second terminal connected to the first terminal of the first transistor T1. The ninth transistor T9 may be turned on according to the fifth gate signal GB received through the fifth gate line GBL, transmit the bias voltage Vbias to the first terminal of the first transistor T1, control the gate-source voltage of the first transistor T1, and thus compensate for the current characteristic change of the first transistor T1.

[0082] The first capacitor C1 may be connected between the first node N1 and the fourth node N4. The first capacitor C1 may store a voltage corresponding to a voltage difference between the first node N1 and the fourth node N4. The first capacitor C1 may be a storage capacitor. The first capacitor C1 may store a threshold voltage of the first transistor T1 and a data signal Vdata written by the second transistor T2.

[0083] The second capacitor C2 may be connected between the driving voltage line VDL and the fourth node N4. The second capacitor C2 may store a voltage corresponding to a voltage difference between the driving voltage line VDL and the fourth node N4. The second capacitor C2 may maintain the data signal Vdata written through the second transistor T2.

[0084] The organic light emitting diode OLED may include a pixel electrode (eg, an anode) and an opposite electrode (eg, a cathode) facing the pixel electrode, and the opposite electrode may receive a second driving voltage ELVSS. The organic light emitting diode OLED may receive a driving current corresponding to a data signal Vdata from the first transistor T1 and emit light in a predetermined color, thereby displaying an image.

[0085] In one embodiment, the plurality of transistors included in the pixel circuit may be P-type transistors. In another embodiment, the plurality of transistors included in the pixel circuit may be N-type transistors, or a portion may be N-type transistors and another portion may be P-type transistors.

[0086] The transistor according to the embodiment of the present invention may be one of an amorphous silicon thin film transistor (amorphous-Si TFT), a low temperature polycrystalline silicon (LTPS: Low Temperature Poly-Silicon) thin film transistor and an oxide thin film transistor (Oxide TFT). The oxide thin film transistor (Oxide TFT) may have an oxide such as amorphous indium gallium zinc oxide (IGZO: Indium-Galium-Zinc-Oxide), zinc oxide (ZnO: Zinc-Oxide), titanium oxide (TiO: TitanumOxide) as a semiconductor layer (active layer).

[0087] Figure 5 It is shown that the supply to Figure 3 Graph of the pixel signal.

[0088] During the non-light emitting period NEP, the gate driving circuit 12A may supply the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB to the first gate line GWL, the second gate line GIL, the third gate line GCL, the fourth gate line EML and the fifth gate line GBL, respectively. The start timing and the end timing of the gate-on voltage holding period and the gate-off voltage holding period of the first gate signal GW, the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB may be the same or different.

[0089] During the non-emission period NEP, the power supply circuit 15A may supply the first driving voltage ELVDD to the driving voltage line VDL, the reference voltage VREF to the reference voltage line VRL, the first initialization voltage VINT to the first initialization voltage line VIL1 , and the second initialization voltage AINT to the second initialization voltage line VIL2 .

[0090] Reference Figure 5, the non-luminous period NEP may include a period for writing a data signal corresponding to an image. The period when the fourth gate signal EM is a gate-off voltage may be the non-luminous period NEP, and the period when the fourth gate signal EM is a gate-on voltage may be the luminous period EP. The non-luminous period NEP may include at least one initialization period and a compensation period. The non-luminous period NEP may include a first interval P1 to a sixth interval P6.

[0091] The first interval P1 and the third interval P3 may be an initialization period for initializing the first node N1 to which the gate of the first transistor T1 is connected.

[0092] In the first interval P1 and the third interval P3, the second gate signal GI of the gate-on voltage (second level voltage) may be supplied to the second gate line GIL. The first gate signal GW, the third gate signal GC, the fourth gate signal EM, and the fifth gate signal GB of the gate-off voltage (first level voltage) may be supplied to the first gate line GWL, the third gate line GCL, the fourth gate line EML, and the fifth gate line GBL, respectively. The fourth transistor T4 may be turned on by the second gate signal GI, and the gate of the first transistor T1 may be initialized to the first initialization voltage VINT.

[0093] The second interval P2 and the fourth interval P4 may be compensation periods for compensating for the threshold voltage of the first transistor T1 .

[0094] In the second interval P2 and the fourth interval P4, the third gate signal GC of the gate-on voltage may be supplied to the third gate line GCL. The first gate signal GW, the second gate signal GI, the fourth gate signal EM, and the fifth gate signal GB of the gate-off voltage may be supplied to the first gate line GWL, the second gate line GIL, the fourth gate line EML, and the fifth gate line GBL, respectively. The third transistor T3, the fifth transistor T5, and the eighth transistor T8 may be turned on by the third gate signal GC.

[0095] The first driving voltage ELVDD may be supplied to the second node N2 through the turned-on fifth transistor T5, and the reference voltage VREF may be supplied to the fourth node N4 through the turned-on eighth transistor T8. The difference (ELVDD-Vth) between the first driving voltage ELVDD and the threshold voltage (Vth) of the first transistor T1 may be supplied to the gate of the first transistor T1 in a diode connection state through the turned-on third transistor T3. A voltage corresponding to the threshold voltage (Vth) of the first transistor T1 may be charged to the first capacitor C1. That is, the pixel PX may compensate for the threshold voltage of the first transistor T1 through the constant voltage reference voltage VREF and the first driving voltage ELVDD.

[0096] During the first interval P1 to the fourth interval P4, initialization and threshold voltage compensation are repeated alternately, so that the on-bias voltage is applied to the first transistor T1 a predetermined number of times, so that the threshold voltage of the first transistor T1 is shifted in a predetermined direction, thereby compensating for hysteresis. The on-bias voltage may be a voltage difference between the gate and the source (first terminal) of the first transistor T1 that turns on the first transistor T1. Initialization and threshold voltage compensation may be repeated alternately multiple times. Figure 5 An example in which initialization and threshold voltage compensation are repeated twice alternately is shown in FIG. In another embodiment, initialization and threshold voltage compensation may be repeated once respectively.

[0097] The fifth interval P5 may be a writing interval (data programming interval) in which a data signal is applied to the pixel PX. In the fifth interval P5, a voltage corresponding to the data signal may be transmitted to the gate of the driving transistor (the first transistor T1).

[0098] In the fifth interval P5, the first gate signal GW of the gate-on voltage may be supplied to the first gate line GWL, and the second gate signal GI, the third gate signal GC, the fourth gate signal EM and the fifth gate signal GB of the gate-off voltage may be supplied to the second gate line GIL, the third gate line GCL, the fourth gate line EML and the fifth gate line GBL, respectively.

[0099] The second transistor T2 may be turned on by the first gate signal GW. The turned-on second transistor T2 may transmit the data signal Vdata supplied from the data line DL to the fourth node N4. Thus, the voltage of the fourth node N4 may change by a voltage corresponding to the difference between the reference voltage VREF and the data signal Vdata, and the voltage of the first node N1 may also change corresponding to the voltage change amount of the fourth node N4. Thus, a data voltage corresponding to the threshold voltage (Vth) of the first transistor T1 and the data signal Vdata may be charged to the first capacitor C1.

[0100] The sixth interval P6 may be a period in which the bias voltage Vbias is applied to the first transistor T1 and the second initialization voltage AINT is applied to the organic light emitting diode OLED.

[0101] In the sixth interval P6, the fifth gate signal GB of the gate-on voltage may be supplied to the fifth gate line GBL. The first gate signal GW, the second gate signal GI, the third gate signal GC and the fourth gate signal EM of the gate-off voltage may be supplied to the first gate line GWL, the second gate line GIL, the third gate line GCL and the fourth gate line EML, respectively.

[0102] The pixel electrode of the organic light emitting diode OLED can be initialized to the second initialization voltage AINT through the turned-on seventh transistor T7. Therefore, the sixth interval P6 can be a period for initializing the pixel electrode of the organic light emitting diode OLED. The bias voltage Vbias of a constant voltage can be supplied to the second node N2 through the turned-on ninth transistor T9. Therefore, the sixth interval P6 can be a bias period for supplying the bias voltage Vbias to the first terminal of the first transistor T1.

[0103] During the light emission period EP, the organic light emitting diode OLED may emit light. During the light emission period EP, a fourth gate signal EM of a gate-on voltage may be supplied to a fourth gate line EML. A first gate signal GW, a second gate signal GI, a third gate signal GC, and a fifth gate signal GB of a gate-off voltage may be supplied to a first gate line GWL, a second gate line GIL, a third gate line GCL, and a fifth gate line GBL, respectively. The fifth transistor T5 and the sixth transistor T6 may be turned on by the fourth gate signal EM.

[0104] A current path from the driving voltage line VDL to the organic light emitting diode OLED may be formed by the turned-on fifth transistor T5 and sixth transistor T6. The first transistor T1 may output a driving current having a magnitude corresponding to the data voltage stored in the first capacitor C1, and the organic light emitting diode OLED may emit light at a brightness corresponding to the magnitude of the driving current regardless of the threshold voltage (Vth) of the first transistor T1.

[0105] Figure 6a and Figure 6b is a diagram illustrating a demultiplexer according to an embodiment, Figure 7 Yes Description Figure 6a and Figure 6b The timing diagram of the switching operation of the demultiplexer is shown in FIG. Figure 6b The demultiplexer is applied Figure 6a Example of a demultiplexer. Figure 6a Can be Figure 3 An embodiment of a demultiplexer DMX is shown in FIG.

[0106] Figure 6a is an example of a demultiplexer DMX that selectively connects the k-th output line OLk with a pair of adjacent 2k-1-th data line DL2k-1 and 2k-th data line DL2k. The demultiplexer DMX may include a first switch SW1 and a second switch SW2.

[0107] The first switch SW1 may be provided between the kth output line OLk and the 2k-1th data line DL2k-1. The first switch SW1 may connect the kth output line OLk and the 2k-1th data line DL2k-1 through the first control signal CLA, and may apply the data signal Vdata applied to the kth output line OLk to the 2k-1th data line DL2k-1.

[0108] The second switch SW2 may be provided between the kth output line OLk and the 2kth data line DL2k. The second switch SW2 may connect the kth output line OLk and the 2kth data line DL2k by the second control signal CLB and may apply the data signal Vdata applied to the kth output line OLk to the 2kth data line DL2k.

[0109] The distribution control signal CCS may include a first control signal CLA and a second control signal CLB. The first control signal CLA and the second control signal CLB may be alternately applied at different timings without overlapping.

[0110] The plurality of pixels PX may include a first pixel PR, a second pixel PB, and a third pixel PG that emit light of different colors from each other. In one embodiment, the first pixel PR and the second pixel PB may be alternately arranged in a column M1 in which the 2k-1th data line DL2k-1 is arranged, and may be connected to the 2k-1th data line DL2k-1. The third pixel PG may be repeatedly arranged in a column M2 in which the 2kth data line DL2k is arranged, and may be connected to the 2kth data line DL2k. One of the 2k-1th data line DL2k-1 and the 2kth data line DL2k may be an odd data line DLo, and the other may be an even data line DLe. Figure 6a 2k-1 data line DL2k-1 is an odd data line DLo and 2k data line DL2k is an even data line DLe. A pair of data lines connected to the demultiplexer DMX may be a pair of odd data lines and even data lines spaced apart and arranged at a column interval. The first pixel PR may be a red pixel emitting red light, the second pixel PB may be a blue pixel emitting blue light, and the third pixel PG may be a green pixel emitting green light.

[0111] exist Figure 6a Pixels PX connected to the n-1th gate line GLn-1 arranged in the n-1th row and the nth gate line GLn arranged in the nth row are shown in FIG. Figure 6a Each of the gate lines GLn-1, GLn shown in FIG. Figure 4a The first gate line GWL is shown in FIG. Figure 6a Each of the gate signals Gn-1, Gn shown in FIG. 4 may be the first gate signal GW shown in FIG. 4 .

[0112] Reference Figure 6b The data distribution unit 170A may include a plurality of demultiplexers 172A, and the pixel unit 11 may include a plurality of pixels PX. The data distribution unit 170A may be Figure 3 An embodiment of the data distribution unit 170 is shown in FIG.

[0113] In the pixel portion 11, the columns in which the first pixels PR and the second pixels PB are alternately arranged and the columns in which the third pixels PG are repeatedly arranged may be alternately repeated in the row direction. A plurality of gate lines and a plurality of data lines may be arranged in the pixel portion 11. In one embodiment, each of the gate lines may be Figure 4a The first gate line GWL shown in FIG. Figure 6b , for ease of explanation, gate signals Gn-3 to Gn of the n-3rd to nth rows, gate lines GLn-3 to GLn, and data lines DL1 to DL8 of the 1st to 8th columns are shown. The data lines may include odd-numbered data lines (e.g., DL1, DL3, DL5, DL7, ...) and even-numbered data lines (e.g., DL2, DL4, DL6, DL8, ...). A pair of data lines connected to the demultiplexer 172A may be a pair of odd-numbered data lines and even-numbered data lines. Below, the demultiplexer 172A connected to the first output line OL1 is used as an example for explanation, which can be applied to the demultiplexer 172A connected to the remaining output lines in the same manner.

[0114] The demultiplexer 172A may include a first switch SW1 and a second switch SW2 .

[0115] The first switch SW1 may be provided between the first output line OL1 and the first data line DL1. The first switch SW1 may be a transistor including a gate connected to the first control line CL1, a first terminal connected to the first output line OL1, and a second terminal connected to the first data line DL1. The first switch SW1 may connect the first output line OL1 with the first data line DL1 by being turned on by a first control signal CLA applied from the first control line CL1, and may apply a data signal Vdata applied to the first output line OL1 to the first data line DL1.

[0116] The second switch SW2 may be provided between the first output line OL1 and the second data line DL2. The second switch SW2 may be a transistor including a gate connected to the second control line CL2, a first terminal connected to the first output line OL1, and a second terminal connected to the second data line DL2. The second switch SW2 may be turned on by a second control signal CLB applied from the second control line CL2 to connect the first output line OL1 with the second data line DL2, and may apply a data signal Vdata applied to the first output line OL1 to the second data line DL2.

[0117] The data signal Vdata may include a first data signal applied to the first pixel PR, a second data signal applied to the second pixel PB, and a third data signal applied to the third pixel PG.

[0118] Figure 7 The control signal applied to the control line of the demultiplexer according to an embodiment is schematically shown. Hereinafter, supplying any signal may refer to supplying the on-voltage of the signal.

[0119] Reference Figure 7 , the first control signal CLA and the second control signal CLB can be transmitted through the first control line CL1 ( Figure 6b ) and the second control line CL2 ( Figure 6b ) from the controller 14 ( Figure 2 ) is supplied to the demultiplexer 172A. The first control signal CLA and the second control signal CLB may be gate control signals for controlling the turning on and off of the first switch SW1 and the second switch SW2 of the demultiplexer 172A. The first control signal CLA and the second control signal CLB may be square wave signals that repeat a turn-on voltage that enables the first switch SW1 and the second switch SW2 to be turned on and a turn-off voltage that enables the first switch SW1 and the second switch SW2 to be turned off. In one embodiment, the turn-on voltage of the first control signal CLA and the second control signal CLB may be a low level voltage (second level voltage), and the turn-off voltage may be a high level voltage (first level voltage).

[0120] The first control signal CLA and the second control signal CLB may be signals having the same waveform and phase shift. For example, the second control signal CLB may have the same waveform as the first control signal CLA, and may be applied with a phase shift (phase delay) at a predetermined interval. In one embodiment, the second control signal CLB may be applied after the first control signal CLA is applied. The timing at which the voltage levels of the first control signal CLA and the second control signal CLB are inverted may be the same. The period of maintaining the on-voltage of the first control signal CLA (hereinafter referred to as the "on-voltage period") and the period of maintaining the off-voltage (hereinafter referred to as the "off-voltage period") may overlap with the off-voltage period and the on-voltage period of the second control signal CLB, respectively. The horizontal period of the first control signal CLA and the second control signal CLB may be approximately 1H.

[0121] Figure 8a is a diagram showing a portion of a display device according to an embodiment. Figure 8a shows a dual gate Figure 4a A fifth transistor and a light emitting element. Figure 8b and Figure 8c is a cross-sectional view for explaining the structure and operation of a fifth transistor according to an embodiment.

[0122] Reference Figure 8a , a thin film transistor T5 including a dual gate may be disposed on the substrate SUB.

[0123] The substrate SUB may include a glass material, a ceramic material, a metal material, or a material having a flexible or bendable property. The substrate SUB may have a single-layer structure of an organic layer or a multi-layer structure of an organic layer and an inorganic layer. For example, the substrate SUB may be a stacked structure of a first substrate layer / a barrier layer / a second substrate layer. The first substrate layer and the second substrate layer may be organic layers respectively including a polymer resin. The first substrate layer and the second substrate layer may include a transparent polymer resin. The barrier layer may be a barrier layer as a barrier layer to prevent penetration of external foreign matter, and may include a silicon nitride (SiN x ) or silicon oxide (SiO x ) or other inorganic materials.

[0124] A buffer layer Buffer may be disposed on the upper portion of the substrate SUB, and a second gate electrode G52 of the thin film transistor T5 including a double gate may be disposed between the substrate SUB and the buffer layer Buffer. The second gate electrode G52 may be disposed to correspond to at least the channel region C5 of the thin film transistor T5. The buffer layer Buffer may include SiO 2 or SiN x A single or multi-layer inorganic insulating layer.

[0125] A semiconductor layer SACT may be disposed on the upper portion of the buffer layer Buffer, and the semiconductor layer SACT may include a silicon semiconductor (p-si: Poly-silicon). The semiconductor layer SACT may have a shape that is bent in various shapes. Figure 8a As shown, the semiconductor layer SACT may include a channel region C5 of the fifth transistor T5, a source region S5 and a drain region D5 on both sides of the channel region C5. When viewed in the z-axis direction, the region overlapping the gate electrode of the thin film transistor may be a channel region. That is, the channel region C5, the source region S5 and the drain region D5 of the fifth transistor T5 may be understood as a partial region of the semiconductor layer SACT. The source region S5 and the drain region D5 of the semiconductor layer SACT may correspond to the first terminal (or second terminal) and the second terminal (or first terminal) of the transistor. The source region or the drain region may also be interpreted as the source electrode or the drain electrode of the transistor according to the circumstances. For example, the source electrode and the drain electrode of the fifth transistor T5 may correspond to the source region S5 and the drain region D5 doped with impurities near the channel region C5, respectively.

[0126] The first insulating layer GI1 may be arranged on the upper portion of the buffer layer Buffer in a manner of covering the semiconductor layer SACT, and the second insulating layer GI2 may be arranged on the upper portion of the first insulating layer GI1. The first gate electrode G51 of the fifth transistor T5 may be arranged between the first insulating layer GI1 and the second insulating layer GI2 in an island form. The first insulating layer GI1 and the second insulating layer GI2 may include silicon nitride (SiN x ) or silicon oxide (SiO x ) and other inorganic substances.

[0127] The third insulating layer ILD1 may be disposed on the upper portion of the second insulating layer GI2, and the fourth insulating layer ILD2 may be disposed on the upper portion of the third insulating layer ILD1. On the third insulating layer ILD1, the third gate line GCL and the fourth gate line EML may extend and be disposed along the x direction. In addition, the connection electrode SD1 may be disposed on the third insulating layer ILD1.

[0128] One end of the connection electrode SD1 can be electrically connected to the drain region D5 of the fifth transistor T5 through a contact hole CNT12 penetrating the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer ILD1. The other end of the connection electrode SD1 can be electrically connected to the connection electrode SD2 arranged on the fourth insulating layer ILD2 through a contact hole CNT2 penetrating the fourth insulating layer ILD2.

[0129] The gate electrodes G51 and G52 of the fifth transistor T5 may include a second gate electrode G52 as part of the third gate line GCL and a first gate electrode G51 as part of the fourth gate line EML. The first gate electrode G51 may be a top gate electrode, and the second gate electrode G52 may be a bottom gate electrode. That is, the fifth transistor T5 may have a dual-gate structure in which control electrodes are provided at the upper and lower parts of the first semiconductor layer SACT, respectively.

[0130] The first gate electrode G51 of the fifth transistor T5 may be electrically connected to the fourth gate line EML through a contact hole CNT11 formed in the second insulating layer GI2 and the third insulating layer ILD1, and the second gate electrode G52 may be electrically connected to the third gate line GCL through a contact hole CNT13 formed in the buffer layer Buffer, the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer ILD1. The drain region D5 of the fifth transistor T5 may be electrically connected to the connection electrode SD1 through a contact hole CNT12 formed in the first insulating layer GI1, the second insulating layer GI2, and the third insulating layer ILD1.

[0131] In another embodiment, if Figure 4b As shown, the third gate line GCL may be connected to the first gate electrode G51 as a top gate electrode, and the fourth gate line EML may be connected to the second gate electrode G52 as a lower gate electrode.

[0132] The fourth insulating layer ILD2 may be arranged on the upper portion of the third insulating layer ILD1, and the driving voltage line VDL may extend and be arranged along the x direction on the fourth insulating layer ILD2. In addition, the connection electrode SD2 may be arranged on the fourth insulating layer ILD2. The driving voltage line VDL may be electrically connected to the connection electrode SD1 through the contact hole CNT2 formed in the fourth insulating layer ILD2. The connection electrode SD1 is electrically connected to the drain region D5 of the fifth transistor T5, and therefore, the driving voltage line VDL may be electrically connected to the drain region D5 of the fifth transistor T5. In another embodiment, in order to improve the resolution of the display device, the driving voltage line VDL may be directly connected to the drain region D5 through the contact hole CNT2 formed in the fourth insulating layer ILD2, without passing through the contact hole CNT12 formed in the third insulating layer ILD1. That is, although not shown, the drain region D5 of the fifth transistor T5 may be electrically connected to the driving voltage line VDL through the contact hole CNT2 formed in the fourth insulating layer ILD2 without the contact hole CNT12 formed in the third insulating layer ILD1.

[0133] The fifth insulating layer VIA may be arranged on the upper portion of the fourth insulating layer ILD2, and the organic light emitting diode OLED may be arranged on the fifth insulating layer VIA as a light emitting element. The organic light emitting diode OLED may include a pixel electrode 810, an intermediate layer 820, and an opposite electrode 830. The pixel electrode 810 may be arranged on the fifth insulating layer VIA. The intermediate layer 820 may be arranged on the upper portion of the pixel electrode 810, and the opposite electrode 830 may be arranged on the upper portion of the intermediate layer 820.

[0134] The intermediate layer 820 of the organic light emitting diode OLED may include a low molecular substance or a high molecular substance. In the case of including a low molecular substance, the hole injection layer (HIL), the hole transport layer (HTL), the emission layer (EML), the electron transport layer (ETL), the electron injection layer (EIL), etc. may have a structure stacked in a single or composite structure, and may include various organic substances such as copper phthalocyanine (CuPc), N, N-di (naphthalene-1-yl)-N, N'-diphenyl-benzidine (NPB: N, N'-Di (naphthalene-1-yl)-N, N'-diphenyl-benzidine), tris-8-hydroxyquinoline aluminum (tris-8-hydroxyquinoline aluminum) (Alq3), etc. These layers may be formed by a vacuum deposition method.

[0135] In the case where the intermediate layer 820 includes a polymer substance, it can generally have a structure including a hole transport layer and a light emitting layer. In this case, the hole transport layer can include PEDOT, and the light emitting layer can include a polymer substance such as a polyphenylenevinylene (PPV: Poly-Phenylenevinylene) system and a polyfluorene (Polyfluorene) system. Such an intermediate layer 820 can be formed by screen printing or inkjet printing method, laser induced thermal imaging (LITI: Laser induced thermal imaging), etc.

[0136] The intermediate layer 820 is not necessarily limited thereto, and can obviously have various structures. In addition, the intermediate layer 820 can also be included as an integral layer in the plurality of pixel electrodes 810 , or can also include a layer patterned to correspond to the plurality of pixel electrodes 810 .

[0137] The counter electrode 830 may be integrally formed in the plurality of organic light emitting diodes and correspond to the plurality of pixel electrodes 810 .

[0138] Such an organic light emitting diode OLED may be easily damaged by moisture or oxygen from the outside, so a thin film encapsulation layer (not shown) or a sealing substrate (not shown) may be arranged on its upper part to cover such an organic light emitting diode and protect it. The thin film encapsulation layer (not shown) may cover the display area DA and extend to the outside of the display area DA. Such a thin film encapsulation layer may include an inorganic encapsulation layer prepared using at least one inorganic substance and an organic encapsulation layer prepared using at least one organic substance.

[0139] A pixel definition layer PDL may be disposed on the upper portion of the fifth insulating layer VIA. The pixel definition layer PDL has an opening corresponding to each pixel (i.e., an opening that exposes at least the central portion of the pixel electrode 810), thereby defining the pixel. In addition, the pixel definition layer PDL increases the distance between the edge of the pixel electrode 810 and the counter electrode 830 on the upper portion of the pixel electrode 810, thereby preventing arcing from being generated at the edge of the pixel electrode 810. For example, the pixel definition layer PDL may be formed using an organic substance such as polyimide or hexamethyldisiloxane (HMDSO).

[0140] Reference Figure 8b The fourth gate signal EM or the third gate signal GC may be applied to the first gate electrode G51 as the top gate electrode. If the gate signal is applied to the first gate electrode G51 so that the gate-source voltage is above the threshold voltage, a first channel may be formed from the drain region D5 to the source region S5.

[0141] Reference Figure 8c , the third gate signal GC or the fourth gate signal EM can be applied to the second gate electrode G52 as the lower gate electrode. If the gate signal is applied to the second gate electrode G52 so that the gate-source voltage is above the threshold voltage, a second channel can be formed from the drain region D5 to the source region S5.

[0142] The thickness T of the insulating layer between the first gate electrode G51 and the semiconductor layer SACT TGI may be smaller than the thickness T of the insulating layer between the second gate electrode G52 and the semiconductor layer SACT. SGI That is, the thickness of the first insulating layer GI1 on which the first gate electrode G51 is disposed may be smaller than the thickness of the buffer layer Buffer on which the second gate electrode G52 is disposed.

[0143] Fig. 9It is a figure which shows the experimental result for demonstrating the effect of this invention.

[0144] Fig. 9 1 is a graph showing the thickness T of the insulating film between the second gate electrode G52 and the semiconductor layer SACT in the thin film transistor T5 having a double gate including the first gate electrode G51 and the second gate electrode G52. SGI 2600 In the case of TGI 1400 In the case of TGI and the insulating film thickness T between the second gate electrode G52 and the semiconductor layer SACT SGI The gate-source voltage V GS The current I flowing through the channel DS A graph of the size of .

[0145] Reference Fig. 9 , we know that the gate-source voltage V GS When both are 15V, the thickness T of the insulating film between the second gate electrode G52 and the semiconductor layer SACT SGI 2600 When a gate signal is applied to the second gate electrode G52, the current I flowing through the second channel on1 The strength of the insulating film between the first gate electrode G51 and the semiconductor layer SACT is compared with TGI 1400 When a gate signal is applied to the first gate electrode G51, the current I flowing through the first channel on2 That is, the smaller the thickness of the insulating film between the gate electrode and the semiconductor layer SACT is, the greater the intensity of the current flowing through the channel formed in the semiconductor layer SACT is.

[0146] In addition, refer to Fig. 9 , we know that the gate-source voltage V GS When both are 15V, the thickness T of the insulating film between the first gate electrode G51 and the semiconductor layer SACT TGI 1400 When a gate signal is applied to the first gate electrode G51, the current I flowing through the first channel on2 The strength of the insulating film between the first gate electrode G51 and the semiconductor layer SACT is compared with TGI and the insulating film thickness T between the second gate electrode G52 and the semiconductor layer SACT SGIWhen a gate signal is applied to the first gate electrode G51 and / or the second gate electrode G52 under the same conditions (sync), the current I flowing through the first channel and / or the second channel on3 That is, the thickness T of the insulating film between the first gate electrode G51 and the semiconductor layer SACT is TGI and the insulating film thickness T between the second gate electrode G52 and the semiconductor layer SACT SGI The more nearly the same (sync) they are, the greater the intensity of the current flowing through the channel formed in the semiconductor layer SACT.

[0147] Therefore, according to one embodiment of the present invention, even if the fifth transistor T5 includes a double gate, the intensity of the current flowing in the second channel formed in the semiconductor layer SACT can be controlled to increase by reducing the thickness of the insulating film between the second gate electrode G52 and the semiconductor layer SACT, or by making the thickness of the insulating film between the second gate electrode G52 and the semiconductor layer SACT similar to the thickness of the insulating film between the first gate electrode G51 and the semiconductor layer SACT.

[0148] In the embodiment of the present invention, the number of gate signals required for pixel driving is reduced by using a thin film transistor including a double gate, so that the number of gate driving circuits can be reduced, thereby reducing the manufacturing cost of the display device.

[0149] The steps of the method or algorithm described in connection with the embodiments of the present invention may be directly implemented by hardware, or may be implemented by a software module executed by hardware, or may be implemented by a combination thereof. The software module may reside in a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a hard disk, a removable hard disk, a CD-ROM, or any form of computer-readable recording medium known in the technical field to which the present invention belongs.

[0150] The embodiments of the present invention are described above with reference to the accompanying drawings, but those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing its technical ideas or essential features. Therefore, it should be understood that the embodiments described above are exemplary in all aspects and are not restrictive.

Claims

1. A display device, as a display device comprising a plurality of pixels, wherein: Each of the plurality of pixels comprises: Light emitting element; a first transistor for controlling a current supplied to the light emitting element; A second transistor connected to the data line; a third transistor connected between the second terminal of the first transistor and the gate of the first transistor; a fifth transistor connected between the first terminal of the first transistor and a driving voltage line; and a sixth transistor connected between the second terminal of the first transistor and the light emitting element, The first gate of the fifth transistor and the gate of the sixth transistor are connected to a fourth gate line supplying a fourth gate signal, and the gate of the third transistor and the second gate of the fifth transistor are connected to a third gate line supplying a third gate signal.

2. The display device according to claim 1, wherein: Each of the plurality of pixels further comprises: a first capacitor connected between the gate of the first transistor and the second terminal of the second transistor; a second capacitor connected between the second terminal of the second transistor and the driving voltage line; a fourth transistor connected between the gate of the first transistor and the first voltage line; a seventh transistor connected between the light emitting element and the second voltage line; an eighth transistor connected between the second terminal of the second transistor and a third voltage line; and A ninth transistor supplies a bias voltage to the first terminal of the first transistor.

3. The display device according to claim 2, wherein: The display device further includes a data driving circuit that supplies a plurality of data signals to the plurality of pixels. The data driving circuit includes a demultiplexer that supplies a data signal to a first data line based on a first control signal, supplies the data signal to a second data line based on a second control signal, and alternately performs supply of the data signal to the first data line and supply of the data signal to the second data line.

4. The display device according to claim 3, wherein: The demultiplexer comprises: A first switch transistor connected to the first data line; and a second switch transistor connected to the second data line, Wherein, after the first control signal is supplied to the gate of the first switch transistor, the second control signal is supplied to the gate of the second switch transistor.

5. The display device according to claim 3, wherein: Each of the plurality of pixels is one of a first pixel emitting red light, a second pixel emitting green light, and a third pixel emitting blue light, The first pixel and the third pixel are connected to the first data line, and the second pixel is connected to the second data line.

6. The display device according to claim 3, wherein: The data driving circuit comprises: A data driving unit, outputting the data signal; and The data distribution unit supplies the data signal alternately to the first data line and the second data line based on the first control signal and the second control signal.

7. The display device according to claim 3, wherein: The gate of the eighth transistor is connected to the third gate line, The gate of the second transistor is connected to a first gate line supplying a first gate signal. The gate of the fourth transistor is connected to a second gate line supplying a second gate signal. A gate of the seventh transistor and a gate of the ninth transistor are connected to a fifth gate line supplying a fifth gate signal.

8. The display device according to claim 7, wherein: The display device further includes a gate driving circuit for supplying a plurality of gate signals to the plurality of pixels. Each of the plurality of pixels operates with a non-light emitting period and a light emitting period during a frame interval, The gate driving circuit supplies a fourth gate signal of a gate-off voltage to the fourth gate line during the non-light-emitting period. In a first interval of the non-light emitting period, a second gate signal of a gate-on voltage is supplied to the second gate line, In a second interval after the first interval in the non-light emitting period, a third gate signal of a gate-on voltage is supplied to the third gate line.

9. The display device according to claim 8, wherein: The gate driving circuit supplies a first gate signal of a gate-on voltage to the first gate line in a writing interval after the second interval in the non-light emitting period.

10. The display device according to claim 9, wherein: The gate driving circuit supplies a fifth gate signal of a gate-on voltage to the fifth gate line in a third section between the writing section and the light-emitting section in the non-light-emitting section.

11. The display device according to claim 10, wherein: The gate driving circuit supplies a fourth gate signal of a gate-on voltage to the fourth gate line during the light emitting period.

12. The display device according to claim 10, wherein: A first on-time during which the gate driving circuit supplies the gate-on voltage in the first section and the second section is longer than a second on-time during which the gate driving circuit supplies the gate-on voltage in the writing section and the third section.

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