GOA device, gate drive circuit and display panel

Abstract

The GOA device comprises a plurality of cascaded GOA units, and the Nth GOA unit comprises a pull-up control unit, a pull-up unit, a pull-down unit and a pull-down control unit. The pull-up control unit is connected with a grid signal point; the pull-down control unit is connected with a grid signal point and the pull-down unit, and the pull-down unit is connected with the Nth-level horizontal scanning line; the pull-up unit is connected with the Nth level of horizontal scanning line; the Nth GOA unit comprises a first switch, the first switch is connected with the node voltage of the (N + m) th GOA unit and is connected with the pull-up unit, the working time of the first switch and the working time of the Nth GOA unit are not at the same moment, and m is a positive integer mgt; 0. According to the embodiment of the invention, the first switch controlled by the node voltage of the (N + m) th GOA unit is additionally arranged, so that the driving capability of the node voltage of the GOA unit on a thin film transistor controlled by a scanning line is enhanced, the rising time and the falling time of a scanning signal are reduced, and the display wrong charging condition can be prevented.

Description

Technical Field

[0001] The present invention relates to the technical field of liquid crystal display, and in particular to a GOA device, a gate drive circuit and a display panel. Background Art

[0002] With the development of liquid crystal display screens, more and more display panels use GOA (Gate Driver on Array, where the gate driving circuit is integrated on an array substrate) circuit to drive the horizontal scan lines, so as to reduce costs and obtain display panels with narrow borders.

[0003] However, as the variety of display screens on the market increases, consumers gradually begin to pay attention to the fineness of the picture, and high-resolution and high-refresh-rate display screens are gradually required by consumers. High-resolution and high-refresh-rate display screens will cause the capacitance and resistance loads of the circuit to increase accordingly, which may increase the fall time of each scan line, which may cause the next scan line to be charged incorrectly, resulting in display abnormalities. Summary of the invention

[0004] In view of at least some of the problems and shortcomings in the prior art, the embodiments of the present invention disclose a GOA device, a gate drive circuit and a display panel to solve the problem that the existing GOA circuit may cause incorrect charging to the next row of scan lines due to the increase in the fall time of the scan line.

[0005] On the one hand, the GOA device provided by an embodiment of the present invention includes a plurality of cascaded GOA units, and the Nth-level GOA unit is used to output a gate drive signal to the Nth-level horizontal scan line, characterized in that the Nth-level GOA unit includes: a pull-up control unit, a pull-up unit, a pull-down unit and a pull-down control unit; wherein the pull-up control unit is connected to a gate signal point; the pull-down control unit is connected to the gate signal point and the pull-down unit, and the pull-down unit is connected to the Nth-level horizontal scan line; the pull-up unit is connected to the Nth-level horizontal scan line; wherein the Nth-level GOA unit also includes a first switch, the first switch is connected to the node voltage of the N+mth-level GOA unit, and the first switch is connected to the pull-up unit, and the node voltage of the N+mth-level GOA unit is used to control the opening and closing of the first switch, wherein the working time of the first switch is not at the same time as the working time of the Nth-level GOA unit, wherein m is a positive integer, m>0.

[0006] The GOA device provided in the embodiment of the present invention enhances the driving capability of the thin film transistor controlled by the node voltage of the GOA unit for the scan line, reduces the rise time and fall time of the scan signal, and thus prevents the display from being mischarged, by adding a first switch controlled by the node voltage of the N+m-th level GOA unit, and the working time of the first switch is not at the same time as the working time of the N-th level GOA unit.

[0007] In one embodiment of the present invention, the pull-down control unit is connected to the N+nth level horizontal scan line, the pull-up control unit is connected to the start signal, the pull-up unit is connected to the clock signal, and the clock signal includes M lines, wherein n is a positive integer, n=M / 2, 0 <m<n。

[0008] In one embodiment of the present invention, the first end of the first switch is connected to the gate signal point of the N+mth level GOA unit, the second end of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third end of the first switch is connected to the Nth level horizontal scan line, and the pull-up unit is connected to the Nth level horizontal scan line.

[0009] In one embodiment of the present invention, the first end of the first switch is connected to the level transmission signal point of the N+m-th level GOA unit, the second end of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third end of the first switch is connected to the N-th level horizontal scan line, and the pull-up unit is connected to the N-th level horizontal scan line.

[0010] In one embodiment of the present invention, when the clock signal connected to the Nth level GOA unit changes from a low level H 0 Cut to high level H 1 When the voltage of the gate signal point in the Nth stage GOA unit is the second voltage H 3 The clock signal connected to the Nth GOA unit is high level H 1 , and the clock signal connected to the N+mth level GOA unit is at a low level H 0 During a time period of , the first switch is in an open state, and the voltage of the gate signal point in the N+mth level GOA unit connected to the first switch changes from a first voltage H to a first voltage H during the time period. 2 is coupled to the first intermediate voltage H 4 , where H 2 <H 4 <H 3 .

[0011] In one embodiment of the present invention, when the clock signal connected to the Nth level GOA unit changes from the high level H 1 Cut to the low level H0 When the voltage of the gate signal point in the Nth level GOA unit is switched to the low level H 0 The clock signal connected to the Nth level GOA unit is low level H 0 , and the clock signal connected to the N+mth level GOA unit is high level H 1 During the time period, the first switch is in the open state, and the voltage of the gate signal point of the N+mth level GOA unit connected to the first switch changes from the second voltage H 3 is coupled to the second intermediate voltage H 5 , where H 0 <H 4 <H 3 .

[0012] In one embodiment of the present invention, the clock signal connected to the Nth level GOA unit is a low level H 0 , and the clock signal connected to the N+mth level GOA unit is high level H 1 During a time period of , the first switch is in an open state, and the voltage of the intermediate signal transmission point of the Nth stage GOA unit changes from the third voltage H to 6 is coupled to the third intermediate voltage H 7 , where H 0 <H 7 <H 6 , H 6 ≤H 1 .

[0013] On the other hand, an embodiment of the present invention provides a gate driving circuit, for example, including the aforementioned GOA device.

[0014] In another aspect, an embodiment of the present invention provides a display panel, for example, including the aforementioned gate driving circuit.

[0015] It can be seen from the above that the above technical features of the present invention can have one or more of the following beneficial effects: the GOA device provided by the embodiment of the present invention, by adding a first switch controlled by the node voltage of the N+m-th level GOA unit, and the working time of the first switch is not at the same time as the working time of the N-th level GOA unit, enhances the driving ability of the thin film transistor controlled by the node voltage of the GOA unit for the scan line, reduces the rise time and fall time of the scan signal, thereby preventing the display from being mischarged. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0017] Figure 1 A circuit diagram of a conventional GOA unit in the related art

[0018] Figure 2 for Figure 1 Timing waveform of the traditional GOA unit.

[0019] Figure 3 An embodiment of the present invention provides an exemplary circuit module schematic diagram of an N-th level GOA device.

[0020] Figure 4 for Figure 3 Another exemplary circuit module schematic diagram of the Nth stage GOA device.

[0021] Figure 5 A schematic diagram of a timing waveform of a GOA unit provided in the first embodiment of the present invention.

[0022] Figure 6 This is a GN simulation comparison waveform diagram of the GOA unit provided in the first embodiment of the present invention.

[0023] Figure 7 This is a QN simulation comparison waveform diagram of the GOA unit provided in the first embodiment of the present invention.

[0024] Figure 8 This is a simulation comparison waveform diagram of the node voltage STN of the GOA unit provided in the second embodiment of the present invention.

[0025] Fig. 9 This is a GN simulation comparison waveform diagram of the GOA unit provided in the second embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the specific embodiments of the present invention and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0027] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0028] The directional terms mentioned in the embodiments of the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only references to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention. For the purpose of understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present invention is not limited to this. When a component such as a layer, film, region or substrate is referred to as "on" another component, the component may be directly on the other component, or there may be an intermediate component. In addition, in the specification, "on..." means above or below the target component, and does not mean that it must be on the top based on gravity.

[0029] In addition, the division of multiple embodiments in the present invention is only for the convenience of description and should not constitute a special limitation. The features in various embodiments can be combined and referenced to each other without contradiction.

[0030] first, Figure 1 This is a circuit diagram of a traditional GOA unit in the related art. Figure 2 for Figure 1 The timing waveform of the traditional GOA unit in FIG. In the related art, a 4K screen with 12 clock signals CK is used as an example. Among them, Figure 2 Q13 / Q14 / GOUT_13 / GOUT_14 correspond to Figure 1 The circuit node voltage QN and the scan voltage GN. Figure 1 and Figure 2 In the traditional GOA unit, when the start signal STV changes from low level H 0 Changes to high level H 1 When the thin film transistor T1 is turned on, the node voltage QN connected to the drain terminal of the thin film transistor T1 increases from the low level H 0 becomes the intermediate voltage H 1Based on the 12 clock signals CK, according to the level transmission relationship of the GOA unit, Q14 is at the first voltage H in the time period t2 to t5. 2 , Q14 is at the second voltage H during the time period t5 to t8 5 , the node voltage QN is connected to the gate terminal of the thin film transistor T2.

[0031] A GOA device provided by an embodiment of the present invention comprises a plurality of cascaded GOA units, wherein the Nth-stage GOA unit is used to output a gate drive signal to the Nth-stage horizontal scan line G(N). Figure 3 , Figure 3 For example, it is an exemplary circuit module schematic diagram of the Nth level GOA device. The Nth level GOA unit 10 includes: a pull-up control unit 100, a pull-up unit 200, a pull-down unit 300, a pull-down control unit 400 and a first switch T0. Among them, the pull-up control unit 100 is connected to the gate signal point Q(N); the pull-down control unit 400 is connected to the gate signal point Q(N) and the pull-down unit 300, and the pull-down unit 300 is also connected to the Nth level horizontal scan line G(N); the pull-up unit is connected to the Nth level horizontal scan line G(N). For example, the voltage at the gate signal point Q(N) is defined as the gate signal point voltage QN, and the voltage at the Nth level horizontal scan line G(N) is defined as the scan voltage GN.

[0032] Further, the first switch T0 is connected to the node voltage of the N+m-th level GOA unit, and the first switch T0 is also connected to the pull-up unit 200, and the node voltage of the N+m-th level GOA unit is used to control the opening and closing of the first switch T0, wherein the working time of the first switch T0 is not at the same time as the working time of the N-th level GOA unit, wherein m is a positive integer, and m>0. For example, the node voltage of the N+m-th level GOA unit is, for example, the gate signal point voltage QN+m of the N+m-th level GOA unit, or the node voltage of the N+m-th level GOA unit is, for example, the level transmission signal point voltage STN+m of the N+m-th level GOA unit. For example, the working time of the N-th level GOA unit is, for example, the time period in which the gate drive signal output to the N-th level horizontal scan line is a high level, and the working time of the first switch T0 can be understood, for example, that the first switch T0 is in an open state, and the first switch T0 has a positive effect on the N-th level GOA unit 10.

[0033] For example, see Figure 5 , the working time of the 13th level GOA unit is, for example, t4 to t7. Figure 5During the period when GOUT_13 is at a high level, the first switch T0 in the 13th-stage GOA unit is in an open state during the time period from t2 to t8, but is only in a working state during the time periods from t3 to t4 and from t7 to t8, which is different from the working time of the 13th-stage GOA unit.

[0034] By adding a first switch controlled by the node voltage of the (N + m)th-stage GOA unit, and the working time of the first switch is not at the same moment as the working time of the Nth-stage GOA unit, the driving ability of the thin-film transistor controlled by the node voltage of the GOA unit for the scanning line is enhanced, and the rise time and fall time of the scanning signal are reduced, thereby preventing the occurrence of display charging errors.

[0035] Specifically, referring to Figure 4 , the pull-up control unit 100 includes a second switch T1. The gate terminal and source terminal of the second switch T1 are connected to the start signal STV, and the drain terminal of the second switch T1 is connected to the gate signal point Q(N). The pull-up unit 200 includes a third switch T2 and a fourth switch T5. The gate terminal of the third switch T2 is connected to the gate signal point Q(N), the source terminal of the third switch T2 is connected to the clock signal CK, and the drain terminal of the third switch T2 is connected to the Nth-level horizontal scanning line G(N) to output a scanning voltage GN. The gate terminal of the fourth switch T5 is connected to the gate signal point Q(N), the source terminal of the fourth switch T5 is connected to the clock signal CK, and the drain terminal of the fourth switch T5 outputs a stage transmission signal voltage STN to provide a gate voltage for the pull-up control unit in the subsequent circuit. The pull-down control unit 400 includes a fifth switch T3, and the pull-down unit 300 includes a sixth switch T4. The gate terminals of the fifth switch T3 and the sixth switch T4 are both connected to the (N + n)th-level horizontal scanning line G(N + n), and the voltage at the (N + n)th-level horizontal scanning line G(N + n) is the scanning voltage GN + n, where n is a positive integer, n = M / 2, and 0 < m < n. The source terminal of the fifth switch T3 is connected to the gate signal point Q(N), the source terminal of the sixth switch T4 is connected to the Nth-level horizontal scanning line G(N), and the drain terminals of the fifth switch T3 and the sixth switch T4 are both connected to a negative voltage (VSS). The Nth-stage GOA unit 10 further includes a capacitor C1. One end of the capacitor C1 is connected to the gate signal point Q(N), and the other end is connected to the Nth-level horizontal scanning line G(N). Wherein, when the scanning voltage GN + n is at a high level H 2 the fifth switch T3 and the sixth switch T4 are turned on, thereby pulling down the scanning voltage GN and the gate signal point voltage QN at both ends of the capacitor C1 to the negative voltage VSS.

[0036] In addition, a reset signal is provided in the circuit, for example, to cooperate with the adjustment of the clock signal CK. If there is no reset signal in the circuit, the voltage of the clock signal CK is set to a negative voltage during the non-display period.

[0037] The present invention provides a first embodiment. In the first embodiment, the gate end of the first switch T0 is connected to the gate signal point of the N+m-th level GOA unit, that is, the first switch is connected to the voltage at the gate signal point in the N+m-th level GOA unit (gate signal point voltage QN+m), the source end of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, and the drain end of the first switch is connected to the N-th level horizontal scan line.

[0038] The following is an example of the specific implementation method in which the display panel includes 12 clock signals and m=1. Based on the fact that the display panel includes 12 clock signals, it can be understood that the first-level GOA unit is connected to the clock signal CK1, the second-level GOA unit is connected to the clock signal CK2... and so on, the 12th-level GOA unit is connected to the clock signal CK12, the 13th-level GOA unit is connected to the clock signal CK1, and the 14th-level GOA unit is connected to the clock signal CK2. When m=1, it can be understood that the first switch T0 in the 13th-level GOA unit is connected to the node voltage Q14 of the 14th-level GOA unit.

[0039] For details, see Figure 5 , Figure 5 Schematic diagram of the timing waveform of the GOA unit provided in the first embodiment of the present invention. The gate signal point voltage Q13 in the 13th stage GOA unit is the first voltage H in the time period t1 to t3. 2 The gate signal point voltage Q14 in the 14th stage GOA unit is the first voltage H in the time period t2 to t4. 2 The clock signal CK1 connected to the 13th level GOA unit is switched to high level H 1 Time (corresponding to Figure 5 At time t4 of the 13th level GOA unit, the gate signal point voltage Q13 in the 13th level GOA unit is the second voltage H 3 , the clock signal connected to the 13th level GOA unit is high level H 1 , and the clock signal connected to the 14th level GOA unit is low level H 0 During the time period (corresponding to Figure 5 In the time period t4 to t5, the first switch T0 in the 13th-stage GOA unit is in an open state, the parasitic capacitance between the gate and the source of the first switch T0 is increased, and the conduction capability of the circuit is enhanced. At this time, the voltage Q14 of the gate signal point in the 14th-stage GOA unit connected to the first switch T0 in the 13th-stage GOA unit changes from the first voltage H to the gate signal point Q2 in the time period t4 to t5. 2 is coupled to the first intermediate voltage H 4 , where H 2 <H 4 <H3 .

[0040] During the time period from t5 to t7, the clock signal CK connected to the 14th level GOA unit maintains a high level, and Q14 maintains the second voltage H 3 The clock signal connected to the 13th level GOA unit is low level H 0 , and the clock signal connected to the 14th level GOA unit is high level H 1 within a certain period of time (e.g. Figure 5 In the time period t7 to t8, the first switch T0 in the 13th-stage GOA unit is in an open state, and the voltage Q14 of the gate signal point of the 14th-stage GOA unit connected to the first switch T0 in the 13th-stage GOA unit changes from the second voltage H 3 is coupled to the second intermediate voltage H 5 , where H 0 <H 5 <H 3 In addition, when the clock signal CK connected to the 14th level GOA unit changes from high level H 2 Cut to low level H 0 When , the high potential in the subsequent GOA unit cascaded with the 14th-stage GOA unit is input to the 14th-stage GOA unit as a pull-down potential, that is, Figure 4 The scanning voltage GN+n at the gate end of the fifth switch T3 and the sixth switch T4 is high (i.e., the voltage at the N+nth level horizontal scanning line G(N+n)), the fifth switch T3 and the sixth switch T4 are turned on, the two ends of the capacitor C1 are connected to the negative voltage VSS, Q14 and Gout14 are discharged, and the voltage is cut to a low level H. 0 .

[0041] For details, see Figure 5 , the gate signal point voltage Q14 in the 14th level GOA unit is at a low level H during the period t1 to t2. 0 Since the number of timing signals CK is 12, it can be seen from the level transmission relationship that the signal provided by the 8th level GOA unit is used as the starting voltage STV of the 14th level GOA unit. Figure 5 It can be seen that the CK signal CK8 connected to the 8th level GOA unit is at a high level H from t2 to t5. 1 , based on the signal provided by the 8th level GOA unit, the gate signal point voltage Q14 in the 14th level GOA unit is pulled up to the first voltage H 2， At this time, since the gate signal point voltage Q14 in the 14th level GOA unit is non-H 0Voltage, the first switch T0 of the 13th level GOA unit is in the open state. Further, in the time period t4 to t5, the first switch T0 of the 13th level GOA unit is in the open state, and the CK1 connected to the 13th level GOA unit is switched to a high level H at this time. 1 , based on the action of the first switch T0 in the 13th stage GOA unit, the gate signal point voltage Q14 in the 14th stage GOA unit connected thereto is increased from the first voltage H 2 is pulled up to the first intermediate voltage H 4 , that is, the conduction capacity of the circuit is improved. As mentioned above, in the time period of t5 to t7, since the timing signal CK2 connected to the 14th level GOA unit is switched to a high level H 1 Therefore, the gate signal point voltage Q14 in the 14th-stage GOA unit is pulled up to the second voltage H3. Further, in the time period t7 to t8, since the timing signal CK2 connected to the 14th-stage GOA unit is still at a high level H 1 Therefore, the gate signal point voltage Q14 in the 14th stage GOA unit should still be the second voltage H 3 However, since the first switch T0 of the 13th stage GOA unit is in the open state, and the CK1 connected to the 13th stage GOA unit is switched to a low level H at this time, 0 , based on the action of the first switch T0 in the 13th stage GOA unit, the gate signal point voltage Q14 in the 14th stage GOA unit connected thereto is increased from the second voltage H 3 is pulled down to the second intermediate voltage H 5 .

[0042] For example, see Figure 6 The GN simulation comparison waveform in FIG. 1 shows that the GOA device provided by the first embodiment of the present invention has a shorter fall time than the traditional GOA device. Furthermore, due to the addition of the first switch T0, during the time period t7 to t8 corresponding to Q14, the CK corresponding to the 13th-level GOA unit changes from a high level H to a low level H at time t7. 2 Cut to low level H 0 , and due to the parasitic capacitance of the gate and source ends of the first switch T0, during this period of time, the waveform of Q14 in the present patent solution will be higher than the second voltage H 3 The voltage is low, which reduces the discharge time of capacitor C1 and also reduces the GN fall time. Figure 7 QN simulation comparison waveform diagram in .

[0043] In summary, the embodiment of the present invention enhances the driving capability of the thin film transistor controlled by the node voltage of the GOA unit for the scan line, reduces the rise time and fall time of the scan signal, and prevents the display from being mischarged by adding a first switch controlled by the node voltage of the N+m-th level GOA unit, and the working time of the first switch is not at the same time as the working time of the N-th level GOA unit.

[0044] In addition, the present invention also provides a second embodiment. In the second embodiment, the gate end of the first switch T0 is connected to the level signal point of the N+m-th level GOA unit, the source end of the first switch T0 is connected to the clock signal or a signal with the same frequency as the clock signal, and the drain end of the first switch is connected to the N-th level horizontal scan line. That is, the difference in connection between the N-th level GOA unit provided in the second embodiment and the N-th level GOA unit provided in the first embodiment is that the gate end of the first switch T0 in the second embodiment is connected to the level signal point of the N+m-th level GOA unit, while the gate end of the first switch T0 in the first embodiment is connected to the gate signal point of the N+m-th level GOA unit, and the rest of the connections and structures are the same.

[0045] Furthermore, the specific implementation manner is described below by taking the display panel including 12 clock signals and m=1 as an example. Figure 8 The node voltage STN waveform of the GOA unit provided in the second embodiment of the present invention. The clock signal connected to the 13th level GOA unit is a low level H 0 , and the clock signal connected to the 14th level GOA unit is high level H 1 During the time period ( Figure 8 During the time period (t1-t2), the first switch is in the open state, and the voltage of the intermediate signal transmission point of the 13th level GOA unit is within the time period ( Figure 8 (t1-t2) from the third voltage H 6 is coupled to the third intermediate voltage H 7 , where H 0 <H 7 <H 6 , H 6 ≤H 1 .

[0046] Specifically, based on the addition of the first switch T0, since the gate terminal of the first switch T0 is connected to the voltage of the subsequent stage STN, the node voltage STN will be coupled due to the sudden change of the voltage at both ends of T0, and the waveform of the node voltage STN is as follows: Figure 8 The principle is the same as the above embodiment 1, and no further details will be given here; for example, see Fig. 9According to the GN simulation comparison waveform diagram in , the GOA device provided by the second embodiment of the present invention has a shorter fall time than the traditional GOA device.

[0047] In summary, the embodiment of the present invention enhances the driving capability of the thin film transistor controlled by the node voltage of the GOA unit for the scan line, reduces the rise time and fall time of the scan signal, and prevents the display from being mischarged by adding a first switch controlled by the node voltage of the N+m-th level GOA unit, and the working time of the first switch is not at the same time as the working time of the N-th level GOA unit.

[0048] In addition, the present invention also provides a gate driving circuit, comprising the aforementioned GOA device.

[0049] Furthermore, the present invention also provides a display panel, comprising the aforementioned GOA device.

[0050] It can be understood that the aforementioned embodiments are merely exemplary descriptions of the present invention. The technical solutions of the various embodiments can be arbitrarily combined and used in combination, provided that the technical features do not conflict, the structures do not contradict, and the purpose of the present invention is not violated.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GOA device, comprising a plurality of cascaded GOA units, wherein the Nth-stage GOA unit is used to output a gate drive signal to the Nth-stage horizontal scan line, characterized in that: The Nth level GOA unit comprises: a pull-up control unit, a pull-up unit, a pull-down unit and a pull-down control unit; Wherein, the pull-up control unit is connected to the gate signal point; the pull-down control unit is connected to the gate signal point and the pull-down unit, the pull-down unit is connected to the Nth level horizontal scan line; the pull-up unit is connected to the Nth level horizontal scan line; The Nth-level GOA unit also includes a first switch, which is connected to the node voltage of the N+mth-level GOA unit and is connected to the pull-up unit. The node voltage of the N+mth-level GOA unit is used to control the opening and closing of the first switch, wherein the working time of the first switch is not at the same time as the working time of the Nth-level GOA unit, wherein m is a positive integer, and m>0.

2. The GOA device according to claim 1, characterized in that The pull-down control unit is connected to the N+nth level horizontal scan line, the pull-up control unit is connected to the start signal, the pull-up unit is connected to the clock signal, and the clock signal includes M lines, wherein n is a positive integer, n=M / 2, 0 <m<n。 3. The GOA device according to claim 2, characterized in that The first end of the first switch is connected to the gate signal point of the N+mth level GOA unit, the second end of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third end of the first switch is connected to the Nth level horizontal scan line, and the pull-up unit is connected to the Nth level horizontal scan line.

4. The GOA device according to claim 2, characterized in that The first end of the first switch is connected to the level transmission signal point of the N+m-th level GOA unit, the second end of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third end of the first switch is connected to the N-th level horizontal scan line, and the pull-up unit is connected to the N-th level horizontal scan line.

5. The GOA device according to claim 3, characterized in that When the clock signal connected to the Nth GOA unit is switched from a low level H0 to a high level H1, the voltage of the gate signal point in the Nth GOA unit is a second voltage H3; During a time period when the clock signal connected to the Nth GOA unit is at a high level H1 and the clock signal connected to the N+mth GOA unit is at a low level H0, the first switch is in an open state, and the voltage of the gate signal point in the N+mth GOA unit connected to the first switch is coupled from the first voltage H2 to the first intermediate voltage H4 during the time period, wherein H2 <H4<H3。 6. The GOA device according to claim 5, characterized in that When the clock signal connected to the Nth GOA unit is switched from the high level H1 to the low level H0, the voltage of the gate signal point in the Nth GOA unit is switched to the low level H0; In the time period when the clock signal connected to the Nth GOA unit is at a low level H0 and the clock signal connected to the N+mth GOA unit is at a high level H1, the first switch is in the open state, and the voltage of the gate signal point of the N+mth GOA unit connected to the first switch is coupled from the second voltage H3 to the second intermediate voltage H5, wherein H0 <H5<H3。 7. The GOA device according to claim 4, characterized in that: In a time period when the clock signal connected to the Nth GOA unit is at a low level H0 and the clock signal connected to the N+mth GOA unit is at a high level H1, the first switch is in an open state, and the voltage of the intermediate signal transmission point of the Nth GOA unit is coupled from the third voltage H6 to the third intermediate voltage H7 in the time period, wherein H0 <H7<H6,H6≤H1。 8. A gate drive circuit, characterized in that: Comprising a GOA device as described in any one of claims 1-7.

9. A display panel, characterized in that: Comprising a GOA device as described in any one of claims 1-7.

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