A dual-path cache half-speed parallel processing very low frequency demodulation method and system

Abstract

The application relates to a very low frequency demodulation method and system of a two-way cache half-speed parallel processing, and relates to the field of signal processing.The method comprises the following steps: converting a very low frequency minimum shift keying signal into a first-way signal and a second-way signal according to the high and low levels of a local baud rate signal; writing the first-way signal into a first memory under the synchronization control of the local baud rate signal; writing the second-way signal into a second memory under the synchronization control of the local baud rate signal; reading the first-way signal from the first memory under the synchronization control of the local baud rate signal and performing first frequency domain conversion processing to obtain a first frequency component; reading the second-way signal from the second memory under the synchronization control of the local baud rate signal and performing second frequency domain conversion processing to obtain a second frequency component; and performing parallel-serial conversion on the first frequency component and the second frequency component under the synchronization control of the local baud rate signal to obtain a serial demodulation output signal. The method can improve the timeliness of demodulation signals in a very low frequency communication system.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of signal processing, in particular to a very low frequency demodulation method and system with double-path cache half-speed parallel processing. BACKGROUND

[0002] The very low frequency communication system works in the 3-30 kHz frequency band, has strong penetration ability, small attenuation, long transmission distance and other characteristics, and plays an important role in communication applications in special environments such as underwater and underground. Due to the limited bandwidth resources of the very low frequency band, frequency shift keying modulation technology is widely used.

[0003] In related technologies, the receiving end of the very low frequency communication system uses frequency domain transformation technology to demodulate the frequency shift keying signal. This technology completes demodulation by analyzing the frequency components of the signal through frequency domain transformation operation on the received signal.

[0004] However, as the baud rate of the communication system increases, the operation speed of the frequency domain transformation is difficult to keep up with the signal input rate, resulting in untimely processing of the received signal, which affects the real-time performance of the system. SUMMARY

[0005] The present application provides a very low frequency demodulation method and system with double-path cache half-speed parallel processing, which is used to improve the timeliness of demodulating signals in a very low frequency communication system.

[0006] In a first aspect, the present application provides a very low frequency demodulation method with double-path cache half-speed parallel processing, applied to a very low frequency demodulation system, which comprises: converting a very low frequency minimum frequency shift keying signal into a first path signal and a second path signal according to the high and low levels of a local baud rate signal, wherein the very low frequency minimum frequency shift keying signal is converted into the first path signal when the local baud rate signal is high, and the very low frequency minimum frequency shift keying signal is converted into the second path signal when the local baud rate signal is low; writing the first path signal into a first memory under the synchronization control of the local baud rate signal, and writing the second path signal into a second memory under the synchronization control of the local baud rate signal; reading out the first path signal from the first memory and performing first frequency domain transformation processing under the synchronization control of the local baud rate signal to obtain a first frequency component, and reading out the second path signal from the second memory and performing second frequency domain transformation processing under the synchronization control of the local baud rate signal to obtain a second frequency component; performing parallel-serial conversion on the first frequency component and the second frequency component under the synchronization control of the local baud rate signal to obtain a serial demodulation output signal.

[0007] By adopting the technical scheme, the very low frequency minimum shift keying signal is converted into the first signal and the second signal according to the high and low levels of the local baud rate signal, serial-parallel conversion shunt processing of the signal is realized, the serial signal is converted into two parallel data streams that can be processed at half speed, the two signals are written into different memories under the synchronous control of the local baud rate signal, frequency domain transformation processing is performed again, the frequency components after processing can be serial-parallel converted to obtain a serial demodulation output signal under the synchronous control of the local baud rate signal, the timing and timeliness and data integrity of the entire demodulation process are ensured, the demodulation efficiency and accuracy are effectively improved, and stable demodulation of the very low frequency minimum shift keying signal is realized.

[0008] With reference to some embodiments of the first aspect, in some embodiments, before the step of converting the very low frequency minimum shift keying signal into the first signal and the second signal according to the high and low levels of the local baud rate signal, the method further comprises: performing synchronization processing on the received very low frequency minimum shift keying signal to obtain a synchronization processing result; generating a local baud rate signal according to the synchronization processing result, and calculating frequency domain transformation parameters including a sampling rate and a transformation length according to the local baud rate signal.

[0009] By adopting the technical scheme, the very low frequency minimum shift keying signal is converted into the first signal and the second signal according to the high and low levels of the local baud rate signal, serial-parallel conversion shunt processing of the signal is realized, the serial signal is converted into two parallel data streams that can be processed at half speed, the two signals are written into different memories under the synchronous control of the local baud rate signal, frequency domain transformation processing is performed again, the frequency components after processing can be serial-parallel converted to obtain a serial demodulation output signal under the synchronous control of the local baud rate signal, the timing and timeliness and data integrity of the entire demodulation process are ensured, the demodulation efficiency and accuracy are effectively improved, and stable demodulation of the very low frequency minimum shift keying signal is realized.

[0010] With reference to some embodiments of the first aspect, in some embodiments, the steps of reading out the first signal from the first memory and performing first frequency domain transformation processing to obtain a first frequency component under the synchronous control of the local baud rate signal, and reading out the second signal from the second memory and performing second frequency domain transformation processing to obtain a second frequency component under the synchronous control of the local baud rate signal, specifically comprise: reading out the first signal from the first memory and performing first frequency domain transformation processing on the first signal to obtain the first frequency component under the synchronous control of the local baud rate signal after frequency division; reading out the second signal from the second memory and performing second frequency domain transformation processing on the second signal to obtain the second frequency component under the synchronous control of the local baud rate signal after frequency division; determining that a frequency corresponding to a maximum amplitude value in the first frequency component is f0, and determining that a frequency corresponding to a maximum amplitude value in the second frequency component is f1.

[0011] By adopting the technical scheme, the signal is read out from the memory and frequency domain conversion processing is performed under the synchronization control of the local baud rate signal after frequency division by two, the clock control after frequency division by two enables the two signals to be processed alternately, forming a pipeline structure, effectively solving the problem of insufficient frequency domain conversion time, determining the frequency corresponding to the maximum amplitude in the frequency component as f0 and f1, and accurately obtaining the key frequency information, which is helpful for accurately judging the bit value of the original data and improving the accuracy of demodulation, so that the demodulation result is more consistent with the actual signal condition, thereby better restoring the information carried by the original signal.

[0012] In combination with some embodiments of the first aspect, in some embodiments, the step of parallel-serial conversion of the first frequency component and the second frequency component under the synchronization control of the local baud rate signal to obtain a serial demodulation output signal specifically includes: generating a demodulation decision result according to f0 in the first frequency component and f1 in the second frequency component under the synchronization control of the local baud rate signal, wherein f0 corresponds to a demodulation value of 0 and f1 corresponds to a demodulation value of 1; and merging the demodulation decision result in a time sequence order to obtain the serial demodulation output signal.

[0013] By adopting the technical scheme, the demodulation decision result is generated according to f0 in the first frequency component and f1 in the second frequency component under the synchronization control of the local baud rate signal, and the corresponding relationship between f0, f1 and the demodulation value ensures the accuracy of the decision. The decision result is merged in a time sequence to obtain a serial demodulation output signal, the time sequence of the original data is restored, and the quality of the demodulation output signal is improved.

[0014] In combination with some embodiments of the first aspect, in some embodiments, the first memory and the second memory write signals at the frequency of the local baud rate signal and read out signals at one-half of the frequency of the local baud rate signal.

[0015] By adopting the technical scheme, the first memory and the second memory write signals at the frequency of the local baud rate signal and read out signals at one-half of the frequency of the local baud rate signal, the writing frequency ensures timely storage of the signals and avoids loss, and the reading frequency realizes buffering and solves the problem of rate mismatch.

[0016] In some embodiments of the first aspect, in the step of reading out the first signal from the first memory and performing first frequency domain transform processing to obtain a first frequency component under the synchronization control of the local baud rate signal, and reading out the second signal from the second memory and performing second frequency domain transform processing to obtain a second frequency component under the synchronization control of the local baud rate signal, the parameter determination method of the frequency domain transform processing comprises: determining the transform time of each frequency domain as one half of the period of the local baud rate signal according to the local baud rate signal; determining a sampling rate and a transform length that satisfy the ratio of the sampling rate to the transform length equaling one half of the frequency of the local baud rate signal according to the transform time; and performing frequency domain transform processing on the first signal and the second signal respectively by using the sampling rate and the transform length.

[0017] By adopting the above technical solution, the frequency domain transform time is determined as one half of the period according to the local baud rate signal, time resources are reasonably allocated, processing is ensured to be timely, the adaptive sampling rate and transform length are determined accordingly, frequency domain transform is ensured to be effective and accurate, the two signals are processed by using these parameters, frequency components are accurately obtained, the accuracy of frequency analysis is improved, adaptability to different signal characteristics is enhanced, and the demodulation result is more consistent with the actual signal.

[0018] In some embodiments of the first aspect, the depths of the first memory and the second memory are both the transform length.

[0019] By adopting the above technical solution, the depths of the first memory and the second memory are the transform length, the amount of data read from the memory is accurately matched with the requirement of transform, and processing inaccuracy caused by data problems is avoided.

[0020] In the second aspect, the embodiments of the present application provide a very low frequency demodulation system, which comprises one or more processors and a memory. The memory is coupled to the one or more processors, and is used to store computer program codes. The computer program codes comprise computer instructions. The one or more processors invoke the computer instructions to enable the very low frequency demodulation system to perform the method described in the first aspect and any possible implementation manner of the first aspect.

[0021] In the third aspect, the embodiments of the present application provide a computer program product comprising instructions. When the computer program product is run on a very low frequency demodulation system, the very low frequency demodulation system is enabled to perform the method described in the first aspect and any possible implementation manner of the first aspect.

[0022] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, including instructions, when the instructions are executed on the very low frequency demodulation system, causing the very low frequency demodulation system to perform the method described in the first aspect and any possible implementation manner of the first aspect.

[0023] It can be understood that the very low frequency demodulation system provided in the second aspect, the computer program product provided in the third aspect and the computer storage medium provided in the fourth aspect are all used to execute the method provided in the embodiments of the present application. Therefore, the beneficial effects that can be achieved are referred to the beneficial effects in the corresponding method, which will not be repeated here.

[0024] The one or more technical solutions provided in the embodiments of the present application have at least the following technical effects or advantages:

[0025] 1. In the present application, the very low frequency minimum shift keying signal is converted into a first signal and a second signal according to the high and low levels of the local baud rate signal, realizing the series-parallel conversion and shunt processing of the signal, converting the serial signal into two parallel data streams that can be processed at half speed, writing the two signals into different memories under the synchronous control of the local baud rate signal, and then performing frequency domain transformation processing. The processed frequency components can be converted into a serial demodulation output signal under the synchronous control of the local baud rate signal, ensuring the timing and timeliness and data integrity of the entire demodulation process, effectively improving the demodulation efficiency and accuracy, and realizing stable demodulation of the very low frequency minimum shift keying signal.

[0026] 2. In the present application, the received very low frequency minimum shift keying signal is processed synchronously to obtain a synchronous processing result. The local baud rate signal generated according to the synchronous processing result can control the subsequent data processing rhythm, and the calculated frequency domain transformation parameter can provide a suitable sampling rate and transformation length for the frequency domain transformation processing, improving the adaptability of the signal processing, ensuring accurate demodulation under different signal conditions, further improving the reliability and stability of the demodulation method, and enabling the entire demodulation system to better cope with various situations, effectively reducing the probability of demodulation errors caused by inappropriate parameters.

[0027] 3. In the present application, the signal is read out from the memory and subjected to frequency domain transformation processing under the synchronous control of the divided-by-two local baud rate signal. The clock control after the division by two enables the two signals to be processed alternately, forming a pipeline structure, effectively solving the problem of insufficient frequency domain transformation time, determining the frequencies f0 and f1 corresponding to the maximum amplitude in the frequency components, accurately obtaining the key frequency information, helping to accurately determine the original data bit value, improving the accuracy of demodulation, making the demodulation result more consistent with the actual signal condition, and thus better restoring the information carried by the original signal. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1is a flowchart of a very low frequency demodulation method with double-path cache half-speed parallel processing in an embodiment of the present application.

[0029] Figure 2 is another flowchart of a very low frequency demodulation method with double-path cache half-speed parallel processing in an embodiment of the present application.

[0030] Figure 3 is an entity device structure diagram of a very low frequency demodulation system in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The terminology used in the following embodiments of the present application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in the description of the application, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0032] Hereinafter, the terms "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second", "third", "fourth", "fifth", "sixth", "seventh" and "eighth" can explicitly or implicitly include one or more of the features, and in the description of the embodiments of the present application, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0033] For ease of understanding, the method provided by the present embodiment is described in the flow. Please refer to Figure 1 is a flowchart of a very low frequency demodulation method with double-path cache half-speed parallel processing in an embodiment of the present application.

[0034] S101, converting the very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of the local baud rate signal, wherein the very low frequency minimum shift keying signal is converted into the first signal when the local baud rate signal is high, and the very low frequency minimum shift keying signal is converted into the second signal when the local baud rate signal is low.

[0035] The Very Low Frequency (VLF) Minimum Shift Keying (MSPSK) signal refers to a digital modulation signal operating in the 3-30kHz frequency band, using two specific frequencies to represent the digits "0" and "1". The local baud rate signal fb is a reference clock obtained after frame header synchronization, with the same rate as the transmitting end, used to control the data processing rhythm. The first signal represents the data stream sampled during the fb high level. The second signal represents the data stream sampled during the fb low level. Serial-to-parallel conversion refers to the process of distributing continuous modulation signals to two parallel channels according to the high and low level timing of fb.

[0036] This step is executed after frame header synchronization and is used to perform serial-to-parallel conversion and signal splitting. Specifically, the system splits the input VLF minimum frequency shift keying signal according to the high or low level state of the local baud rate signal fb. When fb is high, the input signal is directed to the first channel; when fb is low, the input signal is directed to the second channel. This splitting mechanism converts the serial signal that originally needed to be processed at fb rate into two parallel data streams that can be processed at fb / 2 rate, creating conditions for subsequent half-speed processing.

[0037] In some embodiments, serial-to-parallel conversion can be implemented in several ways: Optionally, it can be implemented using a circuit based on D flip-flops, including: configuring two D flip-flops to sample data during high and low levels respectively; using the rising edge of the fb signal to trigger the first D flip-flop and the falling edge to trigger the second D flip-flop; obtaining the two data streams through an output buffer. Optionally, it can be implemented using a multiplexer, including: configuring a 1:2 multiplexer circuit; connecting the fb signal to the gating control terminal; conducting the first output when fb is high and the second output when fb is low; and buffering and shaping the output signal. It is understood that other circuit structures can also be used to implement the serial-to-parallel conversion function, which is not limited here.

[0038] S102. Write the first signal into the first memory under the synchronous control of the local baud rate signal, and write the second signal into the second memory under the synchronous control of the local baud rate signal.

[0039] In this context, the first memory (FIFO1) and the second memory (FIFO2) are first-in, first-out (FIFO) memory cells used for buffering data, and their depth is equal to the frequency domain transformation length (n). A write operation refers to storing the split signal into the corresponding memory under the control of the fb. Synchronization control means using the clock edge of the fb to trigger data writing, ensuring the accuracy of the write timing. The memory depth being equal to the transformation length ensures the complete data sample required for one frequency domain transformation.

[0040] This step is executed after the serial-parallel conversion is completed, and realizes the cache storage of the two-way signals. Specifically, when the fb is high, the system writes the first-way signal into the fifo1; when the fb is low, the second-way signal is written into the fifo2. The writing process adopts the fb rate, and the subsequent reading adopts the fb / 2 rate, and the difference between the writing and reading rates realizes the data caching function. The writing operation of each memory is strictly performed according to the timing of the fb, and the continuity and integrity of the data are ensured.

[0041] In some embodiments, the data caching can be realized in various ways: optionally, an asynchronous FIFO structure is adopted to realize the data caching, including: configuring two FIFO memories with independent read and write clocks; connecting the fb to the write clock end; setting a write address counter; monitoring the FIFO state flag to control the data writing. Optionally, a dual-port RAM structure is adopted to realize the data caching, including: configuring two dual-port RAM units; using the fb to drive the write address counter; resetting when the count value reaches n; and controlling the data writing timing through the write enable. It can be understood that other storage structures can also be used to realize the data caching function, which is not limited here.

[0042] S103, reading out the first-way signal from the first memory and performing first frequency domain transformation processing under the synchronization control of the local baud rate signal to obtain a first frequency component, and reading out the second-way signal from the second memory and performing second frequency domain transformation processing under the synchronization control of the local baud rate signal to obtain a second frequency component.

[0043] The frequency domain transformation processing refers to a mathematical operation process of converting a time domain signal into a frequency domain representation, and is realized by using a fast Fourier transform. The frequency component refers to n frequency components with different amplitudes after transformation, wherein the amplitude corresponding to the fi-th frequency component is ai. The synchronization control indicates that the data reading and processing timing is controlled using a clock obtained by dividing the local baud rate signal fb by two. The first and second frequency domain transformation processing respectively correspond to independent processing processes of the two-way signals, and the processing parameters include a sampling rate fc and a transformation length n, and satisfy the relationship fc / n=fb / 2. The reading operation refers to a process of taking data from the memory at a rate of fb / 2.

[0044] This step is executed after the cache storage of the two-way signals is completed, and realizes the half-speed parallel frequency domain processing. Specifically, the system divides the local baud rate signal fb by two to obtain a processing clock with a frequency of fb / 2, which controls the reading out and transformation processing of the two-way signals. When one-way signal is performing frequency domain transformation, the other-way signal is performing data acquisition, forming a pipeline structure of alternating processing. Each time, n data points are taken for FFT operation to obtain n frequency components. This half-speed processing mechanism decomposes the original operation at the fb rate into two parallel operations at the fb / 2 rate, solving the problem of insufficient frequency domain transformation time.

[0045] In some embodiments, the half-rate frequency domain processing can be implemented in various ways: alternatively, using a hardware FFT processor, including: configuring a dedicated FFT processor chip; setting the processing parameters fc and n; sending the memory output data into the FFT processor; reading the spectrum results after the processing is completed; performing amplitude calculation on the spectrum data. Alternatively, using a software FFT algorithm, including: configuring a DSP processor; loading a base-2 FFT program; reading an n-point data sequence from the memory; performing FFT operation to obtain complex spectrum; calculating the amplitude of each frequency component. It can be understood that other algorithms or processors can also be used to implement the frequency domain transformation function, which is not limited here.

[0046] S104, parallel-serial conversion of the first frequency component and the second frequency component under the synchronization control of the local baud rate signal to obtain a serial demodulation output signal.

[0047] Wherein, the parallel-serial conversion refers to the process of recombining two parallel frequency components into a single data stream. The serial demodulation output signal refers to a bit stream recombined according to the original data timing, wherein the frequency f0 corresponds to the demodulation value 0, and the frequency f1 corresponds to the demodulation value 1. The local baud rate signal synchronization control indicates that the clock edge of fb is used to trigger data conversion and output. The frequency component refers to the characteristic frequency obtained after frequency domain transformation, which is used to determine the bit value of the original data.

[0048] This step is executed after the completion of the two-way frequency domain transformation processing, and realizes the recombination and output of the demodulation result. Specifically, the system processes the two-way frequency components alternately according to the rhythm of the local baud rate signal fb. In each cycle of fb, the corresponding frequency component is converted into a digital bit value, and is output in time sequence. This process recombines the two-way fb / 2 rate parallel data into a fb rate serial data stream, and restores the timing relationship of the original data.

[0049] In some embodiments, the parallel-serial conversion can be implemented in various ways: alternatively, using a multiplexer, including: configuring a 2:1 digital multiplexer; connecting the two-way frequency components to the data input end; using fb to control the channel selection; configuring a latch at the output end; outputting the serial data in time sequence. Alternatively, using a shift register, including: configuring a dual-port shift register; loading the first-way data at the high level of fb; loading the second-way data at the low level of fb; using fb to drive the shift operation; obtaining the data stream from the serial output end. It can be understood that other circuit structures can also be used to implement the parallel-serial conversion function, which is not limited here.

[0050] The method provided by the embodiment is further described in more detail below. Please refer to Figure 2This is another flowchart illustrating the very low frequency demodulation method for dual-path buffer half-speed parallel processing in this application embodiment.

[0051] S201. Perform synchronization processing on the received very low frequency minimum frequency shift keying signal to obtain the synchronization processing result.

[0052] Very Low Frequency (VLF) Minimum Shift Keying (MSPSK) is a digital modulation signal operating in the 3-30kHz frequency band, using two frequencies, f0 and f1, to represent digits 0 and 1, respectively. Synchronization processing is a signal processing technique used to extract timing information from the received signal, ensuring that the data transmission rhythm at the receiving and transmitting ends is consistent. The synchronization processing result includes bit synchronization and frame synchronization information. Bit synchronization is used to determine the sampling time of each bit, and frame synchronization is used to determine the start position of the data frame.

[0053] In this step, the system first digitally samples the received Very Low Frequency Minimum Shift Keying (VLFK) signal, and then extracts the signal's timing features using methods such as correlation calculations or envelope detection. Specifically, zero-crossing detection can be used to detect signal transition points, and the time intervals between adjacent transition points can be statistically analyzed to establish a time histogram. By analyzing the peak positions of the time histogram, the bit period information of the signal can be obtained. Simultaneously, the boundaries of the data frame are determined by detecting a specific synchronization header sequence. The final output synchronization processing result includes bit clock recovery information and frame synchronization marker information.

[0054] S202. Generate a local baud rate signal based on the synchronization processing result, and calculate the frequency domain transformation parameters based on the local baud rate signal. The frequency domain transformation parameters include the sampling rate and the transformation length.

[0055] The local baud rate signal is a clock signal related to the data transmission rate, used to control data sampling and processing. Frequency domain transform parameters are key parameters required for frequency domain analysis, including the sampling rate (i.e., the number of sampling points per unit time) and the transform length (i.e., the number of data points processed in one transform).

[0056] In this step, the system generates a square wave clock signal with the same frequency as the received signal baud rate, based on the synchronization processing result obtained in step S201, as the local baud rate signal. Then, based on the period of this local baud rate signal, a suitable sampling rate and transform length are calculated. The sampling rate must satisfy the Nyquist sampling theorem, i.e., it must be at least twice the highest signal frequency. The transform length needs to be balanced between time resolution and frequency resolution, and is generally chosen as an integer multiple of the ratio of the sampling rate to the local baud rate signal frequency.

[0057] S203, converting the very low frequency minimum shift keying signal into a first signal and a second signal according to the high and low levels of the local baud rate signal, wherein the very low frequency minimum shift keying signal is converted into the first signal when the local baud rate signal is at a high level, and the very low frequency minimum shift keying signal is converted into the second signal when the local baud rate signal is at a low level.

[0058] The first signal and the second signal are the very low frequency minimum shift keying signals processed by splitting, and correspond to signal segments during the high and low levels of the local baud rate signal respectively. The high and low levels refer to two logic states of the digital signal, and the high level is usually represented as "1" and the low level is represented as "0".

[0059] In this step, the system realizes the splitting of the signal by judging the level state of the local baud rate signal. When the local baud rate signal is at a high level, the sampling value of the very low frequency minimum shift keying signal during this period is output to the first path; when the local baud rate signal is at a low level, the sampling value of the very low frequency minimum shift keying signal during this period is output to the second path. This splitting method can be realized by a digital switch or a multiplexer, and the control signal is the local baud rate signal.

[0060] S204, writing the first signal into a first memory under the synchronization control of the local baud rate signal, and writing the second signal into a second memory under the synchronization control of the local baud rate signal.

[0061] The first memory and the second memory (fifo1 and fifo2) are two independent first-in-first-out buffer units, and their depths are equal to the transform length n. The writing operation refers to storing data into the memory unit in sequence under the synchronization control of the local baud rate signal fb. The synchronization control is specifically manifested as triggering the data writing action using the rising edge or the falling edge of the local baud rate signal fb. The first signal and the second signal are two digital signal streams obtained by splitting according to the high and low levels of fb in the previous step.

[0062] In the specific implementation process, the first signal is written into fifo1 during the high level of fb, and the second signal is written into fifo2 during the low level of fb. The writing clock of the two memories uses fb, and the writing address is generated by a modulo n counter. The writing enable signal of each memory is controlled by the level state of fb: the fifo1 writing enable is valid when fb is at a high level, and the fifo2 writing enable is valid when fb is at a low level. When the writing address count reaches n-1, it is automatically reset to zero, forming a cyclic writing process. The data bit width of the memory needs to meet the signal quantization accuracy requirement, and a 12-bit or 16-bit structure is usually used. This double fifo structure realizes the signal buffering and splitting functions, and provides data support for subsequent parallel processing.

[0063] S205, reading the first signal from the first memory under the synchronization control of the halved local baud rate signal, and performing first frequency domain transform processing on the first signal to obtain the first frequency component.

[0064] Halving refers to reducing the signal frequency to half of the original, and the implementation method is to halve the local baud rate signal fb to obtain a new clock signal with a frequency of fb / 2. Frequency domain transform processing is a mathematical operation process of converting time domain sampling data into frequency domain representation, which is realized by using fast Fourier transform (FFT). The first frequency component refers to n frequency components obtained after FFT operation, each component containing amplitude and phase information.

[0065] In this step, first, a D flip-flop is used to halve fb to obtain a readout clock with a frequency of fb / 2. Under the control of the readout clock, n data points are read out from fifo1 to perform a complete FFT operation. The FFT parameters are set as: sampling rate fc, transform length n. The FFT calculation obtains n frequency components, ranging from 0 to fc / 2, with a frequency resolution of fc / n. Each frequency component fi corresponds to an amplitude value ai, and i takes a value in the range of 1 to n. These frequency components constitute the spectral characteristics of the first signal, which are used for subsequent frequency identification. The entire processing process is carried out at the pace of fb / 2, ensuring sufficient time to complete the FFT operation.

[0066] S206, reading the second signal from the second memory under the synchronization control of the halved local baud rate signal, and performing second frequency domain transform processing on the second signal to obtain the second frequency component, the first memory and the second memory writing signals at the frequency of the local baud rate signal, reading signals at half the frequency of the local baud rate signal, the depth of the first memory and the second memory is equal to the transform length.

[0067] This step involves frequency domain transform processing of the second signal and timing control of the read and write of the memory. The memory depth refers to the data storage capacity of fifo1 and fifo2, which is equal to the FFT transform length n. The writing and reading operations are performed at the frequencies of fb and fb / 2, respectively, forming a rate ratio of 2:1, realizing the half-speed processing mechanism. The second frequency component has the same data structure as the first frequency component, also containing n frequency component information.

[0068] In the implementation process, the data reading and FFT processing of fifo2 adopt the same control logic as fifo1, but are staggered by half a cycle in timing. When one signal is performing FFT operation, the other signal is performing data collection, and the two processes are alternately performed to form a pipeline structure. The read address of each memory is generated by an fb / 2 clock driven modulo-n counter, and when the read address reaches n-1, it is reset to 0. The result of the FFT operation is n complex frequency components, where the ith frequency component corresponds to a frequency of i×fc / n Hz and an amplitude of ai. This double-buffering half-speed parallel processing mechanism effectively solves the problem of insufficient FFT operation time at high baud rates and improves the real-time processing capability of the system.

[0069] S207, determine that the frequency corresponding to the maximum amplitude value in the first frequency component is f0, and determine that the frequency corresponding to the maximum amplitude value in the second frequency component is f1.

[0070] The frequency component is the frequency spectrum information obtained after FFT transformation, and each component contains a frequency value and a corresponding amplitude value. The maximum amplitude value refers to the component with the highest amplitude among the n frequency components, and the corresponding frequency is the characteristic frequency to be detected. f0 and f1 represent the characteristic frequencies detected in the first and second signals, respectively, which are used for subsequent demodulation decision. For example, in an n=2048-point FFT result, if the amplitude of a certain frequency component is significantly higher than that of other components, then the frequency is the characteristic frequency to be detected.

[0071] In the specific implementation process, the amplitude values of the n frequency components of the first FFT result are compared one by one. An initial maximum amplitude value amax=0 is set, and the amplitude value of each component is compared with amax in turn. If the amplitude of the current component is greater than amax, the amax value is updated, and the corresponding frequency value is recorded. After the comparison is completed, the recorded frequency is f0. The same method is used to process the second FFT result to obtain f1. To improve detection reliability, an amplitude threshold value also needs to be set, and only amplitudes exceeding the threshold value are involved in the maximum value comparison. The resolution of frequency detection is determined by the FFT parameters, and the interval between adjacent frequency components is fc / n Hz.

[0072] S208, under the synchronization control of the local baud rate signal, generating a demodulation decision result according to f0 in the first frequency component and f1 in the second frequency component, wherein f0 corresponds to a demodulation value of 0 and f1 corresponds to a demodulation value of 1.

[0073] The demodulation decision is the process of converting the detected characteristic frequency into digital bits. The synchronization control of the local baud rate signal ensures that the decision is made at the correct time. The demodulation values 0 and 1 are the two basic states in digital communication, corresponding to the detected f0 and f1 frequencies, respectively. The decision result is the binary decision output in each symbol period, which needs to be generated in time sequence under the control of the baud rate signal.

[0074] The specific implementation process of this step is as follows: first, establish a frequency decision threshold, and denote the two frequencies used by the FSK modulation as F0 and F1. When the detected f0 is close to F0 (the frequency deviation is within the preset range), output the demodulation value 0; when f0 is close to F1, output the demodulation value 1. Similarly, when f1 is close to F0, output 0, and when f1 is close to F1, output 1. The decision process is triggered at the rising edge of the local baud rate signal fb to ensure that the decision result is synchronized with the data clock. The decision result is latched by a D flip-flop to avoid glitch interference. The decision circuit can be implemented using combinational logic, including a frequency comparator and decision logic.

[0075] S209, merge the demodulation decision results in time sequence to obtain the serial demodulation output signal.

[0076] The serial demodulation output signal refers to the process of recombining the decision results of two parallel processes into a single serial data stream. The time sequence refers to rearranging the data bits according to the time sequence of the original data. The merging operation needs to accurately control the alternating output timing of the two data streams to ensure that the data bits are not lost or repeated.

[0077] In the implementation process, a 2:1 digital multiplexer is used to complete the parallel-to-serial conversion. The two data inputs of the multiplexer are connected to the two decision results, and the selection signal uses the local baud rate signal fb. When fb is high, the first decision result is selected, and when fb is low, the second decision result is selected. The output end obtains the complete serial data stream, and the data rate is fb. To ensure that the output data is synchronized with the original data, a D flip-flop can be added at the output end to latch the output data using the rising edge of fb. In addition, a buffer circuit needs to be designed to smooth the glitches that may occur during data switching and improve the quality of the output signal. The entire parallel-to-serial conversion process is strictly controlled in time sequence to ensure the integrity and accuracy of the demodulation output signal.

[0078] The parameter determination method of the frequency domain transformation process includes: determining the transformation time of each frequency domain as half of the period of the local baud rate signal according to the local baud rate signal;

[0079] According to the transformation time, determine a sampling rate and a transformation length that satisfy the ratio of the sampling rate to the transformation length equaling half of the frequency of the local baud rate signal;

[0080] The first signal and the second signal are respectively processed by frequency domain transformation with the sampling rate and the transformation length.

[0081] The local baud rate signal is the reference clock of the system, and its period T=1 / fb determines the basic timing of data processing. The transformation time is the time window required for completing one frequency domain transformation, which is T / 2 in the present design. The sampling rate fc is the number of sampling points per unit time, and the transformation length n is the number of data points for one FFT processing. The ratio fc / n represents the time resolution of FFT operation. The frequency domain transformation processing is a mathematical operation process for converting time domain signals to frequency domain, and is realized by using FFT algorithm. For example, when fb=100Hz, the transformation time is 5ms, and if fc=1024Hz, n=2048 points satisfy the relationship fc / n=fb / 2.

[0082] The first step is to determine the transformation time based on the local baud rate signal fb. Since the double-channel alternate processing mechanism is adopted, the processing time of each channel is half of the baud rate period, i.e. T / 2. This time window should meet the requirement of frequency resolution and ensure that the processing is completed before the next data arrives. In the specific implementation, the processing clock is obtained by dividing fb by two, and the start and end of FFT operation are controlled.

[0083] The second step is to determine the sampling rate fc and the transformation length n. These two parameters must satisfy the relationship fc / n=fb / 2. In the parameter selection, first, the minimum value of the sampling rate fc is determined according to the signal bandwidth, which satisfies the Nyquist sampling theorem. Then the transformation length n=2fc / fb is calculated to satisfy the relationship. In order to facilitate the implementation of FFT, n is taken as an integer power of 2. For example, if the highest signal frequency is 400Hz, fc is at least 800Hz, and actually 1024Hz can be taken. When fb=100Hz, n=2048 points can be obtained.

[0084] The third step is to perform frequency domain transformation processing using the determined parameters. For the first channel signal, n data points are collected during the high level period of fb, and the FFT operation is completed during the low level period of the next cycle; for the second channel signal, data is collected during the low level period of fb, and the FFT operation is completed during the high level period of the next cycle. The two-channel processing is alternately performed without interference. The FFT operation adopts the radix-2 fast algorithm, and the data storage adopts the in-place operation mode to save storage space. The operation result contains n complex frequency components, and the frequency resolution is fc / n Hz.

[0085] The very low frequency demodulation system in the embodiment of the present application will be described from the perspective of hardware processing. Please refer to Figure 3 , which is a schematic diagram of an entity device structure of the very low frequency demodulation system in the embodiment of the present application.

[0086] It should be noted that,Figure 3 The structure of the very low frequency demodulation system shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of the present invention.

[0087] like Figure 3 As shown, the very low frequency demodulation system includes a central processing unit (CPU) 301, which can perform various appropriate actions and processes based on a program stored in read-only memory (ROM) 302 or a program loaded from storage portion 308 into random access memory (RAM) 303, such as performing the methods described in the above embodiments. The RAM 303 also stores various programs and data required for system operation. The CPU 301, ROM 302, and RAM 303 are interconnected via a bus 304. An input / output (I / O) interface 305 is also connected to the bus 304.

[0088] The following components are connected to I / O interface 305: input section 306 including audio input devices, push-button switches, etc.; output section 307 including a liquid crystal display (LCD) and audio output devices, indicator lights, etc.; storage section 308 including a hard disk, etc.; and communication section 309 including a network interface card such as a LAN (Local Area Network) card, modem, etc. Communication section 309 performs communication processing via a network such as the Internet. Drive 310 is also connected to I / O interface 305 as needed. Removable media 311, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 310 as needed so that computer programs read from them can be installed into storage section 308 as needed.

[0089] In particular, according to embodiments of the present invention, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of the present invention include a computer program product comprising a computer program carried on a computer-readable medium, the computer program containing computer programs for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 309, and / or installed from removable medium 311. When the computer program is executed by central processing unit (CPU) 301, it performs the various functions defined in the present invention.

[0090] Note that specific examples of computer-readable storage media can include but are not limited to an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the present disclosure, computer-readable storage media can be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

[0091] The flow charts and block diagrams in the attached drawings are used to illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each block in the flow charts or block diagrams can represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.

[0092] Specifically, the very low frequency demodulation system of the embodiment includes a processor and a memory, and the memory stores a computer program, and the computer program is executed by the processor to implement the very low frequency demodulation method with double-way cache half-speed parallel processing provided in the above embodiment.

[0093] As another aspect, the present application further provides a computer-readable storage medium, which can be included in the very low frequency demodulation system described in the above embodiments, or can exist separately and not be assembled into the very low frequency demodulation system. The storage medium carries one or more computer programs, and when the one or more computer programs are executed by a processor of the very low frequency demodulation system, the very low frequency demodulation system implements the very low frequency demodulation method with double-way cache half-speed parallel processing provided in the above embodiments.

[0094] The above embodiments are only used to illustrate the technical solutions of the present application, but not limit the present application; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

[0095] In the above embodiments, the term "when" can be interpreted to mean "if" or "after" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrase "on determining" or "if detecting (a stated condition or event)" can be interpreted to mean "if determining" or "in response to determining" or "on detecting (a stated condition or event)" or "in response to detecting (a stated condition or event)" depending on the context.

[0096] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by a computer program instructing the relevant hardware to complete, and the program can be stored in a computer readable storage medium. When the program is executed, it can include the processes of the above-mentioned embodiments. The aforementioned storage medium includes ROM or random storage memory RAM, magnetic disk or optical disk and various storage program codes.

Claims

1. A method for demodulating very low frequency signals in a dual-path cache half-rate parallel processing, characterized in that, The method is applied to a very low frequency demodulation system, and comprises the following steps: Converting a very low frequency minimum shift keying signal into a first signal and a second signal according to high and low levels of a local baud rate signal, wherein the very low frequency minimum shift keying signal is converted into the first signal when the local baud rate signal is at a high level, and the very low frequency minimum shift keying signal is converted into the second signal when the local baud rate signal is at a low level; Writing the first signal into a first memory under synchronization control of the local baud rate signal and writing the second signal into a second memory under synchronization control of the local baud rate signal; Reading out the first signal from the first memory under synchronization control of the local baud rate signal and performing first frequency domain transform processing to obtain a first frequency component, and reading out the second signal from the second memory under synchronization control of the local baud rate signal and performing second frequency domain transform processing to obtain a second frequency component; Parallel-serial converting the first frequency component and the second frequency component under synchronization control of the local baud rate signal to obtain a serial demodulation output signal.

2. The method of claim 1, wherein, Before the step of converting the very low frequency minimum shift keying signal into the first signal and the second signal according to the high and low levels of the local baud rate signal, the method further comprises the following steps: Performing synchronization processing on a received very low frequency minimum shift keying signal to obtain a synchronization processing result; Generating a local baud rate signal according to the synchronization processing result, and calculating frequency domain transform parameters including a sampling rate and a transform length according to the local baud rate signal.

3. The method of claim 1, wherein, The steps of reading out the first signal from the first memory under synchronization control of the local baud rate signal and performing first frequency domain transform processing to obtain a first frequency component, and reading out the second signal from the second memory under synchronization control of the local baud rate signal and performing second frequency domain transform processing to obtain a second frequency component, specifically comprise the following steps: Reading out the first signal from the first memory under synchronization control of a divided-by-two local baud rate signal, and performing first frequency domain transform processing on the first signal to obtain the first frequency component; Reading out the second signal from the second memory under synchronization control of the divided-by-two local baud rate signal, and performing second frequency domain transform processing on the second signal to obtain the second frequency component; Determining that a frequency corresponding to a maximum amplitude value in the first frequency component is f0, and determining that a frequency corresponding to a maximum amplitude value in the second frequency component is f1.

4. The method of claim 1, wherein, The step of parallel-serial converting the first frequency component and the second frequency component under synchronization control of the local baud rate signal to obtain a serial demodulation output signal, specifically comprises the following steps: Generating a demodulation decision result according to f0 in the first frequency component and f1 in the second frequency component under synchronization control of the local baud rate signal, wherein f0 corresponds to a demodulation value of 0, and f1 corresponds to a demodulation value of 1; Merging the demodulation decision result in a time sequence to obtain the serial demodulation output signal.

5. The method of claim 1, wherein, The first memory and the second memory write signals at the local baud signal frequency, and read out signals at half of the local baud signal frequency.

6. The method of claim 2, wherein, In the step of reading out a first path signal from the first memory and performing a first frequency domain transform process under the synchronization control of the local baud signal to obtain a first frequency component, and reading out the second path signal from the second memory and performing a second frequency domain transform process under the synchronization control of the local baud signal to obtain a second frequency component, a parameter determination method of the frequency domain transform process comprises: According to the local baud signal, determining that a transform time of each path frequency domain is half of a period of the local baud signal; According to the transform time, determining a sampling rate and a transform length that satisfy a ratio of the sampling rate to the transform length equaling half of the local baud signal frequency; Performing frequency domain transform processes on the first path signal and the second path signal respectively through the sampling rate and the transform length.

7. The method of claim 2, wherein, The depths of the first memory and the second memory are the transform length.

8. A very low frequency demodulation system, characterized by The very low frequency demodulation system comprises one or more processors and a memory; the memory is coupled with the one or more processors, the memory is used to store computer program code, the computer program code comprises computer instructions, and the one or more processors invoke the computer instructions to enable the very low frequency demodulation system to perform the method in any one of claims 1-7.

9. A computer-readable storage medium comprising instructions, characterized in that, When the instructions run on the very low frequency demodulation system, the very low frequency demodulation system is enabled to perform the method in any one of claims 1-7.

10. A computer program product, characterised in that, When the computer program product runs on the very low frequency demodulation system, the very low frequency demodulation system is enabled to perform the method in any one of claims 1-7.

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