Static Flow Control Method, Electronic Device and Medium Based on Vertically Expanded Networking

Abstract

The present invention relates to the field of computer technologies, and particularly to a static flow control method, an electronic device, and a medium based on vertically extended networking. The method includes: S1. Setting a corresponding set of static register groups for the m-th chip Am in the vertically extended networking; S2. Setting the initial value corresponding to each Uim, where Uim satisfies; S3. Chip Am obtaining the data packet Bmi to be sent to Ai, and determining whether the current Uim is greater than or equal to the flow control credit value required by Bmi. If so, execute S4; otherwise, wait until Uim satisfies being greater than or equal to the flow control credit value required by Bmi and then execute S4; S4. Sending Bmi to Ai, and updating Uim = Uim - 1. When chip Am receives the reply information from Ai for Bmi, update Uim = Uim + 1. The present invention reduces the demand for physical memory when the networking scale of the vertically extended networking increases.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a static flow control method, an electronic device, and a medium based on scale-up networking. Background Art

[0002] In traditional scale-up network communication, the flow control mechanism corresponds to the physical cache space. When the number of scale-up network nodes increases, linearly increasing the physical cache will introduce a significant amount of physical cache. For example, 100 cards correspond to several hundred KB to several megabytes, 1000 cards correspond to several megabytes to dozens of megabytes. If the network has tens of thousands of nodes, for the current international state-of-the-art networking scale of 200,000 cards, the required physical cache is greater than several hundred megabytes. The existing flow control mechanisms based on scale-up networking have at least the following disadvantages: 1. Difficult physical implementation: The excessive physical cache of the chip brings too much difficulty to physical implementation. The difficulty of front-end design and DFT design increases exponentially. There are great challenges in layout wiring and production testing. 2. Difficult to ensure chip yield: Excessive physical memory involves a series of engineering problems such as yield and cache repair, which will reduce the chip yield. Therefore, how to reduce the demand for physical memory when the scale of scale-up networking increases, reduce the difficulty of physical implementation, and improve the chip yield has become an urgent technical problem to be solved. Summary of the Invention

[0003] The purpose of the present invention is to provide a static flow control method, an electronic device, and a medium based on scale-up networking, which reduce the demand for physical memory when the scale of scale-up networking increases.

[0004] According to the first aspect of the present invention, there is provided a static flow control method based on scale-up networking, including:

[0005] Step S1: Set a corresponding set of static register groups {G1 m , G2 m ,..., G m ,..., G i m ,..., G M m} for the m-th chip A in the scale-up networking. G i m is the i-th static register corresponding to A m , where the value range of i is from 1 to M, the value range of m is from 1 to M, M is the total number of chips in the scale-up networking, and G i m is used to configure the flow control credit value U of the data packets that A m can send to the i-th chip A i . im ;

[0006] Step S2, set the initial value for each U i m The corresponding initial value, U i m The corresponding initial value is G i m The corresponding maximum flow control credit value, U i m Satisfy , H m is A m The corresponding control granularity, Q i is A i The corresponding physical cache;

[0007] Step S3, A m Obtain the data packet B to be sent to A i , and determine whether the current U mi is greater than or equal to the flow control credit value required by B i m , if so, execute Step S4, otherwise, wait until U mi i m satisfies being greater than or equal to the flow control credit value required by B mi and then execute Step S4;

[0008] Step S4, send B mi to A i , update U i m = U i m - C mi , when A m receives the reply message for B i from A mi , update U i m = U i m + C mi .

[0009] According to the second aspect of the present invention, there is provided an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method according to the first aspect of the present invention.

[0010] <000L0245>According to the third aspect of the present invention, there is provided a computer-readable storage medium storing computer-executable instructions, and the computer instructions are used to execute the method according to the first aspect of the present invention.

[0011] Compared with the prior art, the present invention has obvious advantages and beneficial effects. By means of the above technical solution, a static flow control method, an electronic device and a medium based on vertical expansion networking provided by the present invention can achieve quite remarkable technological progressiveness and practicality, and have wide utilization value in the industry, and it has at least the following beneficial effects:

[0012] The present invention sets a corresponding set of static register groups for each chip in the vertical expansion networking, configures a flow control credit value capable of sending data packets to the target chip in each register, and controls the sending of data packets based on the flow control credit value in the register. Based on the method of the present invention, when the networking scale of the vertical expansion networking increases, it is only necessary to reconfigure a corresponding set of static register groups for each chip, without linearly increasing the physical cache, reducing the demand for physical memory when the networking scale of the vertical expansion networking increases, reducing the physical implementation difficulty, and improving the chip yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0014] Figure 1 It is a flowchart of the static flow control method based on vertical expansion networking provided by the embodiments of the present invention. DETAILED DESCRIPTION

[0015] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0016] The embodiments of the present invention provide a static flow control method based on vertical expansion networking, as Figure 1 shown, including:

[0017] Step S1: Set a corresponding set of static register groups {G1 m , G2 m ,..., G m ,..., G i m ,..., G M m} for the mth chip A in the vertical expansion networking, where G i m is for Am The corresponding i-th static register, where the value range of i is from 1 to M, the value range of m is from 1 to M, M is the total number of chips in the vertical expansion network, G i m For configuring A m Capable of sending to the i-th chip A i The flow control credit value U of the sent data packet i m .

[0018] Among them, all chips in the vertical expansion network are connected to the same switch, and the chips communicate with each other through the switch. A static register bank with the same structure is set for all chips in the vertical expansion network to facilitate the configuration of the flow control credit value of the data packet. The static register bank can be specifically set in the adaptation layer. Each chip is set with a corresponding MAC (Media Access Control Address). The flow control credit value specifically refers to the number of data packets. In the system startup phase or the quasi-static phase, the system completes the configuration of the static register bank. By setting a corresponding set of static register banks {G1 m , G2 m ,..., G m ,..., G i m ,..., G M m} for each A, point-to-point flow control is achieved.

[0019] Step S2, set the initial value corresponding to each U i m The initial value corresponding to U i m The initial value is the maximum flow control credit value corresponding to G i m , U i m Satisfies , H m Is the control granularity corresponding to A m , Q i Is the physical cache corresponding to A i .

[0020] Among them, the value of U i m Changes dynamically according to the sending situation of the data packet, and is used to identify the maximum value of the data packet that the current A m Can send to the i-th chip A i . The value of U i m Satisfies It is indicated that the total physical cache space corresponding to the control credit values in the static register bank for a chip is less than or equal to the physical cache space. Additionally, according to the flexibility of physical implementation, the physical cache space can be enlarged, such as 1.2 times or multiple times, and then the values corresponding to the static register bank can be increased synchronously. The implementation method is flexible, facilitating iterative adjustment in the front-end design and back-end implementation of the chip. Since the static register bank can be statically modified, when the scenario on the system side changes, only the values of the static registers need to be changed to complete the scenario switch. No other hardware needs to be changed. In addition, all H m values can be set to be equal, or can be set separately according to specific application requirements.

[0021] Step S3, A m Obtain the data packet B i to be sent to A mi , and judge whether the current U i m is greater than or equal to the flow control credit value C mi required by B mi . If so, execute step S4; otherwise, wait until U i m satisfies being greater than or equal to the flow control credit value required by B mi and then execute step S4.

[0022] Step S4: Send B mi to A i , update U i m = U i m - C mi . When A m receives the reply information for B i , update U mi i m i = U m mi + C mi .

[0023] The present invention makes full use of the mapping between static flow control and physical cache. When the networking scale reaches hundreds, thousands, or even tens of thousands of cards, the corresponding physical cache only increases several times. For example, in the above example, for a 128-card network, the physical cache does not increase linearly, that is, it does not increase by 128 times, but within several times. Compared with the linear growth of the physical cache, it has better feasibility and rationality. The present invention uses static registers. Compared with the traditional scheme of increasing physical memory, there is no need to implement complex protocols and other processes. The required flow control mechanism is simple, and other access processes are similar to traditional accesses, significantly improving the utilization rate of system resources and communication efficiency.

[0024] As an embodiment, step S1 includes:

[0025] Step S11: Obtain A i The corresponding physical cache Q i For each A m The target physical cache ratio P corresponding to the data packet that can be sent to A i mi For each A m The corresponding control granularity H m .

[0026] It should be noted that both Q i and P mi are known quantities, determined according to the specific application scenario, and thus can be directly obtained. The control granularity m is set according to the specific application scenario.

[0027] Step S12: If i = m, set the initial value of U i m to 0. If i ≠ m, set the initial value of U i m to (P mi ×Q i ) / H m .

[0028] It should be noted that if i = m, it means that U i m represents the flow control credit value of the data packet that A i can send to the i-th chip A i , and it can be directly set to 0.

[0029] As an embodiment, the method further includes: Step S10: When the M value increases, re - execute Steps S1 - S4 based on the updated M value and the control granularity and physical cache corresponding to the newly added chips.

[0030] It should be noted that when the M value increases, it means that the networking scale of the vertical expansion networking increases. In the embodiments of the present invention, there is no need to linearly increase the physical cache, and it is only necessary to re - execute Steps S1 - S4 based on the updated M value and the control granularity and physical cache corresponding to the newly added chips.

[0031] ​In some application scenarios, when the networking scale of vertical expansion networking increases, it is necessary to increase the physical cache corresponding to some chips, but it does not increase linearly. Usually, increasing several times is sufficient to meet the requirements. As an embodiment, the method further includes: Step C10: When the value of M increases, based on the control granularity and physical cache corresponding to the newly added chips, adjust the physical cache of other chips, and re-execute Step S1-Step S4 based on the updated value of M, the control granularity and physical cache corresponding to the newly added chips, and the adjusted physical cache of other chips.

[0032] It should be noted that in actual situations, there is an error between the actual physical cache ratio and the target physical cache ratio. When the error is within a certain range, it can be tolerated, but when the error exceeds the preset error threshold, adjustment is required to meet the error requirements. This will be illustrated by several embodiments below.

[0033] Embodiment 1

[0034] After Step S3, it further includes:

[0035] Step B4: Obtain the actual physical cache ratio R corresponding to each data packet that can be sent to A m that can send to A i . If the difference between R mi and P mi is greater than the preset error threshold, then execute Step B5. mi

[0036] It should be noted that a specific time interval can be set. Every time the corresponding time interval passes, obtain the actual physical cache ratio R corresponding to each data packet that can be sent to A m that can send to A i . mi .

[0037] Step B5: Adjust the control granularity H corresponding to A mi according to the difference between R mi and P m , and return to execute Step S2. m

[0038] It should be noted that specifically, the adjustment step size and other parameters of the control granularity corresponding to A mi can be determined according to the difference between R mi and P m to adjust the control granularity H corresponding to A m . If different A m have different H m , the differences between the corresponding R m and P m of multiple A mi can be combined to adjust different A mi ​m The corresponding control granularity H m . If all H m values are the same, then combine multiple A m corresponding R mi and P mi differences to adjust H m . Existing strategies for adjusting parameters according to differences are all within the protection scope of the present invention and will not be elaborated here.

[0039] Example Two

[0040] After the step S3, it further includes:

[0041] Step B4, obtain the actual physical cache occupancy ratio R m corresponding to the data packet that each A i can send to A mi . If the difference between R mi and P mi is greater than the preset error threshold, then execute step B5.

[0042] It should be noted that a time interval can be specifically set. Every time the corresponding time interval passes, obtain the actual physical cache occupancy ratio R m corresponding to the data packet that each A i can send to A mi .

[0043] Step B5, adjust the control granularity H mi corresponding to A mi according to the difference between R m and P m , and return to execute step S2.

[0044] It should be noted that specifically, parameters such as the adjustment step size of the control granularity corresponding to A mi can be determined according to the difference between R mi and P m to adjust the control granularity H m corresponding to A m . If different A m have different H m , the differences between the R m and P mi corresponding to multiple A mi can be combined to adjust the control granularity H m corresponding to different A m . If all H m values are the same, then combine the differences between the R m and P mi corresponding to multiple A mi to adjust H m. All existing strategies for adjusting parameters according to the difference fall within the protection scope of the present invention and will not be elaborated herein.

[0045] Step B6: If the number of times of returning to execute Step S2 is greater than the preset number threshold, then execute Step B7.

[0046] Step B7: Adjust the size of the physical cache Q corresponding to A according to the difference between R mi and P mi , and return to execute Step S2. i corresponding to the physical cache Q i of

[0047] For the method described in Embodiment 2, first adjust the control granularity. If the requirement cannot be met after the number of times of adjusting the granularity is greater than the preset number threshold, then it is achieved by adjusting the size of the physical cache Q corresponding to A i corresponding to the physical cache Q i of mi and P mi , specifically adjust the size of the physical cache Q corresponding to A according to the difference between R i corresponding to the physical cache Q i of

[0048] Embodiment 3

[0049] After the said Step S3, it further includes:

[0050] Step C4: Obtain the actual physical cache occupancy ratio R corresponding to each data packet that A m can send to A i . If the difference between R mi and P mi is greater than the preset error threshold, then execute Step C5. mi of

[0051] Step C5: Adjust the size of the physical cache Q corresponding to A according to the difference between R mi and P mi , and return to execute Step S2. i corresponding to the physical cache Q i of

[0052] For the method described in Embodiment 2, it is directly achieved by adjusting the size of the physical cache Q corresponding to A according to the difference between R mi and P mi . All existing strategies for adjusting parameters according to the difference fall within the protection scope of the present invention and will not be elaborated herein. i corresponding to the physical cache Q i of

[0053] Specifically, different methods can be selected according to application requirements for adjustment. Through multiple iterations, the error between the actual physical cache ratio and the target physical cache ratio meets the requirements.

[0054] It should be noted that some exemplary embodiments are described as processes or methods depicted as flowcharts. Although the flowcharts depict the steps as sequential processes, many of the steps can be implemented in parallel, concurrently, or simultaneously. In addition, the order of the steps can be rearranged. The process can be terminated when its operations are completed, but there can also be additional steps not included in the drawings. The process can correspond to a method, function, procedure, subroutine, subprogram, and so on.

[0055] An embodiment of the present invention also provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method described in the embodiment of the present invention.

[0056] An embodiment of the present invention also provides a computer-readable storage medium storing computer-executable instructions, and the computer instructions are used to execute the method described in the embodiment of the present invention.

[0057] In the embodiment of the present invention, a corresponding set of static register groups is set for each chip in the vertical expansion network. A flow control credit value capable of sending data packets to the target chip is configured in each register, and the sending of data packets is controlled based on the flow control credit value in the register. Based on the method of the present invention, when the network scale of the vertical expansion network increases, it is only necessary to reconfigure a corresponding set of static register groups for each chip, without linearly increasing the physical cache, reducing the demand for physical memory when the network scale of the vertical expansion network increases, reducing the physical implementation difficulty, and improving the chip yield.

[0058] The above are only preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to the above-disclosed technical content to obtain equivalent embodiments with equivalent changes within the scope of the technical solution of the present invention. However, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A static flow control method based on vertically extended networking, characterized in that Comprising: Step S1: For the m-th chip A in the vertical expansion network m Set a corresponding set of static register groups {G1 m , G2 m ,..., G i m ,..., G M m}, where G i m is the i-th static register corresponding to A m . The value range of i is from 1 to M, and the value range of m is from 1 to M. M is the total number of chips in the vertical expansion network. G i m is used to configure the flow control credit value U m that A i can send to the i-th chip A i m . Step S2, set the initial value for each U i m The corresponding initial value, U i m The corresponding initial value is G i m The corresponding maximum flow control credit value, U i m Satisfy , H m is A m The control granularity corresponding to, Q i is A i The corresponding physical cache; Step S3, A m Obtain the data packet B to be sent to A i mi , determine whether the current U i m is greater than or equal to the flow control credit value C required by B mi mi , if so, execute step S4, otherwise, wait until U i m satisfies being greater than or equal to the flow control credit value required by B mi and then execute step S4;​​ Step S4, send B mi to A i , and update U i m = U i m - C mi , when A m receives the reply message for B i mi , update U i m i = U m mi + C mi .

2. The method according to claim 1, wherein: The step S1 comprises: Step S11, obtain A i corresponding physical cache Q i For each A m able to send to A i target physical cache ratio P corresponding to the data packet mi For each A m corresponding control granularity H m ; Step S12: If i = m, set the initial value of U i m to 0; if i ≠ m, set the initial value of U i m to (P mi × Q i ) / H m .

3. The method according to claim 1, wherein: All H m values are equal.

4. The method according to claim 1, wherein: The method further comprises: step S10, when the value of M increases, re - execute steps S1 - S4 based on the updated value of M, the control granularity corresponding to the newly added chip, and the physical cache.

5. The method according to claim 1, wherein: The method further comprises: step C10, when the value of M increases, adjust the physical caches of other chips based on the control granularity and physical cache corresponding to the newly added chip, and re - execute steps S1 - S4 based on the updated value of M, the control granularity and physical cache corresponding to the newly added chip, and the adjusted physical caches of other chips.

6. The method according to claim 1, wherein: After the step S3, it further comprises: Step B4. Obtain each A m Capable of sending to A i The actual physical cache occupancy ratio R corresponding to the data packet that can be sent mi If the difference between R mi and P mi is greater than the preset error threshold, then execute Step B5. P mi Is the target physical cache occupancy ratio corresponding to the data packet that each A m Can send to A i ; Step B5. Adjust A mi according to the difference between R mi and P m for the corresponding control granularity H m , and return to execute Step S2.

7. The method according to claim 6, wherein: After the step B5, it further comprises: Step B6, if the number of times of returning to execute step S2 is greater than a preset number threshold, then execute step B7; Step B7. Adjust the size of the physical cache Q corresponding to A according to the difference between R mi and P mi , and return to execute Step S2. i i ​​ 8. The method according to claim 1, wherein: After the step S3, it further comprises: Step C4. Obtain each A m Capable of sending to A i The actual physical cache occupancy ratio R corresponding to the data packet mi If the difference between R mi and P mi is greater than the preset error threshold, then execute Step C5, where P mi is the target physical cache occupancy ratio corresponding to the data packet that each A m is capable of sending to A i ; Step C5. Adjust the size of the physical cache Q mi corresponding to A according to the difference between R mi and P i , and return to execute step S2. i ​ 9. An electronic device, characterized in that, Comprising: At least one processor; And a memory communicatively connected to the at least one processor; Wherein, the memory stores instructions executed by the at least one processor, and the instructions are configured to execute the method according to any one of the foregoing claims 1 - 8.

10. A computer-readable storage medium, characterized in that, Stores computer - executable instructions for executing the method according to any one of the foregoing claims 1 - 8.

Images