Display screen overdrive controller

Abstract

The invention discloses a display screen overdrive controller which can improve the compression ratio, reduce image distortion and improve the compression performance, and comprises an image compression and decompression processing unit which is used for carrying out compression and decompression processing on video data. The input data of the input end of the image compression and decompression processing unit is video data, the image compression and decompression processing unit is a compression / decompression data processor based on three values, and the three values comprise a maximum reference value, a minimum reference value and an average reference value.

Description

[0001] This application is a divisional application. The application number of the original application is 202111208741.5, the application date is October 18, 2021, and the name of the invention is “A display overdrive controller”. Technical Field

[0002] The present invention relates to the technical field of display screens, and in particular to a display screen overdrive controller. Background Art

[0003] Liquid crystal display (LCD) technology has been the most mature and widely used display technology in the past two decades. The brightness of different colors in liquid crystal display is mainly achieved by applying different drive control voltages. By applying different voltages to change the rotation angle of liquid crystal molecules, the amount of backlight transmittance is controlled to form the brightness of different colors. However, existing liquid crystal displays have problems such as poor display effect and motion blur. The reason is that if the applied drive control voltage changes, the reaction of the liquid crystal molecules will lag behind the voltage change for a period of time and then slow down, which can easily cause the dynamic picture displayed to have an image blur effect. At present, the commonly used method for improving the dynamic display effect of liquid crystal displays and reducing motion blur is overdrive control, especially for high refresh rate video content display. Overdrive control technology can effectively improve the reaction speed of liquid crystal molecules and reduce the trailing effect of motion images, thereby supporting the display of high frame rate videos.

[0004] In overdrive control technology, in order to speed up the reaction speed of liquid crystal molecules, it is necessary to apply a larger overdrive voltage V+ΔV value on the basis of the normal drive voltage V, and then restore to the normal drive voltage value V after one frame time. The ΔV voltage value required for overdrive is not only related to the grayscale currently displayed by the pixel, but also to the grayscale of the previous frame. Usually, a two-dimensional lookup table is used and triangular interpolation is used to calculate the overdrive voltage value ΔV.

[0005] In order to implement the above-mentioned over-drive technology, the display controller needs to store a frame of image data in a frame buffer for realizing enhanced calculation of over-drive control. The cache space of this frame of data is related to the video resolution. For a high-resolution display, a frame of image data will occupy a larger storage space. The use of larger space storage chips and higher read-write access bandwidth increases the overall cost of the LCD display. The solution to this problem is to introduce image data compression to save memory space and read-write access bandwidth. The use of compression and decompression technology can effectively reduce the storage capacity of the frame buffer, thereby reducing the cost of the display controller.

[0006] Existing circuits for overdrive control of liquid crystal displays usually use the following two compression methods: one is a complex compression algorithm, such as a compression algorithm similar to JPG, which can achieve good compression effects in terms of performance, but will make the implementation circuit very complex, greatly increase the circuit cost, and increase the power consumption of the display system in mobile applications; the other is a simple block coding algorithm, namely the BTC (Block Truncation Coding) algorithm, which is the most widely used image compression algorithm in overdrive control technology. Its principle is to map all pixel gray values ​​to two gray values ​​RV0 and RV1 for a 2x2 or 4x4 block, and then use a bitmap of the corresponding block size to record the mapping relationship of the gray values. The advantages of this compression method are simple algorithm principle, small circuit implementation scale, simple structure, low power consumption and cost; but the disadvantage is that it can only support two gray values, the compressed image has large distortion, poor performance, and a very low compression ratio. Summary of the invention

[0007] In view of the technical problems existing in the prior art such as low compression ratio, large distortion and poor performance of the image compression algorithm in the display screen overdrive control, the present invention provides a display screen overdrive controller, which can improve the compression ratio, reduce image distortion and improve compression performance.

[0008] To achieve the above object, the present invention adopts the following technical solution:

[0009] A display screen overdrive controller includes an image compression and decompression processing unit, characterized in that the image compression and decompression processing unit is used to compress and decompress video data, the input data of the input end of the image compression and decompression processing unit is the video data, and the image compression and decompression processing unit is a compression / decompression data processor based on four values ​​or a compression / decompression data processor based on three values, the four values ​​include a maximum reference value, a minimum reference value, a first intermediate reference value, and a second intermediate reference value; the three values ​​include a maximum reference value, a minimum reference value, and an average reference value.

[0010] It further includes,

[0011] The display screen overdrive controller further includes a frame buffer read-write control unit, a frame buffer unit, a static image detection unit, and an overdrive control circuit unit. The frame buffer read-write control unit is used for read-write control of compressed data frames. The frame buffer unit is used to store compressed data frames. The data frames include previous frame data and current frame data. The static image detection unit is used to detect whether the decompressed previous frame data is consistent with the current frame data to determine whether the displayed video data is a static image. The image compression and decompression processing unit, the frame buffer read-write control unit, and the frame buffer unit are connected in sequence. The image compression and decompression processing unit is also connected in sequence to the static image detection unit and the overdrive control circuit unit. The overdrive control circuit unit is used to obtain a required overdrive voltage value. The output data of the output end of the overdrive control circuit is the processed video data.

[0012] The image compression and decompression processing unit, the frame buffer read and write control unit, the static image detection unit, and the overdrive control circuit unit are integrated into the same chip circuit;

[0013] The image compression and decompression processing unit performs mapping encoding based on the arrangement and combination of four values ​​for the 2x2 partition block, wherein the arrangement and combination of the four values ​​includes 56 combinations, and the 56 combinations are the position distribution arrangement of the four values ​​in the 2x2 partition block in different combinations;

[0014] The image compression and decompression processing unit implements encoding processing of the image data in the video data based on the YCoCg color space. When the color depth of the YCoCg color space is 8 bits, the data format encoded after compression processing of a 2x2 partition block is 48 bits, and the compression ratio is 2:1;

[0015] The four-value compression / decompression data processor is used to implement the encoding compression of the 48-bit data format, based on the YCoCg color space, the YCoCg color space includes three components of Y, Co and Cg, the 48-bit encoding includes a 6-bit mapping code, six 7-bit reference value data, and the two compressed maximum reference values ​​and minimum reference values ​​are 7-bit reference value data stored according to the three components of Y, Co and Cg respectively;

[0016] The image compression and decompression processing unit performs mapping encoding based on the arrangement and combination of three values ​​for the 2x2 partition block, wherein the arrangement and combination of three values ​​includes 26 combination modes, and the 26 combination modes are the position distribution arrangement of the three values ​​in the 2x2 partition block in different combinations;

[0017] The image compression and decompression processing unit implements encoding processing of the image data in the video data based on the YCoCg color space. When the color depth of the YCoCg color space is 8 bits, the format of the encoded data after compression processing is 32 bits, and the compression ratio is 3:1;

[0018] The three-value compression / decompression data processor is used to realize 32-bit coding compression, based on the YCoCg color space, the YCoCg color space includes three components of Y, Co and Cg, the 32-bit coding includes 6-bit mapping coding, the two compressed maximum reference values ​​and minimum reference values ​​are respectively retained according to the Y component. The two compressed 7-bit maximum reference values ​​and 7-bit minimum reference values, and the Co component and the Cg component only store a 6-bit average reference value data;

[0019] The compression / decompression data processor in the image compression and decompression processing unit uses 48-bit compression coding or 32-bit compression coding. In image data processing, the image data is compressed based on the YUV or YCbCr color space, and the data format of the compression coding is consistent with the data format adopted by the YCoCg color space coding compression;

[0020] The display screen is a liquid crystal display.

[0021] The above-mentioned structure of the present invention can achieve the following beneficial effects: the overdrive controller of the present application is used in the display control of the display, the overdrive controller includes an image compression and decompression processing unit, the image compression and decompression processing unit is used to compress and decompress the image, the image compression and decompression processing unit is a compression / decompression data processor based on four values ​​or a compression / decompression data processor based on three values, the four-value compression / decompression data processor or the three-value compression / decompression data processor is used for image data compression with 8-bit color depth, the compressed encoding data formats are 48-bit encoding and 32-bit encoding, respectively, so that the compression ratio reaches 2:1 and 3:1, respectively. It can be seen that compared with the existing compression method with a maximum compression ratio of 1.92:1, after adopting the image compression and decompression processing unit of the present application, the compression ratio is improved, thereby improving the image compression performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. The drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1A system block diagram of a display screen overdrive controller according to the present invention;

[0024] Figure 2 A circuit structure block diagram of an image compression and decompression processing unit of a display screen overdrive controller of the present invention;

[0025] Figure 3 3a and 3b are respectively the data bit table diagrams of the four-value block compression coding and the three-value block compression coding of the present invention;

[0026] Figure 4 It is a schematic diagram of the position structure of arranging pixels in an arrangement and combination manner when the compression / decompression data processor based on four values ​​of the present invention performs image compression or decompression processing;

[0027] Figure 5 A mapping code diagram for image compression by a compression / decompression data processor based on four values ​​of the present invention;

[0028] Figure 6 It is a schematic diagram of the position structure of arranging pixels in an arrangement and combination manner when the ternary compression / decompression data processor of the present invention performs image compression or decompression processing;

[0029] Figure 7 A mapping coding diagram for image compression based on a ternary compression / decompression data processor of the present invention.

[0030] The reference numerals include: 6 - 2x2 pixel partition block, P11, P12, P21 and P22 are pixels at four positions in the partition.

[0031] Wherein, the accompanying drawings are described as follows:

[0032] FIFO - First In First Out Queue Unit

[0033] RGB2YUV——RGB to YUV color space conversion unit

[0034] YUV2RGB——YUV to RGB color space conversion unit

[0035] Bit——A single digit in binary

[0036] Bit map——value mapping encoding

[0037] RV0——Minimum reference value

[0038] RV1——Maximum reference value

[0039] RV m0 ,RV m1 ——Intermediate reference value 0 and intermediate reference value 1 in the four-value case

[0040] RV m ——Intermediate reference value in the three-value case. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "including" and "having" and any variations thereof in the specification and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions. For example, a process, method, apparatus, product or equipment comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0043] In one embodiment of the present invention, an overdrive display controller based on four-value block compression is provided. Figure 1 , including an image compression and decompression processing unit 1, a frame buffer read and write control unit 2, a frame buffer unit 3, a static image detection unit 4 and an overdrive control circuit unit 5.

[0044] The image compression and decompression processing unit 1 includes a compression / decompression data processor; the frame buffer unit 3 includes a buffer register for caching frame data; the frame buffer read and write control unit 2 includes a reader / writer for reading and writing frame data; the static image detection unit 4 includes a comparator for comparing and judging the previous frame data with the current value data; the overdrive control circuit unit 5 includes an overdrive enhancement calculation circuit, the overdrive enhancement calculation circuit includes a comparator, an adder, and a lookup table, the overdrive enhancement calculation circuit is used to calculate and compare the current display data with the previous frame data, and calculate the required overdrive voltage value according to the lookup table, the adder is used to enhance the voltage, and the lookup table is used for table lookup operation to obtain the required overdrive voltage value.

[0045] The image compression and decompression processing unit 1 has an input end for the current original display input video data of the display controller, and an output end for the compressed image data is connected to the input end of the frame buffer read-write control unit 2 and is written into the frame buffer unit 3; at the same time, the compressed image data of the previous frame is read out from the frame buffer unit 3 by the frame buffer read-write control unit 2, and then sent to the image compression and decompression processing unit 1 for decompression processing; the decompressed image data of the previous frame and the current frame are output to the static image detection unit 4. The frame buffer read-write control unit 2 is located between the image compression and decompression processing unit 1 and the frame buffer unit 3, and is used for the read-write control of the compressed data frame. The frame buffer unit 3 is used to store the compressed data frame. The static image detection unit 4 is used to detect whether the decompressed previous frame data is consistent with the current frame, so as to determine whether the displayed video data is a static image.

[0046] Image compression and decompression processing unit 1, see Figure 2 , including a color space conversion module 1, a line buffer 1, an image compression module 1, a FIFO buffer module, an image decompression module 1, a line buffer 2, and a color space conversion module 2 connected in sequence; the image compression and decompression processing unit also includes an image decompression module 2, a line buffer 3, and a color space conversion module 3, the output end of the image compression module 1 and the input end of the image decompression module 2 are respectively connected to the frame buffer read-write control unit, the output end of the image decompression module 2 is connected to the image decompression module 2, the line buffer 3, and the color space conversion module 3 in sequence, the output ends of the color space conversion module 2 and the color space conversion module 3 are both connected to the static image detection unit, the color space conversion module 1 is used to realize the conversion between RGB color space and YUV color space, and convert the RGB image of each frame of data in the video data into a YUV image, the color space conversion module 2 and the color space conversion module 3 are used to realize the conversion between YUV color space and RGB color space, and convert the decompressed YUV image into an RGB image.

[0047] The image compression and decompression processing unit converts the input current original display video data from RGB to YUV format, and then the data code stream after image compression encoding is written into the frame buffer unit by the frame buffer read-write control unit; at the same time, the compressed data code stream of the previous frame image is read out from the frame buffer unit by the frame buffer read-write control unit, and then sent to the image decompression processing unit for data decoding processing; the decompressed image data of the previous frame and the current frame are output to the static image detection unit to detect whether the decompressed previous frame data is consistent with the current frame to determine whether the displayed video data is a static image. The overdrive control circuit unit (including the enhancement voltage calculation circuit) is used to compare the difference between the current display data and the previous frame data, and calculate the required overdrive voltage value according to the lookup table.

[0048] Image compression and decompression processing unit, see Figure 3 , the input video signal is converted into a 4-level grayscale signal according to 2x2 blocks and mapped and encoded, among which only the maximum reference value ( Figure 3 The minimum reference value (indicated by RV0) and the minimum reference value (indicated by RV1) are retained in the compression coding. On a 2x2 partition block, see Figure 4 and Figure 5 , the four values ​​are arranged and combined. The arrangement and combination refers to arranging the four values ​​in a combination of pixels without intermediate reference values ​​RVm0 and RVm1, pixels containing 1 RVm0 or 1 RVm1, pixels containing 2 RVm0 or 2 RVm1, and pixels containing 1 RVm0 and 1 RVm1. There are 56 arrangements in total. The mapping encoding of these 56 arrangements can cover the position distribution arrangements of all four values. See Figure 4 , Figure 4 The number 6 indicates the pixel arrangement before image compression, P11, P12, P21, and P22 indicate pixels respectively, RV0, RV1, RVm0, and RVm1 indicate reference values ​​after pixel compression, and the numbers in brackets indicate the numbers of the permutations and combinations. Figure 5 To adopt the above Figure 4 A specific embodiment of mapping encoding is performed by the mapping encoding method shown, Figure 5 Coding represents the reference value contained in the four values, the bitmap number represents the above 56 arrangements, and the final bitmap coding represents the coding after compression based on the four values. When all the four values ​​are the same value, the number of codes is P=1, when there are no intermediate reference values ​​RVm0 and RVm1 in the four values, the number of codes is P=7, when the four values ​​contain one RVm0 or one RVm1, the number of codes is P=24, when the four values ​​contain 2 RVm0 or 2 RVm1, the number of codes is P=12, when the four values ​​contain 1 RVm0 and 1 RVm1, the number of codes is 12. It can be seen from the final bitmap that the coding after image compression by the compression / decompression data processor of the four values ​​of the present application is 6 bits, and all 56 position combinations can be represented by 6-bit coding.

[0049] The image compression and decompression processing unit can also be a three-valued compression / decompression data processor, which can be regarded as a special case of four-value compression, see Figure 6 and Figure 7 In this case, the three values ​​are arranged and combined on the 2x2 partition block. The arrangement and combination refers to arranging the three values ​​in a combination of pixels without average reference value RVm, pixels containing 1 average reference value RVm, and pixels containing 2 average reference values ​​RVm. There are 26 cases in total, see Figure 6 , Figure 6The reference numeral 6 indicates the arrangement of pixel positions before image compression, P11, P12, P21, and P22 indicate pixels respectively, and RV0, RV1, and RVm indicate reference values ​​after pixel compression. Figure 7 To adopt the above Figure 6 A specific embodiment of mapping encoding is performed by the mapping encoding method shown, Figure 7 Coding represents the reference value included in the four values, the bitmap number represents the above 26 arrangements, and the final bitmap coding represents the coding after compression based on three values. When all three values ​​are the same value, the number of codes is P=1, when there is no intermediate reference value RVm in the three values, the number of codes is P=7, when the three values ​​include one RVm, the number of codes is P=12, and when the three values ​​include 2 RVms, the number of codes is P=6. It can be seen from the final bitmap coding that the coding after image compression by the three-value compression / decompression data processor of the present application is 5 bits, and all 26 position combinations can be represented by 5-bit coding.

[0050] When using the 48-bit compressed bitstream format, see Figure 3 3a in the figure is based on the YCoCg color space. In addition to the 6-bit mapping encoding, the two compressed maximum reference values ​​and minimum reference values ​​are stored as 7-bit data for the three components of Y, Co and Cg. For input image data with 8-bit color depth, the compression ratio can be 2:1.

[0051] When using the 32-bit compressed bitstream format, see Figure 3 3b in the code is based on the YCoCg color space. In addition to the 6-bit mapping encoding, the Y component retains two 7-bit reference values, the maximum reference value and the minimum reference value after compression, and the Co and Cg components only store a 6-bit average reference value data. For 8-bit color depth input image data, the compression ratio can be 3:1.

[0052] When the image compression and decompression processing unit uses a 48-bit or 32-bit compressed bitstream format based on a color space such as YCC, YUV or YCbCr, the result is consistent with the above case.

[0053] Based on the above-mentioned image compression coding mapping method, the present invention provides an image compression and decompression processing circuit based on four-value blocks and its image data mapping working principle and process are as follows:

[0054] First, in the 2x2 partition block, the brightness value Y of each pixel is calculated according to four values: RV0, RV1, RV m0 and RV m1 The classification process is as follows: first determine the maximum reference value RV`1 and the minimum reference value RV`0, and calculate the first reference value RV` m1and the second intermediate reference value RV` m0 :

[0055] RV` m1 =RV`0+(RV`1-RV`0)×2 / 3 (1)

[0056] RV` m0 =RV`0+(RV`1-RV`0) / 3 (2)

[0057] Then, according to the principle of proximity, the pixel brightness Y is assigned to the level of the corresponding value. After the allocation is completed, the number of pixels N0, N1, N2 corresponding to each reference value in the 2x2 partition block is obtained. m0 and N m1 .

[0058] In order to reduce the impact of quantization noise error on the luminance grading results, the reference values ​​RV0 and RV1 need to be recalculated. The calculation process is shown in the following formula:

[0059] N0RV0+N m0 RV m0 +N m1 RV m1 + N1RV1=(∑0P ij )+(∑ m0 P ij )+(∑ m1 P ij )+(∑1P ij ) (3)

[0060]

[0061] Among them, N0, N1, N m0 and N m1 are the number of pixels corresponding to each reference value in the 2x2 partition block, ∑P ij It is the sum of the Y component brightness value and Co / Cg component chromaticity value of the pixel points within the same reference value range. total is the number of pixels in the 2x2 partition block, which is 4 in this implementation.

[0062] Based on the above brightness classification results, the brightness values ​​of each pixel in the 2x2 partition block correspond to Figure 4 A distribution pattern in Figure 5In the above, each distribution pattern corresponds to a 6-bit code, plus the reference values ​​RV0 and RV1 calculated above, the compressed coded data is obtained. If the Y component and Co / Cg component use the 4:4:4 format, the 48-bit compressed code is obtained; if the Y component and Co / Cg component use the 4:2:0 format, the 32-bit compressed code is obtained.

[0063] When restoring image data from compressed coded data, the reverse process of the above process is followed. First, the distribution mode (represented by pattern in the figure) and reference values ​​RV0 and RV1 of the brightness values ​​of each pixel in the 2x2 partition block after classification are obtained from the compressed code, and then RV is calculated using formulas (1) and (2). m0 and RV m1 Then, the brightness level of each pixel is deduced from the distribution pattern, and then the Y component and Co / Cg component values ​​of each pixel are obtained according to the corresponding level of each pixel.

[0064] The image compression and decompression processing unit provided by the present invention can also be a three-value compression / decompression data processor, which is a special case of four-value compression. The working principle and process of the image compression and decompression processing circuit based on three-value blocks and its image data mapping provided by the present invention are as follows:

[0065] First, in the 2x2 partition block, the brightness value Y of each pixel is calculated according to three values: RV0, RV1 and RV m The classification process is as follows: first determine the maximum reference value RV`1 and the minimum reference value RV`0, and calculate the intermediate reference value RV` m

[0066] RV` m =RV`0+(RV`1-RV`0) / 2 (7)

[0067] Then, according to the principle of proximity, the pixel brightness Y is assigned to the level of the corresponding value. After the allocation is completed, the number of pixels N0, N1 and N corresponding to each reference value in the 2x2 partition block is obtained. m .

[0068] In order to reduce the impact of quantization noise error on the luminance grading results, the reference values ​​RV0 and RV1 need to be recalculated. The calculation process is shown in the following formula:

[0069] N0RV0+N m RV m + N1RV1=(∑0P ij )+(∑ m P ij )+(∑1Pij ) (8)

[0070] (N0+N m / 2)RV0+(N1+N m / 2)RV1=(∑0P ij )+(∑ m P ij )+(∑1P ij ) (9)

[0071]

[0072] Among them, N0, N1 and N m are the number of pixels corresponding to each reference value in the 2x2 partition block, ∑P ij It is the sum of the brightness value Y and the chromaticity value Co / Cg of the pixel points within the same reference value range. total is the number of pixels in the 2x2 partition block, which is 4 in this implementation.

[0073] Based on the above brightness classification results, the brightness values ​​of each pixel in the 2x2 partition block correspond to Figure 6 A distribution pattern in Figure 7 In the above, each distribution pattern corresponds to a 5-bit code, plus the reference values ​​RV0 and RV1 calculated above, the compressed bitstream data is obtained. If the Y component and Co / Cg component use the 4:4:4 format, a 48-bit bitstream is obtained; if the Y component and Co / Cg component use the 4:2:0 format, a 32-bit bitstream is obtained.

[0074] When restoring image data from compressed bitstream data, the above process is reversed. First, the distribution pattern and reference values ​​RV0 and RV1 of the brightness values ​​of each pixel in the 2x2 partition block are obtained from the compressed bitstream, and then RV is calculated using formula (7). m Then, the brightness level of each pixel is deduced from the distribution pattern, and then the Y component and Co / Cg component values ​​of each pixel are obtained according to the corresponding level of each pixel.

[0075] The overdrive display controller circuit based on four-value block compression or the overdrive display controller circuit based on three-value block compression provided by the present invention is preferably applied to an overdrive display controller in a liquid crystal display, and can be applied to a circuit controller of a simple image video transmission and storage system with low signal-to-noise ratio requirements, and is particularly suitable for low-delay, high-compression ratio image compression / decompression data processing. Figures 4 to 7It can be seen that the display screen overdrive controller of the present application not only has a high compression ratio and very low latency, but also simplifies the design complexity of the overall circuit solution and reduces the cost of the circuit system.

[0076] The above are only preferred embodiments of the present application, and the present invention is not limited to the above embodiments. It is understood that other improvements and changes directly derived or associated by those skilled in the art without departing from the spirit and concept of the invention should be considered to be included in the scope of protection of the invention.

Claims

1. A display screen overdrive controller, comprising an image compression and decompression processing unit, characterized in that: The image compression and decompression processing unit is used to compress and decompress video data. The input data of the input end of the image compression and decompression processing unit is the video data. The image compression and decompression processing unit is a compression / decompression data processor based on three values, and implements encoding processing of image data in the video data based on the YCoCg color space; the three values ​​include a maximum reference value, a minimum reference value, and an average reference value; when the image compression and decompression processing unit performs mapping encoding based on the permutation and combination of the three values ​​for a 2x2 partition block, the permutation and combination of the three values ​​includes 26 combination methods, corresponding to the position distribution arrangement of the three values ​​combined in different ways; the permutation and combination refers to arranging the four values ​​in a combination of pixels without an average reference value, pixels including 1 average reference value, and pixels including 2 average reference values; the image compression process includes the following: In the 2x2 partition block, the maximum reference value and the minimum reference value are determined according to the three values ​​of the brightness value Y of each pixel, and the intermediate reference value is calculated; Based on the three-value brightness classification, the number of pixels N0, N1 and N2 of the maximum reference value, the minimum reference value and the intermediate reference value RVm at the corresponding level in the 2x2 partition block are determined according to the principle of proximity. m ; Recalculate the maximum reference value RV0 and the minimum reference value RV1 based on the Y component brightness value and Co / Cg component chromaticity value of the pixel point. The formula is as follows: N0RV0+N m RV m +N1RV1=(∑0P ij )+(∑ m P ij )+(∑1P ij ) (N0+N m / 2)RV0+(N1+N m / 2)RV1=(∑0P ij )+(∑ m P ij )+(∑1P ij ) Among them, ∑P ij It is the sum of the Y component brightness value and Co / Cg component chromaticity value of the pixel points within the same reference value range. total is the number of pixels in the 2x2 partition block, the value is 4; Re-grading the brightness of the pixels of the 2x2 partition block according to the newly calculated maximum reference value and minimum reference value; Based on the brightness grading result, the distribution mode of the graded arrangement and combination of brightness values ​​of each pixel in the 2x2 partition block is determined, and compression coding is performed.

2. A display screen overdrive controller according to claim 1, characterized in that: The display screen overdrive controller also includes a frame buffer read-write control unit, a frame buffer unit, a static image detection unit, and an overdrive control circuit unit. The frame buffer read-write control unit is used for read-write control of compressed data frames. The frame buffer unit is used to store compressed data frames. The data frames include previous frame data and current frame data. The static image detection unit is used to detect whether the decompressed previous frame data is consistent with the current frame data to determine whether the displayed video data is a static image. The image compression and decompression processing unit, the frame buffer read-write control unit, and the frame buffer unit are connected in sequence. The image compression and decompression processing unit is also connected in sequence to the static image detection unit and the overdrive control circuit unit. The overdrive control circuit unit is used to obtain the required overdrive voltage value. The output data at the output end of the overdrive control circuit is the processed video data.

3. A display screen overdrive controller according to claim 2, characterized in that: When the color depth of the YCoCg color space is 8 bits, the data format encoded after compression processing of a 2x2 partition block is 32 bits, and the compression ratio is 3:

1.

4. A display screen overdrive controller according to claim 3, characterized in that: The three-value compression / decompression data processor is used to realize 32-bit encoding compression based on the YCoCg color space, the YCoCg color space includes three components of Y, Co and Cg, the 32-bit encoding includes 6-bit mapping encoding, and the two compressed maximum reference values ​​and minimum reference values ​​respectively retain two compressed 7-bit maximum reference value data and 7-bit minimum reference value data according to the Y component, and the Co component and Cg component only store one 6-bit average reference value data respectively.

5. A display screen overdrive controller according to claim 4, characterized in that: The compression / decompression data processor in the image compression and decompression processing unit uses 48-bit compression coding or 32-bit compression coding. In image data processing, the image data is compressed based on the YUV or YCbCr color space, and the data format of the compression coding is consistent with the data format adopted by the YCoCg color space coding compression.

6. A display screen overdrive controller according to claim 5, characterized in that: The display screen is a liquid crystal display.

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