Grid-control Hall element based on silicon-germanium quantum well and implementation method of grid-control Hall element

Abstract

The invention discloses a grid-control Hall element based on a silicon-germanium quantum well and an implementation method of the grid-control Hall element. The silicon germanium quantum well structure is adopted and is compatible with a traditional silicon MOS process, high cost for developing a new material substrate is avoided, and the silicon germanium quantum well structure can be conveniently matched with an existing silicon-based integrated circuit; according to the invention, the carrier concentration is regulated and controlled through the grid voltage, so that constant-voltage and constant-current working modes can be adapted respectively; the mobility can be regulated to be high, and the heat dissipation and power consumption of the device are effectively reduced; in addition, the sensitivity of the Hall element can be flexibly adjusted by the grid voltage, magnetic field ranges under different loads are matched, and different application requirements are met. According to the scheme, the performance and the working flexibility of the device are remarkably improved, the single device has the high-sensitivity measurement capability and adapts to multiple working modes, the number of elements can be reduced, the circuit design can be optimized, and the convenience of large-scale integration and development is improved; the device is applied to magnetic field measurement, and is especially suitable for weak magnetic field detection in a low-temperature environment.

Description

Technical Field

[0001] The invention relates to semiconductor magnetic sensor technology, and in particular to a gate-controlled Hall element based on silicon germanium quantum well and a realization method thereof. Background Art

[0002] The Hall sensor is an electronic device that uses the Hall effect to measure magnetic fields. It has been widely used in industrial control systems, smart instruments, and consumer electronics. The Hall element refers to the part of the sensor where the Hall effect occurs. The Hall effect refers to the fact that when current passes through a conductor or semiconductor placed in a magnetic field, the charge carriers are deflected by the Lorentz force, and a potential difference is generated in the direction perpendicular to the current and the magnetic field. Based on the change in the transverse Hall voltage, the change in the magnetic field can be detected. The Hall sensitivity of the element can be obtained through microscopic derivation: S_I=1 / (ned), S_V=µW / L, where S_I and S_V represent the Hall sensitivity under unit current and unit voltage, respectively, corresponding to constant current and constant voltage modes, n is the carrier concentration, e is the basic charge, d is the thickness of the working material of the Hall element, µ is the carrier mobility, and W and L are the width and length of the conductive channel, respectively. It can be seen that high carrier mobility and low carrier concentration will make the Hall element have high sensitivity. Commercial Hall element materials often use single-element semiconductor materials Si and Ge, but the carrier mobility of these materials is generally not high, and the corresponding Hall element sensitivity is low. Hall elements based on III-V compound semiconductors GaAs and InSb have higher carrier mobility and higher Hall sensitivity. However, the process of this type of Hall element is poorly compatible with the gate control structure, and modulation doping technology is often used, resulting in relatively fixed carrier concentration and mobility in the channel. The function of the element is relatively single, and multiple devices with different functions need to be integrated in different scenarios to meet the needs of actual use, thereby increasing the complexity of the preparation process.

[0003] With the development of materials science and nanotechnology, Hall elements based on two-dimensional materials and semiconductor quantum wells have shown great potential in terms of sensitivity and may gradually replace traditional elements in some high-precision applications. However, the two-dimensional materials that have been widely studied, such as graphene and transition metal dichalcogenides, and III-V compound quantum wells such as GaAs / AlGaAs and AlGaN / GaN, still face problems such as complex preparation processes and incompatibility with traditional silicon MOS processes. These problems seriously restrict the large-scale integration and practical application of Hall elements. Summary of the invention

[0004] In order to solve the problems existing in the above-mentioned prior art, the present invention proposes a gate-controlled Hall element based on silicon germanium quantum well and an implementation method thereof. Silicon germanium quantum well is adopted, which has very high mobility and can sensitively respond to weak magnetic fields, thus solving the problem of low sensitivity of existing Hall elements. The gate voltage regulates the carrier concentration and mobility of the Hall element, thus realizing multiple working modes, thus solving the problems of single function and waste of power consumption of existing devices.

[0005] An object of the present invention is to provide a gate-controlled Hall element based on silicon germanium quantum well.

[0006] The gate-controlled Hall element based on silicon germanium quantum well of the present invention comprises: a substrate, a buffer layer, a silicon germanium quantum well structure, a source electrode, a drain electrode, a measuring electrode, an oxide insulating layer and a gate; wherein the buffer layer is formed on the substrate; and the silicon germanium quantum well structure is formed on the buffer layer; The silicon germanium quantum well structure includes a first barrier layer, a potential well layer, a second barrier layer and a cap layer from bottom to top; the materials of the first barrier layer and the second barrier layer are silicon-germanium compounds, and the material of the potential well layer is germanium. The mobility of germanium is higher than that of silicon. The valence band of the barrier layer is lower than that of the potential well layer, forming a potential well of holes. The holes serve as carriers, thereby confining the holes in the potential well layer, away from ionized impurities, forming a highly mobile two-dimensional hole gas, and the lattice constants of the barrier layer and the potential well layer are similar, and the lattice defects are small; a conductive channel is defined in the potential well layer, and a source electrode, a drain electrode and two pairs of measuring electrodes are arranged around the conductive channel, the source electrode and the drain electrode are respectively located at the two ends of the conductive channel in the longitudinal direction, and the two pairs of measuring electrodes are respectively located at the two sides of the conductive channel in the transverse direction, and the source electrode, the drain electrode and the two pairs of measuring electrodes are respectively electrically connected to the conductive channel to form a bridge-type Hall bar structure; An oxide insulating layer is formed on the silicon germanium quantum well structure; a gate is formed on the oxide insulating layer, and the gate is located directly above the conductive channel; The source electrode and the drain electrode are connected to a constant voltage source in a constant voltage mode, or the source electrode and the drain electrode are connected to a constant current source in a constant current mode; two pairs of measuring electrodes are connected to an external measuring circuit; the gate is connected to a regulating voltage source; A constant voltage or a constant current is input from the source electrode and the drain electrode through a constant voltage source or a constant current source, and a longitudinal current is generated between the source electrode and the drain electrode; a magnetic field perpendicular to the plane of the element is applied, and under the influence of the external magnetic field, holes are accumulated on both sides of the conductive channel controlled by the gate voltage applied by the gate, and the holes are deflected to generate a transverse Hall voltage; the transverse Hall voltage is measured by the measuring electrodes located on both sides of the conductive channel, so that the magnetic field information is obtained through the transverse Hall voltage; By regulating the voltage source to apply gate voltage to the gate, the Fermi level and carrier concentration of the potential well layer are adjusted, and then the carrier mobility is regulated to achieve the purpose of regulating the Hall sensitivity; the carrier concentration of the potential well layer is increased, and the scattering of holes by impurities and defects at distant interfaces is reduced, thereby improving the carrier mobility; In constant current mode, the gate voltage applied to the gate is reduced by adjusting the voltage source to reduce the carrier concentration; or in constant voltage mode, the gate voltage applied to the gate is increased by adjusting the voltage source to increase the carrier mobility, thereby improving the Hall sensitivity in constant current mode or constant voltage mode respectively.

[0007] The substrate uses n-type Si.

[0008] The materials of the first barrier layer and the second barrier layer are silicon germanium compound Si x Ge 1-x , x is the composition of silicon in the first barrier layer and the second barrier layer. The composition x of silicon in the first barrier layer and the second barrier layer is 0.1 to 0.3.

[0009] The buffer layer includes a component-free strain buffer layer and a component-gradient buffer layer. For the barrier layer Si with high Ge content x Ge 1-x The material of the unstrained buffer layer is germanium, and the material of the gradient buffer layer is silicon-germanium compound Si z Ge 1-z , z is the composition of silicon in the composition gradient buffer layer, 0≤z≤x; the composition of silicon in the composition gradient buffer layer gradually changes from 0 to x from bottom to top, and the lattice constant gradually transitions from the strain-free buffer layer to the first barrier layer Si x Ge 1-x ; The setting of the buffer layer can reduce crystal defects and gradually release stress.

[0010] The capping layer is made of silicon; it protects the underlying SiGe surface from natural oxidation and damage.

[0011] The shape of the conductive channel is rectangular, with a length of 100~300μm and a width of 20~80μm; the width W of the conductive channel is appropriately increased and / or the length L is reduced to provide high voltage sensitivity. The source electrode and the drain electrode are located at both ends of the short side of the Hall bar, and the measuring electrodes for measuring the lateral Hall voltage are located on both sides of the long side of the Hall bar, parallel to each other on the same side; aligned to each other on the opposite sides. The multiple transversely parallel electrodes on the long side are set to measure the longitudinal resistance by the four-terminal method, increase the fault tolerance of some electrodes being non-conductive, and can be used in constant current and constant voltage working modes respectively. The thickness of the source electrode, drain electrode and measuring electrode is 50~100nm; the thickness of the oxide insulating layer is 20~80nm; the thickness of the gate is 150~300nm.

[0012] Hall sensitivity reflects the response ability of the Hall element to the magnetic field. S_A is the absolute Hall sensitivity, which indicates the transverse Hall voltage V caused by a unit magnetic field change. xy The amount of change reflects the sensitivity of the component's Hall signal to changes in the magnetic field. S_I and S_V represent the Hall sensitivity per unit current and per unit voltage, respectively. The greater the Hall sensitivity S_I per unit current or the Hall sensitivity S_V per unit voltage, the greater the Hall sensitivity that can be obtained per unit external bias current or voltage. The Hall sensitivity S_I per unit current is inversely proportional to the carrier concentration, while the Hall sensitivity S_V per unit voltage is proportional to the carrier mobility; therefore, by regulating the voltage source to reduce the gate voltage applied to the gate, the carrier concentration is lowered in the constant current mode, and by regulating the voltage source to increase the gate voltage applied to the gate, the carrier mobility is increased in the constant voltage mode, thereby achieving high Hall sensitivity in the constant current mode and constant voltage mode, respectively.

[0013] The voltage range of the constant voltage source is 0.1~1mV, the current range of the constant current source is 0.1~1μA, and the voltage range of the regulated voltage source is -2.5~ -2.2V.

[0014] Another object of the present invention is to provide a method for realizing a gate-controlled Hall element based on silicon germanium quantum well.

[0015] The method for realizing a gate-controlled Hall element based on a silicon-germanium quantum well of the present invention comprises the following steps: 1) Gate-controlled Hall element connection: The source electrode and the drain electrode are connected to a constant voltage source in a constant current mode, or the source electrode and the drain electrode are connected to a constant current source in a constant voltage mode; two pairs of measuring electrodes are connected to an external measuring circuit; the gate is connected to a regulating voltage source; 2) Magnetic field measurement: a) inputting a constant voltage or a constant current from the source electrode and the drain electrode through a constant voltage source or a constant current source to generate a longitudinal current between the source electrode and the drain electrode; b) Apply a magnetic field perpendicular to the plane of the element. Under the influence of the external magnetic field, the holes are deflected and accumulated on both sides of the conductive channel controlled by the gate voltage applied by the gate, generating a lateral Hall voltage. c) measuring the transverse Hall voltage through two pairs of measuring electrodes located on both sides of the conductive channel, thereby obtaining the magnetic field through the transverse Hall voltage; 3) Gate voltage regulation: a) By regulating the voltage source to apply gate voltage to the gate, the carrier concentration of the potential well layer is changed, and then the carrier mobility is adjusted to achieve the purpose of regulating the Hall sensitivity; the carrier concentration of the potential well layer is increased, and the scattering of holes by impurities and defects at distant interfaces is reduced, thereby improving the carrier mobility; b) In constant current mode, the gate voltage applied to the gate is reduced by adjusting the voltage source to reduce the carrier concentration; or in constant voltage mode, the gate voltage applied to the gate is increased by adjusting the voltage source to increase the carrier mobility, thereby improving the Hall sensitivity in constant current mode or constant voltage mode respectively.

[0016] The method for realizing the gate-controlled Hall element based on silicon germanium quantum well of the present invention also includes a method for preparing the gate-controlled Hall element, comprising the following steps: a) forming a buffer layer on a substrate; b) forming a silicon germanium quantum well structure on the buffer layer: forming a first barrier layer, a potential well layer, a second barrier layer and a cap layer in sequence from bottom to top on the buffer layer; the first barrier layer and the second barrier layer are made of silicon germanium compounds, the potential well layer is made of germanium, holes are confined in the potential well layer, and holes serve as carriers to form a highly mobile two-dimensional hole gas; c) defining a conductive channel in the potential well layer, arranging a source electrode, a drain electrode and two pairs of measuring electrodes around the conductive channel, wherein the source electrode and the drain electrode are respectively located at two ends of the conductive channel in the longitudinal direction, and the two pairs of measuring electrodes are respectively located at two sides of the conductive channel in the transverse direction, and the source electrode, the drain electrode and the two pairs of measuring electrodes are respectively electrically connected to the conductive channel to form a bridge-type Hall bar structure; d) forming an oxide insulating layer on the silicon germanium quantum well structure; e) forming a gate on the oxide insulating layer, wherein the gate is located directly above the conductive channel.

[0017] Advantages of the present invention: The present invention adopts a silicon germanium quantum well structure, which is compatible with traditional silicon MOS processes, avoids the high cost of developing new material substrates, and can be easily matched with existing silicon-based integrated circuits; the gate-controlled Hall element proposed in the present invention, on the one hand, can adapt to constant voltage and constant current working modes respectively by regulating the carrier concentration through gate voltage; on the other hand, it can be adjusted to a high mobility, effectively reducing the heat dissipation and power consumption of the device; in addition, the gate voltage can flexibly adjust the sensitivity of the Hall element in the same mode, match the magnetic field range under different loads, and adapt to different application requirements, for example, provide high sensitivity in weak magnetic field detection, and reduce sensitivity in strong magnetic field environment to ensure stability; compared with traditional Hall elements using channel materials with fixed carrier concentration and mobility, the present invention significantly improves the performance and working flexibility of the device, so that a single device has both high-sensitivity measurement capabilities and adapts to multiple working modes, which helps to reduce the number of components, optimize circuit design, and improve the convenience of large-scale integration and development. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A top view of an embodiment of a gate-controlled Hall element based on silicon germanium quantum well of the present invention; Figure 2A cross-sectional view of an embodiment of a gate-controlled Hall element based on silicon germanium quantum well of the present invention; Figure 3 A graph showing gate voltage regulation of carrier concentration and mobility obtained according to an embodiment of a gate-controlled Hall element based on silicon germanium quantum wells of the present invention; Figure 4 The graph is a graph of the Hall sensitivity per unit current and per unit voltage of an embodiment of a gate-controlled Hall element based on silicon germanium quantum well according to the present invention under gate voltage control within a suitable range. DETAILED DESCRIPTION

[0019] The present invention will be further described below through specific embodiments in conjunction with the accompanying drawings.

[0020] like Figure 1 and 2 As shown, the gate-controlled Hall element based on silicon germanium quantum well of this embodiment includes: a substrate, a buffer layer, a silicon germanium quantum well structure, a source electrode 201, a drain electrode 202, a measuring electrode 203, an oxide insulating layer 300 and a gate 400; wherein the buffer layer is formed on the substrate; and the silicon germanium quantum well structure is formed on the buffer layer; The silicon germanium quantum well structure includes a first barrier layer 100, a potential well layer 101, a second barrier layer 102 and a cap layer 103 from bottom to top. The materials of the first barrier layer 100 and the second barrier layer 102 are Si x Ge 1-x , x and 1-x are components of silicon and germanium respectively, the material of the potential well layer 101 is germanium, holes are confined in the potential well layer, and holes, as carriers, are away from ionized impurities to form a two-dimensional hole gas 400 with high mobility; a conductive channel 104 is defined in the potential well layer, and a source electrode, a drain electrode and two pairs of measuring electrodes are arranged around the conductive channel, the source electrode and the drain electrode are respectively located at the two ends of the conductive channel in the longitudinal direction, and the two pairs of measuring electrodes are respectively located at the two sides of the conductive channel in the transverse direction, and the rectangular area surrounded by the source electrode, the drain electrode and the two pairs of measuring electrodes constitute a conductive channel, and the source electrode, the drain electrode and the two pairs of measuring electrodes are respectively electrically connected to the conductive channel to form a bridge-type Hall bar structure; An oxide insulating layer 300 is formed on the silicon germanium quantum well structure; a gate 400 is formed on the oxide insulating layer, and the gate is located directly above the conductive channel; The source electrode is connected to a constant voltage source or a constant current source, and the drain electrode is grounded; two pairs of measuring electrodes are connected to an external measuring circuit; and the gate is connected to a regulating voltage source through a pad.

[0021] The implementation method of the gate-controlled Hall element based on silicon germanium quantum well of this embodiment includes the following steps: 1) Preparation of gate-controlled Hall element: a) Taking n-type Si (001) as the substrate, a buffer layer is formed on the substrate; the buffer layer includes a 600 nm thick unstrained Ge buffer layer and a 2 μm thick compositionally graded Si z Ge 1-z Buffer layer, z gradually changes from 0 to 0.2 from bottom to top; the setting of the buffer layer can reduce crystal defects and gradually release stress; b) Forming a silicon germanium quantum well structure on the buffer layer: The silicon germanium quantum well structure forms the first barrier layer, the potential well layer, the second barrier layer and the cap layer from bottom to top; the first barrier layer is 500nm thick Si 0.2 Ge 0.8 The potential well layer is 18 nm thick Ge, and the second barrier layer is 38 nm thick Si 0.2 Ge 0.8 The capping layer is 2 nm thick Si, forming a silicon germanium quantum well structure; a higher potential barrier is formed in the band structure to limit the carriers in the potential well layer; the capping layer uses Si to protect the structure below to prevent oxidation; The above growth method uses ultra-high vacuum chemical vapor deposition to ensure the interface quality between layers; Hall bar platform etching: take a silicon germanium quantum well structure substrate, clean the sample and blow dry it with high-purity nitrogen; perform photoresist coating, electron beam exposure, development and fixing to determine the shape of the etching area; use the reactive ion etching (RIE) method to etch a Hall bar platform on the silicon germanium quantum well structure, and set a rectangular conductive channel in the potential well layer by the above method, with a length of 195μm and a width of 35μm; c) Preparation of metal Al electrode: The electrode area that needs to contact the conductive channel is exposed on the Hall bar platform. The natural oxide layer on the surface is washed away with hydrofluoric acid HF, and the film is deposited by electron beam evaporation. Note that the vacuum degree of the electron beam cavity should be less than 5×10 -8 Torr, Al with a thickness of 80 nm is used as the measuring electrode, source electrode and drain electrode. After coating, it is annealed in situ for 2 hours to recover the defects caused by etching, exposure and coating. During the annealing process, Al diffuses into Ge to realize the ohmic contact between the electrode and the conductive channel, forming a bridge-type Hall bar structure; finally, a lift-off process is performed to put the coated substrate into acetone to wash away the photoresist. After the excess photoresist and metal are stripped off, the source electrode, drain electrode and measuring electrode of the desired shape can be obtained, and finally the sample is blown dry with high-purity nitrogen; d) Preparation of oxide insulating layer: Atomic layer deposition (ALD) is used to deposit Al2O3 as an oxide insulating layer on the silicon germanium quantum well structure; high-purity nitrogen (carrier gas, TMA trimethylaluminum and water react to generate Al2O3), the temperature is 100~300℃, preferably 150℃, the thickness is about 60nm, and the deposition process is completed in about ten minutes; e) Grid preparation: coating, electron beam exposure, coating, developing, fixing and stripping to obtain the grid; confirm the grid pattern by exposure, and then use electron beam evaporation to coat the metal film Au to obtain the grid; the grid ensures that the conductive channel is covered and the gate voltage of the two-dimensional hole gas is adjustable; 2) Gate-controlled Hall element connection: The source electrode and the drain electrode are connected to a constant voltage source in a constant voltage mode, or the source electrode and the drain electrode are connected to a constant current source in a constant current mode; two pairs of measuring electrodes are connected to an external measuring circuit; the gate is connected to a regulating voltage source; 3) Magnetic field measurement: a) inputting a constant voltage or a constant current from the source electrode and the drain electrode through a constant voltage source or a constant current source to generate a longitudinal current between the source electrode and the drain electrode; applying a gate voltage to the gate by regulating the voltage source; b) Apply a magnetic field perpendicular to the plane of the element. Under the influence of the external magnetic field, the holes are deflected and accumulate on both sides of the conductive channel controlled by the gate voltage applied by the gate, generating a lateral Hall voltage V xy ; c) measuring the transverse Hall voltage through two pairs of measuring electrodes located on both sides of the conductive channel, thereby obtaining the magnetic field through the transverse Hall voltage; 4) Gate voltage regulation: a) By regulating the voltage source to apply gate voltage to the gate, the carrier concentration of the potential well layer is changed, and then the carrier mobility is adjusted to achieve the purpose of regulating the Hall sensitivity; increasing the carrier concentration of the potential well layer is conducive to reducing the scattering of holes by impurities and defects at distant interfaces, thereby improving the carrier mobility; b) In constant current mode, the gate voltage applied to the gate is reduced by adjusting the voltage source to reduce the carrier concentration; or in constant voltage mode, the gate voltage applied to the gate is increased by adjusting the voltage source to increase the carrier mobility, thereby improving the Hall sensitivity in constant current mode or constant voltage mode respectively.

[0022] In subsequent applications, multiple Hall elements are placed vertically to the xyz axis, and each Hall element is sensitive to the magnetic field component on the corresponding axis. The sensitivity of each Hall element is dynamically adjusted by gate voltage, and the size and direction of the magnetic field in the actual three-dimensional space are obtained by combining circuit design and direction correction.

[0023] The basic characterization of the silicon germanium quantum well hole Hall bar is carried out. The drain electrode is grounded and the source electrode inputs a constant alternating current. By changing the gate voltage V g The electrical transport properties of the SiGe quantum well structure, such as n / μ-V, were obtained by using holes as carriers under the conditions of magnetic field B. g . Get the lateral Hall voltage V xyAs the magnetic field B changes, the Hall sensitivity of the element is calculated. Figure 2 As can be seen from the figure, the slope of the curve is large and the sensitivity is high, so it can be used to detect weak magnetic fields. The adjustable gate voltage allows different operating modes or parameter settings to be implemented on the same Hall element, lowering the carrier concentration in constant current mode and increasing the carrier mobility in constant voltage mode, which can improve the Hall sensitivity in constant current mode and constant voltage mode respectively.

[0024] Gate voltage control principle and high sensitivity realization of gate-controlled Hall element: By regulating the voltage source to apply gate voltage to the gate, the Fermi level and carrier concentration of the potential well layer are regulated, and then the carrier mobility is regulated to achieve the purpose of regulating Hall sensitivity; the ability of the gate voltage to regulate the carrier concentration in the potential well layer is determined by the capacitance of its equivalent parallel plate capacitor; for the material of the same oxide insulating layer, the thinner the thickness of the parallel plate capacitor, the larger the capacitance of the parallel plate capacitor, and the stronger the ability of the gate voltage to regulate the carrier concentration and mobility; the ability of the gate voltage to regulate the hole concentration in the potential well layer is determined by the capacitance of its equivalent parallel plate capacitor; the parallel plate capacitance formula C=εS / 4πkt, C is the capacitance of the parallel plate capacitor, ε is the dielectric constant of the oxide insulating layer, S is the facing area of ​​the electrode, k is the electrostatic force constant, and t is the thickness of the oxide insulating layer.

[0025] The physical quantities represented by letters in the following derivation are: B is the magnetic field strength perpendicular to the plane of the Hall bar. μ is the carrier mobility, n is the carrier concentration, e is the basic charge; V xy is the lateral Hall voltage, V xx is the longitudinal voltage, I is the longitudinal current. W is the width of the conductive channel (laterally), and L is the length of the conductive channel (longitudinally). Carrier concentration n=B / eR xy , the thickness of the two-dimensional conductive channel is not considered.

[0026] Carrier mobility µ = σ / ne = 1 / (neρ) = (V xy / V xx )*(L / BW).

[0027] Where σ is conductivity and ρ is resistivity. Hall sensitivity reflects the response ability of the Hall element to the magnetic field. S_A is the absolute Hall sensitivity, which indicates the transverse Hall voltage change caused by a unit magnetic field change, that is, V xy -BThe slope of the linear relationship.

[0028] Absolute Hall sensitivity: ; Hall sensitivity per unit current: ; Hall sensitivity per unit voltage: ; In constant current mode, V xy / I=B / ne; then S_I=V xy / BI=1 / ne, dimension is V / (AT); In constant voltage mode, µ=σ / ne=1 / (neρ)=(V xy / V xx )*(L / BW); then S_V=V xy / (BV xx )=µW / L, the dimension is V / (VT).

[0029] Gate regulation function: gate voltage V g The absolute value is positively correlated with the carrier concentration n and carrier mobility μ. g Or magnetic field B and other conditions for electrical transport measurement, using the above formula Hall sensitivity with gate voltage V g The change curve of n / μ-V g Relationships, such as Figure 3 By simply adjusting the carriers electrically, sensitivity switching under different working conditions can be achieved, such as Figure 4 As shown. Under the geometric conditions of the conductive channel of this embodiment, the length of the conductive channel is 195µm and the width is 35µm. Within the appropriate gate voltage range of the Hall element, the Hall sensitivity S_I under unit current can reach 3000~10000 V / (AT), and the Hall sensitivity S_V under unit voltage can reach 1~6 V / (VT), which means that the Hall element can be highly sensitive in both constant current mode and constant voltage mode, and the sensitivity variation range in a single mode is large, which can adapt to different application requirements.

[0030] Finally, it should be noted that the purpose of publishing the embodiments is to help further understand the present invention, but those skilled in the art can understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the contents disclosed in the embodiments, and the scope of protection claimed by the present invention shall be subject to the scope defined in the claims.

Claims

1. A gate-controlled Hall element based on silicon germanium quantum well, characterized in that: The gate-controlled Hall element comprises: a substrate, a buffer layer, a silicon-germanium quantum well structure, a source electrode, a drain electrode, a measuring electrode, an oxide insulating layer and a gate; wherein the buffer layer is formed on the substrate; and the silicon-germanium quantum well structure is formed on the buffer layer; The silicon germanium quantum well structure includes, from bottom to top, a first barrier layer, a potential well layer, a second barrier layer and a cap layer; the materials of the first barrier layer and the second barrier layer are silicon germanium compounds, and the material of the potential well layer is germanium. Through the limitation of the potential well layer and the material properties of germanium, holes with high mobility are formed in the potential well layer as carriers; a conductive channel is defined in the potential well layer, and a source electrode, a drain electrode and two pairs of measuring electrodes are arranged around the conductive channel. The source electrode and the drain electrode are respectively located at the two ends of the conductive channel in the longitudinal direction, and the two pairs of measuring electrodes are respectively located at the two sides of the conductive channel in the transverse direction. The source electrode, the drain electrode and the two pairs of measuring electrodes are respectively electrically connected to the conductive channel to form a bridge-type Hall bar structure; An oxide insulating layer is formed on the silicon germanium quantum well structure; a gate is formed on the oxide insulating layer, and the gate is located directly above the conductive channel; The source electrode and the drain electrode are connected to a constant voltage source in a constant voltage mode, or the source electrode and the drain electrode are connected to a constant current source in a constant current mode; two pairs of measuring electrodes are connected to an external measuring circuit; the gate is connected to a regulating voltage source; The measurement circuit measures the lateral Hall voltage to obtain external magnetic field information; the voltage source is regulated to change the gate voltage to improve the Hall sensitivity in different modes.

2. The gate-controlled Hall element according to claim 1, characterized in that: The materials of the first barrier layer and the second barrier layer are silicon germanium compound Si x Ge 1-x , x is the composition of silicon in the first barrier layer and the second barrier layer; the composition x of silicon in the first barrier layer and the second barrier layer is 0.1~0.

3.

3. The gate-controlled Hall element according to claim 2, characterized in that: The buffer layer includes a component-free buffer layer and a component-gradient buffer layer. The material of the component-free buffer layer is germanium, and the material of the component-gradient buffer layer is silicon-germanium compound Si z Ge 1-z , z is the composition of silicon in the composition-gradient buffer layer, 0≤z≤x; the composition of silicon in the composition-gradient buffer layer gradually changes from 0 to x from bottom to top, and the lattice constant gradually transitions from the strain-free buffer layer to the first barrier layer.

4. The gate-controlled Hall element according to claim 1, characterized in that: The thickness of the source electrode, the drain electrode and the measuring electrode is 50-100 nm.

5. The gate-controlled Hall element according to claim 1, characterized in that: The thickness of the oxide insulating layer is 20-80 nm.

6. The gate-controlled Hall element according to claim 1, characterized in that: The thickness of the gate is 150-300 nm.

7. A method for realizing a gate-controlled Hall element based on silicon germanium quantum well as claimed in claim 1, characterized in that: The implementation method comprises the following steps: 1) Gate-controlled Hall element connection: The source electrode and the drain electrode are connected to a constant voltage source in a constant current mode, or the source electrode and the drain electrode are connected to a constant current source in a constant voltage mode; two pairs of measuring electrodes are connected to an external measuring circuit; the gate is connected to a regulating voltage source; 2) Magnetic field measurement: a) inputting a constant voltage or a constant current from the source electrode and the drain electrode through a constant voltage source or a constant current source to generate a longitudinal current between the source electrode and the drain electrode; b) Apply a magnetic field perpendicular to the plane of the element. Under the influence of the external magnetic field, the holes are deflected and accumulated on both sides of the conductive channel controlled by the gate voltage applied by the gate, generating a lateral Hall voltage. c) Measuring the transverse Hall voltage through two pairs of measuring electrodes located on both sides of the conductive channel, thereby obtaining magnetic field information through the transverse Hall voltage; 3) Gate voltage regulation: High Hall sensitivity in different modes can be achieved by changing the gate voltage applied to the gate by a regulating voltage source.

8. The implementation method according to claim 7, characterized in that: Also included is a method for preparing a gate-controlled Hall element, comprising the following steps: a) forming a buffer layer on a substrate; b) forming a silicon germanium quantum well structure on the buffer layer: forming a first barrier layer, a potential well layer, a second barrier layer and a cap layer on the buffer layer from bottom to top; the first barrier layer and the second barrier layer are made of silicon germanium compounds, the potential well layer is made of germanium, holes are confined in the potential well layer, and the holes serve as carriers to form a two-dimensional hole gas; c) defining a conductive channel in the potential well layer, arranging a source electrode, a drain electrode and two pairs of measuring electrodes around the conductive channel, wherein the source electrode and the drain electrode are respectively located at two ends of the conductive channel in the longitudinal direction, and the two pairs of measuring electrodes are respectively located at two sides of the conductive channel in the transverse direction, and the source electrode, the drain electrode and the two pairs of measuring electrodes are respectively electrically connected to the conductive channel to form a bridge-type Hall bar structure; d) forming an oxide insulating layer on the silicon germanium quantum well structure; e) forming a gate on the oxide insulating layer, wherein the gate is located directly above the conductive channel.

9. The implementation method according to claim 7, characterized in that: In step 1), the length L is reduced by increasing the width W of the conductive channel, thereby providing high voltage sensitivity.

10. The implementation method according to claim 7, characterized in that: In step 3), gate voltage regulation includes: in constant current mode, reducing the gate voltage applied to the gate by regulating the voltage source to reduce the carrier concentration; or in constant voltage mode, increasing the gate voltage applied to the gate by regulating the voltage source to increase the carrier mobility, which can respectively achieve improved Hall sensitivity in constant current mode or constant voltage mode.

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