Driving circuit, display substrate and display device

Abstract

The invention provides a driving circuit, a display substrate and a display device. The driving circuit comprises an input circuit, a reset circuit, a first node reset circuit and a control node control circuit. The first node reset circuit controls the connection or disconnection between the first node and the first voltage line under the control of the potential of the second node; the control node control circuit controls the connection or disconnection between the control node and the third voltage line under the control of the potential of the first node; the ratio of the channel width-to-length ratio of a transistor of which the grid electrode is electrically connected with the second node included in the first node reset circuit to the channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24. Transistors included in all circuits can be reasonably arranged, electric leakage of the first node can be effectively prevented, the driving capacity of a display product is improved, noise of a control node is prevented from being introduced into the first node through electric leakage, the stability of the driving circuit is improved, and multi-output is prevented.

Description

Driving circuit, display substrate, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a display substrate, and a display device. Background Art

[0002] In recent years, as consumers' demands for display device resolution and refresh rates have steadily increased, the driving capabilities of display panels have also required corresponding upgrades, leading to the emergence of high-mobility oxide transistors. However, their electrical characteristics result in a threshold voltage that is more negative than that of traditional transistors. This means that some transistors in the driver circuit operate with a gate-source voltage of 0V for extended periods, increasing leakage current and power consumption. Furthermore, related technologies fail to rationally layout the transistors in the driver circuit, effectively preventing leakage at the first node and thus failing to improve the driving capabilities of display products. These driver circuits also fail to prevent noise from the control node from being introduced into the first node through leakage, failing to improve the stability of the driver circuit and failing to prevent multiple outputs.

[0003] Summary of the Invention

[0004] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising an input circuit, a reset circuit, a first node reset circuit, and a control node control circuit;

[0005] The input circuit is electrically connected to the input control terminal, the input terminal and the first node respectively, and is used to control the connection or disconnection between the input terminal and the first node under the control of the input control signal provided by the input control terminal;

[0006] The reset circuit is electrically connected to the reset terminal, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the reset signal provided by the reset terminal;

[0007] The first node reset circuit is electrically connected to the second node, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the potential of the second node;

[0008] The control node control circuit is electrically connected to the first node, the third voltage line and the control node respectively, and is used to control the connection or disconnection between the control node and the third voltage line under the control of the potential of the first node;

[0009] The transistor included in the input circuit, the transistor included in the reset circuit, and the transistor included in the first node reset circuit are arranged in sequence along a direction away from the display area;

[0010] A ratio of a channel width-to-length ratio of a transistor whose gate is electrically connected to the second node and included in the first node reset circuit to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0011] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a frame reset circuit;

[0012] The frame reset circuit is electrically connected to the frame reset line, the first node and the second voltage line respectively, and is used to control the connection or disconnection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset line;

[0013] The transistor included in the frame reset circuit is arranged on a side of the transistor included in the first node reset circuit away from the display area.

[0014] Optionally, the input circuit includes at least two input transistors connected in series, and the reset circuit includes at least two reset transistors connected in series.

[0015] Optionally, the first node reset circuit includes at least two transistors whose gates are electrically connected to the second node and connected in series; or,

[0016] The second node includes a first second node and a second second node; the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the first second node, and at least two transistors connected in series with their gates electrically connected to the second second node.

[0017] Optionally, the frame reset circuit includes at least two frame reset transistors connected in series.

[0018] Optionally, the transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit close to the display area.

[0019] Optionally, the control node control circuit includes a control transistor;

[0020] A gate of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node.

[0021] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a shutdown reset circuit;

[0022] The shutdown reset circuit is electrically connected to the fourth voltage line and the drive signal output end respectively, and is used to control the connection or disconnection between the drive signal output end and the fourth voltage line under the control of the fourth voltage signal provided by the fourth voltage line.

[0023] Optionally, the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area.

[0024] Optionally, the shutdown reset circuit includes a shutdown reset transistor;

[0025] The gate of the shutdown reset transistor and the first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and the second electrode of the shutdown reset transistor is electrically connected to the driving signal output end.

[0026] Optionally, the input circuit includes a first input transistor and a second input transistor;

[0027] The gate of the first input transistor is electrically connected to the input control terminal, the first electrode of the first input transistor is electrically connected to the input terminal, and the second electrode of the first input transistor is electrically connected to the control node;

[0028] A gate of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node.

[0029] Optionally, the input control terminal is a carry signal output terminal of an adjacent previous stage driving circuit, and the input terminal is a drive signal output terminal of an adjacent previous stage driving circuit; or,

[0030] The input control terminal and the input terminal are both carry signal output terminals of the adjacent upper-level driving circuit.

[0031] Optionally, the reset circuit includes a first reset transistor and a second reset transistor;

[0032] The gate of the first reset transistor is electrically connected to the reset terminal, the first electrode of the first reset transistor is electrically connected to the first node, and the second electrode of the first reset transistor is electrically connected to the control node;

[0033] A gate of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line.

[0034] Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit is smaller than the channel width-to-length ratio of the second reset transistor.

[0035] Optionally, the first node reset circuit includes a first pull-down transistor and a second pull-down transistor;

[0036] The gate of the first pull-down transistor is electrically connected to the second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;

[0037] A gate of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line.

[0038] Optionally, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0039] Optionally, a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.

[0040] Optionally, the second node includes a first second node and a second second node;

[0041] The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor;

[0042] The gate of the first pull-down transistor is electrically connected to the first second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;

[0043] The gate of the second pull-down transistor is electrically connected to the first second node, the first electrode of the second pull-down transistor is electrically connected to the control node, and the second electrode of the second pull-down transistor is electrically connected to the first voltage line;

[0044] The gate of the third pull-down transistor is electrically connected to the second second node, the first electrode of the third pull-down transistor is electrically connected to the first node, and the second electrode of the third pull-down transistor is electrically connected to the control node;

[0045] A gate of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line.

[0046] Optionally, the channel width-to-length ratio of the second pull-down transistor is greater than that of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is greater than that of the third pull-down transistor.

[0047] Optionally, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24;

[0048] A ratio of a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0049] Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor;

[0050] The gate of the first frame reset transistor is electrically connected to the frame reset line, the first electrode of the first frame reset transistor is electrically connected to the first node, and the second electrode of the first frame reset transistor is electrically connected to the control node;

[0051] A gate of the second frame reset transistor is electrically connected to the frame reset line, a first electrode of the second frame reset transistor is electrically connected to the control node, and a second electrode of the second frame reset transistor is electrically connected to the second voltage line.

[0052] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a carry signal output circuit, a driving signal output circuit, and an energy storage circuit;

[0053] The carry signal output circuit is electrically connected to the first node, the second node, the carry signal output terminal, the clock signal terminal, and the second voltage line, respectively, and is used to control the connection or disconnection between the carry signal output terminal and the clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the carry signal output terminal and the second voltage line under the control of the potential of the second node;

[0054] The drive signal output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the clock signal terminal and the fourth voltage line, respectively, and is used to control the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of the potential of the second node;

[0055] The energy storage circuit is electrically connected to the first node and the driving signal output terminal respectively, and is used for storing electric energy.

[0056] Optionally, the fourth voltage line is used to provide a fourth voltage signal, and the second voltage line is used to provide a second voltage signal;

[0057] The voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.

[0058] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a second node control circuit;

[0059] The second node control circuit is electrically connected to the input control terminal, the first node, the second node and the second voltage line, respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the input control signal provided by the input control terminal, and to control the potential of the second node under the control of the potential of the first node.

[0060] In a second aspect, an embodiment of the present disclosure provides a display substrate, comprising a base and the above-mentioned driving circuit disposed on the base.

[0061] Optionally, the display substrate according to at least one embodiment of the present disclosure further includes an electrostatic protection circuit provided on the base;

[0062] A first end of the electrostatic protection circuit is electrically connected to the drive signal line, and a second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal via a short-circuit line, and the electrostatic protection circuit is used for electrostatic protection;

[0063] The driving signal lines include a DC voltage line, a clock signal line, a control voltage line and a frame reset line.

[0064] Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor and a third protection transistor;

[0065] The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;

[0066] The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;

[0067] The gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the short-circuit line, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor;

[0068] The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor.

[0069] Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor;

[0070] The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;

[0071] The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;

[0072] A first electrode of the third protection transistor is electrically connected to the gate of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to the gate of the fourth protection transistor;

[0073] A first electrode of the fourth protection transistor is electrically connected to the gate of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to the gate of the fifth protection transistor;

[0074] The gate of the fifth protection transistor and the first electrode of the fifth protection transistor are both electrically connected to the short-circuit line, and the second electrode of the fifth protection transistor is electrically connected to the gate of the fourth protection transistor;

[0075] The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;

[0076] The channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;

[0077] The channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor.

[0078] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0079] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0080] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0081] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0082] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0083] FIG5 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0084] FIG6 is a waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG5 operates in the touch scanning phase SC;

[0085] 7 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG5 is in operation in a normal display state;

[0086] FIG8 is a simulated waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG5 is in operation during the touch stage;

[0087] FIG9 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG5 ;

[0088] FIG10 is a layout diagram of at least one embodiment of the driving circuit shown in FIG5 ;

[0089] FIG11 is a layout diagram of the gate metal layer in FIG10 ;

[0090] FIG12 is a layout diagram of the semiconductor layer in FIG10;

[0091] FIG13 is a layout diagram of the conductive layer in FIG10;

[0092] FIG14 is a layout diagram of the source / drain metal layer in FIG10 ;

[0093] FIG15 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0094] FIG16 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0095] FIG17 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0096] FIG18 is a circuit diagram of at least one embodiment of an electrostatic protection circuit;

[0097] FIG19 is a layout diagram of at least one embodiment of an electrostatic protection circuit;

[0098] FIG20 is a circuit diagram of at least one embodiment of an electrostatic protection circuit;

[0099] FIG. 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit. DETAILED DESCRIPTION

[0100] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0101] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0102] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0103] As shown in FIG1 , the driving circuit according to the embodiment of the present disclosure includes an input circuit 11 , a reset circuit 12 , a first node reset circuit 13 , and a control node control circuit 31 ;

[0104] The input circuit 11 is electrically connected to the input control terminal IK1, the input terminal I1 and the first node PU respectively, and is used to control the connection or disconnection between the input terminal I1 and the first node PU under the control of the input control signal provided by the input control terminal IK1;

[0105] The reset circuit 12 is electrically connected to the reset terminal R1, the first node PU and the first voltage line V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage line V1 under the control of the reset signal provided by the reset terminal R1;

[0106] The first node reset circuit 13 is electrically connected to the second node PD, the first node PU and the first voltage line V1 respectively, and is used to control the connection or disconnection between the first node PU and the first voltage line V1 under the control of the potential of the second node PD;

[0107] The control node control circuit 31 is electrically connected to the first node PU, the third voltage line V3 and the control node N0 respectively, and is used to control the connection or disconnection between the control node N0 and the third voltage line V3 under the control of the potential of the first node PU;

[0108] The transistors included in the input circuit 11, the transistors included in the reset circuit 12, and the transistors included in the first node reset circuit 13 are arranged in sequence in a direction away from the display area;

[0109] A ratio of a channel width-to-length ratio of a transistor whose gate is electrically connected to the second node and included in the first node reset circuit to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0110] Optionally, the first voltage line may be a first low voltage line or a second low voltage line, but is not limited thereto.

[0111] In specific implementation, the driving circuit described in the embodiment of the present disclosure may include an input circuit 11, a reset circuit 12 and a first node reset circuit 13. The input circuit 11 controls the connection or disconnection between the input terminal I1 and the first node PU under the control of the input control signal. The reset circuit 12 controls the connection or disconnection between the first node PU and the first voltage line V1 under the control of the reset signal. The first node reset circuit 13 controls the connection or disconnection between the first node PU and the first voltage line V1 under the control of the potential of the second node PD. The transistors included in the input circuit 11, the transistors included in the reset circuit 12 and the transistors included in the first node reset circuit 13 can be arranged in sequence along the direction away from the display area to reasonably layout the transistors included in each circuit and make good use of the horizontal space of the frame of the display substrate.

[0112] Optionally, the third voltage line may be a high voltage line.

[0113] The driving circuit described in at least one embodiment of the present disclosure is additionally provided with a control node control circuit 31. When the potential of the first node PU is a high voltage, the potential of the control node N0 is charged to a high voltage. At this time, the leakage path of the first node PU is from PU to N0, so as to effectively prevent the leakage of the first node PU and enhance the driving capability of the display product.

[0114] In a specific implementation, the ratio of the channel width-to-length ratio of the transistor whose gate is included in the first node reset circuit and is electrically connected to the second node and the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.

[0115] Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit can be 5 / 12, the channel width-to-length ratio of the transistor included in the first node reset circuit and electrically connected to the second node can be 30 / 6, and the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the transistor included in the first node reset circuit and electrically connected to the second node is 1:12, but is not limited to this.

[0116] In at least one embodiment of the present disclosure, the input circuit can be electrically connected to the input control terminal IK1 and the input terminal I1 respectively, and is used to control the connection or disconnection between the input terminal I1 and the first node PU under the control of the input control signal provided by the input control terminal IK1.

[0117] In a specific implementation, the input control terminal IK1 and the input terminal I1 may be different signal terminals, which are connected to different signals respectively; or,

[0118] The input control terminal IK1 and the input terminal I1 may also be the same signal terminal, receiving the same signal.

[0119] In at least one embodiment of the present disclosure, the input circuit includes at least two input transistors connected in series, and the reset circuit includes at least two reset transistors connected in series.

[0120] In a specific implementation, the input circuit may include at least two transistors whose gates are electrically connected to the input control terminal in series, and the reset circuit may include at least two transistors whose gates are electrically connected to the reset terminal in series, so as to replace the transistor whose first pole or second pole is electrically connected to the first node with at least two transistors connected in series, so as to reduce the leakage current of the first node and improve the stability of the driving circuit.

[0121] In at least one embodiment of the present disclosure, the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the second node; or

[0122] The second node includes a first second node and a second second node; the first node reset circuit includes two transistors connected in series with their gates electrically connected to the first second node, and at least two transistors connected in series with their gates electrically connected to the second second node.

[0123] In a specific implementation, when the driving circuit adopts a second node, the first node reset circuit may include at least two transistors whose gates are electrically connected to the second node;

[0124] When the driving circuit uses two second nodes, the first node reset circuit may include two transistors connected in series with their gates electrically connected to the first second node, and at least two transistors connected in series with their gates electrically connected to the second second node;

[0125] In at least one embodiment of the present disclosure, the transistor electrically connected to the first electrode or the second electrode and the first node is replaced by at least two transistors connected in series, so as to reduce leakage current of the first node and improve the stability of the driving circuit.

[0126] As shown in FIG2 , based on the embodiment of the driving circuit shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure further includes a frame reset circuit 21 ;

[0127] The frame reset circuit 21 is electrically connected to the frame reset line STV0, the first node PU and the second voltage line V2, respectively, and is used to control the connection or disconnection between the first node PU and the second voltage line V2 under the control of the frame reset signal provided by the frame reset line STV0;

[0128] The transistor included in the frame reset circuit 21 is arranged on a side of the transistor included in the first node reset circuit 13 away from the display area.

[0129] Optionally, the second voltage line may be a second low voltage line, but is not limited thereto.

[0130] In a specific implementation, the driving circuit described in at least one embodiment of the present disclosure may further include a frame reset circuit 21, which controls the resetting of the potential of the first node PU under the control of a frame reset signal during a blank period between two frames of display time; the transistor included in the frame reset circuit 21 is arranged on the side of the transistor included in the first node reset circuit 13 away from the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the border of the display substrate.

[0131] Optionally, the frame reset circuit includes at least two frame reset transistors connected in series.

[0132] In at least one embodiment of the present disclosure, the frame reset circuit may include at least two transistors whose gates are electrically connected to the frame reset line in series. At least one embodiment of the present disclosure changes the transistor whose first electrode or second electrode is electrically connected to the first node into at least two transistors connected in series to reduce the leakage current of the first node and improve the stability of the driving circuit.

[0133] In at least one embodiment of the present disclosure, the transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit that is close to the display area.

[0134] In a specific implementation, the transistors included in the control node control circuit can be arranged on a side of the transistors included in the input circuit close to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the lateral space of the frame of the display substrate.

[0135] Optionally, the control node control circuit includes a control transistor;

[0136] A gate of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node.

[0137] The driving circuit according to at least one embodiment of the present disclosure further includes a shutdown reset circuit;

[0138] The shutdown reset circuit is electrically connected to the fourth voltage line and the drive signal output end respectively, and is used to control the connection or disconnection between the drive signal output end and the fourth voltage line under the control of the fourth voltage signal provided by the fourth voltage line.

[0139] Optionally, the fourth voltage line may be a first low voltage line.

[0140] In a specific implementation, the driving circuit may further include a shutdown reset circuit, which controls the connection or disconnection between the driving signal output terminal and the fourth voltage line under the control of a fourth voltage signal.

[0141] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure further includes a shutdown reset circuit 41 ;

[0142] The shutdown reset circuit 41 is electrically connected to the fourth voltage line V4 and the drive signal output terminal GT respectively, and is used to control the connection or disconnection between the drive signal output terminal GT and the fourth voltage line V4 under the control of the fourth voltage signal provided by the fourth voltage line V4.

[0143] In at least one embodiment of the present disclosure, when the transistor included in the shutdown reset circuit 41 is an n-type transistor, when the display panel displays normally, the fourth voltage line V4 provides a low voltage signal, and when the display panel is ready to shut down, the voltage signal provided by the fourth voltage line V4 has a high voltage. Under the control of the fourth voltage signal, the shutdown reset circuit 41 controls the connection between the drive signal output terminal GT and the fourth voltage line V4, so that the drive signal output terminal GT outputs a high voltage signal, which can release the residual charge in the pixel, effectively improve the turn-on ability of the drive signal output terminal GT, and avoid poor afterimage.

[0144] In the related art, when the display panel is turned off, the potential of the voltage signal provided by each DC voltage line is pulled up to a high level, and the fourth voltage line V4 inputs the high voltage signal to the AA area (effective display area) through the output reset transistor included in the drive circuit to complete the pixel discharge. However, due to the reliability of the display product, the drift output capability of the output reset transistor decreases, resulting in insufficient gate line opening and incomplete pixel charge release, forming an afterimage. Based on this, at least one embodiment of the present disclosure controls the drive signal output terminal GT to output a high voltage signal under the control of the fourth voltage signal when the display panel is turned off to release the residual charge in the pixel, which can effectively improve the opening capability of the drive signal output terminal GT and avoid poor afterimage.

[0145] In at least one embodiment of the present disclosure, the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area.

[0146] In a specific implementation, the transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area, so as to reasonably arrange the transistors included in each circuit and make good use of the horizontal space of the frame of the display substrate.

[0147] Optionally, the shutdown reset circuit includes a shutdown reset transistor;

[0148] The gate of the shutdown reset transistor and the first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and the second electrode of the shutdown reset transistor is electrically connected to the driving signal output end.

[0149] Optionally, the input circuit includes a first input transistor and a second input transistor;

[0150] The gate of the first input transistor is electrically connected to the input control terminal, the first electrode of the first input transistor is electrically connected to the input terminal, and the second electrode of the first input transistor is electrically connected to the control node;

[0151] A gate of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node.

[0152] In at least one embodiment of the present disclosure, the input control terminal is a carry signal output terminal of an adjacent previous stage driving circuit, and the input terminal is a drive signal output terminal of an adjacent previous stage driving circuit; or,

[0153] The input control terminal and the input terminal are both carry signal output terminals of the adjacent upper-level driving circuit.

[0154] In a specific implementation, the input control terminal can be the carry signal output terminal of the adjacent previous level driving circuit, and the input terminal can be the drive signal output terminal of the adjacent previous level driving circuit; or, the input control terminal and the input terminal can both be the carry signal output terminal of the adjacent previous level driving circuit.

[0155] Optionally, the reset circuit includes a first reset transistor and a second reset transistor;

[0156] The gate of the first reset transistor is electrically connected to the reset terminal, the first electrode of the first reset transistor is electrically connected to the first node, and the second electrode of the first reset transistor is electrically connected to the control node;

[0157] A gate of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line.

[0158] In at least one embodiment of the present disclosure, the control node control circuit includes a transistor having a channel width-to-length ratio that is smaller than a channel width-to-length ratio of the second reset transistor.

[0159] During specific implementation, the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second reset transistor can be adjusted. When the reset signal provided by the reset end arrives, the competitiveness of the second reset transistor is improved, so that the potential of the control node and the potential of the first node are quickly reduced to a low voltage, ensuring that the potential of the second node can be synchronously increased to a high voltage to start noise reduction.

[0160] For example, the channel width-to-length ratio of the transistor included in the control node control circuit may be 5 / 12, and the channel width-to-length ratio of the second reset transistor may be 5 / 6, but is not limited thereto.

[0161] Optionally, the first node reset circuit includes a first pull-down transistor and a second pull-down transistor;

[0162] The gate of the first pull-down transistor is electrically connected to the second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;

[0163] A gate of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line.

[0164] In at least one embodiment of the present disclosure, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

[0165] In a specific implementation, the ratio of the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.

[0166] Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit can be 5 / 12, the channel width-to-length ratio of the second pull-down transistor can be 30 / 6, and the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second pull-down transistor is 1:12, but is not limited to this.

[0167] Optionally, a channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.

[0168] In a specific implementation, the channel width-to-length ratio of the second pull-down transistor can be greater than the channel width-to-length ratio of the first pull-down transistor. By adjusting the channel width-to-length ratio of the first pull-down transistor and the channel width-to-length ratio of the second pull-down transistor, noise of the control node can be prevented from being introduced into the first node through leakage, thereby improving the stability of the drive circuit and preventing multiple outputs.

[0169] For example, the channel width-to-length ratio of the first pull-down transistor may be 15 / 6, and the channel width-to-length ratio of the second pull-down transistor may be 30 / 6, but the present invention is not limited thereto.

[0170] Optionally, the second node includes a first second node and a second second node;

[0171] The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor, and a fourth pull-down transistor;

[0172] The gate of the first pull-down transistor is electrically connected to the first second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node;

[0173] The gate of the second pull-down transistor is electrically connected to the first second node, the first electrode of the second pull-down transistor is electrically connected to the control node, and the second electrode of the second pull-down transistor is electrically connected to the first voltage line;

[0174] The gate of the third pull-down transistor is electrically connected to the second second node, the first electrode of the third pull-down transistor is electrically connected to the first node, and the second electrode of the third pull-down transistor is electrically connected to the control node;

[0175] A gate of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line.

[0176] In at least one embodiment of the present disclosure, the channel width-to-length ratio of the second pull-down transistor is greater than that of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is greater than that of the third pull-down transistor.

[0177] In at least one embodiment of the present disclosure, the channel width-to-length ratio of the second pull-down transistor is greater than that of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor is greater than that of the third pull-down transistor.

[0178] In a specific implementation, the channel width-to-length ratio of the second pull-down transistor can be greater than the channel width-to-length ratio of the first pull-down transistor, and the channel width-to-length ratio of the fourth pull-down transistor can be greater than the channel width-to-length ratio of the third pull-down transistor. By setting as above, noise of the control node can be prevented from being introduced into the first node through leakage, thereby improving the stability of the drive circuit and preventing multiple outputs.

[0179] For example, the channel width-to-length ratio of the first pull-down transistor and the channel width-to-length ratio of the third pull-down transistor may be 15 / 6, and the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor may be 30 / 6, but is not limited thereto.

[0180] Optionally, a ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24;

[0181] A ratio of a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of the control transistor is greater than or equal to 6 and less than or equal to 24.

[0182] In a specific implementation, the ratio of the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted, and the ratio of the channel width-to-length ratio of the fourth pull-down transistor and the channel width-to-length ratio of the transistor included in the control node control circuit can be adjusted to prevent the noise of the control node from being introduced into the first node through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.

[0183] Optionally, the channel width-to-length ratio of the transistor included in the control node control circuit may be 5 / 12, the channel width-to-length ratio of the second pull-down transistor and the channel width-to-length ratio of the fourth pull-down transistor may be 30 / 6, the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the second pull-down transistor is 1:12, and the ratio between the channel width-to-length ratio of the transistor included in the control node control circuit and the channel width-to-length ratio of the fourth pull-down transistor is 1:12, but is not limited to this.

[0184] Optionally, the frame reset circuit includes a first frame reset transistor and a second frame reset transistor;

[0185] The gate of the first frame reset transistor is electrically connected to the frame reset line, the first electrode of the first frame reset transistor is electrically connected to the first node, and the second electrode of the first frame reset transistor is electrically connected to the control node;

[0186] A gate of the second frame reset transistor is electrically connected to the frame reset line, a first electrode of the second frame reset transistor is electrically connected to the control node, and a second electrode of the second frame reset transistor is electrically connected to the second voltage line.

[0187] In at least one embodiment of the present disclosure, a frame reset circuit electrically connected to the first node may be configured to include a first frame reset transistor and a second frame reset transistor connected in series to reduce leakage of the first node.

[0188] The driving circuit according to at least one embodiment of the present disclosure further includes a carry signal output circuit, a driving signal output circuit and an energy storage circuit;

[0189] The carry signal output circuit is electrically connected to the first node, the second node, the carry signal output terminal, the clock signal terminal, and the second voltage line, respectively, and is used to control the connection or disconnection between the carry signal output terminal and the clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the carry signal output terminal and the second voltage line under the control of the potential of the second node;

[0190] The drive signal output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the clock signal terminal and the fourth voltage line, respectively, and is used to control the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and to control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of the potential of the second node;

[0191] The energy storage circuit is electrically connected to the first node and the driving signal output terminal respectively, and is used for storing electric energy.

[0192] Optionally, the second voltage line may be a second low voltage line, and the fourth voltage line may be a first low voltage line.

[0193] In at least one embodiment of the present disclosure, the fourth voltage line is used to provide a fourth voltage signal, and the second voltage line is used to provide a second voltage signal;

[0194] The voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.

[0195] In a specific implementation, the drive circuit may further include a carry signal output circuit and a drive signal output circuit, wherein the carry signal output circuit controls the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the third voltage line under the control of the potential of the second node; the drive signal output circuit controls the connection or disconnection between the drive signal output terminal and the clock signal terminal under the control of the potential of the first node, and controls the connection or disconnection between the drive signal output terminal and the third voltage line under the control of the potential of the second node.

[0196] In a specific implementation, the voltage value of the second voltage signal can be less than the voltage value of the fourth voltage signal. When the input control terminal is the carry signal output terminal of the adjacent previous-level driving circuit and the input terminal is the drive signal output terminal of the adjacent previous-level driving circuit, the gate-source voltage of the transistor used for input is less than 0V, the working state of the transistor used for input changes from the subthreshold region to the off state, and the leakage is reduced when the potential of the first node is raised in the second order.

[0197] The driving circuit according to at least one embodiment of the present disclosure further includes a second node control circuit;

[0198] The second node control circuit is electrically connected to the input control terminal, the first node, the second node and the second voltage line, respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the input control signal provided by the input control terminal, and to control the potential of the second node under the control of the potential of the first node.

[0199] In a specific implementation, the driving circuit may include a second node control circuit, which controls the connection or disconnection between the second node and the fourth voltage line under the control of an input control signal, and controls the potential of the second node under the control of the potential of the first node.

[0200] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure includes a first second node PD1, a second second node PD2, a second node control circuit 43, a tank circuit 40, a carry signal output circuit 44, and a driving signal output circuit 45;

[0201] The first node reset circuit 13 is electrically connected to the first second node PD1, the second second node PD2, the first node PU, and the first voltage line V1, respectively, and is configured to control the connection between the first node PU and the first voltage line V1 under the control of the potential of the first second node PD1, and to control the connection between the first node PU and the first voltage line V1 under the control of the potential of the second second node PD2;

[0202] The second node control circuit 43 is electrically connected to the input control terminal IK1, the first node PU, the first second node PD1, the second second node PD2, and the second voltage line V2, respectively, and is configured to control the connection between the first second node PD1 and the second voltage line V2, and the connection between the second second node PD2 and the second voltage line V2, under the control of the input control signal provided by the input control terminal IK1, and to control the potential of the first second node PD1 and the potential of the second second node PD2 under the control of the potential of the first node PU;

[0203] The first end of the energy storage circuit 40 is electrically connected to the first node PU, and the second end of the energy storage circuit 40 is electrically connected to the driving signal output terminal GT. The energy storage circuit 40 is used to store electrical energy;

[0204] The carry signal output circuit 44 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the carry signal output terminal OC, the clock signal terminal CLK, and the second voltage line V2, respectively, and is used to control the communication between the carry signal output terminal OC and the clock signal terminal CLK under the control of the potential of the first node PU, control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the first second node PD1, and control the communication between the carry signal output terminal OC and the second voltage line V2 under the control of the potential of the second second node PD2;

[0205] The drive signal output circuit 45 is electrically connected to the first node PU, the first second node PD1, the second second node PD2, the drive signal output terminal GT, the clock signal terminal CLK and the fourth voltage line V4, respectively, and is used to control the connection between the drive signal output terminal GT and the clock signal terminal CLK under the control of the potential of the first node PU, control the connection between the drive signal output terminal GT and the fourth voltage line V4 under the control of the potential of the first second node PD1, and control the connection between the drive signal output terminal GT and the fourth voltage line V4 under the control of the potential of the second second node PD2.

[0206] As shown in FIG5 , based on at least one embodiment of the driving circuit shown in FIG4 ,

[0207] The shutdown reset circuit includes a shutdown reset transistor M14;

[0208] The gate of the shutdown reset transistor M14 and the source of the shutdown reset transistor M14 are electrically connected to the first low voltage line VGL, and the drain of the shutdown reset transistor M14 is electrically connected to the driving signal output terminal GT;

[0209] The control node control circuit includes a control transistor M0;

[0210] The gate of the control transistor M0 is electrically connected to the first node PU, the source of the control transistor M0 is electrically connected to the high voltage line VGH, and the drain of the control transistor M0 is electrically connected to the control node N0;

[0211] The input circuit includes a first input transistor M1A and a second input transistor M1B;

[0212] The gate of the first input transistor M1A is electrically connected to the input control terminal IK1, the source of the first input transistor M1A is electrically connected to the input terminal I0, and the drain of the first input transistor M1A is electrically connected to the control node N0;

[0213] The gate of the second input transistor M1B is electrically connected to the input control terminal IK1, the source of the second input transistor M1B is electrically connected to the control node N0, and the drain of the second input transistor M1B is electrically connected to the first node PU;

[0214] The reset circuit includes a first reset transistor M2A and a second reset transistor M2B;

[0215] The gate of the first reset transistor M2A is electrically connected to the reset terminal R1, the source of the first reset transistor M2A is electrically connected to the first node PU, and the drain of the first reset transistor M2A is electrically connected to the control node N0;

[0216] The gate of the second reset transistor M2B is electrically connected to the reset terminal R1, the source of the second reset transistor M2B is electrically connected to the control node N0, and the drain of the second reset transistor M2B is electrically connected to the first low voltage line VGL;

[0217] The first node reset circuit includes a first pull-down transistor M8A, a second pull-down transistor M8C, a third pull-down transistor M8B and a fourth pull-down transistor M8D;

[0218] The gate of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain of the first pull-down transistor M8A is electrically connected to the control node N0;

[0219] The gate of the second pull-down transistor M8C is electrically connected to the first second node PD1, the source of the second pull-down transistor M8C is electrically connected to the control node N0, and the drain of the second pull-down transistor M8C is electrically connected to the first low voltage line VGL;

[0220] The gate of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain of the third pull-down transistor M8B is electrically connected to the control node N0;

[0221] The gate of the fourth pull-down transistor M8D is electrically connected to the second second node PD2, the source of the fourth pull-down transistor M8D is electrically connected to the control node N0, and the drain of the fourth pull-down transistor M8D is electrically connected to the first low voltage line VGL;

[0222] The frame reset circuit includes a first frame reset transistor M15A and a second frame reset transistor M15B;

[0223] The gate of the first frame reset transistor M15A is electrically connected to the frame reset line STV0, the source of the first frame reset transistor M15A is electrically connected to the first node PU, and the drain of the first frame reset transistor M15A is electrically connected to the control node N0;

[0224] The gate of the second frame reset transistor M15B is electrically connected to the frame reset line STV0, the source of the second frame reset transistor M15B is electrically connected to the control node N0, and the drain of the second frame reset transistor M15B is electrically connected to the second low voltage line LVGL;

[0225] The second node control circuit includes a first control transistor M5A, a second control transistor M6A, a third control transistor M16A, a fourth control transistor M5B, a fifth control transistor M6B and a sixth control transistor M16B;

[0226] The gate of the first control transistor M5A and the source of the first control transistor M5A are both electrically connected to the first control voltage line VDDO, and the drain of the first control transistor M5A is electrically connected to the first second node PD1;

[0227] The gate of the second control transistor M6A is electrically connected to the first node PU, the source of the second control transistor M6A is electrically connected to the first second node PD1, and the drain of the second control transistor M6A is electrically connected to the second low voltage line LVGL;

[0228] The gate of the third control transistor M16A is electrically connected to the input control terminal IK1, the source of the third control transistor M16A is electrically connected to the first second node PD1, and the drain of the third control transistor M16A is electrically connected to the second low voltage line LVGL;

[0229] The gate of the fourth control transistor M5B and the source of the second control transistor M5B are both electrically connected to the second control voltage line VDDE, and the drain of the second control transistor M5B is electrically connected to the second second node PD2;

[0230] The gate of the fifth control transistor M6B is electrically connected to the first node PU, the source of the fifth control transistor M6B is electrically connected to the second second node PD2, and the drain of the fifth control transistor M6B is electrically connected to the second low voltage line LVGL;

[0231] The gate of the sixth control transistor M16B is electrically connected to the input control terminal IK1, the source of the sixth control transistor M16B is electrically connected to the second second node PD2, and the drain of the sixth control transistor M16B is electrically connected to the second low voltage line LVGL;

[0232] The energy storage circuit includes a storage capacitor C0;

[0233] The first electrode plate of C0 is electrically connected to the first node PU, and the second electrode plate of C0 is electrically connected to the driving signal output terminal GT;

[0234] The carry signal output circuit includes a carry output transistor M11, a first carry reset transistor M12A and a second carry reset transistor M12B, and the drive signal output circuit includes a drive output transistor M3, a first drive reset transistor M13A, a second drive reset transistor M13B and an output reset transistor M4;

[0235] The gate of the carry output transistor M11 is electrically connected to the first node PU, the source of the carry output transistor M11 is electrically connected to the clock signal terminal CLK, and the drain of the carry output transistor M11 is electrically connected to the carry signal output terminal OC;

[0236] The gate of the first carry reset transistor M12A is electrically connected to the first second node PD1, the source of the first carry reset transistor M12A is electrically connected to the carry signal output terminal OC, and the drain of the first carry reset transistor M12A is electrically connected to the second low voltage line LVGL;

[0237] The gate of the second carry reset transistor M12B is electrically connected to the second second node PD2, the source of the second carry reset transistor M12B is electrically connected to the carry signal output terminal OC, and the drain of the second carry reset transistor M12B is electrically connected to the second low voltage line LVGL;

[0238] The gate of the driving output transistor M3 is electrically connected to the first node PU, the source of the driving output transistor M3 is electrically connected to the clock signal terminal CLK, and the drain of the driving output transistor M3 is electrically connected to the driving signal output terminal GT;

[0239] The gate of the first driving reset transistor M13A is electrically connected to the first second node PD1, the source of the first driving reset transistor M13A is electrically connected to the driving signal output terminal GT, and the drain of the first driving reset transistor M13A is electrically connected to the first low voltage line VGL;

[0240] The gate of the second driving reset transistor M13B is electrically connected to the second second node PD2, the source of the second driving reset transistor M13B is electrically connected to the driving signal output terminal GT, and the drain of the second driving reset transistor M13B is electrically connected to the first low voltage line VGL;

[0241] The gate of the output reset transistor M4 is electrically connected to the reset control signal terminal R0 , the source of the output reset transistor M4 is electrically connected to the drive signal output terminal GT, and the drain of the output reset transistor M4 is electrically connected to the first low voltage line VGL.

[0242] The input control terminal IK1 is the carry signal output terminal of the adjacent previous stage driving circuit, and the input terminal I0 is the drive signal output terminal of the adjacent previous stage driving circuit;

[0243] In at least one embodiment of the driving circuit shown in FIG. 5 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0244] In at least one embodiment of the driving circuit shown in FIG5 , a control transistor M0 is used to control the potential of the control node N0. When the potential of the first node PU is high, the potential of the control node N0 is charged to a high voltage. At this time, the leakage path of the first node PU is from PU to N0, thereby effectively preventing leakage of the first node PU and improving the driving capability of the display product.

[0245] The drain of the first input transistor M1A is electrically connected to the control node N0; the source of the second input transistor M1B is electrically connected to the control node N0; the drain of the first reset transistor M2A is electrically connected to the control node N0; the source of the second reset transistor M2B is electrically connected to the control node N0; the drain of the first pull-down transistor M8A is electrically connected to the control node N0; the source of the second pull-down transistor M8C is electrically connected to the control node N0; the drain of the third pull-down transistor M8B is electrically connected to the control node N0; the source of the fourth pull-down transistor M8D is electrically connected to the control node N0; the drain of the first frame reset transistor M15A is electrically connected to the control node N0; the source of the second frame reset transistor M15B is electrically connected to the control node N0; at least one embodiment of the present disclosure sets the transistor whose source or drain is electrically connected to the first node PU to be two transistors connected in series to reduce the leakage current of the first node PU.

[0246] In at least one embodiment of the driving circuit shown in Figure 5, M0, M2B, M8C, M8D, M15B, M16A and M16B together constitute a PU voltage ensuring unit; when I1 provides a high voltage signal to charge the first node PU of the driving circuit at this level, M16A and M16B are turned on, and the potential of PD1 and the potential of PD2 are quickly pulled down, M8A, M8B, M8C and M8D are turned off, and at the same time the potential of PU rises, M0 is turned on, and the potential of N0 is charged to a high voltage. At this time, the leakage path of PU is PU-N0, and the drain-source voltage of M1A, the drain-source voltage of M2A, the drain-source voltage of M8A, the drain-source voltage of M8B and the drain-source voltage of M15A are greatly reduced, close to 0V or equal to 0V, effectively preventing leakage of the first node PU and improving the driving capability of the display product. At the same time, the channel width-to-length ratio of M0 and the channel width-to-length ratio of M2B are adjusted. When the reset signal arrives, the competitiveness of M2B is improved, so that the potential of N0 and the voltage of the first node PU are quickly pulled down, ensuring that the potential of the pull-down node can be synchronously increased to a high voltage, and the driving signal and carry signal are started to be noise-reduced. Adjust the channel width-to-length ratio of M0, the channel width-to-length ratio of M8C, and the channel width-to-length ratio of M8D so that the ratio of the channel width-to-length ratio of M0 to the channel width-to-length ratio of M8C is 1 / 12, and the ratio of the channel width-to-length ratio of M0 to the channel width-to-length ratio of M8D is 1 / 12. Adjust the channel width-to-length ratio of M8A, the channel width-to-length ratio of M8B, the channel width-to-length ratio of M8C, and the channel width-to-length ratio of M8D, and set the ratio between the channel width-to-length ratio of M8A and the channel width-to-length ratio of M8C to 1 / 2, and set the ratio between the channel width-to-length ratio of M8B and the channel width-to-length ratio of M8D to 1 / 2, so as to prevent the noise of the control node N0 from being introduced into the first node PU through leakage, thereby improving the stability of the driving circuit and preventing multiple outputs.

[0247] In at least one embodiment of the driving circuit shown in FIG5 , the channel width-to-length ratio of M0 may be 5 / 12, the channel width-to-length ratio of M2B may be 5 / 6, the channel width-to-length ratio of M8C may be 30 / 6, the channel width-to-length ratio of M8D may be 30 / 6, and the channel width-to-length ratios of M8A and M8B may be 15 / 6.

[0248] In at least one embodiment of the driving circuit shown in FIG5 , the drain of the first carry reset transistor M12A is electrically connected to the second low voltage line LVGL; the drain of the second carry reset transistor M12B is electrically connected to the second low voltage line LVGL; the drain of the first drive reset transistor M13A is electrically connected to the first low voltage line VGL; the drain of the second drive reset transistor M13B is electrically connected to the first low voltage line VGL;

[0249] The first low-voltage line VGL is used to provide a first low-voltage signal, and the second low-voltage line LVGL is used to provide a second low-voltage signal; the voltage value of the second low-voltage signal can be lower than the voltage value of the first low-voltage signal. When the input control terminal is the carry signal output terminal of the adjacent previous-level driving circuit and the input terminal is the driving signal output terminal of the adjacent previous-level driving circuit, the gate-source voltage of M1A and the voltage of M1B are lower than 0V, the working state of M1A and the working state of M1B change from the subthreshold region to the off state, and the leakage is reduced when the potential of the first node PU is raised in the second order.

[0250] In at least one embodiment of the driving circuit shown in Figure 5, the drain of M2B is electrically connected to the first low voltage line VGL, the voltage value of the second low voltage signal provided by the second low voltage line is less than the voltage value of the first low voltage signal provided by the first low voltage line, the gate-source voltage of M2B, the gate-source voltage of M8C, and the gate-source voltage of M8D are all less than 0V. At this time, the working state of M2B, the working state of M8C, and the working state of M8D change from the subthreshold region to the off state, and the leakage current is greatly reduced.

[0251] As shown in FIG6 , when at least one embodiment of the driving circuit shown in FIG5 operates in the touch scanning stage SC, the potential of the first node PU can be maintained at a high voltage due to the small leakage current of the first node PU.

[0252] In at least one embodiment of the driving circuit shown in FIG5 , by setting M14,

[0253] When the display panel is displaying normally, the first low-voltage line VGL provides a low-voltage signal. When the display panel is ready to shut down, the voltage signal provided by the first low-voltage line LVGL has a high voltage level, M14 is turned on, and the drive signal output terminal GT is controlled to output a high-voltage signal, which can release the residual charge in the pixel and effectively improve the turn-on ability of the drive signal output terminal GT to avoid poor afterimages.

[0254] 7 is a simulation waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG5 is in operation in a normal display state;

[0255] FIG8 is a simulated waveform diagram of the potential of the first node PU when at least one embodiment of the driving circuit shown in FIG5 is in operation during the touch stage. At this time, the highest potential of PU may be around 16.95V.

[0256] FIG. 9 is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG. 5 .

[0257] In at least one embodiment of the driving circuit shown in FIG5 , the channel width-to-length ratio of M14 can be selected based on actual conditions. The channel width-to-length ratio of M14 is usually close to that of M4, ensuring that when the display panel is ready to shut down, the potential of the driving signal provided by GT can be sufficiently and quickly pulled up to a high level.

[0258] When at least one embodiment of the driving circuit shown in FIG. 5 of the present disclosure is in operation, the first control voltage provided by VDDO and the second control voltage provided by VDDE may be square wave signals, and the first control voltage and the second control voltage are in opposite phases to each other, so that PD1 and PD2 work alternately.

[0259] FIG. 10 is a layout diagram of at least one embodiment of the driving circuit shown in FIG. 5 , wherein the driving circuit is disposed on a substrate.

[0260] 11 is a layout diagram of the gate metal layer in FIG10 , FIG12 is a layout diagram of the semiconductor layer in FIG10 , FIG13 is a layout diagram of the conductive layer in FIG10 , and FIG14 is a layout diagram of the source / drain metal layer in FIG10 .

[0261] As shown in FIG10 , CLKA is a first clock signal line, CLKB is a second clock signal line, CLKC is a third clock signal line, CLKD is a fourth clock signal line, STV is a start voltage line, VDDO is a first control voltage line, VDDE is a second control voltage line, STV0 is a frame reset line, LVGL is a second low voltage line, VGL1 is a first low voltage line, VGL2 is a second first low voltage line, and VGH is a high voltage line.

[0262] CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL, and VGL1 extend in a vertical direction;

[0263] CLKA, CLKB, CLKC, CLKD, STV, VDDO, VDDE, STV0, LVGL, and VGL1 are arranged on a side of the driving circuit away from the display area;

[0264] VGL2 and VGH extend in the vertical direction;

[0265] VGL2 and VGH are arranged on a side of the driving circuit close to the display area.

[0266] As shown in FIG10 to FIG14 , the transistors included in the input circuit, the transistors included in the reset circuit, and the transistors included in the first node reset circuit are sequentially arranged in a direction away from the display area;

[0267] M14 is arranged on a side of M0 away from the display area, and M0 is arranged on a side of M1A and M1B away from the display area;

[0268] The orthographic projection of the active pattern of M11 on the substrate, the orthographic projection of the first electrode plate of C0 on the substrate, and the orthographic projection of the active pattern of M1A on the substrate are arranged in sequence along the vertical direction; the orthographic projection of the active pattern of M11 on the substrate, the orthographic projection of the first electrode plate of C0 on the substrate, and the orthographic projection of the active pattern of M1B on the substrate are arranged in sequence along the vertical direction; M11, C0, M1A, and M1B are arranged in a longitudinal space to facilitate the realization of a narrow frame;

[0269] M1A and M1B are arranged side by side, M1A and M1B are arranged in a horizontal direction, and M1B is arranged on a side of M1A away from the display area;

[0270] M14 and M4 are arranged in sequence along the vertical direction to utilize the longitudinal space to layout M14 and M4, which is conducive to achieving a narrow frame;

[0271] M3 and M0 are arranged in sequence along the vertical direction to utilize the longitudinal space to layout M3 and M0, which is conducive to achieving a narrow frame;

[0272] M3 is set between M14 and M11;

[0273] M2A and M2B are placed side by side, and M2B and M2A are arranged in the horizontal direction;

[0274] M8D, M8B, and M7A are arranged in sequence along the vertical direction, and M8D, M8B, and M7B are arranged in sequence along the vertical direction to utilize the vertical space layout of M8D, M8B, M7A, and M7B to achieve a narrow frame;

[0275] The M8C and M8A are arranged vertically in sequence to utilize the vertical space to layout the M8C and M8A, which is conducive to narrow bezels;

[0276] M8D and M8C are arranged side by side, M8B and M8A are arranged side by side, M8C and M8D are arranged in a horizontal direction, M8A and M8B are arranged in a horizontal direction, M8D is arranged on a side of M8C away from the display area, and M8B is arranged on a side of M8A away from the display area;

[0277] M12B, M13B, M13A, and M12A are arranged in sequence along the vertical direction to utilize the vertical space to set up M12B, M13B, M13A, and M12A, which is conducive to achieving a narrow frame;

[0278] M13B is located on the side of M8D away from the display area;

[0279] M6B, M15A and M16A are arranged in sequence along the vertical direction, and M6B, M15B and M16A are arranged in sequence along the vertical direction to utilize the vertical space to set up M6B, M15A, M15B and M16A;

[0280] The M15A and M15B are placed side by side horizontally;

[0281] M6B is located on the side of M12B away from the display area;

[0282] M5B and M5A are arranged in sequence along the vertical direction; M5A is arranged on a side of M6A away from the display area.

[0283] In FIG11 , CLKA1 denotes a first clock signal line portion included in CLKA, CLKB1 denotes a first clock signal line portion included in CLKB, CLKD1 denotes a first clock signal line portion included in CLKD, and CLKD1 denotes a first clock signal line portion included in CLKD.

[0284] In FIG. 12 , A8D is an active pattern of M8D, A8C is an active pattern of M8C, A8B is an active pattern of M8B, and A8A is an active pattern of M8A.

[0285] In FIG14 , CLKA2 is a second clock signal line portion included in CLKA, CLKB2 is a second clock signal line portion included in CLKB, CLKD2 is a second clock signal line portion included in CLKD, and CLKD2 is a second clock signal line portion included in CLKD.

[0286] CLKA2 may be electrically connected to CLKA1 , CLKB2 may be electrically connected to CLKB1 , CLKC2 may be electrically connected to CLKC1 , and CLKD2 may be electrically connected to CLKD1 .

[0287] The difference between at least one embodiment of the driving circuit shown in FIG15 and at least one embodiment of the driving circuit shown in FIG5 is that:

[0288] M0 and control node N0 are not set;

[0289] The drain of the first input transistor M1A is electrically connected to the source of the second input transistor M1B;

[0290] The drain of the first reset transistor M2A is electrically connected to the source of the second reset transistor M2B;

[0291] The drain of the first pull-down transistor M8A is electrically connected to the source of the second pull-down transistor M8C;

[0292] The drain of the third pull-down transistor M8B is electrically connected to the source of the fourth pull-down transistor M8D;

[0293] A drain of the first frame reset transistor M15A is electrically connected to a source of the second frame reset transistor M15B.

[0294] The difference between at least one embodiment of the driving circuit shown in FIG16 and at least one embodiment of the driving circuit shown in FIG15 is that:

[0295] The gate of M1A and the gate of M1B are both electrically connected to I1;

[0296] The drain of M2B is electrically connected to the second low voltage line LVGL, the drain of M8C is electrically connected to the second low voltage line LVGL, and the drain of M8D is electrically connected to the second low voltage line LVGL.

[0297] The difference between at least one embodiment of the driving circuit shown in FIG17 and at least one embodiment of the driving circuit shown in FIG16 is that:

[0298] The input circuit includes an input transistor M1;

[0299] The gate of the input transistor M1 and the source of the input transistor M1 are both electrically connected to the input terminal I0, and the drain of the input transistor M1 is electrically connected to the first node PU;

[0300] The reset circuit includes a reset transistor M2;

[0301] The gate of the reset transistor M2 is electrically connected to the reset terminal R1, the source of the reset transistor M2 is electrically connected to the first node PU, and the drain of the reset transistor M2 is electrically connected to the first low voltage line VGL;

[0302] The first node reset circuit includes a first pull-down transistor M8A and a third pull-down transistor M8B;

[0303] The gate of the first pull-down transistor M8A is electrically connected to the first second node PD1, the source of the first pull-down transistor M8A is electrically connected to the first node PU, and the drain of the first pull-down transistor M8A is electrically connected to the second low voltage line LVGL;

[0304] The gate of the third pull-down transistor M8B is electrically connected to the second second node PD2, the source of the third pull-down transistor M8B is electrically connected to the first node PU, and the drain of the third pull-down transistor M8B is electrically connected to the second low voltage line LVGL;

[0305] The frame reset circuit includes a frame reset transistor M15;

[0306] A gate of the frame reset transistor M15 is electrically connected to the frame reset line STV0 , a source of the frame reset transistor M15 is electrically connected to the first node PU, and a drain of the frame reset transistor M15 is electrically connected to the second low voltage line LVGL.

[0307] The display substrate described in the embodiment of the present disclosure includes a base and the above-mentioned driving circuit disposed on the base.

[0308] The display substrate according to at least one embodiment of the present disclosure further includes an electrostatic protection circuit disposed on the base;

[0309] A first end of the electrostatic protection circuit is electrically connected to the drive signal line, and a second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal via a short-circuit line, and the electrostatic protection circuit is used for electrostatic protection;

[0310] The driving signal lines include a DC voltage line, a clock signal line, a control voltage line and a frame reset line.

[0311] In at least one embodiment of the present disclosure, the driving signal line is a metal line that runs through the entire display panel and is located at the edge of the display panel. When static electricity exists in the external environment, it is extremely susceptible to high voltage and burns. Therefore, an electrostatic protection circuit is provided between the signal line and the shorting bar (shorting line) to disperse the transient voltage and prevent the driving signal line from being burned.

[0312] At least one embodiment of the present disclosure provides a specific structure of an electrostatic protection circuit, which adopts a mixed design of large and small TFTs (thin film transistors). On the basis of ensuring electrostatic release performance, it can reduce the current between signals and reduce crosstalk. At the same time, due to the small size of TFTs, the layout space is smaller.

[0313] Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor and a third protection transistor;

[0314] The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;

[0315] The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;

[0316] The gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the short-circuit line, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor;

[0317] The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor.

[0318] For example, the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be 3.5 / 8, and the channel width-to-length ratio of the second protection transistor may be 3.5 / 50, but is not limited thereto.

[0319] In a specific implementation, the channel width-to-length ratio of the first protection transistor and the channel width-to-length ratio of the third protection transistor may be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-to-length ratio of the second protection transistor may be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30, but is not limited to this.

[0320] Optionally, the electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor;

[0321] The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor;

[0322] The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor;

[0323] A first electrode of the third protection transistor is electrically connected to the gate of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to the gate of the fourth protection transistor;

[0324] A first electrode of the fourth protection transistor is electrically connected to the gate of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to the gate of the fifth protection transistor;

[0325] The gate of the fifth protection transistor and the first electrode of the fifth protection transistor are both electrically connected to the short-circuit line, and the second electrode of the fifth protection transistor is electrically connected to the gate of the fourth protection transistor;

[0326] The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;

[0327] The channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor;

[0328] The channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor.

[0329] For example, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor can be 3.5 / 8, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor can be 3.5 / 50, but is not limited to this.

[0330] In a specific implementation, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30, but is not limited to this.

[0331] As shown in FIG18 , at least one embodiment of the electrostatic protection circuit may include a first protection transistor T1 , a second protection transistor T2 , a third protection transistor T3 , a fourth protection transistor T4 , and a fifth protection transistor T5 ;

[0332] The gate of the first protection transistor T1 and the source of the first protection transistor T1 are both electrically connected to the drive signal line QX, and the drain of the first protection transistor T1 is electrically connected to the gate of the second protection transistor T2;

[0333] The source of the second protection transistor T2 is electrically connected to the gate of the first protection transistor T1, and the drain of the second protection transistor T2 is electrically connected to the gate of the third protection transistor T3;

[0334] The source of the third protection transistor T3 is electrically connected to the gate of the second protection transistor T2, and the drain of the third protection transistor T3 is electrically connected to the gate of the fourth protection transistor T4;

[0335] The source of the fourth protection transistor T4 is electrically connected to the gate of the third protection transistor T3, and the drain of the fourth protection transistor T4 is electrically connected to the gate of the fifth protection transistor T5;

[0336] The gate of the fifth protection transistor T5 and the source of the fifth protection transistor T5 are both electrically connected to the short-circuit line SR, the drain of the fifth protection transistor T5 is electrically connected to the gate of the fourth protection transistor T4; the gate of T5 is electrically connected to the common electrode voltage terminal CM;

[0337] The channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the first protection transistor T1 is greater than the channel width-to-length ratio of the fourth protection transistor T4;

[0338] The channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the second protection transistor T2, and the channel width-to-length ratio of the third protection transistor T3 is greater than the channel width-to-length ratio of the fourth protection transistor T4;

[0339] The channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the second protection transistor T2 , and the channel width-to-length ratio of the fifth protection transistor T5 is greater than the channel width-to-length ratio of the fourth protection transistor T4 .

[0340] In at least one embodiment shown in Figure 18, the channel width-to-length ratio of the first protection transistor, the channel width-to-length ratio of the third protection transistor, and the channel width-to-length ratio of the fifth protection transistor may be greater than or equal to 3.5 / 12 and less than or equal to 3.5 / 6, and the channel width-to-length ratio of the second protection transistor and the channel width-to-length ratio of the fourth protection transistor may be greater than or equal to 3.5 / 80 and less than or equal to 3.5 / 30.

[0341] FIG. 19 is a layout diagram of at least one embodiment of an electrostatic protection circuit.

[0342] In FIG19 , CLKA is a first clock signal line, CLKB is a second clock signal line, CLKC is a third clock signal line, and CLKD is a fourth clock signal line; STV is a start voltage line, VDDO is a first control voltage line, VDDE is a second control voltage line, STV0 is a frame reset line, LVGL is a second low voltage line, and VGL is a first low voltage line;

[0343] The line marked SR is a short line;

[0344] The one labeled E1 is the first electrostatic protection circuit, the one labeled E2 is the second electrostatic protection circuit, the one labeled E3 is the third electrostatic protection circuit, the one labeled E4 is the fourth electrostatic protection circuit, the one labeled E5 is the fifth electrostatic protection circuit, the one labeled E6 is the sixth electrostatic protection circuit, the one labeled E7 is the seventh electrostatic protection circuit, the one labeled E8 is the eighth electrostatic protection circuit, the one labeled E9 is the ninth electrostatic protection circuit, and the one labeled E10 is the tenth electrostatic protection circuit.

[0345] In Figure 19, the first protection transistor in E5 is labeled T1, the second protection transistor in E5 is labeled T2, the third protection transistor in E5 is labeled T3, the fourth protection transistor in E5 is labeled T4, and the fifth protection transistor in E5 is labeled T5.

[0346] As shown in FIG19 , M2 and M4 are arranged side by side in the horizontal direction, and M1 , M3 and M5 are arranged side by side in the horizontal direction.

[0347] In FIG19 , the terminal labeled CM is a common electrode voltage terminal.

[0348] As shown in FIG20 , at least one embodiment of the electrostatic protection circuit may include a first protection transistor T1 and a second protection transistor T2 ;

[0349] The gate of T1 and the source of T1 are both electrically connected to the drive signal line QX, and the drain of T1 is electrically connected to the gate of T2;

[0350] The source of T2 is electrically connected to the gate of T1 , and the gate of T1 is electrically connected to the common electrode voltage terminal CM.

[0351] The channel width-to-length ratio of T1 and the channel width-to-length ratio of T2 may be 3.5 / 180.

[0352] FIG. 21 is a layout diagram of at least one embodiment of an electrostatic protection circuit.

[0353] In FIG21 , CLKA is a first clock signal line, CLKB is a second clock signal line, CLKC is a third clock signal line, and CLKD is a fourth clock signal line; STV is a start voltage line, VDDO is a first control voltage line, VDDE is a second control voltage line, STV0 is a frame reset line, LVGL is a second low voltage line, and VGL is a first low voltage line;

[0354] The line marked SR is a short line;

[0355] The one labeled E1 is the first electrostatic protection circuit, the one labeled E2 is the second electrostatic protection circuit, the one labeled E3 is the third electrostatic protection circuit, the one labeled E4 is the fourth electrostatic protection circuit, the one labeled E5 is the fifth electrostatic protection circuit, the one labeled E6 is the sixth electrostatic protection circuit, the one labeled E7 is the seventh electrostatic protection circuit, the one labeled E8 is the eighth electrostatic protection circuit, the one labeled E9 is the ninth electrostatic protection circuit, and the one labeled E10 is the tenth electrostatic protection circuit.

[0356] In FIG21 , the first protection transistor in E5 is labeled T1, and the second protection transistor in E5 is labeled T2;

[0357] In FIG21 , the terminal labeled CM is a common electrode voltage terminal.

[0358] The display device described in the embodiment of the present disclosure includes the above-mentioned display substrate.

[0359] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit, comprising an input circuit, a reset circuit, a first node reset circuit and a control node control circuit; The input circuit is electrically connected to the input control terminal, the input terminal and the first node respectively, and is used to control the connection or disconnection between the input terminal and the first node under the control of the input control signal provided by the input control terminal; The reset circuit is electrically connected to the reset terminal, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the reset signal provided by the reset terminal; The first node reset circuit is electrically connected to the second node, the first node and the first voltage line respectively, and is used to control the connection or disconnection between the first node and the first voltage line under the control of the potential of the second node; The control node control circuit is electrically connected to the first node, the third voltage line and the control node respectively, and is used to control the connection or disconnection between the control node and the third voltage line under the control of the potential of the first node; The transistor included in the input circuit, the transistor included in the reset circuit and the transistor included in the first node reset circuit are arranged in sequence along a direction away from the display area; A ratio of a channel width-to-length ratio of a transistor whose gate is electrically connected to the second node and included in the first node reset circuit to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

2. The driving circuit according to claim 1, wherein: Also included is a frame reset circuit; The frame reset circuit is electrically connected to the frame reset line, the first node and the second voltage line respectively, and is used to control the connection or disconnection between the first node and the second voltage line under the control of the frame reset signal provided by the frame reset line; The transistor included in the frame reset circuit is arranged on a side of the transistor included in the first node reset circuit away from the display area.

3. The driving circuit according to claim 1, wherein: The input circuit includes at least two input transistors connected in series, and the reset circuit includes at least two reset transistors connected in series.

4. The driving circuit according to claim 1, wherein: The first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the second node; or, The second node includes a first second node and a second second node; the first node reset circuit includes at least two transistors connected in series with their gates electrically connected to the first second node, and at least two transistors connected in series with their gates electrically connected to the second second node.

5. The driving circuit according to claim 2, wherein: The frame reset circuit includes at least two frame reset transistors connected in series.

6. The driving circuit according to claim 1, wherein: The transistor included in the control node control circuit is arranged on a side of the transistor included in the input circuit close to the display area.

7. The driving circuit according to claim 1, wherein: The control node control circuit includes a control transistor; A gate of the control transistor is electrically connected to the first node, a first electrode of the control transistor is electrically connected to the third voltage line, and a second electrode of the control transistor is electrically connected to the control node.

8. The driving circuit according to any one of claims 1 to 7, wherein: Also includes a shutdown reset circuit; The shutdown reset circuit is electrically connected to the fourth voltage line and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the fourth voltage line under the control of a fourth voltage signal provided by the fourth voltage line.

9. The driving circuit according to claim 8, wherein: The transistor included in the shutdown reset circuit is arranged on a side of the transistor included in the input circuit close to the display area.

10. The driving circuit according to claim 8, wherein: The shutdown reset circuit includes a shutdown reset transistor; The gate of the shutdown reset transistor and the first electrode of the shutdown reset transistor are electrically connected to the fourth voltage line, and the second electrode of the shutdown reset transistor is electrically connected to the driving signal output terminal.

11. The driving circuit according to any one of claims 1 to 7, wherein: The input circuit includes a first input transistor and a second input transistor; The gate of the first input transistor is electrically connected to the input control terminal, the first electrode of the first input transistor is electrically connected to the input terminal, and the second electrode of the first input transistor is electrically connected to the control node; A gate of the second input transistor is electrically connected to the input control terminal, a first electrode of the second input transistor is electrically connected to the control node, and a second electrode of the second input transistor is electrically connected to the first node.

12. The driving circuit according to claim 11, wherein: The input control terminal is a carry signal output terminal of the adjacent previous stage driving circuit, and the input terminal is a drive signal output terminal of the adjacent previous stage driving circuit; or, The input control terminal and the input terminal are both carry signal output terminals of the adjacent previous stage driving circuit.

13. The driving circuit according to any one of claims 1 to 7, wherein: The reset circuit includes a first reset transistor and a second reset transistor; The gate of the first reset transistor is electrically connected to the reset terminal, the first electrode of the first reset transistor is electrically connected to the first node, and the second electrode of the first reset transistor is electrically connected to the control node; A gate of the second reset transistor is electrically connected to the reset terminal, a first electrode of the second reset transistor is electrically connected to the control node, and a second electrode of the second reset transistor is electrically connected to the first voltage line.

14. The driving circuit according to claim 13, wherein: The control node control circuit includes a transistor having a channel width-to-length ratio that is smaller than a channel width-to-length ratio of the second reset transistor.

15. The driving circuit according to any one of claims 1 to 7, wherein: The first node reset circuit includes a first pull-down transistor and a second pull-down transistor; The gate of the first pull-down transistor is electrically connected to the second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node; A gate of the second pull-down transistor is electrically connected to the second node, a first electrode of the second pull-down transistor is electrically connected to the control node, and a second electrode of the second pull-down transistor is electrically connected to the first voltage line.

16. The driving circuit according to claim 15, wherein: A ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

17. The driving circuit according to claim 15, wherein: A channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor.

18. The driving circuit according to any one of claims 1 to 7, wherein: The second nodes include a first second node and a second second node; The first node reset circuit includes a first pull-down transistor, a second pull-down transistor, a third pull-down transistor and a fourth pull-down transistor; The gate of the first pull-down transistor is electrically connected to the first second node, the first electrode of the first pull-down transistor is electrically connected to the first node, and the second electrode of the first pull-down transistor is electrically connected to the control node; The gate of the second pull-down transistor is electrically connected to the first second node, the first electrode of the second pull-down transistor is electrically connected to the control node, and the second electrode of the second pull-down transistor is electrically connected to the first voltage line; The gate of the third pull-down transistor is electrically connected to the second second node, the first electrode of the third pull-down transistor is electrically connected to the first node, and the second electrode of the third pull-down transistor is electrically connected to the control node; A gate of the fourth pull-down transistor is electrically connected to the second second node, a first electrode of the fourth pull-down transistor is electrically connected to the control node, and a second electrode of the fourth pull-down transistor is electrically connected to the first voltage line.

19. The driving circuit according to claim 18, wherein: A channel width-to-length ratio of the second pull-down transistor is greater than a channel width-to-length ratio of the first pull-down transistor, and a channel width-to-length ratio of the fourth pull-down transistor is greater than a channel width-to-length ratio of the third pull-down transistor.

20. The driving circuit according to claim 18, wherein: A ratio of a channel width-to-length ratio of the second pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24; A ratio of a channel width-to-length ratio of the fourth pull-down transistor to a channel width-to-length ratio of a transistor included in the control node control circuit is greater than or equal to 6 and less than or equal to 24.

21. The driving circuit according to claim 2, wherein: The frame reset circuit includes a first frame reset transistor and a second frame reset transistor; The gate of the first frame reset transistor is electrically connected to the frame reset line, the first electrode of the first frame reset transistor is electrically connected to the first node, and the second electrode of the first frame reset transistor is electrically connected to the control node; A gate of the second frame reset transistor is electrically connected to the frame reset line, a first electrode of the second frame reset transistor is electrically connected to the control node, and a second electrode of the second frame reset transistor is electrically connected to the second voltage line.

22. The driving circuit according to any one of claims 1 to 7, wherein: It also includes a carry signal output circuit, a drive signal output circuit and an energy storage circuit; The carry signal output circuit is electrically connected to the first node, the second node, the carry signal output terminal, the clock signal terminal and the second voltage line respectively, and is used to control the connection or disconnection between the carry signal output terminal and the clock signal terminal under the control of the potential of the first node, and control the connection or disconnection between the carry signal output terminal and the second voltage line under the control of the potential of the second node; The drive signal output circuit is electrically connected to the first node, the second node, the drive signal output terminal, the clock signal terminal and the fourth voltage line respectively, and is used to control the drive signal output terminal to be connected to the clock signal terminal under the control of the potential of the first node. The clock signal terminals are connected or disconnected, and under the control of the potential of the second node, the drive signal output terminal and the fourth voltage line are controlled to be connected or disconnected; The energy storage circuit is electrically connected to the first node and the drive signal output terminal respectively, and is used for storing electric energy.

23. The driving circuit according to claim 22, wherein: The fourth voltage line is used to provide a fourth voltage signal, and the second voltage line is used to provide a second voltage signal; The voltage value of the fourth voltage signal is equal to the voltage value of the second voltage signal, or the voltage value of the second voltage signal is smaller than the voltage value of the fourth voltage signal.

24. The driving circuit according to any one of claims 1 to 7, wherein: Also included is a second node control circuit; The second node control circuit is electrically connected to the input control terminal, the first node, the second node and the second voltage line, respectively, and is used to control the connection or disconnection between the second node and the second voltage line under the control of the input control signal provided by the input control terminal, and to control the potential of the second node under the control of the potential of the first node.

25. A display substrate, comprising a base and the driving circuit according to any one of claims 1 to 24 disposed on the base.

26. The display substrate according to claim 25, wherein: Also included is an electrostatic protection circuit disposed on the substrate; The first end of the electrostatic protection circuit is electrically connected to the driving signal line, the second end of the electrostatic protection circuit is electrically connected to the common electrode voltage terminal through a short-circuit line, and the electrostatic protection circuit is used for electrostatic protection; The driving signal lines include a DC voltage line, a clock signal line, a control voltage line and a frame reset line.

27. The display substrate according to claim 26, wherein: The electrostatic protection circuit comprises a first protection transistor, a second protection transistor and a third protection transistor; The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor; The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor; The gate of the third protection transistor and the first electrode of the third protection transistor are both electrically connected to the short-circuit line, and the second electrode of the third protection transistor is electrically connected to the gate of the second protection transistor; The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor.

28. The display substrate according to claim 26, wherein: The electrostatic protection circuit includes a first protection transistor, a second protection transistor, a third protection transistor, a fourth protection transistor and a fifth protection transistor; The gate of the first protection transistor and the first electrode of the first protection transistor are both electrically connected to the driving signal line, and the second electrode of the first protection transistor is electrically connected to the gate of the second protection transistor; The first electrode of the second protection transistor is electrically connected to the gate of the first protection transistor, and the second electrode of the second protection transistor is electrically connected to the gate of the third protection transistor; A first electrode of the third protection transistor is electrically connected to a gate of the second protection transistor, and a second electrode of the third protection transistor is electrically connected to a gate of the fourth protection transistor; A first electrode of the fourth protection transistor is electrically connected to a gate of the third protection transistor, and a second electrode of the fourth protection transistor is electrically connected to a gate of the fifth protection transistor; The gate of the fifth protection transistor and the first electrode of the fifth protection transistor are both electrically connected to the short-circuit line, and the second electrode of the fifth protection transistor is electrically connected to the gate of the fourth protection transistor; The channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the first protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor; The channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the third protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor; The channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the second protection transistor, and the channel width-to-length ratio of the fifth protection transistor is greater than the channel width-to-length ratio of the fourth protection transistor.

29. A display device comprising the display substrate according to any one of claims 25 to 28.

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