Display substrate and display device

Abstract

The invention provides a display substrate and a display device, and belongs to the technical field of display. The display substrate comprises a gate drive circuit and a plurality of clock signal lines; the gate driving circuit comprises a plurality of cascaded gate driving units; the plurality of clock signal lines are divided into N groups, and each group comprises two clock signal lines; for two adjacent gate driving units in every 2N cascaded gate driving units, the first clock signal end of the ith gate driving unit is connected with the ith clock signal line, the second clock signal end of the ith gate driving unit is connected with the (i + 1) th clock signal line, and i is a positive integer from 1 to (2N-1); the ith clock signal line and the (i + 1) th clock signal line are opposite in time sequence; for the 2Nth gate driving unit, the first clock signal end is connected with the 2Nth clock signal line, and the second clock signal end is connected with the first clock signal line; the 2Nth clock signal line and the first clock signal line are opposite in time sequence.

Description

Display substrate and display device Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to a display substrate and a display device. Background Art

[0002] Gate Drive on Array (GOA) technology is a commonly used technology in display products that integrates gate drive circuits on a substrate to achieve row-by-row scanning of pixel gates.

[0003] Currently, display devices are increasingly trending toward larger sizes. As the size and resolution of display devices increase, the routing paths of various signal lines become longer, thereby increasing the loading of the clock signal lines connected to the gate drive circuits. The increase in loading prolongs the time it takes for the gate drive circuits to output signals, thereby affecting the effective working time of the pixels and, in turn, the display image.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provide a display substrate and a display device.

[0006] In a first aspect, a technical solution adopted to solve the technical problem of the present disclosure is a display substrate, comprising a base substrate, and a gate drive circuit and a plurality of clock signal lines provided on the base substrate; the gate drive circuit comprises a plurality of cascaded gate drive units;

[0007] The plurality of clock signal lines are divided into N groups, each group including two clock signal lines; N is a positive integer greater than or equal to 2;

[0008] For two adjacent gate driving units in every 2N cascaded gate driving units, the first clock signal terminal of the i-th gate driving unit is connected to the i-th clock signal line, and the second clock signal terminal of the i-th gate driving unit is connected to the i+1-th clock signal line, where i is a positive integer between 1 and (2N-1), the first clock signal terminals are connected to different clock signal lines, and the second clock signal terminals are connected to different clock signal lines; the timing sequences of the i-th clock signal line and the i+1-th clock signal line are opposite;

[0009] For the 2Nth gate driving unit, the first clock signal end is connected to the 2Nth clock signal line, and the second clock signal end is connected to the 1st clock signal line; the timing of the 2Nth clock signal line and the timing of the 1st clock signal line are opposite.

[0010] In some embodiments, a plurality of cascaded gate driving units are arranged side by side along the second direction;

[0011] Any of the clock signal lines extends along the second direction, and the orthographic projections of any group of the clock signal lines on the substrate overlap with the orthographic projections of each stage of the gate driving units on the substrate.

[0012] In some embodiments, the display substrate further includes a driving circuit layer disposed on the base substrate, and a first conductive layer disposed on a side of the driving circuit layer away from the base substrate;

[0013] Each of the clock signal lines is located in the first conductive layer.

[0014] In some embodiments, the display substrate further includes a light emitting device and a third power line; the third power line is connected to the light emitting device;

[0015] The third power line includes a first conductive portion, a second conductive portion, and a third conductive portion connecting the first conductive portion and the second conductive portion; the first conductive portion and the third conductive portion are both located in the first conductive layer;

[0016] The display substrate further includes a second conductive layer located between the first conductive layer and the driving circuit layer. The second conductive portion is located in the second conductive layer, and the second conductive portion is connected to the first conductive portion through a first connecting via, and the second conductive portion is connected to the second conductive portion through a second connecting via.

[0017] In some embodiments, the second conductive portion includes a first end portion and a second end portion, and a main portion connected between the first end portion and the second end portion; the orthographic projection of the main portion on the base substrate is located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate.

[0018] In some embodiments, the gate driving unit includes an output circuit and an output control circuit;

[0019] The orthographic projection of the main body on the base substrate does not overlap with the orthographic projections of the output circuit and the output control circuit in the gate driving circuit on the base substrate.

[0020] In some embodiments, a planarization layer is provided between the first conductive layer and the second conductive layer; the first connecting via and the second connecting via respectively penetrate the planarization layer;

[0021] The thickness of the planarization layer is between 1.5 μm and 2.0 μm.

[0022] In some embodiments, the display substrate further includes a first power line for transmitting a first voltage signal to the gate driving circuit, a second power line for transmitting a second voltage signal to the gate driving circuit, and an input signal line for providing an input signal to the gate driving circuit;

[0023] The first power line, the second power line and the input signal line are all located in the second conductive layer.

[0024] In some embodiments, the display substrate includes a display area and a non-display area, the first power line, the second power line, the second conductive portion, and the input signal line are all located in the non-display area, and the first power line is located on a side of the second conductive portion away from the display area, and the second power line is located on a side of the second conductive portion close to the display area;

[0025] The input signal line is located between the second power line and the second conductive portion.

[0026] In some embodiments, the driving circuit layer includes a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the base substrate;

[0027] The active layer of each transistor in the gate drive circuit is located in the semiconductor layer;

[0028] The control electrodes of each transistor in the gate drive circuit, the first plate of the first capacitor and the first plate of the second capacitor are all located in the third conductive layer;

[0029] The second plate of the first capacitor and the second plate of the second capacitor in the gate drive circuit are both located in the fourth conductive layer;

[0030] The first electrode and the second electrode of each transistor in the gate driving circuit are both located in the fifth conductive layer.

[0031] In some embodiments, the gate driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0032] The fourth conductive layer further includes a first switching electrode for connecting the control electrode of the sixth transistor and the first electrode of the second transistor.

[0033] In some embodiments, the gate driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0034] The control electrode of the third transistor and the control electrode of the first transistor are connected as an integral structure and connected to the second electrode of the second transistor, and the second electrode of the second transistor is multiplexed as the first clock signal terminal of the gate driving unit.

[0035] In some embodiments, the fifth conductive layer also includes a second transfer electrode, which is multiplexed as the second clock signal end of the i-th gate driving unit and the first clock signal end of the i+1-th gate driving unit, and is connected to the control electrode of the seventh transistor of the i-th gate driving unit, the control electrode of the first transistor in the i+1-th gate driving unit, and the control electrode of the third transistor.

[0036] In some embodiments, the fifth conductive layer further includes a third switching electrode, wherein the third switching electrode is connected to the control electrode of the eighth transistor in the i-th level gate driving unit and the second electrode of the third transistor in the (i+1)-th level gate driving unit.

[0037] In some embodiments, the fifth conductive layer also includes a fourth transfer electrode, which is multiplexed as the output end of the i-th gate driving unit and the input end of the i+1-th gate driving unit, and connects the second electrode of the fifth transistor and the second electrode of the fourth transistor in the i-th gate driving unit, and the second electrode of the first transistor in the i+1-th gate driving unit.

[0038] In some embodiments, the gate driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0039] The active layer of the fourth transistor is shared by the active layer of the fifth transistor; the active layer of the fourth transistor includes a first semiconductor, a second semiconductor, and a third semiconductor arranged side by side and spaced apart along a first direction;

[0040] The orthographic projections of the first semiconductor, the second semiconductor, and the third semiconductor on the substrate respectively overlap with the orthographic projections of the control electrode of the fourth transistor on the substrate;

[0041] The orthographic projections of the first semiconductor, the second semiconductor, and the third semiconductor on the substrate respectively overlap with the orthographic projections of the control electrode of the fifth transistor on the substrate.

[0042] In some embodiments, the first conductive portion includes a plurality of openings extending through the first conductive portion along its thickness direction, and the plurality of openings are arranged side by side along the second direction to form a column of openings; and the plurality of columns of openings are arranged side by side along the first direction.

[0043] In some embodiments, the display substrate includes a display area and a non-display area, and the display substrate further includes an initialization signal line located in the non-display area and a pixel driving circuit located in the display area;

[0044] The initialization signal line is located in the second conductive layer and is connected to the pixel driving circuit.

[0045] In a second aspect, an embodiment of the present disclosure further provides a display device, comprising a display substrate as described in any one of the first aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] FIG1 is a schematic diagram of an existing 8T1C pixel driving circuit;

[0047] FIG2 is an output waveform diagram of the circuit shown in FIG1 under an ideal state;

[0048] FIG3 is an output waveform diagram of the circuit shown in FIG1 under actual conditions;

[0049] FIG4 is a schematic diagram of a cascade connection of a conventional gate driving unit;

[0050] FIG5 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0051] FIG6 is a plan view of stacked film layers of a gate driving circuit provided by an embodiment of the present disclosure;

[0052] FIG7 is a plan view of a first conductive layer and a second conductive layer stacked according to an embodiment of the present disclosure;

[0053] FIG8 is a plan view of a first conductive layer provided by an embodiment of the present disclosure;

[0054] FIG9 is a plan view of a second conductive layer provided in an embodiment of the present disclosure;

[0055] FIG10 is a plan view of a semiconductor provided by an embodiment of the present disclosure;

[0056] FIG11 is a plan view of a third conductive layer provided in an embodiment of the present disclosure;

[0057] FIG12 is a plan view of a fourth conductive layer provided in an embodiment of the present disclosure;

[0058] FIG13 is a plan view of a fifth conductive layer provided in an embodiment of the present disclosure;

[0059] FIG14 is a circuit diagram of an 8T2C circuit provided in an embodiment of the present disclosure;

[0060] FIG15 is an operating timing diagram of the 8T2C gate drive circuit shown in FIG14 ;

[0061] FIG16 is a plan view of a stack of a semiconductor layer and a third conductive layer provided in an embodiment of the present disclosure;

[0062] FIG17 is a plan view of a stack of semiconductor layers, a third conductive layer, a fourth conductive layer, and a fifth conductive layer provided in an embodiment of the present disclosure.

[0063] The reference numerals are: GOA, gate drive unit; CK, first clock signal terminal; CB, second clock signal terminal; M1, first conductive layer; M2, second conductive layer; VGL, first power line; VGH, second power line; GSTV, input signal line; VL, first voltage signal; VH, second voltage signal; VSS, third power line; VSS1, first conductive portion; VSS2, second conductive portion; VSS3, third conductive portion; V1, first connecting via; V2, second connecting via; H, opening; X, first direction; Y, second direction; O1, semiconductor layer; M3, third conductive layer; M4, fourth conductive layer; M5, fifth conductive layer; C1, first capacitor; C11, first plate of first capacitor; C12, first plate of first capacitor Second plate; C2, second capacitor; C21, first plate of second capacitor; C22, second plate of second capacitor; 11, input circuit; 12, first control circuit; 13, second control circuit; 14, third control circuit; 15, output control circuit; 16, output circuit; N1, first node; N2, second node; N3, third node; T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; STV, input end; OUT, output end; S1, first transfer electrode; S2, second transfer electrode; S3, third transfer electrode; S4, fourth transfer electrode; S5, fifth transfer electrode. DETAILED DESCRIPTION

[0064] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0065] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0066] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0067] It should be noted that in the drawings of the specification, in order to facilitate the display of the positional relationship of the film layer structure, part of the film layer is drawn semi-transparently, but this does not mean that the actual structure of the film layer is a transparent film layer, that is, there is no restriction on the material of the film layer.

[0068] In the related art, a commonly used pixel driver circuit for driving pixel light emission is, for example, an 8T1C (8 transistors, 1 capacitor) pixel driver circuit. Figure 1 shows a schematic diagram of an existing 8T1C pixel driver circuit. Five scanning driver circuits are required to work together to control the EM, GateN, GateP, ResetH, and ResetP terminals, respectively, to drive the pixel to emit light. As can be seen, the scanning driver circuit affects pixel light emission, and the gate driver circuit (GOA), in particular, is directly related to the quality of the displayed image. Taking a resolution of 2232 (columns) × 3184 (rows) as an example, at a refresh rate of 120Hz, the time allocated to a row of pixels within a frame is only 1s / 120Hz / 3184 = 2.6µs. The ideal pixel driver circuit output waveform is shown in Figure 2, where "H" represents the duration of driving a row of pixels. Ideally, the voltage transition between the first power line VGL and the second power line VGH should occur instantaneously. However, the gate driver circuit has an RC element (R represents resistance and C represents capacitance), resulting in a slow transition between VGL and VGH during the actual output waveform, as shown in Figure 3. Furthermore, the greater the gate driver circuit's load (R and C), the longer the rising and falling edges Tr and Tf of the gate driver circuit's output waveform (severely exceeding 1µs), which excessively consumes the effective operating time of the pixel driver circuit. Because the gate driver circuit (which controls the switching of the fourth transistor T4 in the pixel driver circuit and writes the data voltage signal (Data)) is turned on row by row, only one row of pixels is turned on at a time, the gate driver circuit is most severely affected by the load, thus affecting the display quality.

[0069] For example, FIG4 is a schematic diagram of a cascade of existing gate drive units. As shown in FIG4 , the existing gate drive circuit includes n cascaded gate drive units GOA, a first clock signal line GCK, and a second clock signal line GCB. Each gate drive unit GOA includes a first clock signal terminal CK and a second clock signal terminal CB. The first clock signal line GCK is connected to the first clock signal terminal CK of each cascaded gate drive unit GOA, and the second clock signal line GCB is connected to the second clock signal terminal CB of each cascaded gate drive unit GOA. Conventional gate drive circuits generally only design two clock signal lines, namely the first clock signal terminal CK and the second clock signal terminal CB as shown in FIG4 . However, the first clock signal terminal CK and the second clock signal terminal CB need to carry each cascaded gate drive unit GOA, resulting in a large overall RC, which results in a large delay in the rising edge Tr and falling edge Tf of the gate drive circuit output waveform. This transition occupies the effective working time output to the pixel drive circuit, which will seriously affect the quality of the displayed image.

[0070] In view of this, an embodiment of the present disclosure provides a display substrate, which is provided with multiple clock signal lines for a gate driving circuit, and the multiple clock signal lines are divided into N groups, each group including two clock signal lines; for two adjacent gate driving units in every 2N cascaded gate driving units, the first clock signal end of the i-th gate driving unit is connected to the i-th clock signal line, and the second clock signal end of the i-th gate driving unit is connected to the i+1-th clock signal line, and the timing of the i-th clock signal line and the i+1-th clock signal line are opposite; for the 2N-th gate driving unit, the first clock signal end is connected to the 2N-th clock signal line, and the second clock signal end is connected to the 1st clock signal line; the timing of the 2N clock signal line and the 1st clock signal line are opposite, and it is ensured that the clock signal lines connected to each first clock signal end are different, and the clock signal lines connected to each second clock signal end are different, so as to reduce the load on each clock signal line, thereby shortening the effective working time occupied by the gate driving circuit in the pixel driving circuit, and improving the uniformity of the image quality of large-screen display.

[0071] The specific structure of a display substrate provided by an embodiment of the present disclosure is described in detail below.

[0072] FIG5 is a schematic diagram of the structure of a display substrate provided in an embodiment of the present disclosure. As shown in FIG5 , the display substrate includes a base substrate, a gate drive circuit disposed on the base substrate, and multiple clock signal lines. The gate drive circuit includes multiple cascaded gate drive units (GOAs). The multiple clock signal lines are divided into N groups, each group including two clock signal lines. N is a positive integer greater than or equal to 2. FIG5 uses N=2 as an example for illustration. Other values ​​for N are not listed here.

[0073] For each of the 2N cascaded gate drive units GOA, the first clock signal terminal CK of the i-th gate drive unit GOA_i is connected to the i-th clock signal line, and the second clock signal terminal CB of the i-th gate drive unit GOA_i is connected to the i+1-th clock signal line, where i is a positive integer from 1 to (2N-1). Each first clock signal terminal CK is connected to a different clock signal line, and each second clock signal terminal CB is connected to a different clock signal line. The timing sequence of the i-th clock signal line and the i+1-th clock signal line is opposite. For the 2N-th gate drive unit GOA_2N, the first clock signal terminal CK is connected to the 2N-th clock signal line, and the second clock signal terminal CB is connected to the 1st clock signal line. The timing sequence of the 2N-th clock signal line and the 1st clock signal line is opposite.

[0074] For example, as shown in FIG5 , for each of the four cascaded gate drive units GOA, the first clock signal terminal CK of the first gate drive unit GOA_1 is connected to the first clock signal line, i.e., the first clock signal line GCK11 in the first group; the second clock signal terminal CB of the first gate drive unit GOA_1 is connected to the second clock signal line, i.e., the second clock signal line GCB12 in the first group. The timing of the first clock signal line and the second clock signal line are opposite, i.e., the timing of GCK11 and GCB12 are opposite. The first clock signal terminal CK of the second gate drive unit GOA_2 is connected to the second clock signal line, i.e., the second clock signal line GCB12 in the first group; the second clock signal terminal CB of the second gate drive unit GOA_2 is connected to the third clock signal line, i.e., the first clock signal line GCK21 in the second group. Among them, the timing of the second clock signal line and the third clock signal line is opposite, that is, the timing of GCB12 and GCK21 is opposite. The first clock signal terminal CK of the third gate drive unit GOA_3 is connected to the third clock signal line, that is, the first clock signal line GCK21 in the second group; the second clock signal terminal CB of the third gate drive unit GOA_3 is connected to the fourth clock signal line, that is, the second clock signal line GCB22 in the second group. Among them, the timing of the third clock signal line and the fourth clock signal line is opposite, that is, the timing of GCK21 and GCB22 is opposite. The first clock signal terminal CK of the fourth gate drive unit GOA_4 is connected to the fourth clock signal line, that is, the second clock signal line GCB22 in the second group; the second clock signal terminal CB of the fourth gate drive unit GOA_4 is connected to the first clock signal line, that is, the first clock signal line GCK11 in the first group. The timing of the fourth clock signal line is opposite to that of the first clock signal line, that is, the timing of GCB22 and GCK11 is opposite.

[0075] Figure 6 is a plan view of the stacked film layers of the gate drive circuit provided in an embodiment of the present disclosure, Figure 7 is a plan view of the stacked first conductive layer M1 and the second conductive layer M2 provided in an embodiment of the present disclosure, Figure 8 is a plan view of the first conductive layer M1 provided in an embodiment of the present disclosure, Figure 9 is a plan view of the second conductive layer M2 provided in an embodiment of the present disclosure, Figure 10 is a plan view of the semiconductor provided in an embodiment of the present disclosure, Figure 11 is a plan view of the third conductive layer M3 provided in an embodiment of the present disclosure, Figure 12 is a plan view of the fourth conductive layer M4 provided in an embodiment of the present disclosure, and Figure 13 is a plan view of the fifth conductive layer M5 provided in an embodiment of the present disclosure.

[0076] Exemplarily, the display substrate includes a display area and a non-display area, and the gate driving circuit is located in the non-display area.

[0077] In some embodiments, as shown in FIG. 6 , a plurality of cascaded gate driving units GOA are arranged side by side along the second direction Y.

[0078] As shown in FIG6 and FIG7 , any clock signal line extends along the second direction Y, and the orthographic projection of any group of clock signal lines on the substrate overlaps with the orthographic projection of each level of gate driving unit GOA on the substrate.

[0079] In this embodiment, the orthographic projections of the clock signal lines on the substrate overlap with the orthographic projections of the gate driving units GOA at each level on the substrate, which can reduce the space occupied by the non-display area and is conducive to achieving a narrow frame.

[0080] In some embodiments, as shown in FIG6 and FIG8 , the display substrate further includes a driving circuit layer disposed on the base substrate, and a first conductive layer M1 disposed on a side of the driving circuit layer away from the base substrate; each clock signal line is located on the first conductive layer M1 .

[0081] As shown in Figures 6, 7 and 8, taking two groups of clock signal lines as an example, each clock signal line includes a first clock signal line GCK11 of the first group, a second clock signal line GCB12 of the first group, a first clock signal line GCK21 of the second group, and a second clock signal line GCB22 of the second group.

[0082] In some embodiments, as shown in Figures 6, 7, and 9, the display substrate further includes a second conductive layer M2 located between the first conductive layer M1 and the drive circuit layer. The display substrate further includes a first power line VGL for transmitting a first voltage signal VL to the gate drive circuit, a second power line VGH for transmitting a second voltage signal VH to the gate drive circuit, and an input signal line GSTV for providing an input signal to the gate drive circuit; the first power line VGL, the second power line VGH, and the input signal line GSTV are all located in the second conductive layer M2.

[0083] Prior art typically places signal lines on the same layer, for example, the clock signal line is located on the second conductive layer M2 along with other power lines and the input signal line GSTV. The present disclosure places each clock signal line on the first conductive layer M1, layered with other power lines and the input signal line GSTV. This reduces the non-display area compared to conventional technology. Furthermore, because two insulating layers separate the first conductive layer M1 from the drive circuit layer, each clock signal line located on the first conductive layer M1 can effectively reduce its own parasitic capacitance, thereby reducing the load on each clock signal line and improving the uniformity of image quality across large-screen displays.

[0084] In some embodiments, as shown in Figures 8 and 9, the display substrate further includes a light-emitting device (not shown in the figures) and a third power line VSS; the third power line VSS is connected to the light-emitting device; the third power line VSS includes a first conductive part VSS1, a second conductive part VSS2, and a third conductive part VSS3 connecting the first conductive part VSS1 and the second conductive part VSS2; the first conductive part VSS1 and the third conductive part VSS3 are both located in the first conductive layer M1; the display substrate further includes a second conductive layer M2 located between the first conductive layer M1 and the driving circuit layer, the second conductive part VSS2 is located in the second conductive layer M2, and the second conductive part VSS2 is connected to the first conductive part VSS1 through the first connecting via V1, and the second conductive part VSS2 is connected to the second conductive part VSS2 through the second connecting via V2.

[0085] In some embodiments, as shown in Figure 9, the display substrate includes a display area and a non-display area, the first power line VGL, the second power line VGH, the second conductive part VSS2 and the input signal line GSTV are all located in the non-display area, and the first power line VGL is located on the side of the second conductive part VSS2 away from the display area, and the second power line VGH is located on the side of the second conductive part VSS2 close to the display area; the input signal line GSTV is located between the second power line VGH and the second conductive part VSS2.

[0086] In some embodiments, as shown in Figures 7, 8 and 9, the second conductive portion VSS2 includes a first end and a second end, and a main body portion VSS21 connected between the first end and the second end; the orthographic projection of the main body portion VSS21 on the base substrate is located between the orthographic projection of the first conductive portion VSS1 on the base substrate and the orthographic projection of the third conductive portion VSS3 on the base substrate.

[0087] Exemplarily, the main portion VSS21 of the second conductive portion VSS2 extends along the first direction X. The first end of the second conductive portion VSS2 is connected to the first conductive portion VSS1 through the first connection via V1 ; the second end of the second conductive portion VSS2 is connected to the third conductive portion VSS3 through the second connection via V2 .

[0088] Exemplarily, the third conductive portion VSS3 includes a first end portion VSS31 and a second end portion (not shown), and a main portion VSS32 connected between the first end portion VSS31 and the second end portion. The main portion VSS32 of the third conductive portion VSS3 extends along the first direction X. The first end portion VSS31 of the third conductive portion VSS3 is connected to the second end portion of the second conductive portion VSS2 via a third connection via V3. The second end portion of the third conductive portion VSS3 is electrically connected to the second electrode (e.g., cathode) of the light-emitting device.

[0089] Exemplarily, the main portions VSS32 of the third conductive portion VSS3 are arranged side by side along the second direction Y and extend to the display area along the first direction X. The main portions VSS3 of the third conductive portion VSS3 are distributed in a mesh pattern in the display area to reduce the voltage across the third power line VSS.

[0090] The cross-layer connection design of the third power line VSS disclosed in the present invention provides space for wiring of each clock signal line in the first conductive layer M1.

[0091] In some embodiments, as shown in Figure 6, the gate driving unit GOA includes an output circuit 16 and an output control circuit 15; the orthographic projection of the main body VSS21 on the substrate substrate does not overlap with the orthographic projection of the output circuit 16 and the output control circuit 15 in the gate driving circuit on the substrate substrate, thereby avoiding the influence of the third power line VSS on the output circuit 16 and the output control circuit 15 of the gate driving unit GOA.

[0092] In some embodiments, a planarization layer is provided between the first conductive layer M1 and the second conductive layer M2; the first connection via V1 and the second connection via V2 respectively penetrate the planarization layer; the thickness of the planarization layer is between 1.5 and 2.0 μm, which can effectively reduce the parasitic capacitance of the clock signal line.

[0093] In some embodiments, as shown in Figure 6 and Figures 10 to 13, the driving circuit layer includes a semiconductor layer 01, a third conductive layer M3, a fourth conductive layer M4 and a fifth conductive layer M5 sequentially arranged on the base substrate; the active layer of each transistor in the gate driving circuit is located in the semiconductor layer 01; the control electrode of each transistor in the gate driving circuit, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 are all located in the third conductive layer M3; the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 in the gate driving circuit are both located in the fourth conductive layer M4; the first electrode and the second electrode of each transistor in the gate driving circuit are both located in the fifth conductive layer M5.

[0094] In some embodiments, as shown in FIG. 14 , the gate driving unit GOA includes an input circuit 11 , a first control circuit 12 , a second control circuit 13 , a third control circuit 14 , an output control circuit 15 , and an output circuit 16 . Among them, the input circuit 11 is configured to input the input signal transmitted by the input signal line GSTV to the first node N1 in response to receiving the first clock signal from the first clock signal terminal CK; the first control circuit 12 is configured to control the level of the second node N2 in response to the first voltage signal VL transmitted by the first power line VGL, the level of the first node N1 and the first clock signal; the second control circuit 13 is configured to control the level of the first node N1 in response to the level of the second node N2, the second clock signal from the second clock signal terminal CB and the second voltage signal VH transmitted by the second power line VGH; the third control circuit 14 is configured to control the level of the third node N3 in response to the level of the first node N1 and the second clock signal from the second clock signal terminal CB; the output control circuit 15 is configured to control the level of the output terminal OUT in response to the level of the second node N2 and the second voltage signal VH; the output circuit 16 is configured to output the second clock signal from the second clock signal terminal CB to the output terminal OUT in response to the level of the third node N3.

[0095] For example, in the embodiment of the present disclosure, the gate drive unit GOA can be an 8T2C (8 transistors 2 capacitors) circuit. FIG14 is a circuit diagram of the 8T2C circuit provided in the embodiment of the present disclosure. As shown in FIG14 , the input circuit 11 includes a first transistor T1; the control electrode of the first transistor T1 is connected to the first clock signal terminal CK, the second electrode of the first transistor T1 is connected to the input terminal STV, and the first electrode of the first transistor T1 is connected to the first node N1. The first control circuit 12 includes a second transistor T2 and a third transistor T3; the control electrode of the second transistor T2 is connected to the first node N1, the second electrode of the second transistor T2 is connected to the first clock signal terminal CK (and thus to the first clock signal line), and the first electrode of the second transistor T2 is connected to the second node N2; the control electrode of the third transistor T3 is connected to the first clock signal terminal CK (and thus to the first clock signal line), the second electrode of the third transistor T3 is connected to the first power terminal (and thus to the first power line VGL), and the first electrode of the third transistor T3 is connected to the second node N2. The second control circuit 13 includes a sixth transistor T6 and a seventh transistor T7; the control electrode of the sixth transistor T6 is connected to the second node N2, the first electrode of the sixth transistor T6 is connected to the second power supply terminal (and thus to the second power supply line VGH), and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7; the control electrode of the seventh transistor T7 is connected to the second clock signal terminal CB (and thus to the second clock signal line), and the first electrode of the seventh transistor T7 is connected to the first node N1. The third control circuit 14 includes an eighth transistor T8; the control electrode of the eighth transistor T8 is connected to the first power supply terminal (and thus to the first power supply line VGL), the second electrode of the eighth transistor T8 is connected to the first node N1, and the first electrode of the eighth transistor T8 is connected to the third node N3. The output control circuit 15 includes a fourth transistor T4 and a first capacitor C1; the control electrode of the fourth transistor T4 is connected to the second node N2, the first electrode of the fourth transistor T4 is connected to the second power supply terminal (and thus to the second power supply line VGH), and the second electrode of the fourth transistor T4 is connected to the output terminal OUT (and thus to the fourth switching electrode); the first plate C11 of the first capacitor C1 is connected to the second node N2, and the second plate C12 of the first capacitor C1 is connected to the second power supply terminal (the second power supply line VGH). The output circuit 16 includes a fifth transistor T5 and a second capacitor C2; the control electrode of the fifth transistor T5 is connected to the third node N3, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CB (and thus to the second clock signal line), and the second electrode of the fifth transistor T5 is connected to the output terminal OUT (and thus to the fourth switching electrode); the first plate C21 of the second capacitor C2 is connected to the third node N3, and the second plate C22 of the second capacitor C2 is connected to the output terminal OUT (and thus to the fourth switching electrode).

[0096] It should be noted that the first transistor T1 to the eighth transistor T8 are all described above using P-type transistors as an example, that is, each transistor is turned on (on-level) when the gate is connected to a low level, and is turned off (off-level) when the gate is connected to a high level. In this case, the first electrode of the transistor can be the source, the second electrode of the transistor can be the drain, and the control electrode is the gate.

[0097] Of course, the gate driving unit GOA in the embodiment of the present disclosure is not limited to the 8T2C circuit, and other circuits can also be used.

[0098] For example, FIG15 is a timing diagram of the operation of the 8T2C gate drive circuit shown in FIG14 . As shown in FIG15 , the operation principle of the gate drive circuit is as follows:

[0099] During input phase t1, the first clock signal provided on the first clock signal line GCK is a low-level signal, the second clock signal provided on the second clock signal line GCB is a high-level signal, and the input signal provided on the input signal line GSTV is a low-level signal, for example, equal to the first voltage signal VL. Because the first clock signal is a low-level signal, the first transistor T1 is turned on, and the input signal is transmitted to the first node N1 via the first transistor T1. Because the first transistor T1 has a threshold loss when transmitting a low-level signal, the voltage at the first node N1 is Vin-Vth1, or VL-Vth1, where Vin represents the voltage of the input signal and Vth1 represents the threshold voltage of the first transistor T1. Because the gate of the eighth transistor T8 receives the first voltage signal VL, the eighth transistor T8 is turned on. Consequently, the voltage VL-Vth1 at the first node N1 is transmitted to the third node N3 via the eighth transistor T8. For example, the threshold voltage of the eighth transistor T8 is represented as Vth8. Similarly, because the eighth transistor T8 has a threshold loss when transmitting a low-level signal, the voltage at the third node N3 is VL-VthN3, where VthN3 is the smaller of Vth1 and Vth8. The voltage at the third node N3 can control the conduction of the fifth transistor T5, and the second clock signal is written to the output terminal OUT via the fifth transistor T5 as the output signal. That is, in the input phase t1, the output signal is the high-level second clock signal, that is, the second voltage signal VH.

[0100] In the input stage t1, since the first clock signal is a low-level signal, the third transistor T3 is turned on, and the first voltage signal VL is transmitted to the second node N2 via the third transistor T3. Since the voltage of the first node N1 is VL - Vth2, the second transistor T2 is turned on, and the low-level first clock signal is transmitted to the second node N2 via the second transistor T2. For example, the threshold voltage of the second transistor T2 is denoted as Vth2, and the threshold voltage of the third transistor T3 is denoted as Vth3. When Vth3 < Vth2 + Vth1, the voltage of the second node N2 is VL - Vth2 - Vth1; when Vth3 > Vth2 + Vth1, the voltage of the second node N2 is VL - Vth3. At this time, both the fourth transistor T4 and the sixth transistor T6 are turned on. Since the second clock signal is a high-level signal, the seventh transistor T7 is turned off.

[0101] In the output stage t2, the first clock signal provided on the first clock signal line GCK is a high-level signal, the second clock signal provided on the second clock signal line GCB is a low-level signal, and the input signal provided on the input signal line GSTV is a high-level signal. The fifth transistor T5 is turned on, and the second clock signal is written to the output terminal OUT via the fifth transistor T5 as the output signal. In the input stage t1, the voltage of the second plate C22 of the second capacitor C2 connected to the output terminal OUT is the second voltage signal VH, and the voltage of the first plate C21 of the second capacitor C2 connected to the third node N3 is VL - VthN3. In the output stage t2, the voltage of the second plate C22 of the second capacitor C2 connected to the output terminal OUT becomes VL. Due to the bootstrap effect of the second capacitor C2, the voltage of the first plate C21 of the second capacitor C2 connected to the third node N3 is 2VL - VthN3 - VH, that is, the voltage of the third node N3 becomes 2VL - VthN3 - VH. At this time, the eighth transistor T8 is turned off, and the fifth transistor T5 can be better turned on, and the output signal is the first voltage signal VL.

[0102] In the output stage t2, the first clock signal is a high-level signal, so both the first transistor T1 and the third transistor T3 are turned off. The voltage of the first node N1 remains VL - VthN3, the second transistor T2 is turned on, and the high-level first clock signal is transmitted to the second node N2 via the second transistor T2, that is, the voltage of the second node N2 is the second voltage signal VH. Thus, both the fourth transistor T4 and the sixth transistor T6 are turned off. Since the second clock signal is a low-level signal, the seventh transistor T7 is turned on.

[0103] During buffering phase t3, the first clock signal provided on the first clock signal line GCK and the second clock signal provided on the second clock signal line GCB are both high-level signals, and the input signal provided on the input signal line GSTV is also high-level. The fifth transistor T5 is turned on, and the second clock signal is written to the output terminal OUTGOUT via the fifth transistor T5 as the output signal. At this point, the output signal is the high-level second clock signal, i.e., the second voltage signal VH. Due to the bootstrapping effect of the second capacitor C2, the voltage at the third node N3 reaches VL - VthN3.

[0104] During the buffering phase t3, the first clock signal is high, turning off both the first transistor T1 and the third transistor T3. The voltage at the third node N3 becomes VL - VthN3. At this point, the eighth transistor T8 is turned on, and the voltage at the first node N1 is also VL - VthN3. The second transistor T2 is turned on, and the high-level first clock signal is transmitted to the second node N2 via the second transistor T2. That is, the voltage at the second node N2 becomes the second voltage signal VH. Consequently, the fourth transistor T4 and the sixth transistor T6 are turned off. Because the second clock signal is high, the seventh transistor T7 is turned off.

[0105] In the first sub-phase t41 of the stable phase t4, the first clock signal provided on the first clock signal line GCK is a low-level signal, the second clock signal provided on the second clock signal line GCB is a high-level signal, and the input signal provided on the input signal line GSTV is a high-level signal, for example, the input signal is equal to the second voltage signal VH. Because the first clock signal is a low-level signal, the first transistor T1 is turned on, and the input signal is transmitted to the first node N1 via the first transistor T1. Because the first transistor T1 transmits a high-level signal without threshold loss, the voltage at the first node N1 is Vin (i.e., the second voltage signal VH), and the second transistor T2 is turned off. Because the eighth transistor T8 is turned on, the voltage at the third node N3 is the same as that at the first node N1. In other words, the voltage at the third node N3 is VH, and the fifth transistor T5 is turned off. Since the first clock signal is a low-level signal, the third transistor T3 is turned on, the voltage of the second node N2 is VL-Vth3, the fourth transistor T4 and the sixth transistor T6 are both turned on, and the second voltage signal VH is transmitted to the output terminal OUT via the fourth transistor T4, that is, the output signal is the second voltage signal VH.

[0106] In the second sub-phase t42 of the stable phase t4, the first clock signal provided on the first clock signal line GCK is a high-level signal, the second clock signal provided on the second clock signal line GCB is a low-level signal, and the input signal provided on the input signal line GSTV is a high-level signal. The voltages at the third node N3 and the first node N1 are Vin (i.e., the second voltage signal VH), and the fifth transistor T5 and the second transistor T2 are both turned off. The first clock signal is a high-level signal, so the first transistor T1 and the third transistor T3 are both turned off. Due to the holding effect of the first capacitor C1, the voltage at the second node N2 remains at VL-Vth3. The fourth transistor T4 and the sixth transistor T6 are both turned on, and the second voltage signal VH is transmitted to the output terminal OUT via the fourth transistor T4, resulting in the output signal being the second voltage signal VH.

[0107] In the second sub-phase t42, since the second clock signal is a low-level signal, the seventh transistor T7 is turned on, so that the second voltage signal VH is transmitted to the first node N1 and the third node N3 via the sixth transistor T6 and the seventh transistor T7, so that the voltage of the third node N3 and the voltage of the first node N1 are maintained at a high level.

[0108] In the third sub-phase t43 of the stable phase t4, the first clock signal provided on the first clock signal line GCK and the second clock signal provided on the second clock signal line GCB are both high-level signals, and the input signal provided on the input signal line GSTV is also high-level. The voltages at the third node N3 and the first node N1 are both VH, and the fifth transistor T5 and the second transistor T2 are turned off. The first clock signal is high-level, so the first transistor T1 and the third transistor T3 are both turned off. The voltage at the second node N2 remains at VL-Vth3, and the fourth transistor T4 and the sixth transistor T6 are both turned on. The second voltage signal VH is transmitted to the output terminal OUT via the fourth transistor T4, and the output signal is the second voltage signal VH.

[0109] For example, as shown in FIG5 , the first clock signal terminal CK of the i-th gate driver unit GOA is connected to the i-th clock signal line, and the second clock signal terminal CB of the i-th gate driver unit GOA is connected to the i+1-th clock signal line. In other words, the second clock signal terminal CB of the i-th gate driver unit GOA and the first clock signal terminal CK of the i+1-th gate driver unit GOA are connected to the same clock signal line. According to the working timing of the clock signal lines (the first clock signal line GCK and the second clock signal line GCB) as shown in Figure 15, taking the second clock signal terminal CB of the first-level gate driving unit GOA and the first clock signal terminal CK of the second-level gate driving unit GOA connected to the second clock signal line (that is, the second clock signal line GCB12) as an example, the second clock signal provided by the second clock signal line GCB12 to the first-level gate driving unit GOA in the input stage t1 is a high-level signal. In the next stage, that is, the output stage t2, the second clock signal provided by the second clock signal line GCB12 to the first-level gate driving unit GOA is a low-level signal, and the first clock signal provided to the second-level gate driving unit GOA is a low-level signal, so that the second-level gate driving unit GOA enters the input stage t1.

[0110] In this embodiment, the second clock signal terminal CB of the i-th gate driving unit GOA_i and the first clock signal terminal CK of the i+1-th gate driving unit GOA_i+1 are connected to the same clock signal line. The timing principle of the clock signal line is utilized to ensure that the next-level gate driving unit GOA enters the normal working timing, and while reducing the load of the clock signal line, the wiring space of the overall clock signal line is reduced.

[0111] 16 is a plan view of the stack of the semiconductor layer 01 and the third conductive layer M3 provided in an embodiment of the present disclosure. FIG17 is a plan view of the stack of the semiconductor layer 01, the third conductive layer M3, the fourth conductive layer M4, and the fifth conductive layer M5 provided in an embodiment of the present disclosure.

[0112] In some embodiments, as shown in Figures 6, 11, 12, 13, and 17, the fourth conductive layer M4 further includes a first transfer electrode S1 for connecting the control electrode T63 of the sixth transistor T6 and the first electrode T21 of the second transistor T2. Specifically, the fifth conductive layer M5 further includes a fifth transfer electrode S5, one end of the fifth transfer electrode S5 being connected to the control electrode T63 of the sixth transistor T6, and the other end being connected to one end of the first transfer electrode S1, and the other end of the first transfer electrode S1 being connected to the first electrode T21 of the second transistor T2.

[0113] In some embodiments, as shown in Figures 11, 13, 16 and 17, the control electrode T33 of the third transistor T3 and the control electrode T13 of the first transistor T1 are connected as an integrated structure and connected to the second electrode T22 of the second transistor T2, and the second electrode T22 of the second transistor T2 is multiplexed as the first clock signal terminal CK of the gate driving unit GOA.

[0114] In some embodiments, as shown in Figures 11, 13, 16 and 17, the fifth conductive layer M5 also includes a second switching electrode S2, which is multiplexed as the second clock signal terminal CB of the i-th gate driving unit GOA_i, and the first clock signal terminal CK of the i+1-th gate driving unit GOA_i+1, and is connected to the control electrode T73 of the seventh transistor T7 of the i-th gate driving unit GOA_i, the control electrode T13 of the first transistor T1 in the i+1-th gate driving unit GOA_i+1, and the control electrode T33 of the third transistor T3.

[0115] In this embodiment, the control electrode T73 of the seventh transistor T7 of the i-th gate driving unit GOA_i and the control electrode T13 of the first transistor T1 in the i+1-th gate driving unit GOA_i+1 share the same via hole for connecting to the clock signal line, thereby saving space for the gate driving circuit.

[0116] The embodiment of the present disclosure does not add a new mask, so the design of the present disclosure improves the display quality without increasing the cost.

[0117] In some embodiments, as shown in Figures 11, 13, 16 and 17, the fifth conductive layer M5 also includes a third transfer electrode S3, which connects the control electrode T83 of the eighth transistor T8 in the i-th gate driving unit GOA_i and the second electrode T32 of the third transistor T3 in the i+1-th gate driving unit GOA.

[0118] In this embodiment, the control electrode T83 of the eighth transistor T8 in the i-th gate driving unit GOA_i and the second electrode T32 of the third transistor T3 in the (i+1)-th gate driving unit GOA are connected using the third transfer electrode S3. In this way, the T83 of the previous stage and the T32 of the next stage can share a via hole connected to VGL, thereby saving space in the gate driving circuit.

[0119] In some embodiments, as shown in Figures 13, 16 and 17, the fifth conductive layer M5 also includes a fourth transfer electrode S4, which is multiplexed as the output terminal OUT of the i-th gate driving unit GOA_i and the input terminal STV of the i+1-th gate driving unit GOA, and is connected to the second electrode T52 of the fifth transistor T5 and the second electrode T42 of the fourth transistor T4 in the i-th gate driving unit GOA_i, and the second electrode T12 of the first transistor T1 in the i+1-th gate driving unit GOA_i+1.

[0120] In some embodiments, as shown in FIG11 , the first electrode plate C11 of the first capacitor C1 , the control electrode T43 of the fourth transistor T4 , and the control electrode T63 of the sixth transistor T6 are an integrally formed structure.

[0121] In some embodiments, as shown in FIG11 , the first electrode C21 of the second capacitor C2 and the control electrode T53 of the fifth transistor T5 are an integrally formed structure.

[0122] In some embodiments, as shown in FIG13 , the first electrode T31 of the third transistor T3 and the first electrode T21 of the second transistor T2 are integrally formed.

[0123] In some embodiments, as shown in FIG. 13 , the first electrode T11 of the first transistor T1 and the first electrode T71 of the seventh transistor T7 are integrally formed.

[0124] In some embodiments, as shown in FIG. 13 , the first electrode T61 of the sixth transistor T6 and the first electrode T41 of the fourth transistor T4 are integrally formed and reused as the second power supply terminal (and further connected to the second power line VGH).

[0125] In some embodiments, as shown in FIG13 , the first electrode T51 of the fifth transistor T5 is multiplexed as the second clock signal terminal CB (and further connected to the second clock signal line GCB).

[0126] In some embodiments, as shown in FIG. 13 , the second electrode T22 of the second transistor T2 is multiplexed as the first clock signal terminal CK (and further connected to the first clock signal line GCK).

[0127] In some embodiments, as shown in Figures 10, 11 and 16, the active layer of the fourth transistor T4 and the active layer of the fifth transistor T5 are shared; the active layer of the fourth transistor T4 includes a first semiconductor 41, a second semiconductor 42 and a third semiconductor 43 arranged side by side and at intervals along the first direction X; the orthographic projections of the first semiconductor 41, the second semiconductor 42 and the third semiconductor 43 on the substrate overlap with the orthographic projections of the control electrode T43 of the fourth transistor T4 on the substrate; the orthographic projections of the first semiconductor 41, the second semiconductor 42 and the third semiconductor 43 on the substrate overlap with the orthographic projections of the control electrode T53 of the fifth transistor T5 on the substrate.

[0128] In this embodiment, the active layer of the fourth transistor T4 and the active layer of the fifth transistor T5 are shared, which facilitates fabrication. Furthermore, the active layer is divided into a plurality of first semiconductors 41, second semiconductors 42, and third semiconductors 43, which are spaced apart to isolate static electricity and release stress.

[0129] In some embodiments, as shown in FIG. 7 and FIG. 8 , the first conductive portion VSS1 includes a plurality of openings H extending through the first conductive portion VSS1 along its thickness direction. The plurality of openings H are arranged side by side along the second direction Y to form a column of openings H. The plurality of columns of openings H are arranged side by side along the first direction X.

[0130] The provision of multiple openings in this embodiment facilitates the release of moisture from the organic layer below the third power line VSS.

[0131] In some embodiments, as shown in Figures 6, 7 and 9, the display substrate includes a display area and a non-display area. The display substrate also includes initialization signal lines located in the non-display area and a pixel driving circuit located in the display area; the initialization signal lines Vinit1~3 are located in the second conductive layer M2 and are connected to the pixel driving circuit.

[0132] The pixel driving circuit is, for example, an 8T1C low temperature polycrystalline oxide (LTPO) circuit.

[0133] The present disclosure also provides a display device comprising the display substrate of any of the above-described embodiments. The display device may be, for example, a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, vehicle-mounted device, or any other product with a display function. Other essential components of the display device are readily understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0134] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display substrate, comprising a base substrate, and a gate driving circuit and a plurality of clock signal lines arranged on the base substrate; the gate driving circuit comprises a plurality of cascaded gate driving units; The plurality of clock signal lines are divided into N groups, each group including two clock signal lines; N is a positive integer greater than or equal to 2; For two adjacent gate driving units in every 2N cascaded gate driving units, the first clock signal terminal of the i-th gate driving unit is connected to the i-th clock signal line, and the second clock signal terminal of the i-th gate driving unit is connected to the i+1-th clock signal line, wherein i is a positive integer from 1 to (2N-1), the clock signal lines connected to the first clock signal terminals are different, and the clock signal lines connected to the second clock signal terminals are different; the timing of the i-th clock signal line and the i+1-th clock signal line are opposite; For the 2Nth gate driving unit, the first clock signal end is connected to the 2Nth clock signal line, and the second clock signal end is connected to the 1st clock signal line; the timing of the 2Nth clock signal line is opposite to that of the 1st clock signal line.

2. The display substrate according to claim 1, wherein: A plurality of cascaded gate driving units are arranged side by side along the second direction; Any of the clock signal lines extends along the second direction, and the orthographic projection of any group of the clock signal lines on the substrate overlaps with the orthographic projection of each level of the gate driving units on the substrate.

3. The display substrate according to claim 1, wherein: The display substrate further comprises a driving circuit layer disposed on the base substrate, and a first conductive layer disposed on a side of the driving circuit layer away from the base substrate; Each of the clock signal lines is located in the first conductive layer.

4. The display substrate according to claim 3, wherein: The display substrate further comprises a light emitting device and a third power line; the third power line is connected to the light emitting device; The third power line includes a first conductive portion, a second conductive portion, and a The first conductive portion and the third conductive portion are both located in the first conductive layer; The display substrate further includes a second conductive layer located between the first conductive layer and the driving circuit layer, the second conductive portion is located in the second conductive layer, and the second conductive portion is connected to the first conductive portion through a first connecting via, and the second conductive portion is connected to the second conductive portion through a second connecting via.

5. The display substrate according to claim 4, wherein: The second conductive portion includes a first end portion, a second end portion, and a main body portion connected between the first end portion and the second end portion; the main body portion has an orthographic projection on the base substrate located between the orthographic projection of the first conductive portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate.

6. The display substrate according to claim 5, wherein: The gate driving unit includes an output circuit and an output control circuit; The orthographic projection of the main body on the base substrate has no overlap with the orthographic projection of the output circuit and the output control circuit in the gate driving circuit on the base substrate.

7. The display substrate according to claim 4, wherein: A planarization layer is disposed between the first conductive layer and the second conductive layer; the first connecting via hole and the second connecting via hole respectively penetrate the planarization layer; The thickness of the planarization layer is between 1.5 μm and 2.0 μm.

8. The display substrate according to claim 4, wherein: The display substrate further includes a first power line for transmitting a first voltage signal to the gate driving circuit, a second power line for transmitting a second voltage signal to the gate driving circuit, and an input signal line for providing an input signal to the gate driving circuit; The first power line, the second power line and the input signal line are all located in the second conductive layer.

9. The display substrate according to claim 8, wherein: The display substrate comprises a display area and a non-display area, the first power line, the second power line, the second conductive part and the input signal line are all located in the non-display area, and the first power line is located on a side of the second conductive part away from the display area, and the second power line is located on a side of the second conductive part close to the display area; The input signal line is located between the second power line and the second conductive portion.

10. The display substrate according to claim 3, wherein: The driving circuit layer includes a semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially arranged on the base substrate; The active layer of each transistor in the gate drive circuit is located in the semiconductor layer; The control electrodes of each transistor in the gate drive circuit, the first electrode plate of the first capacitor and the first electrode plate of the second capacitor are all located in the third conductive layer; The second electrode plate of the first capacitor and the second electrode plate of the second capacitor in the gate driving circuit are both located in the fourth conductive layer; The first electrode and the second electrode of each transistor in the gate driving circuit are both located in the fifth conductive layer.

11. The display substrate according to claim 10, wherein: The gate driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The fourth conductive layer further includes a first switching electrode for connecting the control electrode of the sixth transistor and the first electrode of the second transistor.

12. The display substrate according to claim 10, wherein: The gate driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The control electrode of the third transistor and the control electrode of the first transistor are connected as an integrated structure and connected to the second electrode of the second transistor, and the second electrode of the second transistor is multiplexed as the first clock signal terminal of the gate driving unit.

13. The display substrate according to claim 12, wherein: The fifth conductive layer also includes a second transfer electrode, which is multiplexed as the second clock signal end of the i-th gate driving unit and the first clock signal end of the i+1-th gate driving unit, and is connected to the control electrode of the seventh transistor of the i-th gate driving unit, the control electrode of the first transistor in the i+1-th gate driving unit, and the control electrode of the third transistor.

14. The display substrate according to claim 12, wherein: The fifth conductive layer further includes a third switching electrode, and the third switching electrode is connected to the control electrode of the eighth transistor in the i-th stage gate driving unit and the second electrode of the third transistor in the (i+1)-th stage gate driving unit.

15. The display substrate according to claim 12, wherein: The fifth conductive layer also includes a fourth transfer electrode, which is multiplexed as the output end of the i-th gate driving unit and the input end of the i+1-th gate driving unit, and connects the second electrode of the fifth transistor and the second electrode of the fourth transistor in the i-th gate driving unit, and the second electrode of the first transistor in the i+1-th gate driving unit.

16. The display substrate according to claim 10, wherein: The gate driving unit includes a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; The active layer of the fourth transistor is shared by the active layer of the fifth transistor; the active layer of the fourth transistor comprises a first semiconductor, a second semiconductor and a third semiconductor which are arranged side by side and spaced apart along a first direction; The orthographic projections of the first semiconductor, the second semiconductor and the third semiconductor on the substrate overlap with the orthographic projections of the control electrode of the fourth transistor on the substrate respectively; The orthographic projections of the first semiconductor, the second semiconductor, and the third semiconductor on the substrate overlap with the orthographic projections of the control electrode of the fifth transistor on the substrate.

17. The display substrate according to claim 4, wherein: The first conductive part includes a plurality of openings penetrating along the thickness direction thereof, and the plurality of openings are arranged side by side along the second direction to form a row of openings; and the plurality of rows of openings are arranged side by side along the first direction.

18. The display substrate according to claim 4, wherein: The display substrate comprises a display area and a non-display area, and the display substrate further comprises an initialization signal line located in the non-display area and a pixel driving circuit located in the display area; The initialization signal line is located in the second conductive layer and connected to the pixel driving circuit.

19. A display device, wherein: The display substrate comprises the display substrate as claimed in any one of claims 1 to 18.

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