Automatic frequency detection circuit and method based on COT architecture DCDC

Abstract

The invention discloses an automatic frequency detection circuit and method based on a COT architecture DCDC, the automatic frequency detection circuit comprises a detection time generation circuit DETIMER, an FPWM duration generation circuit FPWMTIMER and a detection logic circuit DETLOGIC, a signal HSON is used as frequency information input, a signal RCP is used as a timing starting signal, and after detection is completed, the signal FPWMEN is output to a ZCD module to close zero-crossing limitation, so that a DCDC system enters an FPWM mode. Output current and voltage information does not need to be sampled, and frequency change is detected in real time.

Description

Technical Field

[0001] The present invention relates to a frequency detection circuit and method, in particular to an automatic frequency detection circuit and method based on a COT architecture DCDC, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] With the continuous growth of electronic products in consumer electronics, industrial electronics, and automotive electronics, the demand for power management ICs continues to rise, such as DC-DC switching power supplies, which are widely used. At the same time, as the load of electronic equipment increases and the power increases, the demand for high-voltage and high-current DC-DC is increasing. In order to further increase the input voltage, it means that the duty cycle is further reduced. The COT control method is usually used. As the input voltage rises, the frequency is reduced to meet the requirements of extremely small duty cycles.

[0003] The traditional COT control method of DC-DC switching power supply has a fast dynamic response speed, but when switching from heavy load to light load, it is limited by the fixed on-time. The frequency is very low under light load, and the inductor current regulation is slow, because the output voltage regulation is slow. There are several main ways to optimize the dynamic performance. The key is to introduce the information of the inductor current change through the loop for adaptive adjustment. One is to change the fixed on-time, such as Figure 1 As shown in the figure, the AOT structure is used for regulation; the second is to adjust the PWM signal by sampling the inductor current information. The above optimization methods can make the switching frequency change slowly when the output voltage or load current changes suddenly, thereby improving the dynamic response speed.

[0004] However, the problem with adaptive frequency regulation is that it requires the use of an inductor current signal for feedback. First, there is a speed delay in sampling, and second, there is also a delay in the feedback loop, making it impossible to provide feedback and adjust the sudden change in a timely manner. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an automatic frequency detection circuit and method based on a COT architecture DCDC, which can detect frequency changes in real time without sampling output current and voltage information.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: An automatic frequency detection circuit based on a COT architecture DCDC comprises a detection time generation circuit DET_TIMER, an FPWM duration generation circuit FPWM_TIMER and a detection logic circuit DET_LOGIC. The detection time generation circuit DET_TIMER counts time T_DET. The detection logic circuit DET_LOGIC detects whether N cycles are exceeded within the time T_DET. If exceeded, the detection time generation circuit DET_TIMER is reset. If not exceeded, the FPWM duration generation circuit FPWM_TIMER is started. After receiving a start signal, the FPWM duration generation circuit FPWM_TIMER starts to count time T_FPWM and outputs a signal FPWM_EN to a ZCD module within the time T_FPWM to turn off zero-crossing restriction so that a DCDC system enters an FPWM mode.

[0007] Furthermore, the detection time generating circuit DET_TIMER includes a current source IDET, a detection capacitor CDET, an NMOS tube NM1, an NMOS tube NM2 and a Schmitt trigger SMIT1, the positive electrode of the current source IDET is connected to the power supply AVDD, the negative electrode of the current source IDET is connected to the input end of the Schmitt trigger SMIT1, one end of the detection capacitor CDET, the drain of the NMOS tube NM1 and the drain of the NMOS tube NM2 and generates a signal VC_DET, the gate of the NMOS tube NM1 is connected to the signal TIME_OUT_CLRB, the gate of the NMOS tube NM2 is connected to the signal TIMER_START, the source of the NMOS tube NM1, the source of the NMOS tube NM2 and the other end of the detection capacitor CDET are grounded, and the output end of the Schmitt trigger SMIT1 outputs the signal TIMER_OUT.

[0008] Furthermore, the FPWM duration generation circuit FPWM_TIMER includes a current source IEXT, a charging capacitor CEXT, an NMOS tube NM3, an NMOS tube NM4, a PMOS tube PM1, a Schmitt trigger SMIT2 and an invertor INV4, the positive electrode of the current source IEXT and the source electrode of the PMOS tube PM1 are connected to the power supply AVDD, the negative electrode of the current source IEXT is connected to the drain electrode of the NMOS tube NM4, the gate electrode of the NMOS tube NM4 and the gate electrode of the PMOS tube PM1 are connected to the signal TFPWM_START, and the NM The source of the OS transistor NM4 is connected to the drain of the PMOS transistor PM1, the input end of the Schmitt trigger SMIT2, one end of the charging capacitor CEXT and the drain of the NMOS transistor NM3 to generate a signal VC_EXT, the gate of the NMOS transistor NM3 is connected to the signal TFPWM_CLR, the source of the NMOS transistor NM3 and the other end of the charging capacitor CEXT are grounded, the output end of the Schmitt trigger SMIT2 is connected to the input end of the invertor INV4 and outputs a signal FPWM_EN, and the output end of the invertor INV4 outputs a signal FPWM_ENB.

[0009] Furthermore, the detection logic circuit DET_LOGIC includes AND gates AND1, AND gates AND3, D flip-flops DFF1~DFFN, N-1 input AND gates AND4, NOT gates INV1, INV2, INV3, OR gates OR1, pulse generators OS1, OS2, OS3, three-input AND gates AND2, D flip-flops DFF_CO and D flip-flops DFF_TS, the first input end of the AND gate AND1 is connected to the signal HSON, the second input end of the AND gate AND1 is connected to the signal COUNT_OVERB, the output end of the AND gate AND1 is connected to the CK end of the D flip-flop DFF1, and the nth D flip-flop among the D flip-flops DFF1~DFFN DFFn, n=2, 3, ..., N, the Q terminal of the D flip-flop DFF1 generates a signal Q1, the QN terminal of the D flip-flop DFFn-1 is connected to the D terminal of the D flip-flop DFFn-1 and the CK terminal of the D flip-flop DFFn, the Q terminals of the D flip-flops DFF2 to DFFN are sequentially connected to the N-1 input terminals of the N-1 input AND gate AND4, the output terminal of the N-1 input AND gate AND4 is connected to the input terminal of the invertor INV1 and the CK terminal of the D flip-flop DFF_CO and generates a signal COUNT_OVER, the output terminal of the invertor INV1 outputs the signal COUNT_OVERB, the first input terminal of the AND gate AND3 is connected to the signal COUNT_OVERB, and the second input terminal of the AND gate AND3 is connected to the The output of the AND gate AND3 is connected to the first input of the three-input AND gate AND2, the input of the pulse generator OS1 is connected to the signal TIMER_OUT, the output of the pulse generator OS1 is connected to the input of the inverter INV2 and generates the signal TIME_OUT_CLRB, the output of the inverter INV2 is connected to the second input of the three-input AND gate AND2 and generates the signal TIME_OUT_CLR, the first input of the OR gate OR1 is connected to the signal FPWM_ENB, the second input of the OR gate OR1 is connected to the signal Q1, the output of the OR gate OR1 is connected to the input of the pulse generator OS2, the output of the pulse generator OS2 is connected to the input of the inverter INV3 and generates signal TIMER_START, the output end of the invertor INV3 is connected to the third input end of the three-input AND gate AND2 and the RN end of the D flip-flop DFF_CO and generates a signal RESET1_B, the output end of the three-input AND gate AND2 is connected to the RN ends of the D flip-flops DFF1~DFFN and generates a signal RESET2_B, the QN end of the D flip-flop DFF_CO is connected to the D end of the D flip-flop DFF_CO, the Q end of the D flip-flop DFF_CO is connected to the RN end of the D flip-flop DFF_TS, the CK end of the D flip-flop DFF_TS is connected to the signal RCP, the Q end of the D flip-flop DFF_TS is connected to the input end of the pulse generator OS3 and generates a signal TFPWM_START,The output end of OS3 generates a signal TFPWM_CLR, and the SN ends of the D flip-flops DFF1 to DFFN, the SN end of the D flip-flop DFF_CO, the SN end of the D flip-flop DFF_TS, and the D end of the D flip-flop DFF_TS are connected to the power supply AVDD.

[0010] Furthermore, the signal HSON is output by a LOGIC module.

[0011] Furthermore, the signal RCP is output by a ZCD module.

[0012] A detection method of an automatic frequency detection circuit based on a COT architecture DCDC comprises the following steps: In the detection time generating circuit DET_TIMER, when the first cycle arrives, the signal TIMER_START inputs a high narrow pulse signal, the NMOS tube NM2 is turned on to discharge the residual charge on the detection capacitor CDET to the ground, and then the NMOS tube NM2 is turned off to ensure that the timing start time signal VC_DET is 0. At this time, the current of the current source IDET flows to the detection capacitor CDET to charge the detection capacitor CDET, and the signal VC_DET begins to gradually increase until after the time T_DET, the signal TIMER_OUT turns high and returns to the detection logic circuit DET_LOGIC. After the detection logic circuit DET_LOGIC detects and returns the signal TIME_OUT_CLRB, the signal VC_DET is pulled low, and the signal TIMER_OUT is pulled low; In the FPWM duration generation circuit FPWM_TIMER, when the signal TFPWM_START turns high, the signal VC_EXT is pulled low when the signal TFPWM_CLR turns high. Then, because the signal TFPWM_START is high, the PMOS tube PM1 is turned off, the NMOS tube NM4 is turned on, and the current of the current source IEXT flows to the charging capacitor CEXT and charges the charging capacitor CEXT. The signal VC_EXT on the upper plate of the charging capacitor CEXT begins to gradually increase until the time T_FPWM, the signal FPWM_EN turns high and is output to the ZCD module for FPWM mode control; the signal FPWM_ENB turns low and returns to the detection logic circuit DET_LOGIC; In the detection logic circuit DET_LOGIC, when the signal HSON turns high, since the signal COUNT_OVERB is initially high, the output signal of the AND gate AND1 turns high. After the CK end of the D flip-flop DFF1 turns high, since the D end of the D flip-flop DFF1 is connected to the QN end, the initial value is high, so the signal Q1 turns high. At this time, the output signal of the OR gate OR1 turns high, and after the pulse processing of the pulse generator OS2, the output signal TIMER_START is a narrow pulse high signal. The narrow pulse of the signal TIMER_START is output to the detection time generation circuit DET_T IMER, after the timing time T_DET, the signal TIMER_OUT turns high; if the signal COUNT_OVER turns high during this period, it means that the frequency of the signal HSON is high; if the signal COUNT_OVER does not turn high, it means that the frequency of the signal HSON is low, then the signal TFPWM_START and the signal TFPWM_CLR turn high and are output to the FPWM duration generation circuit FPWM_TIMER. After the timing time T_FPWM, the signal FPWM_EN is output to the ZCD module to control the DCDC system to enter the FPWM mode within the time T_FPWM.

[0013] Compared with the prior art, the present invention has the following advantages and effects: the present invention provides an automatic frequency detection circuit and method based on COT architecture DCDC, which can detect frequency changes in real time without sampling output current and voltage information; when the load current suddenly changes and the DCDC system enters DCM from CCM, the frequency change can be detected through the cyclic T_DET time window, and FPWM can be turned on in the first cycle of the frequency change, and the T_FPWM time is maintained, and the inductor current is adjusted before returning to DCM. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 It is a schematic diagram of an automatic frequency detection circuit based on COT architecture DCDC of the present invention.

[0015] Figure 2 It is a circuit diagram of the detection time generating circuit DET_TIMER of the present invention.

[0016] Figure 3 4 is a circuit diagram of an FPWM duration generating circuit FPWM_TIMER of the present invention.

[0017] Figure 4 It is a circuit diagram of the detection logic circuit DET_LOGIC of the present invention.

[0018] Figure 5 It is a detection timing diagram of an automatic frequency detection circuit based on a COT architecture DCDC of the present invention.

[0019] Figure 6 Schematic diagram of a DCDC system using automatic frequency detection technology in the prior art. DETAILED DESCRIPTION

[0020] In order to elaborate on the technical scheme adopted by the present invention to achieve the predetermined technical purpose, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and the technical means or technical features in the embodiments of the present invention can be replaced without paying creative work. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0021] like Figure 1 As shown, an automatic frequency detection circuit based on a COT architecture DCDC of the present invention comprises a detection time generation circuit DET_TIMER, an FPWM duration generation circuit FPWM_TIMER and a detection logic circuit DET_LOGIC. The detection time generation circuit DET_TIMER counts the time T_DET. The detection logic circuit DET_LOGIC detects whether it exceeds N cycles within the time T_DET. If it exceeds, the detection time generation circuit DET_TIMER is reset, and the detection time generation circuit DET_TIMER performs the next timing; if it does not exceed, the FPWM duration generation circuit FPWM_TIMER is started. After receiving the start signal, the FPWM duration generation circuit FPWM_TIMER starts the timing time T_FPWM and outputs a signal FPWM_EN to the ZCD module within the time T_FPWM to turn off the zero-crossing limit and make the DCDC system enter the FPWM mode. The present invention detects the change of frequency through the cyclic T_DET time window. When the heavy load is switched to the light load and the frequency suddenly decreases, the FPWM is turned on in the first cycle of the frequency change, and the T_FPWM time is maintained. After the inductor current is adjusted, it returns to the low frequency of the light load. The present invention adopts the HSON signal output by the system LOGIC as the frequency information input, and adopts the RCP signal output by the system zero-crossing detection module ZCD as the timing start signal. After the detection is completed, the FPWM_EN signal is output, the ZCD module of the system is connected, the zero-crossing limit is turned off, and the system enters the FPWM mode.

[0022] like Figure 2As shown, the detection time generating circuit DET_TIMER includes a current source IDET, a detection capacitor CDET, an NMOS tube NM1, an NMOS tube NM2 and a Schmitt trigger SMIT1, the positive electrode of the current source IDET is connected to the power supply AVDD, the negative electrode of the current source IDET is connected to the input end of the Schmitt trigger SMIT1, one end of the detection capacitor CDET, the drain of the NMOS tube NM1 and the drain of the NMOS tube NM2 and generates a signal VC_DET, the gate of the NMOS tube NM1 is connected to the signal TIME_OUT_CLRB, the gate of the NMOS tube NM2 is connected to the signal TIMER_START, the source of the NMOS tube NM1, the source of the NMOS tube NM2 and the other end of the detection capacitor CDET are grounded, and the output end of the Schmitt trigger SMIT1 outputs the signal TIMER_OUT.

[0023] like Figure 3 As shown, the FPWM duration generating circuit FPWM_TIMER includes a current source IEXT, a charging capacitor CEXT, an NMOS tube NM3, an NMOS tube NM4, a PMOS tube PM1, a Schmitt trigger SMIT2 and an NOT gate INV4, the positive electrode of the current source IEXT and the source electrode of the PMOS tube PM1 are connected to the power supply AVDD, the negative electrode of the current source IEXT is connected to the drain electrode of the NMOS tube NM4, the gate electrode of the NMOS tube NM4 and the gate electrode of the PMOS tube PM1 are connected to the signal TFPWM_START, and the NMOS The source of the transistor NM4 is connected to the drain of the PMOS transistor PM1, the input end of the Schmitt trigger SMIT2, one end of the charging capacitor CEXT and the drain of the NMOS transistor NM3 to generate a signal VC_EXT, the gate of the NMOS transistor NM3 is connected to the signal TFPWM_CLR, the source of the NMOS transistor NM3 and the other end of the charging capacitor CEXT are grounded, the output end of the Schmitt trigger SMIT2 is connected to the input end of the invertor INV4 and outputs a signal FPWM_EN, and the output end of the invertor INV4 outputs a signal FPWM_ENB.

[0024] like Figure 4As shown, the detection logic circuit DET_LOGIC includes AND gates AND1, AND gates AND3, D flip-flops DFF1~DFFN, N-1 input AND gates AND4, NOT gates INV1, INV2, INV3, OR gates OR1, pulse generators OS1, OS2, OS3, three-input AND gates AND2, D flip-flops DFF_CO and D flip-flops DFF_TS, the first input terminal of the AND gate AND1 is connected to the signal HSON, the second input terminal of the AND gate AND1 is connected to the signal COUNT_OVERB, the output terminal of the AND gate AND1 is connected to the CK terminal of the D flip-flop DFF1, and the nth D flip-flop DFF among the D flip-flops DFF1~DFFN is connected to the CK terminal of the D flip-flops DFF1. n, n=2, 3, …, N, the Q terminal of the D flip-flop DFF1 generates a signal Q1, the QN terminal of the D flip-flop DFFn-1 is connected to the D terminal of the D flip-flop DFFn-1 and the CK terminal of the D flip-flop DFFn, the Q terminals of the D flip-flops DFF2~DFFN are sequentially connected to the N-1 input terminals of the N-1 input AND gate AND4, the output terminal of the N-1 input AND gate AND4 is connected to the input terminal of the invertor INV1 and the CK terminal of the D flip-flop DFF_CO and generates a signal COUNT_OVER, the output terminal of the invertor INV1 outputs the signal COUNT_OVERB, the first input terminal of the AND gate AND3 is connected to the signal COUNT_OVERB, and the second input terminal of the AND gate AND3 is connected to the signal The output of the AND gate AND3 is connected to the first input of the three-input AND gate AND2, the input of the pulse generator OS1 is connected to the signal TIMER_OUT, the output of the pulse generator OS1 is connected to the input of the NOT gate INV2 and generates the signal TIME_OUT_CLRB, the output of the NOT gate INV2 is connected to the second input of the three-input AND gate AND2 and generates the signal TIME_OUT_CLR, the first input of the OR gate OR1 is connected to the signal FPWM_ENB, the second input of the OR gate OR1 is connected to the signal Q1, the output of the OR gate OR1 is connected to the input of the pulse generator OS2, the output of the pulse generator OS2 is connected to the input of the NOT gate INV3 and generates the signal signal TIMER_START, the output end of the invertor INV3 is connected to the third input end of the three-input AND gate AND2 and the RN end of the D flip-flop DFF_CO and generates a signal RESET1_B, the output end of the three-input AND gate AND2 is connected to the RN ends of the D flip-flops DFF1~DFFN and generates a signal RESET2_B, the QN end of the D flip-flop DFF_CO is connected to the D end of the D flip-flop DFF_CO, the Q end of the D flip-flop DFF_CO is connected to the RN end of the D flip-flop DFF_TS, the CK end of the D flip-flop DFF_TS is connected to the signal RCP, the Q end of the D flip-flop DFF_TS is connected to the input end of the pulse generator OS3 and generates a signal TFPWM_START,The output end of OS3 generates a signal TFPWM_CLR, and the SN ends of the D flip-flops DFF1 to DFFN, the SN end of the D flip-flop DFF_CO, the SN end of the D flip-flop DFF_TS, and the D end of the D flip-flop DFF_TS are connected to the power supply AVDD.

[0025] The signal HSON is obtained by the output of the LOGIC module. The signal RCP is obtained by the output of the ZCD module.

[0026] A detection method of an automatic frequency detection circuit based on a COT architecture DCDC comprises the following steps: In the detection time generating circuit DET_TIMER, when the first cycle arrives, the signal TIMER_START inputs a high narrow pulse signal, the NMOS tube NM2 is turned on to discharge the residual charge on the detection capacitor CDET to the ground, and then the NMOS tube NM2 is turned off to ensure that the timing start time signal VC_DET is 0. At this time, the current of the current source IDET flows to the detection capacitor CDET to charge the detection capacitor CDET, and the signal VC_DET begins to gradually increase until after time T_DET, the signal TIMER_OUT turns high and returns to the detection logic circuit DET_LOGIC. After the detection logic circuit DET_LOGIC returns the signal TIME_OUT_CLRB, pulls the signal VC_DET low, and the signal TIMER_OUT is pulled low.

[0027] In the FPWM duration generating circuit FPWM_TIMER, when the signal TFPWM_START turns high, the signal VC_EXT is pulled low when the signal TFPWM_CLR turns high. Then, since the signal TFPWM_START is high, the PMOS tube PM1 is turned off, the NMOS tube NM4 is turned on, and the current of the current source IEXT flows to the charging capacitor CEXT and charges the charging capacitor CEXT. The signal VC_EXT on the upper plate of the charging capacitor CEXT begins to gradually increase. After the time T_FPWM, the signal FPWM_EN turns high and is output to the ZCD module for controlling the FPWM mode; the signal FPWM_ENB turns low and is returned to the detection logic circuit DET_LOGIC.

[0028] In the detection logic circuit DET_LOGIC, when the signal HSON turns high, since the signal COUNT_OVERB is initially high, the output signal of the AND gate AND1 turns high. After the CK end of the D flip-flop DFF1 turns high, since the D end of the D flip-flop DFF1 is connected to the QN end, the initial value is high, so the signal Q1 turns high. At this time, the output signal of the OR gate OR1 turns high, and after the pulse processing of the pulse generator OS2, the output signal TIMER_START is a narrow pulse high signal. The narrow pulse of the signal TIMER_START is output to the detection time generation circuit DET_T IMER, after the timing time T_DET, the signal TIMER_OUT turns high; if the signal COUNT_OVER turns high during this period, it means that the frequency of the signal HSON is high; if the signal COUNT_OVER does not turn high, it means that the frequency of the signal HSON is low, then the signal TFPWM_START and the signal TFPWM_CLR turn high and are output to the FPWM duration generation circuit FPWM_TIMER. After the timing time T_FPWM, the signal FPWM_EN is output to the ZCD module to control the DCDC system to enter the FPWM mode within the time T_FPWM.

[0029] like Figure 5 As shown, the frequency of the signal HSON of the DCDC system is maintained high before time t4, and the first flip of the signal Q1 is at time t1, and the detection time generation circuit DET_TIMER starts timing. At time t3 after T_DET time, the signal TIMER_OUT turns high; at the same time, the signal Q2 and QN are ANDed, and the signal COUNT_OVER turns high at time t2. This shows that before time t3, the frequency of the signal HSON is consistently high, and the timing of T_FPWM will not be turned on. The detection result is consistent with the frequency result of the actual signal HSON. At time t4, the frequency of the signal HSON suddenly becomes low, and the signal TIMER_OUT turns high at time t5 after timing T_DET. During this period, the signal COUNT_OVER has been low, indicating that the frequency is low at this time. When the signal RCP of the DCDC system turns high at time t6, the signal TFPWM_START turns high. After the timing T_FPWM time, at time t7, the signal TFPWM_START turns low and the timing ends. The system has been working in FPWM mode during this process. After time t7, the FPWM mode is exited and the frequency of the signal HSON decreases. T_DET, the number of D flip-flops DFFN and the value of time T_FPWM can be set according to the switching frequency of the actual application, so that it can be applied to the DCDC system of COT architecture at any frequency.

[0030] The present invention provides an automatic frequency detection circuit and method based on COT architecture DCDC, which can detect frequency changes in real time without sampling output current and voltage information; when the load current suddenly changes and the DCDC system enters DCM from CCM, the frequency change can be detected through the cyclic T_DET time window, and FPWM is turned on in the first cycle of the frequency change, and the T_FPWM time is maintained, and the inductor current is regulated before returning to DCM.

[0031] The above is only a preferred embodiment of the present invention and does not limit the present invention in any form. Although the present invention has been disclosed as a preferred embodiment as above, it is not used to limit the present invention. Any technician familiar with this profession can make some changes or modify the technical contents disclosed above into equivalent embodiments without departing from the scope of the technical solution of the present invention. However, any simple modification, equivalent replacement and improvement made to the above embodiments without departing from the content of the technical solution of the present invention, based on the technical essence of the present invention, within the spirit and principles of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims

1. An automatic frequency detection circuit based on COT architecture DCDC, characterized in that: It includes a detection time generating circuit DET_TIMER, an FPWM duration generating circuit FPWM_TIMER and a detection logic circuit DET_LOGIC. The detection time generating circuit DET_TIMER counts the time T_DET. The detection logic circuit DET_LOGIC detects whether N cycles are exceeded within the time T_DET. If exceeded, the detection time generating circuit DET_TIMER is reset. If not exceeded, the FPWM duration generating circuit FPWM_TIMER is started. After receiving a start signal, the FPWM duration generating circuit FPWM_TIMER starts to count the time T_FPWM and outputs a signal FPWM_EN to the ZCD module within the time T_FPWM to turn off the zero-crossing limit so that the DCDC system enters the FPWM mode.

2. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The detection time generating circuit DET_TIMER includes a current source IDET, a detection capacitor CDET, an NMOS tube NM1, an NMOS tube NM2 and a Schmitt trigger SMIT1. The positive electrode of the current source IDET is connected to the power supply AVDD, the negative electrode of the current source IDET is connected to the input end of the Schmitt trigger SMIT1, one end of the detection capacitor CDET, the drain of the NMOS tube NM1 and the drain of the NMOS tube NM2 and generates a signal VC_DET, the gate of the NMOS tube NM1 is connected to the signal TIME_OUT_CLRB, the gate of the NMOS tube NM2 is connected to the signal TIMER_START, the source of the NMOS tube NM1, the source of the NMOS tube NM2 and the other end of the detection capacitor CDET are grounded, and the output end of the Schmitt trigger SMIT1 outputs the signal TIMER_OUT.

3. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The FPWM duration generation circuit FPWM_TIMER comprises a current source IEXT, a charging capacitor CEXT, an NMOS tube NM3, an NMOS tube NM4, a PMOS tube PM1, a Schmitt trigger SMIT2 and an invertor INV4, the positive electrode of the current source IEXT and the source electrode of the PMOS tube PM1 are connected to the power supply AVDD, the negative electrode of the current source IEXT is connected to the drain electrode of the NMOS tube NM4, the gate electrode of the NMOS tube NM4 and the gate electrode of the PMOS tube PM1 are connected to the signal TFPWM_START, the NMOS The source of the transistor NM4 is connected to the drain of the PMOS transistor PM1, the input end of the Schmitt trigger SMIT2, one end of the charging capacitor CEXT and the drain of the NMOS transistor NM3 to generate a signal VC_EXT, the gate of the NMOS transistor NM3 is connected to the signal TFPWM_CLR, the source of the NMOS transistor NM3 and the other end of the charging capacitor CEXT are grounded, the output end of the Schmitt trigger SMIT2 is connected to the input end of the invertor INV4 and outputs a signal FPWM_EN, and the output end of the invertor INV4 outputs a signal FPWM_ENB.

4. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The detection logic circuit DET_LOGIC comprises AND gates AND1, AND gates AND3, D flip-flops DFF1 to DFFN, N-1 input AND gates AND4, NOT gates INV1, INV2, INV3, OR gates OR1, pulse generators OS1, OS2, OS3, three-input AND gates AND2, D flip-flops DFF_CO and D flip-flops DFF_TS, the first input end of the AND gate AND1 is connected to the signal HSON, the second input end of the AND gate AND1 is connected to the signal COUNT_OVERB, the output end of the AND gate AND1 is connected to the CK end of the D flip-flop DFF1, and the nth D flip-flop DFFn among the D flip-flops DFF1 to DFFN is connected to the CK end of the D flip-flops DFF1 to DFFN. , n=2, 3, ..., N, the Q terminal of the D flip-flop DFF1 generates a signal Q1, the QN terminal of the D flip-flop DFFn-1 is connected to the D terminal of the D flip-flop DFFn-1 and the CK terminal of the D flip-flop DFFn, the Q terminals of the D flip-flops DFF2 to DFFN are sequentially connected to the N-1 input terminals of the N-1 input AND gate AND4, the output terminal of the N-1 input AND gate AND4 is connected to the input terminal of the invertor INV1 and the CK terminal of the D flip-flop DFF_CO and generates a signal COUNT_OVER, the output terminal of the invertor INV1 outputs the signal COUNT_OVERB, the first input terminal of the AND gate AND3 is connected to the signal COUNT_OVERB, and the second input terminal of the AND gate AND3 is connected to the signal RCP, the output of the AND gate AND3 is connected to the first input of the three-input AND gate AND2, the input of the pulse generator OS1 is connected to the signal TIMER_OUT, the output of the pulse generator OS1 is connected to the input of the NOT gate INV2 and generates the signal TIME_OUT_CLRB, the output of the NOT gate INV2 is connected to the second input of the three-input AND gate AND2 and generates the signal TIME_OUT_CLR, the first input of the OR gate OR1 is connected to the signal FPWM_ENB, the second input of the OR gate OR1 is connected to the signal Q1, the output of the OR gate OR1 is connected to the input of the pulse generator OS2, the output of the pulse generator OS2 is connected to the input of the NOT gate INV3 and generates the signal signal TIMER_START, the output end of the invertor INV3 is connected to the third input end of the three-input AND gate AND2 and the RN end of the D flip-flop DFF_CO and generates a signal RESET1_B, the output end of the three-input AND gate AND2 is connected to the RN ends of the D flip-flops DFF1~DFFN and generates a signal RESET2_B, the QN end of the D flip-flop DFF_CO is connected to the D end of the D flip-flop DFF_CO, the Q end of the D flip-flop DFF_CO is connected to the RN end of the D flip-flop DFF_TS, the CK end of the D flip-flop DFF_TS is connected to the signal RCP, the Q end of the D flip-flop DFF_TS is connected to the input end of the pulse generator OS3 and generates a signal TFPWM_START,The output end of OS3 generates a signal TFPWM_CLR, and the SN ends of the D flip-flops DFF1 to DFFN, the SN end of the D flip-flop DFF_CO, the SN end of the D flip-flop DFF_TS, and the D end of the D flip-flop DFF_TS are connected to the power supply AVDD.

5. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The signal HSON is output by the LOGIC module.

6. The automatic frequency detection circuit based on COT architecture DCDC according to claim 1, characterized in that: The signal RCP is output by the ZCD module.

7. A detection method for an automatic frequency detection circuit based on a COT architecture DCDC according to any one of claims 1 to 6, characterized in that The following steps are involved: In the detection time generating circuit DET_TIMER, when the first cycle arrives, the signal TIMER_START inputs a high narrow pulse signal, the NMOS tube NM2 is turned on to discharge the residual charge on the detection capacitor CDET to the ground, and then the NMOS tube NM2 is turned off to ensure that the timing start time signal VC_DET is 0. At this time, the current of the current source IDET flows to the detection capacitor CDET to charge the detection capacitor CDET, and the signal VC_DET begins to gradually increase until after the time T_DET, the signal TIMER_OUT turns high and returns to the detection logic circuit DET_LOGIC. After the detection logic circuit DET_LOGIC detects and returns the signal TIME_OUT_CLRB, the signal VC_DET is pulled low, and the signal TIMER_OUT is pulled low; In the FPWM duration generation circuit FPWM_TIMER, when the signal TFPWM_START turns high, the signal VC_EXT is pulled low when the signal TFPWM_CLR turns high. Then, because the signal TFPWM_START is high, the PMOS tube PM1 is turned off, the NMOS tube NM4 is turned on, and the current of the current source IEXT flows to the charging capacitor CEXT and charges the charging capacitor CEXT. The signal VC_EXT on the upper plate of the charging capacitor CEXT begins to gradually increase until the time T_FPWM, the signal FPWM_EN turns high and is output to the ZCD module for FPWM mode control; the signal FPWM_ENB turns low and returns to the detection logic circuit DET_LOGIC; In the detection logic circuit DET_LOGIC, when the signal HSON turns high, since the signal COUNT_OVERB is initially high, the output signal of the AND gate AND1 turns high. After the CK end of the D flip-flop DFF1 turns high, since the D end of the D flip-flop DFF1 is connected to the QN end, the initial value is high, so the signal Q1 turns high. At this time, the output signal of the OR gate OR1 turns high, and after the pulse processing of the pulse generator OS2, the output signal TIMER_START is a narrow pulse high signal. The narrow pulse of the signal TIMER_START is output to the detection time generation circuit DET_T IMER, after the timing time T_DET, the signal TIMER_OUT turns high; if the signal COUNT_OVER turns high during this period, it means that the frequency of the signal HSON is high; if the signal COUNT_OVER does not turn high, it means that the frequency of the signal HSON is low, then the signal TFPWM_START and the signal TFPWM_CLR turn high and are output to the FPWM duration generation circuit FPWM_TIMER. After the timing time T_FPWM, the signal FPWM_EN is output to the ZCD module to control the DCDC system to enter the FPWM mode within the time T_FPWM.

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