Controllable data transmission device and method

Abstract

The invention provides a controllable data transmission device and method, and belongs to the technical field of data communication, and the method comprises the steps: a memory module caches to-be-transmitted data, an added memory management module controls the memory module to empty the to-be-transmitted data after determining that an output module outputs all the to-be-transmitted data, and transmits the to-be-transmitted data to the output module; the method at least can be implemented by the following two ways: controlling the memory module to execute the zero-writing operation and executing the power-off operation on the memory module. According to the controllable data transmission device and method provided by the invention, the memory management module is additionally arranged, so that zero writing operation can be performed on the mounted memory module or power supply of the memory can be controlled to realize data erasing, overall power failure of a data storage board card is not needed, and controllable storage of the memory module is realized; the virus Trojan horse infection from the sending end is prevented, and the DDoS attack through a network layer and a transmission layer can be effectively prevented.

Description

Technical Field

[0001] The present invention relates to the technical field of data communication, and in particular to a controllable data transmission device and method. Background Art

[0002] To address the risk of network link attacks, memory is usually used as a storage disk between the sender and the receiver to achieve controllable one-way data transmission. After the sender sends the data to the memory module for buffering, the memory module transmits the data to the receiver at one time. Then, relying on the memory power-off data loss feature, a short power-off operation is performed to clear the data. This prevents virus and Trojan infection from the sender. At the same time, the sender ensures that the memory module is completely cleared the next time it transmits data, thereby preventing Distributed Denial of Service (DDoS) attacks through the network layer and transport layer.

[0003] How to realize the zeroing operation of the memory module is particularly critical. The common method is to achieve the purpose of zeroing by cutting off the power supply of the motherboard.

[0004] The existing technology mainly achieves the purpose of data clearing by powering off and then powering on the data storage board in order to realize controllable data transmission. However, it takes a long time for the entire system to be in a working ready state, and frequent power on and off operations may cause certain electronic components on the board to fail, and cause the power output of the board to fluctuate, greatly reducing its stability of availability. Summary of the invention

[0005] The present invention provides a controllable data transmission device and method, which are used to solve the problem that in the prior art, when implementing a memory clearing operation, the entire data storage board needs to be frequently powered off and then powered on, which causes certain electronic components to fail, and causes the power output of the data storage board to be in a fluctuating state, greatly reducing the stability of its availability.

[0006] The present invention provides a controllable data transmission device, which mainly includes: An input module, used for receiving data to be transmitted; A memory module, connected to the input module via a memory management module, and used for caching the data to be transmitted; An output module, connected to the memory module through the memory management module, and used to read out the data to be transmitted in the memory module; A memory management module, configured to control the memory module to clear the data to be transmitted after determining that the output module outputs all the data to be transmitted; The memory management module controls the memory module to clear the data to be transmitted, and at least two approaches are adopted: controlling the memory module to perform a write-zero operation and performing a power-off operation on the memory module.

[0007] According to a controllable data transmission device provided by the present invention, the controllable data transmission device further includes: A power module, providing power to the memory module; A field effect transistor, wherein the gate is connected to the signal control terminal of the memory management module, the source is connected to the power output terminal of the power module, and the drain is connected to the power input terminal of the memory module.

[0008] According to a controllable data transmission device provided by the present invention, the memory management module stores a data transmission strategy, and the data transmission strategy includes at least one of a memory erasure strategy, a data verification strategy and a transceiver rate control strategy.

[0009] According to a controllable data transmission device provided by the present invention, the memory erasure strategy at least includes a write-zero operation control strategy and a power-off operation control strategy; The memory management module executes the write-zero operation control strategy and controls the memory module to perform the write-zero operation according to a preset frequency; The memory management module executes the power-off operation control strategy and performs a power-off operation on the memory module according to the preset frequency.

[0010] According to a controllable data transmission device provided by the present invention, the memory management module executes the data verification strategy to perform integrity verification on the data to be transmitted cached in the memory module.

[0011] According to a controllable data transmission device provided by the present invention, the memory management module executes the transceiver rate control strategy to control the transmission rate at which the memory module receives the data to be transmitted and reads the data to be transmitted from the memory module.

[0012] According to a controllable data transmission device provided by the present invention, the memory module is a double rate memory DDR, the memory management module is a field programmable gate array FPGA, and the input module and the output module are pluggable optical modules SFP.

[0013] According to a controllable data transmission device provided by the present invention, the controllable data transmission device further includes: A universal asynchronous receiver / transmitter serial port UART, one end of which is connected to the input / output interface of the memory management module.

[0014] According to a controllable data transmission device provided by the present invention, the other end of the UART is connected to an external safety control board; The peripheral security control board is used to respond to the user's mode selection input and send a mode setting instruction to the memory management module through the UART; The mode setting instruction is used to set the operation mode of the memory management module, and the operation mode includes an autonomous control mode or an interactive control mode.

[0015] According to a controllable data transmission device provided by the present invention, the peripheral security control board is also used to execute a user-defined protocol to adjust the data transmission strategy in the memory management module.

[0016] The present invention also provides a controllable data transmission method, which is applied to a memory management module and mainly includes the following steps: After determining that the output module has read all the data to be transmitted from the memory module, controlling the memory module to clear the data to be transmitted; The controlling the memory module to clear the data to be transmitted may be performed in at least two ways: controlling the memory module to perform a write-zero operation and performing a power-off operation on the memory module.

[0017] According to the controllable data transmission method provided by the present invention, after storing the data to be transmitted received by the input module into the memory module, it further comprises: feeding back processing status information through the input module; The processing status information includes data parsing status information, data verification status information, sending confirmation information and zeroing operation information; The parsing status information is used to indicate whether the input module has successfully parsed the data to be transmitted, the data verification status information is used to indicate whether the integrity of the data to be transmitted is normal, the sending confirmation information is used to indicate whether the data to be transmitted is stored in the memory module, and the zeroing operation information is used to indicate the path taken by the memory module to clear the data to be transmitted.

[0018] The controllable data transmission device and method provided by the present invention can perform a write-zero operation on the mounted memory module or control the power supply of the memory to achieve data erasure by adding a memory management module, without the need to cut off the power of the data storage board as a whole, thereby achieving controllable storage of the memory module, and preventing virus and Trojan infection from the sending end, and effectively preventing DDoS attacks through the network layer and the transport layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 This is one of the structural schematic diagrams of the controllable data transmission device provided by the present invention.

[0021] Figure 2 This is the second structural schematic diagram of the controllable data transmission device provided by the present invention.

[0022] Figure 3 This is the third structural schematic diagram of the controllable data transmission device provided by the present invention.

[0023] Figure 4 This is one of the flow charts of the controllable data transmission method provided by the present invention.

[0024] Figure 5 This is the second flow chart of the controllable data transmission method provided by the present invention. DETAILED DESCRIPTION

[0025] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution of the present invention will be clearly and completely described below in conjunction with the drawings of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or device including the elements. Unless otherwise clearly specified and defined, the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be an indirect connection through an intermediate medium, or it can be a communication between the two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to the specific circumstances.

[0027] Combine the following Figure 1-Figure 5 The controllable data transmission device and method provided by the present invention are described, which are controlled by a memory management module to realize controllable memory storage. Data transmission is also completed through a unique protocol, and strategies such as memory power-off, write-zero, and verification are solidified in the memory management module. This design improves the security and stability of the controllable data transmission device.

[0028] Figure 1 is one of the structural diagrams of the controllable data transmission device provided by the present invention, such as Figure 1 As shown, it mainly includes but is not limited to: input module 1, used to receive data to be transmitted; memory module 2, connected to input module 1 through memory management module 3, used to cache data to be transmitted; output module 4, connected to memory module 2 through memory management module 3, used to read out data to be transmitted in memory module 2; memory management module 3, used to control memory module 2 to clear data to be transmitted after determining that output module 4 outputs all data to be transmitted. Among them, memory management module 3 controls memory module 2 to clear data to be transmitted, and at least the following two ways can be adopted: controlling memory module 2 to perform write-zero operation and performing power-off operation on memory module 2.

[0029] The input module 1 is a data receiving end of the controllable data transmission device, and its main function is to receive data to be transmitted. The data to be transmitted can be digital signals in various forms, such as text files, image files, audio files or video files. Optionally, the input module 1 receives data sent by an external device through a data interface (such as a USB interface, a network interface, etc.), and transmits it to the memory module 2 for caching.

[0030] The memory module 2 is used to cache the data to be transmitted, and is connected to the input module 1 through the memory management module 3. The memory module 2 can be implemented using a variety of storage media, such as static random access memory (SRAM), dynamic random access memory (DRAM) or double data rate (DDR). When the input module 1 receives the data to be transmitted, the memory management module 3 writes the data to be transmitted into the memory module 2 so that it is temporarily stored in the memory module 2 for subsequent reading and transmission operations.

[0031] The output module 4 is the data output end of the controllable data transmission device, which is connected to the memory module 2 through the memory management module 3. The function of the output module 4 is to read the data to be transmitted from the memory module 2 and send it to the target device. Similar to the input module 1, the output module 4 can also output data through a variety of data interfaces (such as USB interface, network interface, etc.). During the data transmission process, the output module 4 reads and sends the data in the memory module 2 block by block according to a certain transmission protocol and rate.

[0032] The memory management module 3 is the core component of the controllable data transmission device provided by the present invention, and its main function is to coordinate the data transmission between the input module 1, the memory module 2 and the output module 4, and control the memory module 2 to clear the data to be transmitted after determining that the output module 4 outputs all the data to be transmitted. The memory management module 3 can realize the above functions through hardware circuits and software programs, for example, data transmission control logic and memory clearing control logic are loaded inside it.

[0033] During the transmission of the data to be transmitted, the memory management module 3 first receives the data sent by the input module 1 and writes it into the memory module 2. When the output module 4 starts to read data from the memory module 2, the memory management module 3 monitors in real time the amount of data read in the memory module 2 and the reading progress of the output module 4. Once it is determined that the output module 4 has output all the data to be transmitted, the memory management module 3 triggers a memory clearing operation and controls the memory module to clear the stored data.

[0034] It should be emphasized that the memory management module 3 in the present invention can control the memory module 2 to clear the data to be transmitted in the following two ways: In approach 1, the memory management module 3 controls the memory module 2 to perform a write-zero operation. The memory management module 3 sends a write-zero instruction to the memory module 2, so that the memory module 2 clears all the data in the storage unit. This clearing method is suitable for scenarios with high data security requirements, because the write-zero operation can ensure that the data in the memory module 2 is completely cleared, preventing security risks caused by residual data.

[0035] In approach 2, the memory management module 3 performs a power-off operation on the memory module 2. The memory management module 3 cuts off the power supply of the memory module 2, so that the data stored in the memory module 2 is lost due to the power off. The advantage of this clearing method is that the operation is simple and fast.

[0036] The specific implementation methods of Approach 1 and Approach 2 are described below with reference to specific examples.

[0037] As an optional embodiment, assuming that the memory module 2 uses a DRAM with 1024 storage units, during the write-zero operation, the memory management module 3 will perform the write-zero operation on the 1024 storage units in sequence. The specific operation is as follows: Step 1: The memory management module 3 first points the address pointer to the first storage unit (address 0).

[0038] Step 2: The memory management module 3 sends a write-zero instruction to the DRAM to set the data value of the first storage unit to 0.

[0039] Step 3, the memory management module 3 continues to move the address pointer to the next storage unit (address 1), and repeats the above write-zero operation.

[0040] And so on, until the data values ​​of all 1024 storage units are set to 0. In this way, the data in the memory module 2 is completely cleared to ensure the security of the data.

[0041] As another optional embodiment, assuming that the memory module 2 is a double-rate memory DDR, with 512 storage units, each storing 16 bits of data. During the power-off operation, the memory management module 3 controls the power management module to cut off the power supply of the DDR, and the specific operation is as follows: Step 1: After the memory management module 3 detects that the output module 4 has output all the data to be transmitted, it sends a power-off instruction to the power management module.

[0042] Step 2: After receiving the power-off instruction, the power management module cuts off the power supply of the DDR. Since SRAM is a volatile memory, the data stored in it will be lost immediately once the power is off.

[0043] Step 3, after the power-off operation is completed, the power management module sends a clearing completion signal to the memory management module 3, indicating that the data in the memory module 2 has been cleared. In this way, the data in the memory module 2 is quickly cleared, and the operation is simple and efficient.

[0044] The controllable data transmission device provided by the present invention can perform a write-zero operation on the mounted memory module or control the power supply of the memory to achieve data erasure by adding a memory management module, without the need to cut off the power of the data storage board as a whole, thereby achieving controllable storage of the memory module, preventing virus and Trojan infection from the sending end, and effectively preventing Distributed Denial of Service (DDoS) attacks through the network layer and the transport layer.

[0045] Figure 2 This is the second structural diagram of the controllable data transmission device provided by the present invention, such as Figure 2As shown, in the controllable data transmission device provided by the present invention, the memory module is a double-rate memory DDR, the memory management module is a field programmable gate array (Field Programmable Gate Array, FPGA), and the input module and the output module are pluggable optical modules (Small Form-factor Pluggable, SFP).

[0046] The memory module uses DDR to transmit data at twice the memory clock frequency, thereby improving the data transmission rate and system performance. In this embodiment, DDR is used to cache data to be transmitted, and is connected to the FPGA through a data storage interface.

[0047] The FPGA used in the memory management module has high flexibility and programmability, and can realize complex logic control and data processing functions. In this embodiment, the FPGA, as a memory management module, is responsible for coordinating data transmission between the input module, the memory module, and the output module, and controls the memory module to clear the data to be transmitted after determining that the output module outputs all the data to be transmitted.

[0048] The FPGA integrates a data transmission strategy, which is responsible for receiving the data to be transmitted sent by the input module and writing it into the memory module. At the same time, it monitors the reading progress of the output module. After determining that the output module has output all the data to be transmitted, it controls the memory module to clear the data in the memory unit or perform a power-off operation on the memory unit, thereby achieving safe clearing of the data to be transmitted stored in the memory unit.

[0049] The SFP used in the input module and the output module is a standardized optical module with the characteristics of small size, easy plugging and replacement. In this embodiment, the SFP optical module is used to realize optical signal transmission of data, and is connected to the FPGA through a proprietary data transmission protocol.

[0050] The input SFP optical module is responsible for receiving the optical signal data sent by the external device, converting it into an electrical signal and sending it to the FPGA. After the FPGA receives the electrical signal data, it writes it into the DDR for cache through the data transmission control logic.

[0051] The output SFP optical module is responsible for reading the data to be transmitted from the DDR, converting it into an optical signal and sending it to the target device. After the FPGA determines that the output SFP optical module has read all the data to be transmitted in the DDR, it clears the data to be transmitted stored in the DDR to ensure the safe transmission of the data.

[0052] Figure 3 This is the third structural diagram of the controllable data transmission device provided by the present invention, such as Figure 3As shown, the controllable data transmission device of the present invention includes, in addition to an input module, a memory module, an output module and a memory management module, a power module and a field effect transistor (denoted as Q1) as a power control module. The gate of the field effect transistor is connected to the signal control end of the memory management module, the source is connected to the power output end of the power module, and the drain is connected to the power input end of the memory module.

[0053] Next, we will take the memory management module as FPGA and the memory module as DDR as an example. The power module is responsible for providing a stable power supply for DDR. In this embodiment, the power module can be an independent power supply unit or a power management circuit integrated in the FPGA. The voltage and current output by the power module can meet the working requirements of DDR.

[0054] As a power control module, the field effect transistor can be selected as an N-channel MOSFET to control the power switch of the memory module. The gate of the MOSFET is connected to the signal control terminal of the FPGA, the source is connected to the power output terminal of the power module, and the drain is connected to the power input terminal of the DDR.

[0055] When the FPGA needs to perform a power-off operation on the DDR, it can send a control signal (usually a voltage signal) to the gate of the MOSFET. According to the voltage signal received by the gate, the MOSFET quickly switches from the on state to the off state, thereby disconnecting the power supply of the power module to the DDR. The FPGA controls the power supply of the memory module by controlling the control signal sent to the gate of the MOSFET. In this embodiment, the power-off operation control strategy is integrated inside the FPGA to generate the above control signal.

[0056] The controllable data transmission device provided by the present invention adopts a power module and a field effect transistor as a power control module, thereby realizing precise control of the power supply of the memory module, improving the security of data transmission and the energy efficiency of the system. This design has broad application prospects and practical value.

[0057] As a memory management module, FPGA is responsible for controlling and managing the data transmission and memory clearing operations of memory modules (such as DDR). The following is a specific implementation method of FPGA triggering memory clearing operations: FPGA monitors the entire transmission process of the data to be transmitted from the input module to the memory module and then from the memory module to the output module, including: receiving the data to be transmitted from the input module and writing it into the memory module; monitoring the progress of the output module reading the data to be transmitted from the memory module.

[0058] FPGA determines that the output module has completely read and transmitted all the data to be transmitted in the memory module. This can be achieved in the following ways: a counter is set inside the FPGA to record the amount of data written and read. When the amount of data written and read is equal, the data transmission is considered to be completed. Alternatively, after the output module completes the transmission of all the data to be transmitted, it sends a status signal to the FPGA to notify the FPGA that the transmission of the data to be transmitted is completed.

[0059] After the FPGA determines that the data transfer is complete, it triggers a memory clear operation, which can be achieved through the following steps: The FPGA generates a data clear instruction, which can be a write zero instruction or a power-off instruction. The FPGA sends the data clear instruction to the memory module. If it is a write zero operation, the data clear instruction will instruct the memory module to set the data of all storage cells to zero. If it is a power-off operation, the FPGA will cut off the power supply of the memory module by controlling the field effect transistor (Q1).

[0060] If the memory is cleared by powering off, the FPGA will control the field effect transistor connected between the power module and the memory module, mainly by sending a control signal to the gate of the field effect transistor to switch it from the on state to the off state, thereby cutting off the power from the power module to the memory module. At this time, the FPGA can monitor the power status of the memory module and confirm that the power has been successfully cut off.

[0061] The FPGA in the controllable data transmission device provided by the present invention can effectively manage the data clearing operation of the memory module, ensuring that the data is safely cleared after the transmission is completed, thereby protecting the security of the data and the reliability of the system.

[0062] Based on the content of the above embodiment, as an optional embodiment, the memory management module stores a data transmission strategy, and the data transmission strategy includes at least one of a memory erasure strategy, a data verification strategy and a transceiver rate control strategy.

[0063] The present invention solidifies data transmission strategies in a memory management module (such as FPGA). These data transmission strategies are used to guide the operation of the memory module and the data transmission process, such as powering off the memory module, writing zeros, checking the data received by the memory module, and controlling the sending and receiving rate of the memory module.

[0064] The data transmission strategy is a set of predefined rules and operation steps for optimizing the performance and security of data transmission. In this embodiment, the data transmission strategy includes at least one of the following three strategies: The memory erase policy defines the conditions under which the data erase operation of the memory module is triggered, as well as the specific method of the erase operation. For example, it can be defined that the memory erase is triggered after the data to be transmitted is completely transmitted, before the system is shut down, or when an abnormal situation is detected, and at least a write-zero operation or a power-off operation can be taken.

[0065] Data verification strategy is used to ensure the integrity and correctness of data during transmission, including, for example, one or more of the following verification methods: Cyclic Redundancy Check (CRC), parity check, hash check, etc. Data verification is performed before writing data into the memory module and after reading data from the memory module to ensure that the data has not been tampered with or damaged.

[0066] The receive and send rate control strategy is used to control the data receiving and sending rates to adapt to different network environments and device performance. The receive and send rates can be dynamically adjusted according to factors such as network bandwidth and device processing capabilities to avoid data congestion and improve transmission efficiency.

[0067] As an optional embodiment, the specific steps of implementing the data transmission strategy based on FPGA may include: Step 1: When the controllable data transmission device is started, the FPGA loads a predefined data transmission strategy from its internal memory.

[0068] Step 2: FPGA parses the loaded data transmission strategy and extracts key information such as memory erase conditions, data verification methods, and transceiver rate control parameters.

[0069] Step 3: When the memory erase condition is met (such as data transmission is completed), the FPGA performs the corresponding erase operation, such as cutting off the power supply of the memory module by controlling the field effect transistor or sending a write-zero instruction to the memory module.

[0070] During the process of writing and reading data from the memory module, the FPGA verifies the data entering and leaving the memory module according to the data verification strategy to ensure the integrity and correctness of the data.

[0071] Furthermore, the FPGA will dynamically adjust the memory module's data receiving and sending rates based on the receiving and sending rate control strategy to adapt to the current network environment and device performance.

[0072] Optionally, during the operation of the controllable data transmission device, the above-mentioned fixed data transmission strategy can be updated as needed. For example, the FPGA can receive a new strategy from an external memory or other device and load it into the internal memory.

[0073] The controllable data transmission device provided by the present invention can clear the data in the memory in time to prevent data leakage after the data transmission is completed, ensure the integrity and correctness of the data during the transmission process, improve the reliability of data transmission, and dynamically adjust the data receiving and sending rates to improve the transmission efficiency and avoid data congestion.

[0074] As an optional embodiment, the memory erasure strategy at least includes a write-zero operation control strategy and a power-off operation control strategy. The memory management module executes the write-zero operation control strategy to control the memory module to execute the write-zero operation at a preset frequency; the memory management module executes the power-off operation control strategy to execute the power-off operation on the memory module at a preset frequency.

[0075] The memory management module (such as FPGA) is responsible for executing the above two memory erase strategies, that is, by solidifying the corresponding control logic inside it, it is used to control the memory module to perform write-zero operations or power-off operations at a preset frequency.

[0076] The preset frequency can be set according to business needs. For example, if it is set to a each time strategy, the memory erase strategy will be executed each time the memory module receives data, verifies data, and sends data. For another example, if it is set to an interval of 5 times strategy, the memory erase strategy will be executed after the memory module completes the process of receiving data, verifying data, and sending data for the 1st, 6th, 11th, etc.

[0077] The implementation steps for the write-zero operation control strategy may include: the FPGA generates a write-zero instruction according to a preset frequency; the FPGA sends the write-zero instruction to the memory module to instruct the memory module to set the data of all storage units to zero; after the write-zero operation is completed, the FPGA receives a feedback signal from the memory module to confirm that the write-zero operation has been completed.

[0078] The controllable data transmission device provided by the present invention can effectively control the transmission rate of the memory module receiving the data to be transmitted and reading the data to be transmitted from the memory module through the memory management module to execute the transmission and reception rate control strategy. This design can dynamically adjust the data receiving and sending rates according to the network environment and device performance, thereby avoiding data congestion, improving the efficiency and stability of data transmission, and also helping to optimize the utilization of system resources and ensure the smoothness and reliability of data transmission.

[0079] Based on the contents of the above embodiments, refer to Figure 2 As shown, as an optional embodiment, the memory module of the controllable data transmission device adopts double-rate memory DDR, the memory management module adopts field programmable gate array FPGA, and the input module and the output module adopt pluggable optical module SFP.

[0080] Among them, DDR is a high-performance dynamic random access memory that can transmit data at twice the rate of the memory clock frequency. It is used to cache data to be transmitted and can quickly receive and send data, thereby significantly improving data transmission rate and system performance.

[0081] FPGA is a highly flexible programmable logic device that can implement complex logic control and data processing functions. In this embodiment, FPGA acts as a memory management module, responsible for coordinating data transmission between the input module, memory module and output module, and controls the memory module to clear the data to be transmitted after determining that the output module has output all the data to be transmitted.

[0082] In addition, in this embodiment, the input SFP optical module is responsible for receiving the optical signal data sent by the external device, converting it into an electrical signal and sending it to the FPGA; the output SFP optical module is responsible for reading the data to be transmitted from the DDR, converting it into an optical signal and sending it to the target device.

[0083] Assuming that the data to be transmitted received by the input module is a video file, the input SFP optical module converts it into an electrical signal and sends it to the FPGA; the FPGA writes the data corresponding to these electrical signals into the DDR for cache; the output SFP optical module reads the data from the DDR and converts it into an optical signal and sends it to the target device. After the data transmission is completed, the FPGA controls the DDR to perform a write-zero operation or a power-off operation according to the fixed memory erase strategy to clear the data in the DDR.

[0084] By using DDR as a memory module, FPGA as a memory management module, and SFP as an input and output module, the controllable data transmission device provided by the present invention can achieve efficient data transmission and secure data erasure. The high-speed data transmission capability of DDR combined with the flexible control function of FPGA ensures the efficiency and reliability of data transmission. At the same time, the pluggable design of SFP improves the flexibility and maintainability of the system. This combined design not only improves the efficiency of data transmission, but also enhances the security and stability of the system, and is particularly suitable for application scenarios with high requirements for data transmission speed and security.

[0085] refer to Figure 2 As shown, in this embodiment, the UART is used to expand the function of the controllable data transmission device and provide a communication interface with external devices. The input and output interface of the memory management module (such as FPGA) is used to interact with the UART for data to realize the control of the controllable data transmission device and feedback of status information.

[0086] Assume that in the controllable data transmission device of the present invention, the UART interface is used to communicate with an external device. The external device can send instructions to the memory management module through the UART interface, such as querying the current memory usage, checking the data transmission status, etc. After receiving these instructions, the memory management module will perform corresponding operations according to the instruction content, and feed back the results to the external device through the UART interface. For example, the external device can send a query instruction, and the memory management module will check the usage of the current memory module (such as DDR) and send the results back to the external device through the UART interface.

[0087] By adding a UART interface to the controllable data transmission device, the present invention provides a means of communicating with an external device. This design enables the controllable data transmission device to receive external instructions and feedback status information, thereby enhancing the operability and monitorability of the device. The addition of the UART interface not only improves the functional expansibility of the device, but also provides the external device with the ability to monitor and manage the controllable data transmission device in real time, thereby improving the overall performance and reliability of the system.

[0088] Based on the content of the above embodiment, as an optional embodiment, the other end of the above UART is connected to the external security control board; the external security control board is used to respond to the user's mode selection input and send a mode setting instruction to the memory management module through the UART. The mode setting instruction can be used to set the operating mode of the memory management module, and the operating mode may include an autonomous control mode or an interactive control mode.

[0089] Among them, the peripheral security control board refers to an external device that can be used in conjunction with a controllable data transmission device, such as providing user interaction interface and security control functions, which can receive user input commands and send these commands to the memory management module through the UART interface.

[0090] Mode setting instructions refer to instructions generated by the peripheral security control board based on user input, which are used to set the operating mode of the memory management module. These mode setting instructions are transmitted to the memory management module through the UART interface and executed by it.

[0091] In autonomous control mode, the memory management module automatically performs operations such as data transmission and memory erasure according to pre-set strategies, without the need for real-time intervention from external devices. In interactive control mode, the memory management module performs operations based on real-time instructions sent by the peripheral security control board, allowing users to dynamically adjust data transmission and memory management strategies based on actual conditions.

[0092] Assume that the user needs to set the operation mode of the controllable data transmission device to the interactive control mode. The user selects the "interactive control mode" option on the interface of the peripheral safety control board. After receiving the user's selection, the peripheral safety control board generates the corresponding mode setting instruction and sends it to the memory management module through the UART interface. After receiving the instruction, the memory management module switches to the interactive control mode and waits for further instructions from the peripheral safety control board to perform operations such as data transmission and memory erasure.

[0093] By connecting the other end of the UART to the external safety control board and using the external safety control board to send a mode setting instruction, the controllable data transmission device provided by the present invention can flexibly switch the operation mode according to user needs. This design enables the device to operate efficiently in the autonomous control mode, while providing higher flexibility and adaptability in the interactive control mode to meet the needs of different application scenarios. Users can choose the appropriate operation mode according to actual conditions, thereby improving the security and reliability of data transmission and enhancing the overall performance of the system.

[0094] Based on the content of the above embodiment, as an optional embodiment, the above peripheral security control board can not only send mode setting instructions, but also has the function of executing the user's custom protocol to adjust the data transmission strategy in the memory management module.

[0095] Among them, the custom protocol refers to a communication protocol defined by the user, which is used for data exchange between external devices (such as peripheral safety control boards) and memory management modules. The custom protocol can be designed according to the specific needs of the user to achieve specific functions and operations.

[0096] Data transmission strategy refers to a set of rules and operation steps preset in the memory management module to control the processes of data reception, storage, transmission and erasure. These data transmission strategies can be adjusted according to user needs to optimize the performance and security of data transmission.

[0097] Assume that the user needs to adjust the memory erase policy in the memory management module from "erase after each transmission" to "erase after every 5 transmissions". The user enters the corresponding adjustment instruction on the interface of the peripheral security control board. After receiving the user input, the peripheral security control board generates the corresponding adjustment instruction according to the custom protocol and sends it to the memory management module through the UART interface. After receiving the adjustment instruction, the memory management module modifies its internal memory erase policy, so that the memory erase operation is performed according to the new policy during the subsequent data transmission process.

[0098] The controllable data transmission device provided by the present invention can flexibly adjust the data transmission strategy in the memory management module according to the specific needs of the user by executing the user-defined protocol through the external security control board, which not only improves the flexibility and adaptability of the device, but also enables the user to optimize the performance and security of data transmission according to different application scenarios and security requirements. In particular, the introduction of the customized protocol further enhances the functional extensibility of the device, so that the controllable data transmission device can better meet the diverse needs of users.

[0099] Figure 4 is one of the flow charts of the controllable data transmission method provided by the present invention, such as Figure 4 As shown, a controllable data transmission method provided by the present invention is mainly used in a memory management module, including but not limited to the following steps: Step 11: After determining that the output module has read all the data to be transmitted from the memory module, control the memory module to clear the data to be transmitted.

[0100] Step 12, controlling the memory module to clear the data to be transmitted may be performed in at least two ways: controlling the memory module to perform a write-zero operation and performing a power-off operation on the memory module.

[0101] The write-zero operation refers to setting the data of all storage cells in the memory module to zero. This is an active data clearing method. By sending a write-zero instruction to the memory module, it ensures that the data in the memory is completely cleared to prevent security risks caused by residual data.

[0102] The power-off operation refers to cutting off the power supply to the memory module, and using the volatile characteristics of the memory module (such as dynamic random access memory DRAM or double rate memory DDR, etc.) to cause the stored data to be lost due to power failure. This clearing method is simple and fast to operate, but it relies on the physical characteristics of the memory module.

[0103] Assume that the memory module uses double-rate memory DDR, and the memory management module is implemented using FPGA. During data transmission, FPGA monitors the reading progress of the output module through internal logic. When the output module completes reading all data, FPGA selects one of the clearing methods according to the preset memory erase strategy: Write-zero operation: FPGA sends a write-zero instruction to DDR, and performs a write-zero operation on each storage unit of DDR in turn, setting the data of all storage units to zero.

[0104] Power-off operation: FPGA sends a power-off command to the power management module, cutting off the power supply to DDR, causing the data in DDR to be lost due to power off.

[0105] The controllable data transmission method provided by the present invention can perform a write-zero operation on the mounted memory module or control the power supply of the memory to achieve data erasure by adding a memory management module, without the need to cut off the power of the data storage board as a whole, thereby achieving controllable storage of the memory module, preventing virus and Trojan infection from the sending end, and effectively preventing DDoS attacks through the network layer and the transport layer.

[0106] It should be noted that the controllable data transmission method provided by the present invention can also realize related data transmission operations by controlling and utilizing the controllable data transmission device described in any of the above embodiments during specific operation, which will not be elaborated in this embodiment.

[0107] Figure 5 FIG. 2 is a flow chart of the controllable data transmission method provided by the present invention. Figure 5 As shown, after the data to be transmitted received by the input module is stored in the memory module, it also includes: feeding back processing status information through the input module.

[0108] The controllable data transmission method provided in this embodiment further includes the step of feeding back processing status information through the input module after storing the data to be transmitted received by the input module into the memory module. Such processing status information is crucial to ensuring the reliability and security of data transmission.

[0109] Among them, the processing status information includes data analysis status information, data verification status information, transmission confirmation information and zeroing operation information, etc. These information are generated by the input module during the data transmission and processing process, and are interactively fed back to the sending end or other monitoring system through the data transmission protocol.

[0110] The parsing status information is used to indicate whether the input module successfully parses the data to be transmitted, that is, whether the input module successfully parses the received data to be transmitted. If the input module parses successfully, it means that the data format is correct and can be understood and processed by the system.

[0111] The data verification status information is used to characterize whether the integrity of the data to be transmitted is normal, that is, to confirm whether the integrity of the data to be transmitted is normal. The generation of the data verification status information usually involves an error detection and correction mechanism, such as a cyclic redundancy check (CRC).

[0112] The sending confirmation information is used to indicate whether the data to be transmitted is stored in the memory module, that is, whether the data to be transmitted has been successfully stored in the memory module, which is a key indicator of data transmission reliability.

[0113] The zeroing operation information is used to characterize the path adopted by the memory module to clear the data to be transmitted, that is, to indicate the method adopted by the memory module to clear the data to be transmitted, whether it is through a write-zero operation or a power-off operation.

[0114] by Figure 5 As shown in the figure, the input module receives data through the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) with a communication rate of 10GbE and the Media Access Control (MAC) with a communication rate of 10GbE, and transmits it to the FPGA. The FPGA is responsible for writing the data to the DDR3 memory module and performing a clear operation after the data transmission is completed. In this process, the FPGA generates and feeds back processing status information, which is then returned to the sender through the 10GbE MAC and 10GbE PCS / PMA. The specific implementation steps can be simply described as follows: Step 1: After receiving the data, the input module first parses it. If the parsing is successful, the corresponding data parsing status information is generated and fed back to the sender through the 10GbE MAC and PCS / PMA.

[0115] Step 2: Before writing data into the memory module, an integrity check is performed. The check result generates data check status information and is fed back to the sender.

[0116] Step 3: Once the data is successfully stored in the memory module, a transmission confirmation message is generated and fed back to the sender through the same path.

[0117] Step 4: After the data transmission is completed, a write-to-zero or power-off operation is performed according to a preset strategy. After the operation is completed, zeroing operation information is generated and fed back to the sending end.

[0118] The present invention not only improves the transparency of data transmission, but also enhances the reliability and security of the system by feeding back processing status information during the data transmission process. The sending end can monitor the data transmission status in real time according to the feedback information, adjust the transmission strategy in time, and ensure the integrity and security of the data. In addition, this design is also helpful for fault diagnosis and system maintenance, and improves the stability and availability of the system.

[0119] Through the description of the above implementation methods, those skilled in the art can clearly understand that each implementation method can be implemented by means of software plus a necessary general hardware platform, and of course, can also be implemented by hardware. Based on this understanding, the above technical solution is essentially or the part that contributes to the prior art can be embodied in the form of a software product, and the computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a disk, an optical disk, etc., including a number of instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0120] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A controllable data transmission device, characterized in that: include: An input module, used for receiving data to be transmitted; A memory module, connected to the input module via a memory management module, and used for caching the data to be transmitted; An output module, connected to the memory module through the memory management module, and used to read out the data to be transmitted in the memory module; A memory management module, configured to control the memory module to clear the data to be transmitted after determining that the output module outputs all the data to be transmitted; The memory management module controls the memory module to clear the data to be transmitted, and at least two approaches are adopted: controlling the memory module to perform a write-zero operation and performing a power-off operation on the memory module.

2. The controllable data transmission device according to claim 1, characterized in that: The controllable data transmission device also includes: A power module, providing power to the memory module; A field effect transistor, wherein the gate is connected to the signal control terminal of the memory management module, the source is connected to the power output terminal of the power module, and the drain is connected to the power input terminal of the memory module.

3. The controllable data transmission device according to claim 1, characterized in that: The memory management module stores a data transmission strategy, which includes at least one of a memory erasure strategy, a data verification strategy, and a transceiver rate control strategy.

4. The controllable data transmission device according to claim 3, characterized in that: The memory erasure strategy at least includes a write-zero operation control strategy and a power-off operation control strategy; The memory management module executes the write-zero operation control strategy and controls the memory module to perform the write-zero operation according to a preset frequency; The memory management module executes the power-off operation control strategy and performs a power-off operation on the memory module according to the preset frequency.

5. The controllable data transmission device according to claim 3, characterized in that: The memory management module executes the data verification strategy to perform integrity verification on the data to be transmitted that is cached in the memory module.

6. The controllable data transmission device according to claim 3, characterized in that: The memory management module executes the transceiver rate control strategy to control the transmission rate at which the memory module receives the data to be transmitted and reads the data to be transmitted from the memory module.

7. The controllable data transmission device according to any one of claims 1 to 6, characterized in that: The memory module is a double rate memory DDR, the memory management module is a field programmable gate array FPGA, and the input module and the output module are pluggable optical modules SFP.

8. The controllable data transmission device according to claim 3, characterized in that: The controllable data transmission device also includes: A universal asynchronous receiver / transmitter serial port UART, one end of which is connected to the input / output interface of the memory management module.

9. The controllable data transmission device according to claim 8, characterized in that: The other end of the UART is connected to the peripheral safety control board; The peripheral security control board is used to respond to the user's mode selection input and send a mode setting instruction to the memory management module through the UART; The mode setting instruction is used to set the operation mode of the memory management module, and the operation mode includes an autonomous control mode or an interactive control mode.

10. The controllable data transmission device according to claim 9, characterized in that: The peripheral security control board is also used to execute a user-defined protocol and adjust the data transmission strategy in the memory management module.

11. A controllable data transmission method, applied to a memory management module, characterized in that: include: After determining that the output module has read all the data to be transmitted from the memory module, controlling the memory module to clear the data to be transmitted; The controlling the memory module to clear the data to be transmitted may be performed in at least two ways: controlling the memory module to perform a write-zero operation and performing a power-off operation on the memory module.

12. The controllable data transmission method according to claim 11, characterized in that: After storing the data to be transmitted received by the input module in the memory module, the method further includes: feeding back processing status information through the input module; The processing status information includes data parsing status information, data verification status information, sending confirmation information and zeroing operation information; The data parsing status information is used to indicate whether the input module has successfully parsed the data to be transmitted, the data verification status information is used to indicate whether the integrity of the data to be transmitted is normal, the sending confirmation information is used to indicate whether the data to be transmitted is stored in the memory module, and the zeroing operation information is used to indicate the path taken by the memory module to clear the data to be transmitted.

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