FPGA chip, program testing method and program testing system
By designing an FPGA chip with control module, data processing module, storage module, test interface and communication interface, automatic download and testing of multiple programs is realized, and the problem of low manual download and testing efficiency in the prior art is solved, saving labor costs and improving testing efficiency.
Patent Information
- Application Number
- CN202510080701.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-01-17
- Publication Date
- 2025-05-13
AI Technical Summary
Prior art In FPGA-based program testing, multiple programs need to be manually downloaded and tested, resulting in high labor costs and low testing efficiency.
A FPGA chip is designed, including a control module, a data processing module, a storage module, a test interface and a communication interface, to realize automatic storage, reading and download of multiple programs in the program package, and feedback program execution results to the upper computer equipment.
There is no need to manually download and transmit each program, saving labor costs and improving the testing efficiency of multiple programs.
Smart Images
Figure CN119988115A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to an FPGA chip, a program testing method and a program testing system. Background Art
[0002] Currently, when testing multiple programs based on FPGA, one of the multiple programs needs to be manually downloaded to the test board. After the test board completes the test of the program, the next program is downloaded, and this process is repeated until all programs are downloaded, which requires a lot of manpower and time costs. Summary of the invention
[0003] The purpose of the present invention is to provide an FPGA chip, a program testing method and a program testing system to address the deficiencies in the above-mentioned prior art, so that the storage, reading and automatic sequential downloading of multiple programs in a program package can be completed on the FPGA chip, and finally the program execution results of the multiple programs can be fed back to the host computer device, without the need for manual download and transmission of each program, thereby saving labor costs and improving the testing efficiency of multiple programs.
[0004] To achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
[0005] In a first aspect, an embodiment of the present application provides an FPGA chip, wherein the FPGA chip is provided with: a control module, a data processing module, a storage module, a test interface, and a communication interface; the data processing module is a data processing module composed of a programmable logic unit;
[0006] Wherein, the control module is connected to the test interface to obtain a program package having multiple programs from a host computer device through the test interface; the control module is connected to the storage module to store the program package in the storage module;
[0007] The data processing module is connected to the control module and the storage module, and is used for sequentially reading the current program in the program package from the storage module under the control of the control module, and sending the read current program to the control module;
[0008] The control module is also connected to the communication interface, which is used to connect to the test board, so that the control module downloads the current program to the test board through the communication interface, obtains the program execution result obtained by the test board executing the current program, and feeds back the program execution result to the host computer device through the test interface.
[0009] In an optional implementation, the data processing module includes: a data reading logic unit, a data buffering logic unit, and a data checking logic unit;
[0010] The data reading logic unit is connected to the control module, the storage module and the data buffering logic unit, and the data reading logic unit is used to sequentially read the current program in the program package from the storage module under the control of the control module, and send the read current program to the data buffering logic unit;
[0011] The data buffer logic unit is also connected to the control module and the data verification logic unit, and the data buffer logic unit is used to perform data buffering on the current program sent by the data reading logic unit under the control of the control module, and send the current program to the data verification logic unit;
[0012] The data verification logic unit is also connected to the control module. The data verification logic unit is used to verify the current program sent by the data buffer logic unit under the control of the control module, and send the current program that passes the verification to the control module.
[0013] In an optional implementation, the data reading logic unit is further used to, under the control of the control module, convert the read current program from a parallel data structure into a serial data structure and then send the converted data to the data buffering logic unit.
[0014] In an optional implementation, the FPGA chip further includes: a clock module; the clock module is respectively connected to the control module and the data processing module, and is used to provide a clock synchronization signal.
[0015] In an optional implementation, the FPGA chip further includes: a reset button; the reset button is connected to the data processing module, the clock module and the control module.
[0016] In a second aspect, an embodiment of the present application further provides a program testing method, which is applied to the FPGA chip described in any one of the first aspects above, and the method includes:
[0017] The control module on the FPGA chip receives a program package having multiple programs sent by the host computer device through the test interface, and stores the program package in the storage module on the FPGA chip;
[0018] The control module controls the data processing module to sequentially read the current program in the program package from the storage module, and sends the read current program to the control module;
[0019] The control module transmits the current program to the test board through the communication interface, so that the test board executes the current program to obtain a program execution result of the current program;
[0020] The control module obtains the program execution result returned by the test board through the communication interface;
[0021] The control module sends the program execution result to the host computer device through the test interface.
[0022] In an optional implementation, the data processing module includes: a data reading logic unit, a data buffering logic unit and a data verification logic unit; the control module controls the data processing module to sequentially read the current program in the program package from the storage module, and sends the read current program to the control module, including:
[0023] The control module controls the data reading logic unit to sequentially read the current program in the program package from the storage module, and sends the read current program to the data buffer logic unit;
[0024] The control module controls the data buffering logic unit to perform data buffering on the current program sent by the data reading logic unit, and sends the current program to the data verification logic unit;
[0025] The control module controls the data verification logic unit to verify the current program sent by the data buffer logic unit, and sends the current program that passes the verification to the control module.
[0026] In an optional embodiment, the method further comprises:
[0027] If the control module receives the read empty flag signal transmitted by the data read logic unit, the control module sends a read program end signal to the host computer device through the test interface.
[0028] In an optional embodiment, the method further comprises:
[0029] If the control module receives the overflow flag signal transmitted by the data buffer logic unit, the control module controls the data reading logic unit to reduce the reading speed.
[0030] In a third aspect, an embodiment of the present application further provides a program testing system, the program testing system comprising: a host computer device, a test board, and the FPGA chip described in any one of the first aspects above;
[0031] The host computer device is connected to the test interface in the FPGA chip, and is used to transmit a program package having multiple programs to the control module in the FPGA chip through the test interface, and obtain the program execution result of the current program from the control module through the test interface;
[0032] The test board is connected to the communication interface in the FPGA chip, and is used to obtain the current program through the communication interface, execute the current program, obtain the program execution result of the current program, and feed back the program execution result to the control module through the communication interface.
[0033] The beneficial effects of this application are:
[0034] An FPGA chip, a program testing method and a program testing system provided in an embodiment of the present application, wherein the FPGA chip is provided with: a control module, a data processing module, a storage module, a test interface and a communication interface; the data processing module is a data processing module composed of a programmable logic unit, wherein the control module is connected to the test interface to obtain a program package having multiple programs from a host computer device through the test interface; the control module is connected to the storage module to store the program package in the storage module; the data processing module is connected to the control module and the storage module, and the data processing module is used to sequentially read the current program in the program package from the storage module under the control of the control module, and send the read current program to the control module, and the control module is also connected to the communication interface, and the communication interface is used to connect to a test board, so that the control module downloads the current program to the test board through the communication interface, obtains the program execution result obtained by the test board executing the current program, and feeds back the program execution result to the host computer device through the test interface.
[0035] The FPGA chip of the present application can utilize the control function of the control module, the programmable logic function of the data processing module, and the storage function of the storage module. It can complete the storage, reading, and automatic sequential downloading of multiple programs in a program package on the FPGA chip, and finally feedback the program execution results of multiple programs to the host computer device. There is no need to manually download and transmit each program, which saves labor costs and improves the testing efficiency of multiple programs. BRIEF DESCRIPTION OF THE DRAWINGS
[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.
[0037] Figure 1A schematic diagram of a program testing system provided in an embodiment of the present application;
[0038] Figure 2 A schematic diagram of an FPGA chip provided in an embodiment of the present application;
[0039] Figure 3 A schematic diagram of another FPGA chip provided in an embodiment of the present application;
[0040] Figure 4 A flowchart of a program testing method provided in an embodiment of the present application;
[0041] Figure 5 A flowchart of another program testing method provided in an embodiment of the present application.
[0042] Description of main component symbols: 100-FPGA chip; 110-control module; 120-data processing module; 121-data reading logic unit; 122-data buffering logic unit; 123-data verification logic unit; 130-storage module; 140-test interface; 150-communication interface; 160-clock module; 170-reset button; 200-host computer device; 300-test board. DETAILED DESCRIPTION
[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.
[0044] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.
[0045] In the description of the present application, it should be noted that if the terms "upper", "lower", etc. appear, the orientation or position relationship indicated is based on the orientation or position relationship shown in the drawings, or is the orientation or position relationship in which the product of the application is usually placed when used. It is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application.
[0046] In addition, the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.
[0047] It should be noted that, in the absence of conflict, the features in the embodiments of the present application may be combined with each other.
[0048] In order to realize automatic batch downloading of programs, the present application embodiment provides a program testing system. Figure 1 A schematic diagram of a program testing system provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the program testing system includes: a host computer device 200, a test board 300 and a FRGA chip, wherein the host computer device 200 is connected to the test interface 140 in the FPGA chip 100, and is used to transmit a program package having multiple programs to the control module 110 in the FPGA chip 100 through the test interface 140, and obtain the program execution result of the current program from the control module 110 through the test interface 140.
[0049] The test board 300 is connected to the communication interface 150 in the FPGA chip 100, and is used to obtain the current program through the communication interface 150, execute the current program, obtain the program execution result of the current program, and feed back the program execution result to the control module 110 through the communication interface 150.
[0050] Specifically, the testing process for the current program is as follows: the host computer device 200 determines multiple programs that need to be tested, and packages the multiple programs to generate a program package, and then sends the program package to the FPGA chip 100. The control module 110 in the FPGA chip 100 controls the data processing module 120 to sequentially read the multiple programs in the program package to determine the current program. The FPGA chip 100 transmits the current program to the test board 300, and the test board 300 tests the current program to obtain the program execution result of the current program, and feeds the program execution result back to the control module 110. The control module 110 returns the program execution result to the host computer device 200, so that the host computer device 200 can view the program execution result. Since there are multiple programs in the program package, the host computer device 200 finally transmits a program package with multiple programs at one time, and can obtain the program execution results of multiple programs.
[0051] Currently, when testing multiple programs, the host computer device 200 needs to transmit the multiple programs multiple times. After the test board 300 feeds back the program execution result of a program, the host computer device 200 consumes a lot of time in transmitting the next program, which increases the time cost. However, according to the method provided in the embodiment of the present application, the host computer device 200 transmits a program package with multiple programs at one time, and processes the program package through the FPAG chip. Finally, the host computer device 200 can obtain the program execution results of multiple programs without manually downloading and transmitting each program, thereby saving labor costs and improving the testing efficiency of multiple programs.
[0052] The embodiment of the present application also provides a possible implementation of the FPGA chip 100. Figure 2 A schematic diagram of an FPGA chip 100 provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the FPGA chip 100 is provided with: a control module 110, a data processing module 120, a storage module 130, a test interface 140 and a communication interface 150. The data processing module 120 is a data processing module 120 formed by a programmable logic unit.
[0053] The control module 110 is connected to the test interface 140 to obtain a program package having multiple programs from the host device 200 through the test interface 140 ; the control module 110 is connected to the storage module 130 to store the program package in the storage module 130 .
[0054] The data processing module 120 is connected to the control module 110 and the storage module 130 . The data processing module 120 is used to sequentially read the current program in the program package from the storage module 130 under the control of the control module 110 , and send the read current program to the control module 110 .
[0055] The control module 110 is also connected to the communication interface 150, which is used to connect to the test board 300, so that the control module 110 downloads the current program to the test board 300 through the communication interface 150, obtains the program execution result obtained by the test board 300 executing the current program, and feeds back the program execution result to the host computer device 200 through the test interface 140.
[0056] In this embodiment, the FPGA chip 100 is an FPGA chip 100 of a system on chip (SOC) architecture with an embedded control module 110 (Microcontroller Unit, MCU). The test interface 140 can use a joint test action group (JTAG) interface. Since the host device 200 is connected to the test interface 140, the control module 110 can obtain a program package having multiple programs from the host device 200 through the test interface 140, and store the program package in the storage module 130.
[0057] The control module 110 controls the data processing module 120 to sequentially read multiple programs in the program package, determine the current program, and obtain the current program, wherein the current program indicates a program read sequentially, which can be any program among the multiple programs. If the data processing module 120 sequentially reads multiple programs in the program package and reads the second program in the program package, then the current program is the second program.
[0058] Since the communication interface 150 is connected to the test board 300, and the test board 300 is used to test multiple programs, the control module 110 downloads the current program to the test board 300 through the communication interface 150, and the test board 300 executes the current program to obtain the program execution result of the current program. The control module 110 obtains the program execution result of the current program through the communication interface 150, and then feeds back the program execution result to the host computer device 200 through the test interface 140. The host computer device 200 can view the program execution result of the current program. When the test board 300 has tested and executed multiple programs, the host computer device 200 can obtain the program execution results of multiple programs.
[0059] In summary, an FPGA chip provided in an embodiment of the present application is provided with: a control module, a data processing module, a storage module, a test interface and a communication interface; the data processing module is a data processing module composed of a programmable logic unit, wherein the control module is connected to the test interface to obtain a program package having multiple programs from a host computer device through the test interface; the control module is connected to the storage module to store the program package in the storage module; the data processing module is connected to the control module and the storage module, and the data processing module is used to sequentially read the current program in the program package from the storage module under the control of the control module, and send the read current program to the control module, and the control module is also connected to the communication interface, and the communication interface is used to connect to the test board, so that the control module downloads the current program to the test board through the communication interface, obtains the program execution result obtained by the test board executing the current program, and feeds back the program execution result to the host computer device through the test interface.
[0060] The FPGA chip of the present application can utilize the control function of the control module, the programmable logic function of the data processing module, and the storage function of the storage module. It can complete the storage, reading, and automatic sequential downloading of multiple programs in a program package on the FPGA chip, and finally feedback the program execution results of multiple programs to the host computer device. There is no need to manually download and transmit each program, which saves labor costs and improves the testing efficiency of multiple programs.
[0061] Based on the above embodiment, the present application embodiment also provides a schematic diagram of another FPGA chip, Figure 3 A schematic diagram of another FPGA chip provided in an embodiment of the present application, such as Figure 3 As shown, the data processing module 120 includes: a data reading logic unit 121 , a data buffering logic unit 122 and a data checking logic unit 123 .
[0062] The data reading logic unit 121 is connected to the control module 110, the storage module 130 and the data buffering logic unit 122. The data reading logic unit 121 is used to sequentially read the current program in the program package from the storage module 130 under the control of the control module 110, and send the read current program to the data buffering logic unit 122.
[0063] In this embodiment, the data reading logic unit 121 reads each program in sequence according to the arrangement order of multiple programs in the program package. For example, if the first program has been read and the program execution result of the first program has been fed back to the host computer device 200, the data reading logic unit 121 reads the second program in sequence. At this time, the second program is the current program, and the data reading logic unit 121 sends the current program to the data buffering logic unit 122.
[0064] Optionally, the data reading logic unit 121 is further used to convert the read current program from a parallel data structure into a serial data structure and send the result to the data buffering logic unit 122 under the control of the control module 110 .
[0065] Specifically, after reading the current program, the data reading logic unit 121 converts the current program from a parallel data structure to a serial data structure, and then sends it to the data buffering logic unit 122. By converting the data structure, transmission lines are saved and anti-interference capability is improved.
[0066] The data buffer logic unit 122 is also connected to the control module 110 and the data verification logic unit 123. The data buffer logic unit 122 is used to buffer the current program sent by the data reading logic unit 121 under the control of the control module 110, and send the current program to the data verification logic unit 123.
[0067] Among them, the data buffer logic unit 122 can adopt a data first-in-first-out logic unit (First Input First Output, FIFO), and the data buffer logic unit 122 is used to buffer data of the current program, improve the running speed and stability of the FPGA chip 100, and then send the current program to the data verification logic unit 123.
[0068] The data verification logic unit 123 is also connected to the control module 110 . The data verification logic unit 123 is used to verify the current program sent by the data buffer logic unit 122 under the control of the control module 110 , and send the verified current program to the control module 110 .
[0069] Specifically, the data verification logic unit 123 verifies and corrects the current program to ensure the correctness of the current program data. When the verification is successful and it is determined that the current program is correct, the current program is sent to the control module 110 .
[0070] The data reading logic unit, data buffering logic unit and data verification logic unit provided in the present application perform logical processing on multiple programs in a program package, realize sequential reading of multiple programs, determine the current program, and send it to the control module after the current program is verified to be correct, thereby ensuring the accuracy of the test of the current program.
[0071] The present application embodiment also provides another possible implementation of the FPGA chip, and further reference is made to Figure 3, FPGA chip 100 also includes: clock module 160; clock module 160 is connected to control module 110 and data processing module 120 respectively, and is used to provide clock synchronization signal. Clock module 160 can provide a unified time reference to synchronize and coordinate the normal operation of control module 110 and data processing module 120. In addition, the frequency of the clock synchronization signal provided by clock module 160 determines the transmission speed of the current program, and ensures the stability of the current program transmission.
[0072] The present application embodiment also provides another possible implementation of the FPGA chip, and further reference is made to Figure 3 , the FPGA chip 100 further includes: a reset button 170; the reset button 170 is connected to the data processing module 120, the clock module 160 and the control module 110. The reset button 170 can manually reset the FPGA chip 100 when an abnormality occurs in the current program processing of the FPGA chip 100, so that multiple modules in the FPGA chip 100 resume normal operation.
[0073] The present application also provides a possible implementation of a program testing method, which is applied to an FPGA chip. Figure 4 A flowchart of a program testing method provided in an embodiment of the present application; Figure 4 As shown, the method includes:
[0074] S101. A control module on the FPGA chip receives a program package having multiple programs sent by a host computer device through a test interface, and stores the program package in a storage module on the FPGA chip.
[0075] In this embodiment, the FPGA chip is an FPGA chip of SOC architecture with an embedded control module. The test interface can use a JTAG interface. Since the host device is connected to the test interface, the control module can obtain a program package with multiple programs from the host device through the test interface and store the program package in the storage module.
[0076] S102: The control module controls the data processing module to sequentially read the current program in the program package from the storage module, and sends the read current program to the control module.
[0077] Specifically, the control module controls the data processing module to sequentially read multiple programs in the program package, determine the current program, and obtain the current program, wherein the current program indicates a program read sequentially, which can be any program among the multiple programs. If the data processing module sequentially reads multiple programs in the program package and reads the second program in the program package, then the current program is the second program.
[0078] S103, the control module transmits the current program to the test board through the communication interface, so that the test board executes the current program and obtains the program execution result of the current program.
[0079] S104: The control module obtains the program execution result returned by the test board through the communication interface.
[0080] S105. The control module sends the program execution result to the host computer device through the test interface.
[0081] Specifically, since the communication interface is connected to the test board, and the test board is used to test multiple programs, the control module downloads the current program to the test board through the communication interface, so that the test board executes the current program and obtains the program execution result of the current program. The control module obtains the program execution result of the current program from the test board through the communication interface, and then feeds back the program execution result to the host computer device through the test interface. The host computer device can view the program execution result of the current program. When the test board has tested and executed multiple programs, the host computer device can obtain the program execution results of multiple programs.
[0082] In summary, an embodiment of the present application provides a program testing method, which is applied to an FPGA chip. The method includes: a control module on the FPGA chip receives a program package having multiple programs sent by a host computer device through a test interface, and stores the program package in a storage module on the FPGA chip; the control module controls the data processing module to sequentially read the current program in the program package from the storage module, and sends the read current program to the control module; the control module transmits the current program to a test board through a communication interface, so that the test board executes the current program and obtains a program execution result of the current program; the control module obtains the program execution result returned by the test board through the communication interface, and the control module sends the program execution result to the host computer device through the test interface.
[0083] The method of the present application controls the data processing module through the control module, so that the data processing module sequentially reads multiple programs in the program package, determines the current program, and downloads the current program to the test board, so that the test board executes the current program to obtain the program execution result of the current program, and finally sends the program execution result to the host computer device. The host computer device transmits the program package with multiple programs at one time, and the program execution results of the multiple programs can be obtained without manually downloading and transmitting each program, thereby saving labor costs and improving the testing efficiency of multiple programs.
[0084] On the basis of the above-mentioned embodiments, the embodiments of the present application further provide another possible implementation of the program testing method, wherein the data processing module includes: a data reading logic unit, a data buffering logic unit and a data verification logic unit. Figure 5A flowchart of another program testing method provided in an embodiment of the present application is shown in FIG. Figure 5 As shown, the control module controls the data processing module to sequentially read the current program in the program package from the storage module, and sends the read current program to the control module, including:
[0085] S201 , the control module controls the data reading logic unit to sequentially read the current program in the program package from the storage module, and sends the read current program to the data buffering logic unit.
[0086] In this embodiment, the data reading logic unit reads each program in sequence according to the arrangement order of multiple programs in the program package. For example, if the first program has been read and the program execution result of the first program has been fed back to the host computer device, the data reading logic unit reads the second program in sequence. At this time, the second program is the current program, and the data reading logic unit sends the current program to the data buffer logic unit.
[0087] It should be noted that after the data reading logic unit reads the current program, it converts the current program from a parallel data structure to a serial data structure, and then sends it to the data buffer logic unit. By converting the data structure, the transmission line is saved and the anti-interference ability is improved.
[0088] Optionally, if the control module receives a read empty flag signal transmitted by the data read logic unit, the control module sends a read program end signal to the host device through the test interface.
[0089] Specifically, when the data reading logic unit reads the program in the storage module, it determines that multiple programs stored in the storage module are all read. If there is no program in the storage module, a read empty flag signal is sent to the control module. After the control module receives the read empty flag signal, it sends a program reading end signal to the host device through the test interface to inform the host device that a new program package can be transmitted.
[0090] S202: The control module controls the data buffering logic unit to buffer the current program sent by the data reading logic unit, and sends the current program to the data verification logic unit.
[0091] Among them, the data buffer logic unit can adopt a data first-in-first-out logic unit (First Input First Output, FIFO), the data buffer logic unit is used to buffer data of the current program, improve the running speed and stability of the FPGA chip, and then send the current program to the data verification logic unit.
[0092] Optionally, if the control module receives an overflow flag signal transmitted by the data buffer logic unit, the control module controls the data reading logic unit to reduce the reading speed.
[0093] Specifically, a maximum capacity threshold is pre-set in the data buffer logic unit. When it is detected that the data capacity buffered in the data buffer logic unit is greater than or equal to the maximum capacity threshold, an overflow flag signal is sent to the control module. After receiving the overflow flag signal, the control module controls the data reading logic unit to reduce the reading speed to improve the stability of the FPGA chip in processing the current program and prevent congestion.
[0094] S203: The control module controls the data verification logic unit to verify the current program sent by the data buffer logic unit, and sends the verified current program to the control module.
[0095] Specifically, the data verification logic unit verifies and corrects the current program to ensure the correctness of the current program data. When the verification is passed and it is determined that the current program is correct, the current program is sent to the control module.
[0096] In the method provided in the embodiment of the present application, the control module controls the data reading logic unit to sequentially read the current program in the program package from the storage module, and sends the read current program to the data buffering logic unit, the control module controls the data buffering logic unit to buffer the current program sent by the data reading logic unit, and sends the current program to the data verification logic unit, the control module controls the data verification logic unit to verify the current program sent by the data buffering logic unit, and sends the current program that passes the verification to the control module, thereby realizing the sequential reading of multiple programs, determining the current program, and sending the current program to the control module after the current program is verified to be correct, thereby ensuring the accuracy of the test of the current program.
[0097] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. An FPGA chip, characterized in that: The FPGA chip is provided with: a control module, a data processing module, a storage module, a test interface and a communication interface; the data processing module is a data processing module composed of a programmable logic unit; Wherein, the control module is connected to the test interface to obtain a program package having multiple programs from a host computer device through the test interface; the control module is connected to the storage module to store the program package in the storage module; The data processing module is connected to the control module and the storage module, and is used for sequentially reading the current program in the program package from the storage module under the control of the control module, and sending the read current program to the control module; The control module is also connected to the communication interface, which is used to connect to the test board, so that the control module downloads the current program to the test board through the communication interface, obtains the program execution result obtained by the test board executing the current program, and feeds back the program execution result to the host computer device through the test interface.
2. The chip according to claim 1, characterized in that: The data processing module includes: a data reading logic unit, a data buffering logic unit and a data checking logic unit; The data reading logic unit is connected to the control module, the storage module and the data buffering logic unit, and the data reading logic unit is used to sequentially read the current program in the program package from the storage module under the control of the control module, and send the read current program to the data buffering logic unit; The data buffer logic unit is also connected to the control module and the data verification logic unit, and the data buffer logic unit is used to perform data buffering on the current program sent by the data reading logic unit under the control of the control module, and send the current program to the data verification logic unit; The data verification logic unit is also connected to the control module. The data verification logic unit is used to verify the current program sent by the data buffer logic unit under the control of the control module, and send the current program that passes the verification to the control module.
3. The chip according to claim 2, characterized in that: The data reading logic unit is also used to, under the control of the control module, convert the read current program from a parallel data structure into a serial data structure and then send the converted data to the data buffering logic unit.
4. The chip according to claim 1, characterized in that The FPGA chip also includes: a clock module; the clock module is connected to the control module and the data processing module respectively, and is used to provide a clock synchronization signal.
5. The chip according to claim 4, characterized in that: The FPGA chip also includes: a reset button; the reset button is connected to the data processing module, the clock module and the control module.
6. A program testing method, characterized in that: Applied to the FPGA chip described in any one of claims 1 to 4 above, the method comprises: The control module on the FPGA chip receives a program package having multiple programs sent by the host computer device through the test interface, and stores the program package in the storage module on the FPGA chip; The control module controls the data processing module to sequentially read the current program in the program package from the storage module, and sends the read current program to the control module; The control module transmits the current program to the test board through the communication interface, so that the test board executes the current program to obtain a program execution result of the current program; The control module obtains the program execution result returned by the test board through the communication interface; The control module sends the program execution result to the host computer device through the test interface.
7. The method according to claim 6, characterized in that The data processing module includes: a data reading logic unit, a data buffering logic unit and a data checking logic unit; the control module controls the data processing module to sequentially read the current program in the program package from the storage module, and sends the read current program to the control module, including: The control module controls the data reading logic unit to sequentially read the current program in the program package from the storage module, and sends the read current program to the data buffer logic unit; The control module controls the data buffering logic unit to perform data buffering on the current program sent by the data reading logic unit, and sends the current program to the data verification logic unit; The control module controls the data verification logic unit to verify the current program sent by the data buffer logic unit, and sends the current program that passes the verification to the control module.
8. The method according to claim 7, characterized in that The method further comprises: If the control module receives the read empty flag signal transmitted by the data read logic unit, the control module sends a read program end signal to the host computer device through the test interface.
9. The method according to claim 7, characterized in that The method further comprises: If the control module receives the overflow flag signal transmitted by the data buffer logic unit, the control module controls the data reading logic unit to reduce the reading speed.
10. A program testing system, characterized in that: The program testing system comprises: a host computer device, a test board and the FPGA chip described in any one of claims 1 to 4 above; The host computer device is connected to the test interface in the FPGA chip, and is used to transmit a program package having multiple programs to the control module in the FPGA chip through the test interface, and obtain the program execution result of the current program from the control module through the test interface; The test board is connected to the communication interface in the FPGA chip, and is used to obtain the current program through the communication interface, execute the current program, obtain the program execution result of the current program, and feed back the program execution result to the control module through the communication interface.