A micro-architecture design space exploration method based on deep learning

Abstract

The application discloses a micro-architecture design space exploration method based on deep learning, comprising: obtaining target processor micro-architecture parameters, constituting a design space, obtaining performance indicators of different design points in the design space, and dividing key modules based on the design points; creating a directed acyclic graph according to the key modules, constructing a prediction model using a graph attention network to obtain a parameter optimal solution in the directed acyclic graph that meets a design target; splicing the directed acyclic graph into a global graph to obtain interconnection parameters of the key modules, introducing federal learning to train a global prediction model, and predicting and evaluating performance data of the parameter optimal solution based on the global graph; and when the performance evaluation result meets a preset performance standard, outputting target configuration parameters of the target processor under each configuration dimension. The application performs micro-architecture design space exploration in a graph embedding space, provides decision support for chip design, and improves design efficiency and flexibility by taking the idea of coordination between different design stages and design modes.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor micro-architecture design, and more particularly, to a micro-architecture design space exploration method based on deep learning. BACKGROUND

[0002] With the advent of the era of big data and the Internet of Things, important breakthroughs have been made in the research of algorithm models such as neural networks and graph computing for data-intensive applications. Data-intensive applications often rely on the storage and processing of massive amounts of data, but traditional computer hardware facilities have gradually been unable to meet the computing needs of the above application scenarios. The reason is that, on the one hand, Moore's Law is slowing down, and the size of the transistor has almost reached the physical limit, making it difficult to maintain the speed of improvement in computing power and energy efficiency; on the other hand, no matter how the chip integration is improved, a large proportion of energy is still needed to move data to the processor, and the potential of hardware computing resources is difficult to fully exploit.

[0003] The effect of micro-architecture design space exploration determines the market competitiveness of the processor, but the exploration process is complex and time-consuming, posing a high challenge to the design personnel. First, the load running during processor evaluation is large and time-consuming, and second, micro-architecture design involves numerous and complex circuit modules. Based on the register transfer level (RTL), the design and evaluation of the circuit are time-consuming, and the simulation speed is several orders of magnitude slower than the physical machine, which takes months to complete a complete evaluation of a load. In the face of increasingly complex micro-architecture design and exponentially increasing design space, full-space brute-force exploration cannot be achieved. Therefore, how to adopt the idea of coordination between different design stages and design modes in micro-architecture design, consider the mutual influence of different stages, and realize parameter optimization is the key point. SUMMARY

[0004] To solve the above technical problems, the present application provides a micro-architecture design space exploration method based on deep learning, which aims to solve the problems of tedious and time-consuming existing micro-architecture design process, and difficulty in achieving global performance optimization.

[0005] The present application provides a micro-architecture design space exploration method based on deep learning, which includes:

[0006] Obtaining target processor micro-architecture parameters, combining the micro-architecture parameters to form a design space, obtaining the performance indicators of different design points in the design space, and clustering the design points to obtain the key module division results;

[0007] Creating a directed acyclic graph according to the design points in the key module and the corresponding performance indicators, obtaining the embedded representation of the design points through graph representation learning, and constructing a prediction model using a graph attention network to obtain the optimal solution of the parameters in the directed acyclic graph that meet the design target;

[0008] The directed acyclic graphs are spliced into a global graph to obtain interconnection parameters between key modules, a federated learning algorithm is introduced to initialize a global prediction model, and the global prediction model is used to predict a micro-architecture parameter optimal solution set based on the global graph;

[0009] When the performance evaluation result meets the preset performance standard, the target configuration parameters of the target processor under each configuration dimension are output.

[0010] In this scheme, a target processor micro-architecture parameter is obtained, a design space is formed according to the micro-architecture parameter combination, and performance indicators of different design points in the design space are obtained.

[0011] The design target of the target processor is collected, the micro-architecture parameters involved are determined based on the design target, different feature vectors are generated according to the micro-architecture parameter combination, the feature vectors are taken as design points, and all design points are aggregated to form a design space.

[0012] A large amount of hardware test instance data is obtained, and the micro-architecture parameters corresponding to the design points are used to filter corresponding performance results in the hardware test instance data, corresponding performance indicator labels are obtained according to the performance results, and performance indicator label sets corresponding to each design point are obtained.

[0013] A search window is constructed, the Pearson correlation coefficients of the design target and the performance indicator label sets corresponding to each design point are calculated in the search window, and the performance indicator labels of each design point that meet the correlation degree standard are obtained after traversing the entire design space.

[0014] The performance indicators of different design points in the design space are determined according to the performance indicator labels obtained in each design point.

[0015] In this scheme, the design points are clustered to obtain key module division results, specifically:

[0016] The design points with performance indicator labels are obtained, and clustering is performed using a clustering algorithm, an initial clustering center is randomly selected, Mahalanobis distance is selected as a metric function, and a membership matrix of the design points to the initial clustering center is calculated according to the metric function.

[0017] The maximum membership degree of the design points is obtained, when the maximum membership degree is greater than a preset hard clustering standard, the design points are attributed to the class cluster corresponding to the maximum membership degree, and when the maximum membership degree of the sample does not meet the preset hard clustering standard, it is judged whether the maximum membership degree of the design point to each class cluster meets a preset soft clustering standard, if multiple class clusters meet, the design points are attributed to the multiple class clusters.

[0018] Iterative clustering is performed through clustering center updating, and when the maximum iteration number is met, the class cluster division corresponding to the last clustering result is selected to generate a key module division result.

[0019] In this scheme, a directed acyclic subgraph is created based on the design points and corresponding performance indicators in the key modules. The embedding representation of the design points is then obtained through graph representation learning. Specifically:

[0020] In the key module, a node set is generated based on the design points with performance index labels, and an edge structure set is generated based on the operation associations between the design points. A directed acyclic subgraph corresponding to the key module is created based on the node set and the edge structure set.

[0021] In the directed acyclic subgraph, the initial weights of each node are calculated according to the preset Pareto rank algorithm. The design point nodes in the directed acyclic subgraph are pre-trained and embedded using meta-path embedding to obtain the meta-paths of each design point node.

[0022] In the meta-path, a graph attention mechanism is used to obtain the importance of each meta-path neighbor to the design point node. Based on the importance, the weight of the meta-path neighbor is obtained. Based on the initial weight and the weight, the meta-path neighbors are weighted and averaged to obtain the output of the design point node after graph attention aggregates the neighbor features, and the embedded representation of the design point is generated.

[0023] In this scheme, a graph attention network is used to construct a prediction model to obtain the optimal parameter solution that satisfies the design objective in the directed acyclic subgraph, specifically:

[0024] The corresponding load is read using the design target, and the load is run through the simulator to simulate the design points in each key module. The performance index evaluation value of each design point under the load is output, and a training set is constructed based on the performance index evaluation value.

[0025] The concept of global regret is introduced into the graph attention network to construct a prediction model. The model is trained using the training set, and the embedding representation of the design point is obtained based on the training set and the directed acyclic subgraph of the key module.

[0026] Based on the embedded representation, the weights of each edge corresponding to each design point are read, the weights are converted into global regrets, a greedy strategy is used to search for the initial optimal path, and then the initial optimal path is iteratively optimized using the 2-Opt heuristic algorithm to obtain the optimal solution of parameters for each design point that satisfies the design objective.

[0027] In this scheme, the directed acyclic subgraphs are concatenated into a global graph to obtain the interconnection parameters between key modules, specifically as follows:

[0028] Based on the operational relationships between key modules, the corresponding directed acyclic subgraphs are spliced ​​together to generate a global graph. An encoder is then constructed using a multi-layer graph convolutional neural network to learn the representation of the global graph.

[0029] The performance correlation of the key module in the micro-architecture is obtained in the construction of the adjacency matrix in the global graph, different weights are assigned to the neighbor nodes by combining average pooling and maximum pooling;

[0030] By aggregation of the neighbor nodes, the representation of the global graph node is updated, the updated global graph node representation is imported into the decoder, the RNN network is used for feature reorganization, and high-dimensional features are output, the interconnection parameters between the subgraphs of the key modules are obtained by using the high-dimensional features, and the edge structure of the global graph is set according to the interconnection parameters.

[0031] In the scheme, the global prediction model is initialized by introducing a federated learning algorithm, and specifically:

[0032] The prediction model corresponding to each key module is taken as a local model, the error value of the performance index prediction value of the local model and the performance index evaluation value in the training set is obtained, the prediction model of each key module is retrained by introducing federated learning, and the local model is selectively selected and uploaded to the server for model aggregation after training, and the average error of each local model is calculated;

[0033] The error of the aggregated global prediction model is taken as a reference value, the local model is scored to generate a confidence according to the average error, the local model with an average detection error greater than the reference value is screened, and the score of the screened local model is set to zero;

[0034] The local model with a score other than zero is uploaded and compressed according to the confidence, each local model is aggregated, the parameters of the local model and the global prediction model are updated, the optimal model parameters are obtained after iteration, and the global prediction model is output.

[0035] In the scheme, the global prediction model is used to predict the optimal solution set of the micro-architecture parameters based on the global graph, and specifically:

[0036] The parameter optimal solution of the design point output by the prediction model corresponding to each key module is mapped into the global graph, the global prediction model is trained, the global regret of the key module node corresponding edge is obtained, a greedy strategy is used to search an initial optimal path, and the initial optimal path is iteratively optimized by combining a 2-Opt heuristic algorithm to obtain the parameter optimal solution of each key module node.

[0037] The micro-architecture parameters of the design point are configured according to the parameter optimal solution of each key module node, and are integrated into the micro-architecture parameter optimal solution set, the micro-architecture parameter optimal solution set is put into a virtual prototype platform to obtain simulation verification data, and if a preset design target is reached, the target configuration parameters of the target processor under each configuration dimension are output.

[0038] Compared with the prior art, the beneficial effects of the present application are:

[0039] The application carries out micro-architecture design space exploration in graph embedding space, provides decision support for chip design, and improves design efficiency and flexibility by taking the idea of coordination of different design stages and design modes. The message passing mechanism of the graph attention network effectively learns the relevant information between nodes, and captures the gap between each edge and the optimal strategy. According to the attention mechanism, the weight of each edge is obtained to solve the global regret, and then a better initial solution is obtained through the greedy search strategy, which reduces the number of heuristic iteration rounds and improves the prediction accuracy of the prediction model, thereby improving the exploration efficiency of the overall design space. And through federated learning, the local model is integrated to make the global prediction model obtain better accuracy and generalization ability. BRIEF DESCRIPTION OF DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments or examples of the present application, the drawings needed to be used in the embodiments or examples will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0041] Figure 1 A flowchart of a micro-architecture design space exploration method based on deep learning is shown.

[0042] Figure 2 A flowchart of obtaining the optimal solution of parameters meeting the design target in the directed acyclic graph is shown.

[0043] Figure 3 A flowchart of initializing a global prediction model by introducing a federated learning algorithm is shown.

[0044] Figure 4 A framework of a micro-architecture design space exploration system based on deep learning is shown. DETAILED DESCRIPTION

[0045] In order to more clearly illustrate the technical solutions in the embodiments or examples of the present application, the drawings needed to be used in the embodiments or examples will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0046] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, however, the present application can also be implemented in other ways different from those described herein, therefore, the scope of protection of the present application is not limited by the specific embodiments disclosed below.

[0047] Figure 1 A flowchart of a micro-architecture design space exploration method based on deep learning is shown. A flowchart of a micro-architecture design space exploration method based on deep learning is shown.

[0048] As Figure 1 shown, the embodiment provides a micro-architecture design space exploration method based on deep learning, including:

[0049] S102, obtaining target processor micro-architecture parameters, combining the micro-architecture parameters to form a design space, obtaining performance indicators of different design points in the design space, clustering the design points to obtain key module division results;

[0050] S104, creating a directed acyclic graph according to the design points and corresponding performance indicators in the key module, obtaining embedded representations of the design points through graph representation learning, and constructing a prediction model using a graph attention network to obtain a parameter optimal solution in the directed acyclic graph that meets the design target;

[0051] S106, splicing each directed acyclic graph into a global graph to obtain interconnection parameters between key modules, introducing a federated learning algorithm to initialize a global prediction model, and using the global prediction model to predict a set of micro-architecture parameter optimal solutions based on the global graph;

[0052] S108, when the performance evaluation result meets the preset performance standard, outputting the target configuration parameters of the target processor under each configuration dimension.

[0053] It should be noted that the design target of the target processor is collected, the micro-architecture parameters involved are determined based on the design target, in order to formalize the representation, different feature vectors are generated according to the combination of the micro-architecture parameters, the feature vectors are taken as design points, and all design points are aggregated to form a design space; a large amount of hardware test instance data is obtained, and the corresponding performance results are filtered in the hardware test instance data using the micro-architecture parameters corresponding to the design points, the corresponding performance indicator labels are obtained according to the performance results, the performance indicator label set corresponding to each design point is obtained, including execution time, cycle number, number of instructions per cycle, energy consumption, power, area, and energy-delay product. A search window is constructed, the Pearson correlation coefficients of the design target and the performance indicator label set corresponding to each design point are calculated in the search window, and the performance indicator labels of each design point that meet the correlation degree standard are obtained after traversing the entire design space; the performance indicators of different design points in the design space are determined according to the performance indicator labels obtained in each design point.

[0054] It should be noted that the design points with performance index labels are obtained, and clustering is performed by using a K-means clustering algorithm, an initial clustering center is randomly selected, and the K-means clustering algorithm is optimized according to a genetic algorithm to set an optimal initial clustering center. Mahalanobis distance is selected as a measurement function, and a membership matrix of the design points to the initial clustering center is calculated according to the measurement function; a maximum membership degree of the design points is obtained, and when the maximum membership degree is greater than a preset hard clustering standard, the design points are attributed to a class cluster corresponding to the maximum membership degree; when the maximum membership degree of the sample does not satisfy the preset hard clustering standard, it is judged whether the maximum membership degree of the design points to each class cluster satisfies a preset soft clustering standard, and if multiple class clusters satisfy the standard, the design points are attributed to the multiple class clusters; iterative clustering is performed through clustering center updating, and when a maximum iteration number is satisfied, a class cluster corresponding to a last clustering result is selected to generate a key module division result. Since the same design point usually contains repeated processor prototype data, the design points are soft clustered and divided into multiple class clusters that meet the standard, the hard clustering result is supplemented, and the division precision is improved.

[0055] It should be noted that a node set is generated in a key module according to design points with performance index labels, an edge structure set is generated according to operation instruction association between the design points, and a directed acyclic graph corresponding to the key module is created based on the node set and the edge structure set; a corresponding load is read by using a design target, and each design point in each key module is simulated by running the load through a simulator, and a performance index evaluation value of each design point under the load is output.

[0056] In the Pareto algorithm, in all design points, the 1 group of design points not dominated by other design points is called the Pareto optimal solution set; for each design point, its initial non-dominated set is empty, and other design points are traversed: if the performance index evaluation value of other design points is higher than that of the design point, the other design points are added to the non-dominated set of the design point; if the performance index evaluation value of other design points is lower than that of the design point, the number of design points that can dominate the design point is increased by one; after the traversal is completed, if the number of design points that can dominate the design point is zero, the design point is added to the front set, and the corresponding Pareto level is set to the first level; the non-dominated set is traversed for each design point in the front set until the number of dominations is zero, and the Pareto level of each design point is output; wherein, with each additional round of traversal, the Pareto level of the design point in each round of the front set is increased by one level based on the last round. In the directed acyclic graph, the initial weight of each node is calculated by the above steps, the design point nodes in the directed acyclic graph are pre-embedded by using meta-path embedding, and the meta-path of each design point node is obtained; preferably, the design point nodes in the directed acyclic graph are embedded by using Metapath2vec++ pre-embedding high-dimensional representation space.

[0057] In the graph attention network, in the process of each step of message passing, each node receives information from its adjacent nodes and generates new messages to send to other nodes through some calculations, each layer operates on the graph representation of the data and outputs a new graph representation, the importance of each meta-path neighbor to the design point node is obtained in the meta-path by using the graph attention mechanism, the weight of the meta-path neighbor is obtained based on the importance, and the meta-path neighbor is weighted and averaged based on the initial weight combined with the weight to obtain the output of the design point node after the graph attention aggregation neighbor feature, and the embedding representation of the design point is generated.

[0058] Figure 2 A flowchart for obtaining a parameter optimal solution that meets a design target in a directed acyclic graph is shown.

[0059] According to an embodiment of the present application, a prediction model is constructed by using a graph attention network to obtain a parameter optimal solution that meets a design target in a directed acyclic graph, specifically:

[0060] S202, a corresponding load is read by using a design target, a simulator is used to run the load to simulate the design points in each key module, and the performance index evaluation value of each design point under the load is output, and a training set is constructed according to the performance index evaluation value;

[0061] S204, introduce the global regret idea in the graph attention network, construct a prediction model, train using the training set, and obtain the embedding representation of the design point according to the training set and the directed acyclic graph of the key module;

[0062] S206, according to the embedding representation, read the weight of each edge corresponding to each design point, convert the weight into global regret, search the initial optimal path using the greedy strategy, and combine the 2-Opt heuristic algorithm to iteratively optimize the initial optimal path to obtain the parameter optimal solution of each design point satisfying the design target.

[0063] It should be noted that, since the greedy strategy is prone to local optimization, in order to improve the performance of the heuristic algorithm of the greedy strategy, a common method is to set regret to measure the future cost of an action, while the action will produce an immediate reward to alleviate the short-sightedness of the greedy combinatorial optimization algorithm. In the directed acyclic graph, the regret is extended to the weight of each edge relative to the global optimal solution. The global regret represents the weight of each edge in the directed acyclic graph, including the weight obtained by the graph attention mechanism and the initial weight of the node. The difference between each edge and the optimal solution is represented in the form of weight. The greedy strategy evaluates the advantages and disadvantages of each route through the global regret, and selects the path with the lowest cost in turn. Finally, a better design point meta-path is constructed, and the parameter optimal solution of each design point satisfying the design target is obtained.

[0064] The basic idea of the 2-Opt algorithm is to improve the quality of the solution by adjusting two edges on the path. First, select two points i and k in the path, and flip the path between the two points. Compare the length of the original path and the flipped path. If the flipped path is better, accept the flip and repeat the above process. Otherwise, give up the flip and continue to find new point pairs. The 2-Opt algorithm has high search efficiency and can find approximate solutions in a short time.

[0065] According to the operation association between the key modules, the corresponding directed acyclic graphs are spliced to generate a global graph. A multi-layer graph convolutional neural network is used to construct an encoder to learn and represent the global graph. In the global graph, an adjacency matrix is constructed to obtain the performance association of the key modules in the microarchitecture. Average pooling and maximum pooling are combined to assign different weights to neighbor nodes. Through the aggregation of neighbor nodes, the representation of the global graph nodes is updated. The updated global graph node representation is imported into the decoder. The RNN network is used for feature reorganization to output high-dimensional features. The interconnection parameters between the key module subgraphs are obtained using the high-dimensional features. According to the interconnection parameters between the key modules, the edge structure of the global graph is set, and the associated modules are taken as nodes in the global graph.

[0066] Figure 3 A flowchart for initializing a global prediction model by introducing a federated learning algorithm is shown.

[0067] According to the embodiment of the present application, the federal learning algorithm is introduced to initialize the global prediction model, specifically:

[0068] In S302, the prediction model corresponding to each key module is taken as a local model, the error value of the performance index prediction value of the local model and the performance index evaluation value in the training set is obtained, the federal learning is introduced to retrain the prediction model of each key module, the local model is selectively selected after training and uploaded to the server for model aggregation, and the average error of each local model is calculated;

[0069] In S304, the error of the aggregated global prediction model is taken as a reference value, the local model is scored to generate a confidence according to the average detection error, the local model with an average detection error greater than the reference value is screened out, and the score of the screened local model is set to zero;

[0070] In S306, the local model with a score other than zero is uploaded and compressed according to the confidence, each local model is aggregated, the parameters of the local model and the global prediction model are updated, the optimal model parameters are obtained after iteration, and the global prediction model is output.

[0071] It should be noted that the federal learning is used to realize the integrated learning of the local model, obtain more superior precision and generalization ability, dynamically select the local model for uploading in the federal learning, suppress the unsatisfactory local model with a score of zero, optimize the aggregation speed of the model, and redivide the parameters of the global prediction model to the unsatisfactory local model for iterative training after parameter updating. After multiple rounds of uploading and issuing, the model converges after training, and the global prediction model is constructed. The optimal solution of the parameter of the design point output by the prediction model corresponding to each key module is mapped to the global graph, guiding the training of the global prediction model. The global regret of the edge corresponding to the key module node is obtained, and the greedy strategy is used to search for an initial optimal path. Then, the initial optimal path is iteratively optimized by combining the 2-Opt heuristic algorithm to obtain the optimal solution of the parameter of each key module node. The micro-architecture parameters of the design point are configured according to the optimal solution of the parameter of each key module node, integrated into the optimal solution set of the micro-architecture parameters, and put into a virtual prototype platform to obtain simulation verification data, for example, verified by Proteus software on a BOOM processor. If the preset design target is reached, the target configuration parameters of the target processor under each configuration dimension are output.

[0072] Figure 4 The architecture of the micro-architecture design space exploration system based on deep learning is shown.

[0073] The embodiment provides a micro-architecture design space exploration system 4 based on deep learning, which comprises a data acquisition module 401, a key module division module 402, a simulator module 403, a local prediction model module 404, a global prediction model module 405 and a simulation verification module 406.

[0074] The data acquisition module is responsible for acquiring target processor micro-architecture parameters, constituting a design space, and acquiring performance indexes of different design points in the design space.

[0075] The key module division module is responsible for clustering the design points to obtain a key module division result, and creating a directed acyclic graph according to the design points in the key module and the corresponding performance indexes.

[0076] The simulator module is responsible for simulating each design point by running a load, outputting a performance index evaluation value of each design point under the load, and constructing a training set.

[0077] The local prediction model module is responsible for obtaining an embedding representation of the design point through graph representation learning, constructing and training a prediction model by using a graph attention network and the training set, and obtaining a parameter optimal solution set meeting a design target.

[0078] The global prediction model module is responsible for splicing the directed acyclic graphs into a global graph to obtain interconnection parameters between the key modules, introducing a federated learning algorithm to initialize a global prediction model, and predicting a micro-architecture parameter optimal solution set based on the global graph by using the global prediction model.

[0079] The simulation verification module is responsible for verifying the micro-architecture parameter optimal solution set on a BOOM processor by using Proteus software, and when a performance evaluation result meets a preset performance standard, outputting target configuration parameters of the target processor under each configuration dimension according to the micro-architecture parameter optimal solution set.

[0080] The embodiment provides a computer readable storage medium, wherein the computer readable storage medium comprises a micro-architecture design space exploration method program based on deep learning, and the micro-architecture design space exploration method program based on deep learning is executed by a processor to realize the steps of the micro-architecture design space exploration method based on deep learning.

[0081] In several embodiments provided in the present application, it should be understood that the disclosed devices and methods can be implemented in other manners. The above described device embodiments are merely exemplary. For example, the division of the units is merely a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the units shown or discussed can be indirect coupling or communication connection through some interfaces, devices or units, and can be electrical, mechanical or in other forms.

[0082] In addition, each function unit in the embodiments of the present application can be integrated into one processing unit, each unit can be a separate unit, or two or more units can be integrated into one unit; the above integrated unit can be implemented in the form of hardware, or in the form of hardware plus software function unit.

[0083] Those skilled in the art can understand that all or part of the steps of the above method embodiments can be completed by a program instructing related hardware, and the foregoing program can be stored in a computer readable storage medium, and the program is executed to perform the steps of the above method embodiments; and the foregoing storage medium includes mobile storage devices, read-only memory (ROM), random access memory (RAM), magnetic discs or optical discs, and various media that can store program codes.

[0084] Alternatively, the above integrated unit of the present application, if implemented in the form of a software function module and sold or used as an independent product, can also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application can be embodied in the form of a software product, and the computer software product is stored in a storage medium, and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. The foregoing storage medium includes: mobile storage devices, ROM, RAM, magnetic discs or optical discs, and various media that can store program codes.

[0085] The above description is merely specific embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed in the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A deep learning based microarchitecture design space exploration method, characterized in that, The method comprises the following steps: Obtaining target processor micro-architecture parameters, combining the micro-architecture parameters to form a design space, obtaining performance indicators of different design points in the design space, and clustering the design points to obtain a key module division result; Creating a directed acyclic graph according to the design points and corresponding performance indicators in the key module, obtaining the embedded representation of the design points through graph representation learning, and constructing a prediction model using a graph attention network to obtain the parameter optimal solution in the directed acyclic graph that meets the design target; Splicing each directed acyclic graph into a global graph to obtain the interconnection parameters between key modules, introducing a federated learning algorithm to initialize a global prediction model, and predicting the optimal solution set of the micro-architecture parameters based on the global graph using the global prediction model; When the performance evaluation result meets the preset performance standard, the target configuration parameters of the target processor under each configuration dimension are outputted; Creating a directed acyclic graph according to the design points and corresponding performance indicators in the key module, and obtaining the embedded representation of the design points through graph representation learning, specifically: Generating a node set according to the design points with performance indicator labels in the key module, generating an edge structure set according to the operation association between the design points, and creating a directed acyclic graph corresponding to the key module based on the node set and the edge structure set; Calculating the initial weight of each node in the directed acyclic graph according to a preset Pareto level algorithm, pre-training the design point nodes in the directed acyclic graph using meta-path embedding, and obtaining the meta-path of each design point node; Using a graph attention mechanism in the meta-path to obtain the importance of each meta-path neighbor to the design point node, obtaining the weight of the meta-path neighbor based on the importance, and performing weighted averaging on the meta-path neighbor based on the initial weight and the weight to obtain the output of the design point node after the graph attention aggregation neighbor feature, and generating the embedded representation of the design point; Constructing a prediction model using a graph attention network to obtain the parameter optimal solution in the directed acyclic graph that meets the design target, specifically: Reading the corresponding load using the design target, simulating the design points in each key module by running the load through a simulator, outputting the performance indicator evaluation value of each design point under the load, and constructing a training set according to the performance indicator evaluation value; Introducing a global regret idea in the graph attention network to construct a prediction model, training the training set, and obtaining the embedded representation of the design point according to the training set and the directed acyclic graph of the key module; Reading the weight of each edge corresponding to each design point according to the embedded representation, converting the weight into a global regret, searching for an initial optimal path using a greedy strategy, and iteratively optimizing the initial optimal path using a 2-Opt heuristic algorithm to obtain the parameter optimal solution of each design point that meets the design target.

2. The deep learning based microarchitecture design space exploration method of claim 1, wherein, Obtaining target processor micro-architecture parameters, combining the micro-architecture parameters to form a design space, obtaining performance indicators of different design points in the design space, specifically: Collecting design targets of a target processor, determining micro-architecture parameters involved based on the design targets, generating different feature vectors according to the micro-architecture parameters, taking the feature vectors as design points, and aggregating all the design points to form a design space; Obtaining a large amount of hardware test instance data, and filtering corresponding performance results in the hardware test instance data by using micro-architecture parameters corresponding to the design points, obtaining corresponding performance index labels according to the performance results, and obtaining a performance index label set corresponding to each design point; Building a search window, calculating a Pearson correlation coefficient of the design target and the performance index label set corresponding to each design point in the search window, and obtaining performance index labels of each design point that meet a correlation degree standard after traversing the entire design space; Determining performance indexes of different design points in the design space according to the performance index labels obtained in each design point.

3. The deep learning based microarchitecture design space exploration method of claim 1, wherein, Clustering the design points to obtain a key module division result, specifically: Obtaining design points with performance index labels, and clustering by using a clustering algorithm, randomly selecting an initial clustering center, selecting Mahalanobis distance as a measurement function, and calculating a membership matrix of the design points to the initial clustering center according to the measurement function; Obtaining a maximum membership degree, when the maximum membership degree is greater than a preset hard clustering standard, the design point is attributed to a class cluster corresponding to the maximum membership degree, and when the maximum membership degree of the sample does not meet the preset hard clustering standard, it is judged whether the maximum membership degree of the design point to each class cluster meets a preset soft clustering standard, if multiple class clusters meet, the design point is attributed to the multiple class clusters; Iterative clustering is performed through clustering center updating, and when a maximum iteration number is met, a class cluster division corresponding to a last clustering result is selected to generate a key module division result.

4. The deep learning based microarchitecture design space exploration method of claim 1, wherein, Splicing each directed acyclic graph into a global graph to obtain interconnection parameters between key modules, specifically: Splicing the corresponding directed acyclic graphs according to the operation association between the key modules to generate a global graph, and learning and representing the global graph by using a multi-layer graph convolutional neural network to construct an encoder; Building an adjacency matrix in the global graph to obtain performance association of the key modules in the micro-architecture, and assigning different weights to neighbor nodes by using average pooling and maximum pooling combination; Through aggregation of the neighbor nodes, the representation of the global graph nodes is updated, the updated global graph node representation is imported into a decoder, features are reorganized by using an RNN network, high-dimensional features are output, the interconnection parameters between the key module subgraphs are obtained by using the high-dimensional features, and an edge structure of the global graph is set according to the interconnection parameters.

5. The deep learning based microarchitecture design space exploration method of claim 1, wherein, Initializing a global prediction model by introducing a federated learning algorithm, specifically: Taking the prediction models corresponding to each key module as local models, obtaining error values of performance index prediction values of the local models and performance index evaluation values in a training set, retraining the prediction models of each key module by introducing the federated learning, selectively selecting the local models to upload to a server for model aggregation after the training, and calculating average errors of each local model; The error of the global prediction model after aggregation is taken as a benchmark value, the local models are scored to generate confidence according to the average error, the local models with average detection error greater than the benchmark value are screened, and the scores of the screened local models are set to zero; The local models with non-zero scores are uploaded and compressed according to the confidence, each local model is aggregated, the parameter updating of the local model and the global prediction model is performed, the optimal model parameter is obtained through iteration, and the global prediction model is output.

6. The deep learning based microarchitecture design space exploration method of claim 1, wherein, The global prediction model is used to predict the optimal solution set of the micro-architecture parameters based on the global graph, specifically as follows: The parameter optimal solution of the design point output by the prediction model corresponding to each key module is mapped to the global graph, the global prediction model is guided to train, the global regret of the key module node corresponding edge is obtained, the initial optimal path is searched by using a greedy strategy, the initial optimal path is iteratively optimized by combining a 2-Opt heuristic algorithm, and the parameter optimal solution of each key module node is obtained; The micro-architecture parameter optimal solution set is configured according to the parameter optimal solution of each key module node, the micro-architecture parameter optimal solution set is integrated into the micro-architecture parameter optimal solution set, the micro-architecture parameter optimal solution set is put into a virtual prototype platform to obtain simulation verification data, and if a preset design target is reached, the target configuration parameters of the target processor under each configuration dimension are output.

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