Quantum bit mapping algorithm based on dynamic coupling optimization

Abstract

The invention discloses a quantum bit mapping algorithm based on dynamic coupling optimization, and the algorithm comprises the steps: (1) calculating a physical quantum bit distance through employing a Floyd-Warshall algorithm, constructing a directed acyclic graph (DAG) of a logic quantum circuit and an inverse graph r (DAG) of the DAG, and generating an initial mapping Pi; (2) an SABRE algorithm is used for traversing an original line and a reverse line of the original line, and initial mapping is optimized; (3) creating a buffer area B (vi) for each physical quantum bit vi, storing a single quantum bit gate to be executed, and setting a current mapping progress P (vi) of the vi; and (4) traversing the original line by using a quantum bit mapping algorithm based on dynamic coupling optimization, inserting an additional exchange operation SWAP, and generating a physical quantum line which can be directly executed on NISQ equipment. According to the quantum bit mapping algorithm based on dynamic coupling optimization, the logic equivalence is ensured, the line depth is remarkably reduced, and the parallelism degree is improved.

Description

Technical Field

[0001] The present invention relates to a quantum bit mapping algorithm based on dynamic coupling optimization, and belongs to the technical field of quantum circuit automation design. Background Art

[0002] With the continuous advancement of quantum computing technology, how to efficiently run quantum circuits on actual quantum devices has become a research hotspot in the automated design of quantum circuits. However, current quantum devices generally face limitations in connectivity, and it is necessary to dynamically and reasonably map the quantum bits involved in the logical quantum circuits to the physical quantum bits.

[0003] The key to solving the qubit mapping problem is to convert the given logical quantum circuit LC = {Q, C} and the coupling graph AG = {V, E} of the NISQ device into a physical quantum circuit PC that maintains logical equivalence and complies with the connection constraints of the physical device by inserting additional swap SWAP gates, ensuring that the quantum circuit can run smoothly on the NISQ device. The optimization goal of qubit mapping is to minimize the depth of the output circuit.

[0004] The quantum bit mapping problem mainly includes determining the initial quantum bit mapping scheme and inserting the swap SWAP gate into the original quantum circuit.

[0005] Initial mapping determination: For a logical quantum circuit, the first task is to establish a correspondence between its logical qubits and physical qubits. This initial mapping needs to ensure that each logical qubit has and only has one corresponding physical qubit. That is, the initial mapping π: Q→V is a single shot, that is, for any logical bit q, q′∈Q,

[0006] SWAP gate insertion: During the algorithm execution, for the current quantum bit mapping π and the quantum gate CNOT (q 1 ,q 2 ), if the quantum gate cannot be executed under the current mapping, that is It is necessary to adjust the mapping scheme by inserting an appropriate SWAP gate (or a series of SWAP gates) to ensure that the adjusted mapping can support the execution of the quantum gate, that is, the changed mapping π′ satisfies (π′(q 1 ),π′(q 2 ))∈E. By inserting appropriate SWAP gates into the quantum circuit, a physical quantum circuit adapted to a given physical device can be constructed.

[0007] At present, the commonly used quantum bit mapping algorithms include converting the problem into an equivalent mathematical problem and then solving it using a general optimization algorithm. However, these algorithms cannot meet the needs of large quantum chips, and the initial mapping scheme does not consider global optimization enough. Therefore, how to improve the scalability of the algorithm, improve the quality of the initial mapping scheme, and increase the parallelism of the output lines has become a research hotspot in this field.

[0008] The present invention proposes a quantum bit mapping algorithm based on dynamic coupling optimization. The algorithm generates a high-quality initial mapping scheme through forward traversal and reverse traversal, creates a buffer to temporarily suspend the execution of single quantum bit gates, and records the current mapping progress of physical quantum bits, thereby reducing the depth of the output circuit and improving the parallelism of the quantum circuit.

[0009] This paper mainly focuses on the quantum bit mapping problem, and aims to provide an efficient quantum bit mapping algorithm, optimize the initial mapping scheme, and consider the impact of single quantum bit gates on the output line depth, in order to apply it to large quantum chips. Summary of the invention

[0010] Terminology explanation:

[0011] (1) Quantum bit: The basic unit of data storage in a quantum computer. Quantum algorithms operate on quantum bits to complete specific tasks.

[0012] (2) Quantum gates: divided into single quantum gates and multi-quantum gates, which realize specific functions by changing the state of the quantum bits being operated. In the present invention, quantum gates are divided into single quantum gates and double quantum gates according to the number of quantum bits being operated. A single quantum gate can change the state of a single quantum bit, while a double quantum gate can change the state of two quantum bits at the same time. In addition, two special double quantum gates are also required in the present invention: a swap gate and a controlled NOT gate, which are represented by SWAP(i, j) and CNOT(i, j) respectively.

[0013] (3) Quantum circuit: A commonly used way to describe quantum algorithms, composed of quantum bits and a series of quantum gates. When designing a quantum circuit, users usually do not consider the actual execution limitations of quantum computers. Therefore, before executing the quantum algorithm described by the quantum circuit on a quantum computer, it is necessary to convert the quantum circuit designed by the user into a new circuit that meets the execution limitations of the quantum computer, while ensuring that the two remain logically equivalent in function. The present invention refers to the quantum circuit designed by the user as a logical quantum circuit (denoted as LC = {Q, C}, which includes a set of logical quantum bits Q and a set of quantum gates C), and the quantum circuit after conversion is called a physical quantum circuit (denoted as PC).

[0014] (4) Dependency graph of quantum circuit: It is represented by a directed acyclic graph (DAG), which is built based on the dependency relationship between quantum gates and is used to represent the execution order between quantum gates in a quantum circuit. The nodes in the DAG represent quantum gates, and the edges represent the dependency relationship between quantum gates. The DAG can be used to analyze the execution order of quantum gates in a quantum circuit and find out which quantum gates can be executed in parallel and which quantum gates need to be executed sequentially.

[0015] (5) Layers of quantum circuits: In a quantum circuit, if all quantum gates are moved as far to the left as possible, the quantum gates that are in the same column after the left shift are classified into the same layer. The front layer F refers to the set of quantum gates that can be executed directly and immediately in the dependency graph DAG without waiting for other quantum gates to complete. The extended set E implements the "look ahead" function of the SABRE algorithm and contains the nearest successor node of each gate in F in the DAG.

[0016] (6) Decay coefficient: denoted as decay(v i ), achieving a trade-off between the output circuit depth and the number of inserted SWAP gates, so that the SABRE algorithm can generate hardware-compatible circuits with different optimization goals. Physical qubit v i The decay coefficient decay(v i ) has an initial value of 1. When the quantum bit participates in SWAP, its decay coefficient will increase by δ, i.e. decay(v i )←decay(v i )+δ.

[0017] (7) NISQ device coupling graph: AG = {V, E}, where V is the set of physical qubits and E is the set of two qubits that can be connected to each other. In some NISQ devices, the connections between physical qubits are not unlimited, but are limited to executing double quantum gates on specific qubit pairs. This connection restriction can be represented by a coupling graph.

[0018] (8) Quantum bit mapping: When executing quantum algorithms in a quantum computer, it is necessary to map the quantum bits in the logical quantum circuit to actual physical quantum bits. The symbol π represents the quantum bit mapping, which indicates the physical quantum bits corresponding to the logical quantum bits under the mapping scheme. For example, the initial quantum bit mapping scheme is q 0 Map to v 0 ,q 1 Map to v 1 ,q 2 Map to v 2 , that is, π(q i )=v i , At this point, the established quantum bit mapping scheme can be adjusted by inserting a swap gate SWAP into the physical quantum circuit. Assume that there is π(q 0 )=v 0 ,π(q 1 )=v 1 , by inserting a switch gate SWAP(v 0 , v 1 ), a new quantum bit mapping scheme can be obtained, so that in the new mapping scheme π(q 0 )=v 1 ,π(q 1 )=v 0 .

[0019] (9) Floyd-Warshall algorithm: an algorithm for finding the shortest paths between all pairs of vertices in a graph. The algorithm uses the idea of ​​dynamic programming to solve the problem by gradually updating the shortest path length between pairs of vertices in the graph. Its core is to construct a distance matrix, in which each element represents the shortest path length between two vertices.

[0020] (10) SWAP distance matrix: denoted as D swap [i][j] represents the distance between physical qubits on the physical device. The rows and columns of the matrix correspond to physical qubits, for example, v 0 , v 1 , v 2 Each element in the matrix represents the i Move to v j The number of additional SWAP gates required to be inserted. When there is no direct connection between some physical qubits, the distance between them is infinite.

[0021] (11) Single-qubit gate buffer: denoted as B(v i ) is used to temporarily store single-qubit gates that have not yet been executed. When a single-qubit gate appears on a physical qubit, it is not executed immediately, but is placed in the corresponding buffer. The single-qubit gate in the buffer is not executed until a new executable two-qubit gate (CNOT gate or SWAP gate) is encountered. The purpose is to prevent the single-qubit gate from being executed too early, resulting in too many subsequent SWAP gates being inserted, causing an increase in the depth of the output circuit.

[0022] (12) The current mapping conversion progress of the physical quantum bit is denoted as P(v i ), which is used to track each physical quantum bit v iThe degree of mapping progress during the line conversion process. Each physical qubit has its progress indicator, with an initial value of 0; when executing a single-qubit gate, the progress of the physical qubit actually operated by the gate is increased by 1; when executing a CNOT gate, the progress of the two physical qubits actually operated by the gate is adjusted to the larger value of the two progresses plus 1; when inserting a SWAP gate, the progress of the two physical qubits actually operated by the gate is adjusted to the larger value of the two progresses plus 3. The purpose is to determine which qubit mapping progresses too fast and which qubits progress too slowly, so as to better select the insertion position of the SWAP gate.

[0023] Technical solution: The present invention globally optimizes the quantum bit mapping scheme by traversing the original quantum circuit and its reverse circuit, creates a buffer to temporarily suspend the execution of single quantum bit gates and records the current mapping progress of physical quantum bits to reduce the depth of the output circuit. When there are quantum gates that cannot be directly executed in the current layer, the search process is optimized by searching for the SWAP gates related to the quantum bits in the previous layer and selecting the SWAP with the lowest cost to insert until the entire logical quantum circuit is mapped to the target physical device.

[0024] The technical solutions adopted are:

[0025] (1) Preprocessing: Calculate the SWAP distance matrix D using the Floyd-Warshall algorithm swap [i][j], construct a DAG graph to represent the execution dependency between all quantum gates in the logic quantum circuit LC, and at the same time construct the reverse graph r(DAG) of the DAG graph, put all quantum gates with in-degree 0 in the DAG graph into the front layer list F, and put all quantum gates with in-degree 0 in r(DAG) into the reverse circuit LC of the logic quantum circuit r The front layer list F r , randomly generate the initial mapping π;

[0026] (2) Taking π as the initial mapping and F as the front layer, the SABRE algorithm is used to traverse LC to obtain the final mapping π f ;

[0027] (3) π f is the initial mapping, with F r For the front layer, use the SABRE algorithm to LC r Traverse and get the updated initial mapping π ini ;

[0028] (4) Restore the DAG graph and the previous layer F;

[0029] (5) Initialize each physical quantum bit v i The decay coefficient decay(v i )、Buffer B(vi ) and the current mapping progress P(v i );

[0030] (6) π ini For the initial mapping, with F as the front layer, the quantum bit mapping algorithm based on dynamic coupling optimization is used to traverse LC to obtain the converted quantum circuit PC with the SWAP gate inserted.

[0031] In the steps, the quantum bit mapping algorithm based on dynamic coupling optimization is an improvement of the original SABRE algorithm, and the method of traversing the logical quantum circuit is as follows:

[0032] (1) Check whether the quantum gates in the previous layer can be directly executed. If they can be directly executed, add them to the executable gate list exe list and execute step (2); if none of the quantum gates in the previous layer can be directly executed, execute step (3);

[0033] (2) Traverse each gate g in exe_list. If g is a single-qubit gate, execute step (2.1); if g is a CNOT gate, execute step (2.2);

[0034] (2.1) Add the single-qubit gate g(q) to the buffer B(v) corresponding to the physical qubit v=π(q), and execute step (2.3);

[0035] (2.2) CNOT gate g(q 0 ,q 1 ) 0 ,q 1 The two physical quantum bits (v 0 =π(q 0 ),v 1 =π(q 1 )) of buffer B(v 0 )、B(v 1 ) is added to the physical quantum circuit, and the current mapping progress P(v 0 )、P(v 1 )(P(v 0 )←P(v 0 )+|B(v 0 )|,P(v 1 )←P(v 1 )+|B(v 1 )|, where |B(v)| represents the number of single-qubit gates stored in buffer B(v)), clear buffer B(v 0 )、B(v 1 ), g(q 0 ,q 1) is added to the physical quantum circuit and the current mapping progress P(v 0 )、P(v 1 )(P(v 0 )←max(P(v 0 ), P(v 1 ))+1,P(v 1 )←max(P(v 0 ), P(v 1 ))+1); execute step (2.3);

[0036] (2.3) Remove g from the previous layer and update the previous layer according to the dependency graph;

[0037] (3) Search for candidate swap operations SWAP and add them to the candidate set can list, and select the swap gate SWAP with the smallest cost (v 0 , v 1 ), where v 0 The current mapping progress is less than v 1 The current mapping progress, that is, P(v 0 ) <P(v 1 ), execute step (4);

[0038] (4) v 0 Buffer B(v 0 ) from B(v 0 ) is removed and added to the physical quantum circuit, where k←min(P(v 1 )-P(v 0 ),|B(v 0 )|), and update the current mapping progress P(v 0 )(P(v 0 )←P(v 0 )+k), add the exchange gate selected in step (3) to the physical quantum circuit; update v 0、 v 1 The corresponding decay coefficient (decay(v 0 )←decay(v 0 )+δ,decay(v 1 )←decay(v 1 )+δ), swap v 0 、v 1 The corresponding buffer B(v 0 )、B(v 1 ), update the current mapping progress P(v 0 )、P(v 1 )(P(v 0 )←max(P(v 0 ), P(v 1))+3,P(v 1 )←max(P(v 0 ), P(v 1 ))+3), update the current mapping scheme;

[0039] (5) Steps (1) to (4) are executed repeatedly until the previous layer is empty, that is, all quantum gates in the original logical quantum circuit have been added to the converted physical quantum circuit.

[0040] Among them, the method of searching for candidate SWAP gates and calculating their costs is as follows:

[0041] (1) Check all CNOT gates in the previous layer that cannot be directly executed (single quantum gates have been stored in the buffer), extract the logical qubits they act on, and use the current mapping scheme to find the physical qubits corresponding to these logical qubits;

[0042] (2) In the coupling graph AG, calculate all the edges E involved in the physical qubits. The connections between the two physical qubits corresponding to the edges in the set E are candidate SWAP gates, and add them to the candidate list can list;

[0043] (3) For each SWAP gate in the can list, use the function Calculate its cost, where SWAP.v 0 ,SWAP.v 1 represents the two physical quantum bits acted upon by the SWAP gate, gq 1 、gq 2 represents the two logical qubits acted upon by the CNOT gate g, |F| refers to the number of gates contained in the previous layer, |E| refers to the number of gates contained in the extended set, |V| refers to the number of edges in the coupling graph AG, and W is the weight representing the influence of the extended set.

[0044] Benefits and effects: The present invention provides a quantum bit mapping algorithm based on dynamic coupling optimization, which can significantly reduce the depth of quantum circuits after conversion. When applied to large quantum chips, compared with existing quantum bit mapping algorithms, the algorithm exhibits superior performance, which not only helps to improve the fidelity and parallelism of quantum algorithms, but also significantly enhances the execution efficiency and overall quality of quantum algorithms. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is the overall flow chart of the present invention;

[0046] Figure 2 An example of a coupling diagram AG of a NISQ device to be considered for the present invention;

[0047] Figure 3 A schematic diagram of inserting a SWAP gate to adjust the mapping scheme of the present invention;

[0048] Figure 4 This is a flow chart of a quantum bit mapping algorithm based on dynamic coupling optimization in the present invention;

[0049] Figure 5 It is a sub-process flow chart of traversing the quantum gates in the executable gate list exe_list in the present invention;

[0050] Figure 6 This is a sub-process flow chart of inserting a SWAP gate in the present invention. DETAILED DESCRIPTION

[0051] The present invention is further described in detail below in conjunction with the accompanying drawings.

[0052] like Figure 1 The overall flow chart of the algorithm is shown, which includes the following steps:

[0053] (1) Preprocessing: Calculate the SWAP distance matrix D using the Floyd-Warshall algorithm swap [i][j], construct a DAG graph to represent the execution dependency between all quantum gates in the logic quantum circuit LC, and construct the reverse graph r(DAG) of the DAG graph, put all quantum gates with in-degree 0 in the DAG graph into the front layer list F, and put all quantum gates with in-degree 0 in r(DAG) into the reverse circuit LC of the logic quantum circuit r The front layer list F r , randomly generate the initial mapping π;

[0054] (2) Taking π as the initial mapping and F as the front layer, the SABRE algorithm is used to traverse LC to obtain the final mapping π f ;

[0055] (3) π f is the initial mapping, with F r For the front layer, use the SABRE algorithm to LC r Traverse and get the updated initial mapping π ini ;

[0056] (4) Restore the DAG graph and the previous layer F;

[0057] (5) Initialize the physical quantum bit v i Attenuation coefficient decay(v i ), create its buffer B(v i ), and set its current mapping progress P(v i );

[0058] (6) π ini For the initial mapping, with F as the front layer, the quantum bit mapping algorithm based on dynamic coupling optimization is used to traverse LC to obtain the converted quantum circuit PC with the SWAP gate inserted.

[0059] like Figure 2 Shown is the coupling diagram AG for a NISQ device. The qubit mapping algorithm needs to take these connectivity constraints into account.

[0060] like Figure 3 The figure shows the flowchart of the proposed quantum bit mapping algorithm based on dynamic coupling optimization, which takes the initial mapping π, the front layer F, the logical quantum circuit dependency graph DAG, and the coupling graph AG of the physical device as input, and includes the following steps:

[0061] (1) Determine whether the quantum gates in F can be directly executed according to AG. If they can be directly executed, add them to the executable gate list exe_list, and execute the sub-process of traversing the quantum gates in exe_list, that is, step (2); if none of the quantum gates in F can be directly executed, execute step (3);

[0062] (2) Traverse each gate g in exe_list. If g is a single-qubit gate, record it as g(q) and execute step (2.1); if g is a CNOT gate, record it as g(q 0 ,q 1 ), execute step (2.2);

[0063] (2.1) Add g(q) to the buffer B(π(q)) and execute step (2.3);

[0064] (2.2) g(q 0 ,q 1 ) 0 ,q 1 The corresponding two physical quantum bits v 0 、v 1 (v 0 =π(q 0 ),v 1 =π(q 1 )) of buffer B(v 0 )、B(v 1 ) to the physical quantum circuit PC, and let P(v 0 )←P(v 0 )+|B(v 0 )|,P(v 1 )←P(v 1 )+|B(v 1 )|, clear B(v 0 )、B(v1 ); then g(q 0 ,q 1 ) is added to PC, and P(v 0 )←max(P(v 0 ), P(v 1 ))+1,P(v 1 )←max(P(v 0 ), P(v 1 ))+1;Finally, execute step (2.3);

[0065] (2.3) Finally, remove g from F and update F according to DAG;

[0066] (3) Search for candidate SWAPs and add them to the candidate set can_list, and select the switch gate SWAP with the smallest cost (v 0 , v 1 ), where P(v 0 ) <P(v 1 ), and execute the sub-process of inserting the SWAP gate, i.e. step (4);

[0067] (4) B(v 0 ) from B(v 0 ) is removed and added to PC, where k←min(P(v 1 )-P(v 0 ),|B(v 0 )|), and let P(v 0 )←P(v 0 )+k, and the switch gate SWAP(v 0 , v 1 ) is added to PC; let decay(v o )←decay(v 0 )+δ,decay(v 1 )←decay(v 1 )+δ, swap v 0 、v 1 The corresponding B(v 0 )、B(v 1 ), and let P(v 0 )←max(P(v 0 ), P(v 1 ))+3,P(v 1 )←max(P(v 0 ), P(v 1 ))+3, finally update the mapping scheme π;

[0068] (5) Repeat steps (1) to (4) until F is empty, that is, all quantum gates in the original logic quantum circuit LC have been added to PC.

Claims

1. A quantum bit mapping algorithm based on dynamic coupling optimization, characterized in that It includes the following steps: Step 1: Use the Floyd-Warshall algorithm to calculate the distances between all physical quantum bits, construct a directed acyclic graph (DAG) to represent the execution dependencies between all quantum gates in the logical quantum circuit, and construct the reverse graph r(DAG) of the DAG; put all quantum gates without predecessor nodes in the DAG into the front-layer list F, and put all quantum gates without predecessor nodes in r(DAG) into the front-layer list F of the reverse circuit of the logical quantum circuit r , randomly generate the initial mapping π; Step 2: Using π as the initial mapping and F as the front layer, use the SABRE algorithm to traverse the original logic quantum circuit to obtain the final mapping π f ; Step 3: Use π f As the initial mapping and F r As the front layer, use the SABRE algorithm to traverse the reverse circuit of the original logic quantum circuit to obtain the updated initial mapping π ini ; Step 4: Restore the DAG graph and the previous layer F; Step 5: For each physical qubit v i Create a buffer B(v i ), which is used to store the single-qubit gate to be executed on the physical qubit, and to set v i The current mapping progress P(v i ); Step 6: Using π ini As the initial mapping and with F as the front layer, the quantum bit mapping algorithm based on dynamic coupling optimization is used to traverse the original logical quantum circuit to obtain the updated quantum circuit with the additional swap operation SWAP inserted.

2. The quantum bit mapping algorithm based on dynamic coupling optimization according to claim 1 is characterized in that: The specific steps of the said Step 5 are as follows: Step 5.1: Check whether the quantum gates in the previous layer can be directly executed. If they can be directly executed, add them to the executable gate list exe_list and execute Step 5.2; if none of the quantum gates in the previous layer can be directly executed, execute Step 5.3; Step 5.2: Traverse each gate g in exe_list. If g is a single-qubit gate, execute Step 5.2.1; if g is a CNOT gate, execute Step 5.2.2; Step 5.2.1: Add the single-qubit gate g(q) to the buffer B(v) corresponding to the physical qubit v = π(q), and execute Step 5.2.3; Step 5.2.2: Add all the single-qubit gates in the buffers B(v0) and B(v1) corresponding to the two physical qubits (v0 = π(q0), v1 = π(q1)) on which the CNOT gate g(q0, q1) acts to the physical quantum circuit, and update the current mapping progress P(v0) and P(v1) (P(v0) ← P(v0) + |B(v0)|, P(v1) ← P(v1) + |B(v1)|, where |B(v)| represents the number of single-qubit gates stored in the buffer B(v)), empty the buffers B(v0) and B(v1), add g(q0, q1) to the physical quantum circuit, and update the current mapping progress P(v0) and P(v1) (P(v0) ← max(P(v0), P(v1)) + 1, P(v1) ← max(P(v0), P(v1)) + 1); execute Step 5.2.3; Step 5.2.3: Remove g from the previous layer and update the previous layer according to the dependency graph; Step 5.3: Search for candidate swap operations SWAP and add them to the candidate set can_list, and select the swap gate SWAP(v0, v1) with the minimum cost, where the current mapping progress of v0 is less than that of v1, i.e., P(v0) < P(v1), and execute Step (4); Step 5.4: Remove the first k single-qubit gates from the buffer B(v0) of v0 and add them to the physical quantum circuit, where k ← min(P(v1) - P(v0), |B(v0)|), and update the current mapping progress P(v0) (P(v0) ← P(v0) + k), add the swap gate selected in Step 5.3 to the physical quantum circuit; update the decay coefficients corresponding to v0 and v1 (decay(v0) ← decay(v0) + δ, decay(v1) ← decay(v1) + δ), swap the buffers B(v0) and B(v1) corresponding to v0 and v1, update the current mapping progress P(v0) and P(v1) (P(v0) ← max(P(v0), P(v1)) + 3, P(v1) ← max(P(v0), P(v1)) + 3), and update the current mapping scheme; Step 5.5: Loop through steps 5.1 to 5.4 until the front layer is empty, that is, all quantum gates in the original logical quantum circuit have been added to the converted physical quantum circuit.

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