Shifting register, driving circuit, driving method and display device

Abstract

The invention provides a shift register, a driving circuit, a driving method and a display device, and relates to the technical field of display. The shift register comprises a first control circuit configured to provide a first power supply voltage to a first node under the control of a first clock signal; a gating circuit configured to provide a first clock signal to the first node under the control of a plurality of gating signals; an input circuit configured to provide a first power supply voltage to a second node under the control of the potential of the first node and a second clock signal, and control the potential of the second node by using a control signal; a second control circuit configured to provide a third power supply voltage or a fourth power supply voltage to a third node under the control of a potential of a second node and a second power supply voltage of a second power supply; and the output circuit is configured to provide a third clock signal or a second power supply voltage to the output end as an output scanning signal under the control of the potentials of the second node and the third node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method and a display device. Background Art

[0002] In order to achieve good compatibility between power consumption and high refresh rate, monitors usually use regional high refresh rate technology, which requires the driver circuit to have the ability to be flexibly turned on. Common shift register driver circuits have a single driving capability for monitors and cannot make real-time adjustments based on the image, thus failing to meet the more flexible high refresh rate requirements for monitors. Summary of the invention

[0003] The present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0004] According to a first aspect, the present disclosure provides a shift register, comprising: a first control circuit, configured to provide a first power supply voltage of a first power supply to a first node under the control of a first clock signal from a first clock terminal; a gating circuit, configured to provide a first clock signal to the first node under the control of multiple gating signals from multiple gating terminals; an input circuit, configured to provide the first power supply voltage to a second node under the control of the potential of the first node and the second clock signal from the second clock terminal, and to control the potential of the second node using a control signal from a control terminal; a second control circuit, configured to provide a third power supply voltage of a third power supply or a fourth power supply voltage of a fourth power supply to a third node under the control of the potential of the second node and the second power supply voltage of the second power supply; and an output circuit, configured to provide a third clock signal from a third clock terminal or a second power supply voltage to an output terminal as an output scan signal under the control of the potentials of the second node and the third node.

[0005] According to a second aspect, the present disclosure provides a driving circuit, comprising M shift registers as provided in any embodiment of the present disclosure; wherein, the mth shift register is electrically connected to the first selection line, the m+xth shift register is electrically connected to the second selection line, the selection signal output by the first selection line and the selection signal output by the second selection line are not at a valid level at the same time, 1≤m≤Mx, 1≤x<M, M is a positive integer greater than 1, and m and x are positive integers.

[0006] According to a third aspect, the present disclosure provides a display device, including a display panel; and a driving circuit as provided in an embodiment of the present disclosure; wherein the display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0007] According to the fourth aspect, the present disclosure provides a driving method, which is applied to the shift register provided by the embodiment of the present disclosure, including: during the duration of the first level of the qth clock sub-signal, the q+1th clock sub-signal jumps from the second level to the first level, 1≤q≤Q-1, q is an integer; during the duration of the first level of the Qth clock sub-signal, the control signal jumps from the second level to the first level; wherein the third clock signal includes Q clock sub-signals whose valid levels are shifted in sequence, Q is a positive integer; the 1st clock signal and the control signal are not valid levels at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

[0009] Figure 2 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0010] Figure 3 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0011] Figure 4A is a signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0012] Figure 4B is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0013] Figure 5 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0014] Figure 6 is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0015] Fig. 7A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0016] Figure 7B and Figure 7C is a signal timing diagram of a shift register according to another embodiment of the present disclosure;

[0017] Figure 8 is a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure;

[0018] Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0019] Fig.10 is a flowchart of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the embodiments of the present disclosure clearer, the technical scheme in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work belong to the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only used for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0021] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the usual meanings understood by those skilled in the art. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0022] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to two components being directly connected, or may refer to two components being connected via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0023] The source and drain of the switch transistor used in the embodiment of the present disclosure are symmetrical, so the source and drain can be interchanged. In the embodiment of the present disclosure, according to its function, the control electrode can be called the control electrode, one of the source and the drain can be called the first electrode, and the other of the source and the drain can be called the second electrode.

[0024] It should be noted that in the description of the embodiments of the present disclosure, the symbol SCOUT can represent both a scan signal and an output terminal of the scan signal. Similarly, the symbol GVDD can represent both a power supply and a voltage provided by the power supply, the symbol VGL can represent both a power supply and a voltage provided by the power supply, and the symbol VGH can represent both a power supply and a voltage provided by the power supply. For example, the power supply VGL and the power supply LVGL can provide a low voltage, and the power supply VGH and the power supply GVDD can provide a high level. The following embodiments are the same, and similar parts will not be repeated.

[0025] Figure 1 is a schematic diagram of the structure of a shift register according to an embodiment of the present disclosure.

[0026] like Figure 1As shown, the shift register 100 includes a first control circuit 110 , a gating circuit 120 , an input circuit 130 , a second control circuit 140 and an output circuit 150 .

[0027] In the embodiment of the disclosure, the first control circuit 110 is electrically connected to the first clock terminal CLK1 , the first power source VGH, and the first node P. The first control circuit 110 provides the first power source voltage VGH of the first power source VGH to the first node P under the control of the first clock signal CLK1 from the first clock terminal CLK1 .

[0028] For example, the first clock signal CLK1 can control the first power supply VGH to switch between the connected and disconnected states with the first node P. For example, when the first clock signal CLK1 controls the first power supply VGH to switch between the first node P and the connected state, the first control circuit 110 writes the first power supply voltage VGH to the first node P.

[0029] In the disclosed embodiment, the gating circuit 120 is electrically connected to a plurality of gating terminals D0-Dn, a first clock terminal CLK1 and a first node P. The gating circuit 120 provides a first clock signal CLK1 to the first node P under the control of a plurality of gating signals from the plurality of gating terminals.

[0030] For example, the plurality of gating signals D0-Dn can control the first clock terminal CLK1 to be in a connected state or a disconnected state with the first node P. When the plurality of gating signals D0, ..., Dn control the first clock terminal CLK1 to be in a conductive state with the first node P, the gating circuit 120 can write the first clock signal CLK1 to the first node P.

[0031] In the embodiment of the present disclosure, when the plurality of selection signals D0 to Dn are all at a low level and the first clock signal CLK1 is at a low level, the first node P is at a high potential, and the circuit is in the selection stage. When at least one of the plurality of selection signals D0 to Dn is at a high level and the first clock signal CLK1 is at a low level, the low level of the first clock signal CLK1 is provided to the first node P, and the potential of the first node P is pulled low, and the shift register 100 is in the non-selection stage.

[0032] In the embodiment of the present disclosure, the input circuit 130 is electrically connected to the second clock terminal CLK2, the control terminal CS, the first power supply VGH, the first node P, and the second node QN. Under the control of the potential of the first node P and the second clock signal CLK2 from the second clock terminal CLK2, the input circuit 130 provides the first power supply voltage VGH to the second node QN, and controls the potential of the second node QN using the control signal CS from the control terminal CS.

[0033] For example, the second clock signal CLK2 and the first node P can jointly control the switching between the first power supply VGH and the second node QN between being connected or disconnected. For example, when the second clock signal CLK2 and the first node P control the first power supply VGH and the second node QN to be connected, the input circuit 130 writes the first power supply voltage VGH to the second node QN to pull up the potential of the second node QN.

[0034] The control signal CS is used to stabilize the potential of the second node QN and control the potential of the second node QN not to be pulled down. Under the control of the control signal CS, the input circuit 130 can also pull up the potential of the second node QN to stabilize the high potential of the second node QN.

[0035] In the embodiment of the present disclosure, the second control circuit 140 is electrically connected to the second node QN, the third power supply GVDD, the fourth power supply LVGL, the second power supply VGL and the third node QB. Under the control of the potential of the second node QB and the second power supply voltage VGL of the second power supply VGL, the second control circuit 140 provides the third power supply voltage GVDD of the third power supply GVDD or the fourth power supply voltage LVGL of the fourth power supply LVGL to the third node QB.

[0036] For example, the third power supply voltage GVDD and the potential of the second node QN can jointly control the fourth power supply LVGL and the third node QB to switch between being in a connected or disconnected state. For example, when the third power supply voltage GVDD and the potential of the second node QN control the fourth power supply LVGL and the third node QB to be in a connected state, the second control circuit 140 writes the fourth power supply voltage LVGL to the third node QB to lower the potential of the third node QB.

[0037] In the embodiment of the present disclosure, the output circuit 150 is electrically connected to the second node QN, the third node QB, the third clock terminal CLKE and the output terminal SCOUT. Under the control of the potentials of the second node QN and the third node QB, the output circuit 150 provides the third clock signal CLKE from the third clock terminal or the second power supply voltage VGL to the output terminal SCOUT as an output scan signal.

[0038] For example, the potential of the third node QB can control the second power supply VGL and the output terminal SCOUT to be in a connected state or a disconnected state. When the potential of the third node QB controls the second power supply VGL and the output terminal SCOUT to be in a connected state, the output circuit 140 provides the second power supply voltage VGL to the output terminal SCOUT, and the output terminal SCOUT outputs a low level signal.

[0039] For example, the potential of the second node QN can control the third clock terminal CLKE and the output terminal SCOUT to be in a connected state or a disconnected state. When the potential of the second node QN controls the third clock terminal CLKE and the output terminal SCOUT to be in a connected state, the output circuit 140 provides the third clock signal CLKE to the output terminal SCOUT, and the output terminal SCOUT outputs the third clock signal CLKE.

[0040] When the shift register 100 is in the non-selected stage, the second control circuit 140 controls the second node QB to be low level and the third node QB to be high level, so that the shift register 100 can output a low voltage in the non-selected stage. When the shift register is in the selected stage, the second control circuit 140 controls the second node to be low level and the third node QB to be low level, so that the output circuit 150 of the shift register outputs normally, and realizes the potential reversal of the second node QN and the third node QB.

[0041] In the embodiment of the present disclosure, when the multiple selection signals are all at low level, the first node P is maintained at a high potential, so that the second node QN is at a high potential, thereby ensuring that the output terminal SCOUT of the output circuit 150 is normally output, and the shift register 100 maintains the selection stage. When one of the multiple selection signals is at a high level, the potential of the first node P is pulled down, so that the second node QN is at a low potential, the output terminal SCOUT of the output circuit 150 outputs a low level signal, and the shift register 100 is in a non-selection stage.

[0042] The scan signal outputted by the output terminal SCOUT can be used to drive the N-type transistor in the pixel circuit. For example, when the level of the scan signal is high, the N-type transistor is turned on, and the data signal can be written, thereby realizing screen refresh. When the level of the scan signal is low, the N-type transistor is turned off, and the data signal cannot be written, thereby realizing that the screen is not refreshed and remains unchanged.

[0043] For example, the level of the selection signal D0-Dn can indicate whether the transistor in the pixel circuit electrically connected to the shift register 100 is turned on. For example, when the selection signal D0-Dn is at a low level, the first power supply voltage VGH is written into the first node P, the potential of the first node P is pulled high, and the output terminal SCOUT outputs the third clock signal CLKE as a scanning signal. At this time, the N-type transistor in the pixel circuit can be switched to a conducting state, and the corresponding display screen is refreshed.

[0044] When any of the selection signals D0 to Dn is at a high level, the potential of the first node P is pulled down by the low level of the first clock signal CLK1, the second node QN is at a low potential, and the level of the scanning signal output by the output terminal SCOUT remains at a low level. At this time, the N-type transistor in the pixel circuit remains in a cut-off state based on the low-level scanning signal, and the corresponding display screen is not refreshed.

[0045] According to the embodiment of the present disclosure, by controlling the potentials of the first node P and the second node QN according to the selection signal, it can be determined whether the shift register 100 is in the selection stage, thereby controlling whether a pixel row electrically connected to the shift register 100 is refreshed. In a driving circuit including a plurality of shift registers, any shift register can be selected for selection by the selection signal, so that each pixel row in the pixel circuit has the ability to be flexibly turned on, thereby realizing the control of whether a single pixel row is refreshed.

[0046] In the embodiment of the present disclosure, the second node QN is used to control the third clock signal CLKE to be output to the output terminal SCOUT. Under the action of the high potential of the second node QN, the third clock terminal CLKE and the output terminal SCOUT are in a connected state, and the output circuit 140 provides the third clock signal CLKE to the output terminal SCOUT, and the output terminal SCOUT outputs the third clock signal CLKE. The control signal CS is used to control the second node QN to be stably maintained at a high level, so that the output terminal SCOUT can be controlled to stably output the scanning signal to reduce noise.

[0047] Figure 2 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0048] like Figure 2 As shown, the shift register 200 includes a first control circuit 210 , a gating circuit 220 , an input circuit 230 , a second control circuit 240 , an output circuit 250 , a pull-down circuit 260 , and a reset circuit 270 .

[0049] In the embodiment of the present disclosure, the first control circuit 210, the gating circuit 220, the input circuit 230, the second control circuit 240 and the output circuit 250 respectively refer to the first control circuit 110, the gating circuit 120, the input circuit 130, the second control circuit 140 and the output circuit 150 described above, which are not repeated for the sake of simplicity.

[0050] In an embodiment of the present disclosure, the pull-down circuit 260 is electrically connected to the first node P, the second node QN, the third node QB, the second clock terminal CLK2, and the fourth power supply LVGL. Under the control of the potential of the first node P and the second clock signal CLK2, the pull-down circuit 260 provides the fourth power supply voltage LVGL to the potential of the third node QB. Under the control of the third node QB, the pull-down circuit 260 provides the fourth power supply voltage LVGL to the second node QN.

[0051] For example, the potential of the first node P and the second clock terminal CLK2 can control the fourth power supply LVGL and the third node QB to be in a connected state or a disconnected state. When the potential of the first node P and the second clock signal CLK2 control the fourth power supply LVGL and the third node QB to be in a connected state, the pull-down circuit 260 provides the fourth power supply voltage LVGL to the third node QB to pull down the potential of the third node QB.

[0052] Under the low potential of the third node QB, the fourth power supply LVGL is connected to the second node QN. At this time, the pull-down circuit 260 provides the fourth power supply voltage LVGL to the second node QN to pull down the potential of the second node QN.

[0053] When the output circuit 250 outputs the third clock signal CLKE to the output terminal SCOUT, the pull-down circuit 260 controls the potential of the second node QB to be low level, thereby preventing the second node QB from being coupled to a high potential, causing the scan signal to generate noise.

[0054] In an embodiment of the present disclosure, the reset circuit 270 is electrically connected to the first clock terminal CLK1, the fourth node Q, and the fourth power supply LVGL. Under the control of the first clock signal CLK1, the reset circuit 270 provides the fourth power supply voltage LVGL to the fourth node Q to pull down the potential of the fourth node Q. At this time, the first node P is at a high level. Under the control of the high level of the first node P, the reset circuit 270 provides the potential of the fourth node Q to the second node QN to pull down the potential of the second node QN, thereby resetting the potential of the second node QN and the potential of the fourth node Q. When the shift register 100 is in the gating stage, the reset circuit 270 can continuously reset the fourth node Q.

[0055] In an embodiment of the present disclosure, the input circuit 230 is electrically connected to the first power supply VGH, the second clock terminal CLK2, the control terminal CS, the first node P, the second node QN, and the fourth node Q. Under the control of the second clock signal CLK2, the input circuit 230 provides the first power supply voltage VGH to the fourth node Q. Under the control of the potential of the first node P, the input circuit 230 provides the potential of the fourth node Q to the second node QN. Under the control of the control signal CS, the input circuit 230 couples the control signal CS to the second node QN.

[0056] For example, the second clock signal CLK2 can control the first power supply VGH to be in a connected state or a disconnected state with the fourth node Q. When the second clock signal CLK2 controls the first power supply VGH to be in a connected state with the fourth node Q, the input circuit 230 provides the first power supply voltage VGH to the fourth node Q to pull up the potential of the fourth node Q.

[0057] The potential of the first node P can control the connection state or disconnection state between the second node QN and the fourth node Q. When the potential of the first node P controls the connection state between the second node QN and the fourth node Q, the input circuit 230 provides the high potential of the fourth node Q to the second node QN to pull up the potential of the second node QN.

[0058] The high potential of the second node QN can control the output circuit 250 to provide the third clock signal CLKE to the output terminal SCOUT to output the scan signal.

[0059] When the level of the control signal CS changes, the input circuit 230 can couple the level change of the control signal CS to the second node QN. For example, when the potential of the control signal CS is pulled high, the high level of the control signal CS can be coupled to the second node QN, thereby pulling the potential of the second node QN high again.

[0060] Under the control of the high level of the second node QN, the output circuit 250 can stably output the third clock signal CLKE to reduce the noise of the scan signal.

[0061] In the embodiment of the present disclosure, the output circuit 250 may include a plurality of sub-output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals for driving a plurality of rows of sub-pixel units. It should be noted that the present disclosure does not limit the number of output terminals.

[0062] For example, the third clock terminal CKLE may include a first sub-clock terminal and a second sub-clock terminal, and the output terminal SCOUT may include a first sub-output terminal and a second sub-output terminal.

[0063] Under the control of the potential of the second node QN, the output circuit 250 outputs the first clock sub-signal from the first sub-clock terminal to the first sub-output terminal. When the first sub-output terminal outputs the first clock sub-signal, the output circuit 250 couples the first clock sub-signal to the second node QN, thereby raising the potential of the second node QN. Under the control of the second node QN whose potential is raised, the output circuit 250 outputs the second clock sub-signal from the second sub-clock terminal to the second sub-output terminal. Since the potential of the second node QN is raised by the first clock sub-signal, the second node QN can be stably maintained at a high potential, and at this time, the second sub-clock terminal and the second sub-output terminal can be stably controlled to be in a connected state.

[0064] During the duration of the first level of the second clock sub-signal, the first clock sub-signal jumps from the first level to the second level, and the control signal jumps from the second level to the first level.

[0065] For example, the first level is a high level, and the second level is a low level. During the duration of the first level of the second clock sub-signal, if the first clock sub-signal is a high level, the high level of the first clock signal is coupled to the second node QN, and the potential of the second node QN is further pulled up. When the first clock sub-signal jumps from a high level to a low level, the potential of the second node QN is affected by the potential change of the first clock sub-signal, and the potential of the second node QN will decrease accordingly. In this case, the control signal CS jumps from a low level to a high level. The input circuit 230 couples the high level of the control signal CS to the second node QN, and at this time, the potential of the second node QN can also be pulled up, and the potential of the second node QN can be maintained at the potential before the first clock sub-signal jumps from a high level to a low level, thereby ensuring that the second sub-output terminal stably outputs the second clock sub-signal and reduces the noise of the scan signal output by the second sub-output terminal.

[0066] Figure 3 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0067] like Figure 3 As shown, the shift register 300 includes a first control circuit 310 , a gating circuit 320 , an input circuit 330 , a second control circuit 340 , an output circuit 350 , a pull-down circuit 360 , and a reset circuit 370 .

[0068] In the embodiment of the present disclosure, the first control circuit 310 includes a transistor T1, a transistor T11, a transistor T13, a capacitor C1 and a capacitor C2. The gating circuit 320 includes transistors T2 to T9, a transistor T10 and a transistor T12 connected in parallel, wherein transistors T2 to T9 can be gating transistors. The input circuit 330 includes a transistor T14 and a transistor T22. The second control circuit 340 includes a transistor T15, a transistor T16, a transistor T17, a transistor T18 and a transistor T19. The output circuit 350 includes a transistor T28 to a transistor T35 and a capacitor C3 to a capacitor C6. The pull-down circuit 360 includes a transistor T20, a transistor T21, a transistor T23, a transistor T24 and a transistor T25. The reset circuit 370 includes a transistor T26 and a transistor T27. Transistors T1 to T35 are all N-type transistors.

[0069] In the embodiment of the present disclosure, the second node is a second node Q1 separated from the third node Q. The output terminal includes an output terminal SCout(i), an output terminal SCout(i+1), an output terminal SCout(i+2) and an output terminal SCout(i+3). The third clock terminal includes a clock terminal CLKE1, a clock terminal CLKE2, a clock terminal CLKE3 and a clock terminal CLKE4. The clock terminal CLKD is a control terminal.

[0070] The control electrode of the transistor T1 is electrically connected to the first clock terminal CLK1 , the first electrode of the transistor T1 is electrically connected to the first power source VGH, and the second electrode of the first transistor T1 is electrically connected to the control electrode of the transistor T11 .

[0071] The control electrode of the transistor T11 is electrically connected to the first end of the capacitor C1 , the first electrode of the transistor T11 is electrically connected to the power supply VGH, and the second electrode of the transistor T11 is electrically connected to the first node P. The second end of the capacitor C1 is electrically connected to the first node P.

[0072] A control electrode of the transistor T13 is electrically connected to the first node P, a first electrode of the transistor T13 is electrically connected to a first power source VGH, and a second electrode of the transistor T13 is electrically connected to a second electrode of the transistor T12.

[0073] A first terminal of the capacitor C2 is electrically connected to the first power source VGH, and a second terminal of the capacitor C2 is electrically connected to the first node P.

[0074] The control electrodes of transistors T2 to T9 are electrically connected to the enable terminals D0 to D7 respectively, the second electrodes of transistors T2 to T9 are electrically connected to the first clock terminal CLK1, and the first electrodes of transistors T2 to T9 are electrically connected to the second electrodes of transistors T10 and T12.

[0075] The control electrodes of the transistors T10 and T12 are electrically connected to the third node QB, the first electrode of the transistor T10 is electrically connected to the first end of the capacitor C1, and the first electrode of the transistor T12 is electrically connected to the first node P.

[0076] A control electrode of the fourteenth transistor T14 is electrically connected to the second clock terminal CLK2 , a first electrode of the fourteenth transistor T14 is electrically connected to the first power source VGH, and a second electrode of the fourteenth transistor T14 is electrically connected to the fourth node Q.

[0077] A control electrode of the transistor T22 is electrically connected to the first node P, a first electrode of the transistor T22 is electrically connected to the fourth node Q, and a second electrode of the transistor T22 is electrically connected to the second node Q1.

[0078] The control electrode and the first electrode of the transistor T15 are electrically connected to the third power supply GVDD, and the second electrode of the transistor T15 is electrically connected to the first electrode of the transistor T16.

[0079] A control electrode of the transistor T16 is electrically connected to the third power source GVDD, and a second electrode of the transistor T16 is electrically connected to a control electrode of the transistor T18.

[0080] A control electrode of the transistor T17 is electrically connected to the second node Q1 , a first electrode of the transistor T17 is electrically connected to a control electrode of the transistor T18 , and a second electrode of the transistor T17 is electrically connected to a second power source VGL.

[0081] A first electrode of the transistor T18 is electrically connected to the third power source GVDD, and a second electrode of the transistor T18 is electrically connected to the third node QB.

[0082] A control electrode of the transistor T19 is electrically connected to the second node Q1 , a first electrode of the transistor T19 is electrically connected to the third node QB, and a second electrode of the transistor T19 is electrically connected to the fourth power source LVGL.

[0083] The control electrode of the transistor T20 is electrically connected to the first node P, the first electrode of the transistor T20 is electrically connected to the third node QB, and the second electrode of the transistor T20 is electrically connected to the first electrode of the transistor T21.

[0084] A control electrode of the transistor T21 is electrically connected to the first clock terminal CLK1 , and a second electrode of the transistor T21 is electrically connected to the fourth power source LVGL.

[0085] The control electrodes of transistor T23 and transistor T24 are electrically connected to the third node QB. Transistor T23 and transistor T24 are connected in series, a first electrode of transistor T23 is electrically connected to the second node Q1, and a second electrode of transistor T24 is electrically connected to the fourth power supply LVGL.

[0086] A control electrode of the transistor T25 is electrically connected to the second node Q1 , a first electrode of the transistor T25 is electrically connected to a second electrode of the transistor T23 , and a second electrode of the transistor T25 is electrically connected to a first power source VGH.

[0087] The transistor T26 and the thirtieth transistor T27 are connected in series, the control electrodes of the transistor T26 and the thirtieth transistor T27 are electrically connected to the first clock terminal CLK1, the first electrode of the transistor T26 is electrically connected to the fourth node Q, and the second electrode of the thirtieth transistor T27 is electrically connected to the fourth power supply LVGL.

[0088] In the embodiment of the present disclosure, the control electrode of transistor T28, the control electrode of transistor T30, the control electrode of transistor T32, and the control electrode of transistor T34 are all electrically connected to the second node Q1, and the control electrode of transistor T29, the control electrode of transistor T31, the control electrode of transistor T33, and the control electrode of transistor T35 are all electrically connected to the third node QB.

[0089] A first electrode of the transistor T28 is electrically connected to the clock terminal CLKE1 , and a second electrode of the transistor T28 is electrically connected to the output terminal SCout(i).

[0090] A control electrode of the transistor T29 is electrically connected to the third node QB, a first electrode of the transistor T29 is electrically connected to the second power source VGL, and a second electrode of the transistor T29 is electrically connected to the output terminal SCout(i).

[0091] A first terminal of the capacitor C3 is connected to the second node Q1 , and a second terminal of the capacitor C3 is connected to the output terminal SCout(i).

[0092] The control electrode of the transistor T30 is electrically connected to the second node Q1 , the first electrode of the transistor T30 is electrically connected to the clock terminal CLKE2 , and the second electrode of the transistor T30 is electrically connected to the output terminal SCout(i+1).

[0093] A control electrode of the transistor T31 is electrically connected to the third node QB, a first electrode of the transistor T31 is electrically connected to the second power source VGL, and a second electrode of the transistor T31 is electrically connected to the output terminal SCout(i+1).

[0094] A first terminal of the capacitor C4 is electrically connected to the second node Q1 , and a second terminal of the capacitor C4 is electrically connected to the output terminal SCout(i+1).

[0095] A first electrode of the transistor T32 is electrically connected to the clock terminal CLKE3 , and a second electrode of the transistor T32 is electrically connected to the output terminal SCout(i+2).

[0096] A control electrode of the transistor T33 is electrically connected to the third node QB, a first electrode of the transistor T33 is electrically connected to the second power source VGL, and a second electrode of the transistor T33 is electrically connected to the output terminal SCout(i+2).

[0097] A first terminal of the capacitor C5 is connected to the second node Q1 , and a second terminal of the capacitor C5 is connected to the output terminal SCout(i+2).

[0098] A control electrode of the transistor T34 is electrically connected to the second node Q1 , a first electrode of the transistor T34 is electrically connected to the clock terminal CLKE4 , and a second electrode of the transistor T34 is electrically connected to the output terminal SCout(i+3).

[0099] A control electrode of the transistor T35 is electrically connected to the third node QB, a first electrode of the transistor T35 is electrically connected to the second power source VGL, and a second electrode of the transistor T35 is electrically connected to the output terminal SCout(i+3).

[0100] A first terminal of the capacitor C6 is electrically connected to the second node Q1 , and a second terminal of the capacitor C6 is electrically connected to the output terminal SCout(i+3).

[0101] It should be noted that the present disclosure does not limit the number of output terminals.

[0102] Figure 4A and Figure 4B yes Figure 3 Signal timing diagram of the shift register in the figure, Figure 4A The timing waveforms of each signal in each stage during the forward scanning process are shown.

[0103] Below Figure 3 The structure of the shift register shown in the figure is taken as an example, combined with Figure 4A and Figure 4B The signal timing diagram shown describes the working process of the shift register provided by the embodiment of the present disclosure. The forward scanning working process of the shift register includes five stages.

[0104] For example, Figure 4A The figure shows the signal timing of the shift register 300 in the five stages S1-S5 during the forward scanning process. Figure 4A The timing of signals provided to the first stage shift register among the plurality of cascaded shift registers is shown.

[0105] In the first stage S1, the first clock signal CLK1 will first output a high level, the transistor T1 is turned on, the first power supply voltage VGH is provided to the control electrode of the transistor T11 through the transistor T1, and the transistor T11 is turned on. The first power supply voltage VGH is provided to the first node P through the transistor T11, so that the potential of the first node P is pulled up to a high level. The transistor T26 and the transistor T27 are turned on. The fourth power supply voltage LVGL is provided to the fourth node Q through the transistor T25 and the transistor T26, and the potential of the fourth node Q is pulled down. The high potential of the first node P controls the transistor T22 to turn on, and the low potential of the fourth node Q is provided to the second node Q1, pulling down the potential of the second node Q1, thereby resetting the fourth node Q and the second node Q1.

[0106] During the forward scanning operation, when the first clock signal CLK1 is at a high level, the above nodes can also be reset.

[0107] The first clock signal CLK1 changes from a high level to a low level, the selection signals D0 to D7 are at a low level, the second clock signal CLK2 is at a low level, and the clock signals CLKE1 to CLKE4 are at a low level.

[0108] The fourth power supply voltage LVGL is lower than the second power supply voltage VGL. Since the threshold voltage Vth of transistors T29, T31, T33 and T35 is prone to negative drift and cause leakage, when the fourth power supply voltage LVGL is lower than the second power supply voltage VGL, Vgs (LVGL-VGL) of the transistors in the cut-off state can be negative.

[0109] When the first clock signal CLK1 is at a high level, the transistor T1 is turned on under the control of the first clock signal CLK1. Since the first power supply voltage VGH is provided to the first end of the capacitor C1 through the transistor T1, the capacitor C1 is charged. The capacitor C1 stores a high level, so that the potential of the first node P is at a high level.

[0110] Under the control of the third power supply voltage GVDD, the transistors T15 , T16 , and T18 are turned on, so that the third node QB is at a high level.

[0111] Under the control of the high level of the third node QB, the transistors T23 and T24 are turned on, and the fourth power voltage LVGL is provided to the second node Q1 through the transistors T24 and T23, so that the potential of the second node Q1 is pulled down.

[0112] Under the control of the high level of the first node P, the transistor T22 is turned on, and the low level of the second node Q1 is provided to the fourth node Q through the transistor T22, so that the potential of the fourth node Q remains at a low level.

[0113] Under the control of the selection signals D0 to D7, the transistors T2 to T9 are turned off, the potential of the first node P is not reduced by the influence of the transistors T2 to T9, and the potential of the first node P is maintained at a high level.

[0114] When the first clock signal CLK1 changes from a high level to a low level, under the control of the first clock signal CLK1, the transistor T1 is turned off, and since the capacitor C1 maintains a high potential, the transistor T11 remains on, so that the first power supply voltage VGH is provided to the first node P, and the first node P remains at a high level.

[0115] In the second stage S2 , the first clock signal CLK1 is at a low level, and the second clock signal CLK2 is at a high level.

[0116] Under the control of the second clock signal CLK2, the transistor T14 is turned on, and the first power supply voltage VGH is provided to the fourth node Q through the transistor T14, so that the potential of the fourth node Q is high. Under the control of the high level of the first node P, the transistor T22 is turned on. The high level of the fourth node Q is provided to the second node Q1 through the transistor T22.

[0117] Under the control of the high level of the second node Q1, the transistors T17 and T19 are turned on, the second power supply voltage VGL is provided to the transistor T18 through the transistor T17, and under the control of the second power supply voltage VGL, the transistor T18 is turned off.

[0118] Under the control of the second clock signal CLK2, the transistor T21 is turned on. Under the control of the high level of the first node P, the transistor T20 is turned on. At this time, the fourth power supply voltage LVGL is provided to the third node QB through the transistor T20 and the transistor T21, so that the potential of the third node QB is pulled down.

[0119] In the embodiment of the present disclosure, when the selection signals D0 to D7 are all low level and the first clock signal CLK1 is low level, the first and second electrodes of transistors T2 to T9 are both low level. However, since the threshold voltage Vth is usually a negative value, if there is no transistor T10 and transistor T12, transistors T2 to T9 may not be completely cut off, and Vgs is less than 0, thereby causing the potential of the first node P to become a low level under the influence of the first clock signal CLK1. The transistors T10 and T12 provided in the shift register of the present disclosure are cut off under the control of the low potential of the third node QB, thereby avoiding leakage caused by the first node P being connected to the low potential through transistors T2 to T9.

[0120] In addition, when the second node Q1 is at a high level, transistors T17 and T19 are turned on. Since transistors T15, T16 and T18 are relatively small as a whole, when transistor T17 is turned on, the control electrode of transistor T18 drops to a negative voltage and works in a saturation region. When transistor T19 is turned on, it works in a linear region. Therefore, the third node QB is controlled to be at a low level, and the second control circuit 340 achieves the effect of potential inversion.

[0121] In the third phase S3 , the first clock signal CLK1 and the second clock signal CLK2 maintain a low level.

[0122] Under the control of the second clock signal CLK2, the potentials of the fourth node Q and the second node Q1 are kept at high level, and the third node QB is at low level. Under the control of the high level of the second node Q1, the transistors T28, T30, T32 and T34 are turned on.

[0123] The clock signal CLKE1 is provided to the output terminal SCout(i) through the transistor T28, so the scan signal output by the output terminal SCout(i) is the same as the clock signal CLKE1. The clock signal CLKE2 is provided to the output terminal SCout(i+1) through the transistor T30, so the scan signal output by the output terminal SCout(i+1) is the same as the clock signal CLKE2. The clock signal CLKE3 is provided to the output terminal SCout(i+2) through the transistor T32, so the scan signal output by the output terminal SCout(i+2) is the same as the clock signal CLKE3. The clock signal CLKE4 is provided to the output terminal SCout(i+3) through the transistor T34, so the scan signal output by the output terminal SCout(i+3) is the same as the clock signal CLKE4.

[0124] Due to the bootstrap effect of capacitors C3, C4, C5 and C6, after transistor T28 is turned on, capacitor C3 couples the high level of output terminal SCout(i) to the second node Q1. After transistor T30 is turned on, capacitor C4 couples the high level of output terminal SCout(i+1) to the second node Q1. After transistor T32 is turned on, capacitor C5 couples the high level of output terminal SCout(i+2) to the second node Q1. After transistor T30 is turned on, capacitor C6 couples the high level of output terminal SCout(i+3) to the second node Q1.

[0125] Since transistor T28, transistor T30, transistor T32 and transistor T34 are all controlled by the second node Q1, in the process of sequentially providing the potential of the second node Q1 to the control electrode of transistor T28, the control electrode of transistor T30, the control electrode of transistor T32 and the control electrode of transistor T34, the high potential of the second node Q1 is gradually consumed, and thus the control capability of transistor T28, transistor T30, transistor T32 and transistor T34 may gradually weaken.

[0126] The bootstrap effect of capacitors C3, C4, C5 and C6 can further increase the potential of the second node Q2, thereby achieving stable control of the control electrodes of transistors T28, T30, T32 and T34.

[0127] When the output terminal SCout(i) outputs the clock signal CLKE1, the capacitor C3 pulls up the potential of the second node Q1. When the output terminal SCout(i+1) outputs the clock signal CLKE2, the capacitor C4 pulls up the potential of the second node Q1. At this time, in the process of the output terminal SCout(i) outputting the clock signal CLKE1, it is first controlled by the stable high level of the second node Q1, and then the high potential of the second node Q1 is increased by the bootstrap effect of the capacitors C3 and C4, so that the output terminal SCout(i) can be controlled to stably output the scanning signal and reduce noise.

[0128] The process of outputting the scanning signal at the output terminal SCout(i+1) and the output terminal SCout(i+2) is similar, and will not be described again for the sake of brevity.

[0129] When the output terminal SCout(i+2) outputs the clock signal CLKE4, the capacitor C5 and the capacitor 6 pull up the potential of the second node Q1. However, when the output terminal SCout(i+1) outputs the clock signal CLKE2 from a high level to a low level, the bootstrap effect of the capacitor C5 on the second node Q1 disappears, and the potential of the second node Q1 decreases. At this time, the clock signal CLKD is at a high level, and the capacitor C7 can couple the high level of the clock signal CLKD to the second node Q1 through the bootstrap effect, thereby ensuring that the second node Q1 can control the transistor T35 to be in a stable on state, thereby reducing the noise of the clock signal CLKE4 output from the output terminal SCout(i+2).

[0130] At the end of the third stage S3, since the capacitor C1 is discharged, the potential of the first node P becomes low level under the control of the low level of the first clock signal CLK1. The gating stage of the shift register ends, and the output terminals SCout(i), SCout(i+1), SCout(i+2) and SCout(i+3) maintain outputting low level signals.

[0131] In the fourth stage S4 , the first clock signal CLK1 is at a high level.

[0132] Under the control of the first clock signal CLK1, the transistors T26 and T27 are turned on, and the fourth power voltage LVGL is provided to the fourth node Q through the transistors T27 and T26, so that the potential of the fourth node Q is pulled low.

[0133] Under the control of the first clock signal CLK1, the transistor T1 is turned on, and the first power supply voltage VGH is provided to the first node P through the transistor T11, so that the potential of the first node P becomes a high level, and the capacitor C1 that is discharged in the third stage S3 is recharged. At this time, the transistor T22 is turned on, and the potential of the second node Q1 is reduced to a low level.

[0134] Under the control of the low level of the second node Q1, the transistors T17 and T19 are turned off, and the transistor T18 is turned on. The third power supply voltage GVDD is provided to the third node QB through the transistor T18, so that the potential of the third node QB is at a high level.

[0135] In the fifth stage S5 , the selection signal D0 of the selection terminal D0 is at a high level, and the first clock signal CLK1 is at a low level.

[0136] Under the control of the selection signal D0, the transistor T2 is turned on. Under the control of the high level of the third node QB, the transistors T10 and T12 are turned on, and the first clock signal CLK1 is provided to the control electrode of the transistor T11 through the transistors T2 and T10, and the transistor T11 is turned off. The first clock signal CLK1 is provided to the first node P through the transistors T2 and T12, so that the potential of the first node P becomes a low level.

[0137] Under the control of the low level of the first node P, the transistor T22 is turned off, so that the potential of the second node Q1 decreases to a low level, and the transistors T28, T30, T32 and T34 are turned off.

[0138] Under the control of the high level of the third node QB, transistors T29, T31, T33 and T35 are turned on, and the second power supply voltage VGL is provided to the output terminal SCout(i), the output terminal SCout(i+1), the output terminal SCout(i+2) and the output terminal SCout(i+3).

[0139] Under the control of the first clock signal CLK1 and the selection signal D0, the shift register is in a non-selection stage.

[0140] In the disclosed embodiment, the shift register is selected by a total of 14 signals including the selection signals D0-D7, the clock signals CLK1 and CLK2, and the clock signals CLKE1-CLKE4, and the architecture is simplified. Each shift register can provide four scan signals under the control of the second node Q1. The potential of the second node Q1 is stabilized by the capacitor C7, without separating multiple second nodes to control multiple output terminals respectively, thereby simplifying the structure of the shift register. When the number of second nodes Q1 is reduced, the number of pull-down tubes in the pull-down circuit 360 is also simplified, further simplifying the circuit structure.

[0141] Multiple strobe signals can support the strobe display of multiple pixel rows. For example, the number of strobe signals is 2n, the number of decoding bits realized by the strobe signals is n, and the maximum number of rows supported is 2. n For example, the number of decoding bits realized by the selection signals D0-D7, D0'-D7' is 8.

[0142] The driving circuit GOA is composed of shift registers 300, and every two shift registers 300 form a driving unit. The two shift registers in the same driving unit receive the same strobe signal.

[0143] For example, the selection signals D0 to D7 are inverted signals of the selection signals D0' to D7', respectively. Among them, the selection signal D0 and the selection signal D0' are not at the effective level at the same time, the selection signal D1 and the selection signal D1' are not at the effective level at the same time, the selection signal D2 and the selection signal D2' are not at the effective level at the same time, the selection signal D3 and the selection signal D3' are not at the effective level at the same time, the selection signal D4 and the selection signal D4' are not at the effective level at the same time, the selection signal D5 and the selection signal D5' are not at the effective level at the same time, the selection signal D6 and the selection signal D6' are not at the effective level at the same time, and the selection signal D7 and the selection signal D7' are not at the effective level at the same time.

[0144] In the GOA composed of the shift register provided in the embodiment of the present disclosure, 8 selection signals can support 2048 (2 8 *8) Row strobe. If the number of rows needs to be increased, each additional strobe signal can support double the number of rows.

[0145] During the reverse scanning process, a clock signal that is inverse to the first clock signal CLK1 can be provided to the first clock terminal of the last shift register in the driving circuit, and a clock signal that is inverse to the second clock signal CLK2 can be provided to the second clock terminal of the last shift register in the driving circuit. Figure 4A The descriptions are similar and will not be repeated for brevity.

[0146] Figure 4B 4 is a signal timing diagram of a shift register according to another embodiment of the present disclosure.

[0147] Figure 4B The timing of signals provided to the last stage shift register among a plurality of cascaded shift registers is shown.

[0148] Figure 4B The timing changes of the first clock signal CLK1, the second clock signal CLK2, the selection signals D0 to D7, the clock signals CLK1 to CLKE4, and the potential changes of the first node P, the third node QB, and the fourth node Q can be referred to. Figure 4A For the sake of brevity, similar parts will not be repeated.

[0149] like Figure 4B As shown, in the second stage S2 and the third stage S3, the clock signal CLKD is at a high level. In this case, when the potential of the second node Q1 is pulled high in the second stage S2, the high potential of the clock signal CLKD is coupled to the second node Q1. Therefore, compared to Figure 4A The potential of the second node Q1 is shown, Figure 4B The potential of the second node Q1 is shown to be increased and pulled high a second time.

[0150] In this case, the potential of the second node Q1 can be stabilized at a higher potential in advance, so that the output terminals SCout(i), SCout(i+1), SCout(i+2) and SCout(i+3) can be controlled to stably output scan signals and reduce noise.

[0151] Figure 5 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0152] like Figure 5 As shown, the shift register 500 includes a first control circuit 510 , a gating circuit 520 , an input circuit 530 , a second control circuit 540 , an output circuit 550 , a pull-down circuit 560 , and a reset circuit 570 .

[0153] In the embodiment of the present disclosure, the first control circuit 510, the gating circuit 520, the second control circuit 540, the pull-down circuit 560 and the reset circuit 570 can respectively refer to the structures of the first control circuit 310, the gating circuit 320, the second control circuit 340, the pull-down circuit 360 and the reset circuit 370 described above, which are similar and will not be repeated for the sake of simplicity.

[0154] In the embodiment of the present disclosure, a first terminal of the capacitor C7 of the input circuit 530 is electrically connected to the clock signal CLKE1 , and a second terminal of the capacitor C7 is electrically connected to the second node Q1 .

[0155] For example, in a driving circuit composed of a plurality of shift registers 500, the first stage shift register may be electrically connected to the clock terminal CLKE1, the clock terminal CLKE2, the clock terminal CLKE3 and the clock terminal CLKE4, and output the clock signals CLKE1, the clock signal CLKE2, the clock signal CLKE3 and the clock signal CLKE4 to four output terminals respectively. The second stage shift register may be electrically connected to the clock terminal CLKE5, the clock terminal CLKE6, the clock terminal CLKE7 ​​and the clock terminal CLKE8, and output the clock signals CLKE5, the clock signal CLKE6, the clock signal CLKE7 ​​and the clock signal CLKE8 to four output terminals respectively.

[0156] The previous stage shift register may be electrically connected to the first clock terminal CLK1 and the second clock terminal CLK2. The next stage shift register may be electrically connected to the clock terminal CLK3 and the clock terminal CLK4.

[0157] The timing of the clock signals CLKE1 to CLKE8 and the timing of the clock signals CLK1 to CLK4 are as follows: Figure 6 shown.

[0158] The previous stage shift register may use the clock signal CLKE5 as a control signal, and the next stage shift register may use the clock signal CLKE1 as a control signal.

[0159] The high levels of clock signals CLKE1 to CLKE8 are shifted and outputted in sequence, and the high levels of clock signals CLK1 to CLK4 are shifted and outputted in sequence. Clock signals CLKE1 and CLKE5 are inverted clock signals, and clock signals CLKE1 and CLKE5 are not valid levels at the same time.

[0160] In the embodiment of the present disclosure, the clock signal CLKE1 and the clock signal CLKE5 are used as control signals, so as to reduce signal routing in the driving circuit, simplify the circuit structure, and reduce the circuit area.

[0161] Figure 6The potential changes of the first node P, the second node Q1, the third node QB and the fourth node Q shown can be referred to Figure 4A For the sake of brevity, similar parts will not be repeated.

[0162] Fig. 7A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0163] like Fig. 7A As shown, the driving circuit 700 includes M shift registers. For example, the shift register may be any one of the shift register 100, the shift register 200, the shift register 300 and the shift register 500 described above.

[0164] In the embodiment of the present disclosure, the mth shift register is electrically connected to the first selection line, the m+xth shift register is electrically connected to the second selection line, the selection signal electrically output by the first selection line and the selection signal output by the second selection line are not at the valid level at the same time, 1≤m≤Mx, 1≤x<M, M is a positive integer greater than 1, and m and x are positive integers.

[0165] For example, the strobe terminal D0 of the first shift register is electrically connected to the strobe signal line d0, and the strobe terminal D0 of the third shift register is electrically connected to the strobe signal line d0'. The strobe signals provided by the strobe signal line d0' and the strobe signal line d0 are not simultaneously at valid levels.

[0166] For example, when the strobe signal d0' is at a high level, the strobe signal d0 is at a low level. When the strobe signal d0 is at a high level, the strobe signal d0' is at a low level.

[0167] In the embodiment of the present disclosure, the driving circuit 700 further includes clock lines clke1 to clke8 , a first control line clkd1 and a second control line clkd3 .

[0168] The control terminal CS of the mth shift register is electrically connected to the first control line clkd1 , and the third clock terminals CLKE1 ˜ CLKE4 of the mth shift register are electrically connected to the clock lines clke1 ˜ clke4 , respectively.

[0169] The control terminal CS of the m+yth shift register is electrically connected to the second control line clkd3, and the third clock terminals CLKE1-CLKE4 of the m+yth shift register are electrically connected to the clock lines clke5-clke8, 1≤m≤≤My, 1≤y<M, y is a positive integer.

[0170] For example, the control terminal CS of the first shift register GOA1 is electrically connected to the first control line clkd1, and the third clock terminals CLKE1-CLKE4 of the first shift register GOA1 are electrically connected to the clock lines clke1-clke4 respectively. The control terminal CS of the second shift register GOA2 is electrically connected to the second control line clkd3, and the third clock terminals CLKE1-CLKE4 of the second shift register GOA2 are electrically connected to the clock lines clke5-clke8.

[0171] In the embodiment of the present disclosure, the control signal CLKD1 output by the first control line c1kd1 and the control signal CLKD3 output by the second control line clkd3 are not at the valid level at the same time, the control signal CLKD1 output by the first control line clkd1 can be consistent with the level change of the clock signal CLKE5 output by the clock line clke5, and the control signal CLKD3 output by the second control line clkd3 can be consistent with the level change of the clock signal CLKE1 output by the clock line clke1.

[0172] In some embodiments, the shift registers GOA1 to GOAM of the driving circuit 700 can refer to Figure 3 For example, the operation process of the shift register GOA1 can refer to Figure 3 and Figure 4A In this case, the timing of each signal received by the driving circuit 700 can be as follows: Fig. 7A shown.

[0173] According to an embodiment of the present disclosure, Fig. 7A It shows the signal changes of clock signals CLK1 to CLK4, clock signals CLKE1 to CLKE8, selection signals D0 to D7, the first node P, the second node Q1, the second subnode Q2, the third node QB, the fourth node Q, and the scan signal SCout(1) to SCout(4).

[0174] Figure 7B The timing changes of the scan signals SCout(1) to SCout(4) of the first node P, the second node Q1, the second subnode Q2, the third node QB and the fourth node Q are similar to the timing changes of the signals described above and will not be repeated for the sake of simplicity.

[0175] In some embodiments, the shift registers GOA1 to GOAM of the driving circuit 700 can refer to Figure 3 For example, the operation process of the shift register GOA1 can refer to Figure 3 and Figure 4B In this case, the timing of each signal received by the driving circuit 700 can be as follows: Figure 7C shown.

[0176] Figure 7C The timing changes of the scan signals SCout(1) to SCout(4) of the first node P, the second node Q1, the second subnode Q2, the third node QB and the fourth node Q are similar to the timing changes of the signals described above and will not be repeated for the sake of simplicity.

[0177] In the embodiments of the present disclosure, the clock signal output by the clock line clk3 connected to the shift register GOA2 described above has a similar function to the clock signal output by the clock line clk1 connected to the shift register GOA1 described above, the clock signal output by the clock line clk4 connected to the shift register GOA2 described above has a similar function to the clock signal output by the clock line clk2 connected to the shift register GOA1 described above, the clock signals output by the clock lines clke5 to clke8 connected to the shift register GOA2 described above have similar functions to the clock signals output by the clock lines clke1 to clke4 connected to the shift register GOA1 described above, the clock signals output by the clock line clkd3 connected to the shift register GOA2 described above have similar functions to the clock signals output by the clock line clkd1 connected to the shift register GOA1 described above, and for the sake of simplicity, they will not be repeated here.

[0178] In the embodiment of the present disclosure, the driving circuit 700 may include P driving unit groups, each of which may include multiple shift registers according to the embodiment of the present disclosure. The multiple shift registers included in the driving unit group are connected in the same manner as the multiple gate lines.

[0179] For example, the driving unit group 710 includes a shift register GOA1 and a shift register GOA2. The shift register GOA1 and the shift register GOA2 are connected to the plurality of gate lines in the same manner. It should be noted that: Fig. 7A The structure in which each driving unit group in the driving circuit 700 includes two shift registers is only schematically shown.

[0180] In the disclosed embodiment, the plurality of gating lines may include a plurality of gating lines d0 to d7 of a first gating group and a plurality of gating lines d0' to d7' of a second gating group. For example, the shift registers in the p-th driving unit group are all electrically connected to the first gating group, the shift registers in the p+1-th driving unit group are all electrically connected to the second gating group, the gating signal output by the first gating group is opposite to the gating signal output by the second gating group, 1≤p<P, and P is a positive integer greater than 1.

[0181] In the embodiment of the present disclosure, the M shift registers do not need to be cascaded, and the output signal is not controlled by other shift registers. The application of the driving circuit 700 can realize the output of a random frame displacement signal.

[0182] In an embodiment of the present disclosure, the number of gate lines included in the first gating group is the same as the number of gate lines included in the second gating group, and the number of gate lines included in each gating group is the same as the number of gating transistors included in the shift register. For example, the first gating group includes 8 gate lines d0 to d7, and the second gating group includes 8 gate lines d0' to d7'.

[0183] The gating signal output by each gating line in the gating group controls a gating transistor respectively. The present disclosure does not limit the number of gating lines and gating transistors, and the number of gating lines and gating transistors can be set according to actual needs.

[0184] In an embodiment of the present disclosure, the connection mode of the multiple shift registers included in the pth driving unit group is the same as the connection mode of the multiple gate lines included in the first gating group, and the connection mode of the multiple shift registers included in the p+1th driving unit group is the same as the connection mode of the multiple second gating lines included in the second gating group.

[0185] For example, one driving unit group may include two shift registers, and the shift registers in the group are connected to the strobe terminal in the same manner. For two adjacent driving unit groups, the shift registers in different driving unit groups are connected to the strobe terminal in different manners.

[0186] For example, the selection signal D0 and the selection signal D0' are not at the valid level at the same time, the selection signal D1 and the selection signal D1' are not at the valid level at the same time, the selection signal D2 and the selection signal D2' are not at the valid level at the same time, the selection signal D3 and the selection signal D3' are not at the valid level at the same time, the selection signal D4 and the selection signal D4' are not at the valid level at the same time, the selection signal D5 and the selection signal D5' are not at the valid level at the same time, the selection signal D6 and the selection signal D6' are not at the valid level at the same time, and the selection signal D7 and the selection signal D7' are not at the valid level at the same time.

[0187] Figure 8 is a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure.

[0188] like Figure 8 As shown, the driving circuit 800 includes M shift registers. For example, the shift register may be any one of the shift register 100, the shift register 200, the shift register 300 and the shift register 500 described above.

[0189] In the embodiment of the present disclosure, the connection relationship between the gate terminals D0-D7 of the shift register and the gate line, the connection relationship between the clock terminals CLK1 and CLK2 and the clock lines clk1-clk4, and the connection relationship between the clock terminals CLKE1-CLKE4 and the clock lines clke1-clke8 can be referred to. Fig. 7A , for the sake of brevity, I will not go into details.

[0190] In the embodiment of the present disclosure, the control terminal CS of the mth shift register is electrically connected to the clock line clke5, and the control terminal CS of the m+yth shift register is electrically connected to the clock line clke1, 1≤m≤My, 1≤y<M, y is a positive integer;

[0191] For example, the control terminal CS of the first shift register GOA1 is electrically connected to the clock line clke5, and the control terminal CS of the second shift register GOA2 is electrically connected to the clock line clke1.

[0192] In the embodiment of the present disclosure, the clock signal CLKE5 of the clock line clke5 and the clock signal CLKE1 output by the clock line clke1 are not at the valid level at the same time.

[0193] In some embodiments, the shift registers GOA1 to GOAM of the driving circuit 800 can refer to Figure 5 For example, the operation process of the shift register GOA1 can refer to Figure 5 and Figure 6 In this case, the timing of each signal received by the driving circuit 800 can be as follows: Figure 6 shown.

[0194] In the embodiments of the present disclosure, the clock signal output by the clock line c1k3 connected to the shift register GOA2 described above has a similar function to the clock signal output by the clock line clk1 connected to the shift register GOA1 described above, the clock signal output by the clock line clk4 connected to the shift register GOA2 described above has a similar function to the clock signal output by the clock line clk2 connected to the shift register GOA1 described above, the clock signals output by the clock lines clke5 to clke8 connected to the shift register GOA2 described above have similar functions to the clock signals output by the clock lines clke1 to clke4 connected to the shift register GOA1 described above, the clock signal output by the clock line clke1 connected to the shift register GOA2 described above has similar functions to the clock signal output by the clock line clke5 connected to the shift register GOA1 described above, and for the sake of simplicity, they will not be repeated here.

[0195] In the embodiment of the present disclosure, the driving circuit 800 may also include P driving unit groups, each of which may include multiple shift registers as in the embodiment of the present disclosure. The multiple shift registers included in the driving unit group are connected in the same manner as the multiple gate lines.

[0196] For example, the driving unit group 810 may refer to the driving unit group 710 described above, which will not be described again for the sake of brevity.

[0197] Fig. 9 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0198] like Fig. 9 As shown, the display device 900 includes a display panel 910 and a driving circuit 920 .

[0199] In the embodiment of the present disclosure, the display panel 910 includes a plurality of sub-pixel units Pixel arranged in an array, and the driving circuit is used to drive the sub-pixel units Pixel. Each row of pixel units Piex1 in the display panel 910 forms a pixel row 911.

[0200] In the embodiment of the present disclosure, the driving circuit 920 may be the driving circuit 700 and the driving circuit 800 described above, which will not be described in detail herein. A shift register 921 in the driving circuit 920 may drive a pixel row 911, thereby controlling whether a single pixel row is enabled.

[0201] It should be noted that the number of sub-pixel units included in the display panel 910 is only for illustrative purposes, and the present disclosure does not limit the number of sub-pixel units.

[0202] The driving circuit 920 includes a plurality of shift registers supporting gating, each of which is connected to sub-pixel units of different rows. When a row of sub-pixel units needs to be refreshed, the driving circuit can grate the corresponding shift register to achieve the refresh of the sub-pixel units of the specified row.

[0203] Fig.10 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0204] like Fig.10 As shown, the driving method may include operations S1010 - S1020 .

[0205] In the embodiment of the present disclosure, the driving method may be applied to the shift register 100 , the shift register 200 , the shift register 300 , and the shift register 500 described above.

[0206] In operation S1010, during the duration of the first level of the qth clock sub-signal, the q+1th clock sub-signal jumps from the second level to the first level. 1≤q≤Q-1, q is an integer.

[0207] In operation S1020, the control signal jumps from the second level to the first level during a duration of the first level of the Q-th clock sub-signal.

[0208] In the embodiment of the present disclosure, operations S1010 - S1020 are similar to the operations performed by the shift register 300 and the shift register 500 described above, and are not described in detail herein.

[0209] In the embodiment of the present disclosure, the third clock signal includes Q clock sub-signals whose effective levels are sequentially shifted, where Q is a positive integer. The first clock signal and the control signal are not simultaneously effective levels. For example, the third clock signal includes clock signals CLKE1 to CLKE4. The first clock signal may be clock signal CLKE1.

[0210] The flow charts and block diagrams in the accompanying drawings illustrate the possible architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0211] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways, even if such combinations and / or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and / or claims of the present disclosure may be combined and / or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and / or combinations fall within the scope of the present disclosure.

[0212] The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: A first control circuit configured to provide a first power supply voltage of a first power supply to a first node under the control of a first clock signal from a first clock terminal; a gating circuit configured to provide the first clock signal to the first node under the control of a plurality of gating signals from a plurality of gating terminals; an input circuit configured to provide the first power supply voltage to the second node under the control of the potential of the first node and the second clock signal from the second clock terminal, and to control the potential of the second node using a control signal from the control terminal; a second control circuit configured to provide a third power supply voltage of a third power supply or a fourth power supply voltage of a fourth power supply to a third node under the control of the potential of the second node and the second power supply voltage of the second power supply; The output circuit is configured to provide a third clock signal from a third clock terminal or the second power supply voltage to an output terminal as an output scanning signal under the control of the potentials of the second node and the third node.

2. The shift register according to claim 1, wherein: The input circuit is electrically connected to the first power supply, the second clock terminal, the control terminal, the first node, the second node and a fourth node; The input circuit is configured as: Under the control of the second clock signal, providing the first power supply voltage to the fourth node; Under the control of the potential of the first node, providing the potential of the fourth node to the second node; as well as Under control of the control signal, the control signal is coupled to the second node.

3. The shift register according to claim 1, wherein: The third clock terminal includes a first sub-clock terminal and a second sub-clock terminal, the output terminal includes a first sub-output terminal and a second sub-output terminal; the output circuit is configured as follows: Under the control of the potential of the second node, outputting the first clock sub-signal from the first sub-clock terminal to the first sub-output terminal; as well as Under the control of the potential of the second node, outputting the second clock sub-signal from the second sub-clock terminal to the second sub-output terminal; Wherein, during the duration of the first level of the second clock sub-signal, the first clock sub-signal jumps from the first level to the second level, and the control signal jumps from the second level to the first level.

4. The shift register according to claim 1, further comprising: a pull-down circuit electrically connected to the first node, the second node, the third node, the second clock terminal, and the fourth power supply; The pull-down circuit is configured as: Under the control of the potential of the first node and the second clock signal, supplying the fourth power supply voltage to the potential of the third node; as well as Under control of the third node, the fourth power supply voltage is provided to the second node.

5. The shift register according to claim 1, further comprising: A reset circuit, electrically connected to the first clock terminal, the fourth node, and the fourth power supply; The reset circuit is configured to provide the fourth power supply voltage to the fourth node under control of the first clock signal.

6. The shift register according to claim 1, wherein: The gating circuit is electrically connected to the plurality of gating terminals and the first node, and the gating circuit is configured as: The first clock signal is provided to the first node under the control of a first level of any one of the plurality of selection signals.

7. The shift register according to claim 6, wherein: The gating circuit is also electrically connected to the third node, and the gating circuit is further configured to: The first clock signal is provided to the potential of the first node under the control of the first level of the third node and the first level of any one of the plurality of selection signals.

8. The shift register according to claim 1, wherein: The input circuit includes a first transistor, a second transistor and a first capacitor; Wherein, the control electrode of the first transistor is electrically connected to the second clock terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the fourth node; a control electrode of the second transistor is electrically connected to the first node, a first electrode of the second transistor is electrically connected to the fourth node, and a second electrode of the second transistor is electrically connected to the second node; and A first end of the first capacitor is the control end, and a second end of the first capacitor is electrically connected to the second node.

9. The shift register according to claim 1, wherein: The gating circuit includes a third transistor, a fourth transistor, and a plurality of gating transistors; wherein the control electrode of the third transistor is electrically connected to the third node, the first electrode of the third transistor is electrically connected to the first control circuit, and the second electrode of the third transistor is electrically connected to the first electrodes of the plurality of selection transistors; The control electrode of the fourth transistor is electrically connected to the third node, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the first electrodes of the plurality of gate transistors; The control electrodes of the plurality of gating transistors are electrically connected to the plurality of gating terminals respectively, and the second electrodes of the plurality of gating transistors are electrically connected to the first clock terminal.

10. The shift register according to claim 4, wherein: The pull-down circuit includes a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor and a ninth transistor; wherein the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the third node, and the second electrode of the fifth transistor is electrically connected to the first electrode of the sixth transistor; The control electrode of the sixth transistor is electrically connected to the first clock terminal, and the second electrode of the sixth transistor is electrically connected to the fourth power supply; The control electrode of the seventh transistor and the control electrode of the eighth transistor are electrically connected to the third node; The seventh transistor is connected in series with the eighth transistor, a first electrode of the seventh transistor is electrically connected to the second node, and a second electrode of the eighth transistor is electrically connected to the fourth power supply; A control electrode of the ninth transistor is electrically connected to the second node, a first electrode of the ninth transistor is electrically connected to a second electrode of the seventh transistor, and a second electrode of the ninth transistor is electrically connected to the first power source.

11. The shift register according to claim 1, wherein: The first control circuit includes a tenth transistor, an eleventh transistor, a twelfth transistor, a second capacitor and a third capacitor; Wherein, the control electrode of the tenth transistor is electrically connected to the first clock terminal, the first electrode of the tenth transistor is electrically connected to the first power supply, and the second electrode of the tenth transistor is electrically connected to the control electrode of the eleventh transistor; The first pole of the eleventh transistor is electrically connected to the first power supply, and the second pole of the eleventh transistor is electrically connected to the first node; The control pole of the twelfth transistor is electrically connected to the first node, the first pole of the twelfth transistor is electrically connected to the first power supply, and the second pole of the twelfth transistor is electrically connected to the strobe circuit; The first end of the second capacitor is electrically connected to the control pole of the eleventh transistor, and the second end of the second capacitor is electrically connected to the first node; and The first end of the third capacitor is electrically connected to the first power supply, and the second end of the third capacitor is electrically connected to the first node.

12. The shift register according to claim 1, wherein: The second control circuit includes a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, and a seventeenth transistor; Wherein, the control pole and the first pole of the thirteenth transistor are electrically connected to the third power supply, and the second pole of the thirteenth transistor is electrically connected to the first pole of the fourteenth transistor; The control pole of the fourteenth transistor is electrically connected to the third power supply, and the second pole of the fourteenth transistor is electrically connected to the control pole of the sixteenth transistor; The control pole of the fifteenth transistor is electrically connected to the second node, the first pole of the fifteenth transistor is electrically connected to the control pole of the sixteenth transistor, and the second pole of the fifteenth transistor is electrically connected to the second power supply; The first pole of the sixteenth transistor is electrically connected to the third power supply, and the second pole of the sixteenth transistor is electrically connected to the third node; The control pole of the seventeenth transistor is electrically connected to the second node, the first pole of the seventeenth transistor is electrically connected to the third node, and the second pole of the seventeenth transistor is electrically connected to the fourth power supply.

13. The shift register according to claim 5, wherein: The output circuit includes an eighteenth transistor and a nineteenth transistor; Wherein, the eighteenth transistor and the nineteenth transistor are connected in series, the control poles of the eighteenth transistor and the nineteenth transistor are electrically connected to the first clock terminal, the first pole of the eighteenth transistor is electrically connected to the fourth node, and the second pole of the nineteenth transistor is electrically connected to the fourth power supply.

14. A driving circuit comprising: M shift registers according to any one of claims 1-13; Wherein, the m-th shift register is electrically connected to the first strobe line, the (m + x)-th shift register is electrically connected to the second strobe line, and the strobe signals output by the first strobe line and the second strobe line are not both at the effective level at the same time, 1 ≤ m ≤ M - x, 1 ≤ x < M, M is a positive integer greater than 1, and m and x are positive integers.

15. The driving circuit according to claim 14, further comprising a first clock line, a second clock line, a first control line, and a second control line; in, The control terminal of the m-th shift register is electrically connected to the first control line, and the third clock terminal of the m-th shift register is electrically connected to the first clock line; The control terminal of the (m + y)-th shift register is electrically connected to the second control line, and the third clock terminal of the (m + y)-th shift register is electrically connected to the second clock line, 1 ≤ m ≤ M - y, 1 ≤ y < M, and y is a positive integer; Among them, the control signal output by the first control line and the control signal output by the second control line are not at the valid level at the same time, the control signal output by the first control line is consistent with the level change of the clock signal output by the second clock line, and the control signal output by the second control line is consistent with the level change of the clock signal output by the first clock line.

16. The driving circuit according to claim 14, further comprising a first clock line and a second clock line; in, The third clock terminal of the mth shift register is electrically connected to the first clock line, and the control terminal of the mth shift register is electrically connected to the second clock line; The third clock terminal of the m+yth shift register is electrically connected to the second clock line, and the control terminal of the m+yth shift register is electrically connected to the first clock line, 1≤m≤My, 1≤y<M, y is a positive integer; The clock signal output by the first clock line and the clock signal output by the second clock line are not at the valid level at the same time.

17. The driving circuit according to claim 14, wherein: Comprising P driving unit groups, P is a positive integer, and each of the driving unit groups comprises a plurality of shift registers according to any one of claims 1 to 13; The plurality of shift registers included in the driving unit group are connected in the same manner as the plurality of gate lines.

18. A display device comprising: Display panel; as well as The driving circuit according to any one of claims 14 to 17; Wherein, the display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

19. A driving method, applied to the shift register according to any one of claims 1 to 13, comprising: During the duration of the first level of the qth clock sub-signal, the q+1th clock sub-signal jumps from the second level to the first level, 1≤q≤Q-1, q is an integer; During the duration of the first level of the Qth clock sub-signal, the control signal jumps from the second level to the first level; The third clock signal includes Q clock sub-signals whose effective levels are sequentially shifted, where Q is a positive integer; and the first clock signal and the control signal are not at effective levels at the same time.

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