Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device.According to the display panel, an nth-level gate drive circuit comprises a (2n-1) th signal output end and a 2nth signal output end, the (2n-1) th signal output end is electrically connected with a (2n-1) th scanning line, and the 2nth signal output end is electrically connected with a 2nth scanning line; the first pull-up module is electrically connected between the (2n-1) th clock signal line and the (2n-1) th signal output end, and the second pull-up module is electrically connected between the 2n th clock signal line and the 2n th signal output end, so that the first-stage gate drive circuit can output scanning signals to the two scanning lines. The original two-stage gate drive circuit can share at least part of transistors in the pull-up module, the pull-down maintenance module and the pull-down module, so that the space occupied by the gate drive circuit is reduced, and the frame of the display panel can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] GOA (Gate On Array, array substrate row drive) technology refers to a driving method that realizes row-by-row scanning of the gate by making the gate row scanning drive signal on the array substrate. Since GOA technology can eliminate the gate drive chip and circuit board, save the space of the gate drive chip and circuit board, and can achieve a narrow border, GOA technology is widely used in display panels. In order to achieve the increase and decrease of the potential of the signal output terminal and the internal node, the gate drive circuit will be provided with a pull-up control unit, a pull-up unit, a pull-down unit, a pull-down maintenance unit, etc. Each unit will be provided with at least one transistor, and the units need to be connected by wiring, resulting in a large space occupied by the gate drive circuit, resulting in a larger border of the display panel.

[0003] Therefore, the existing display panel has a technical problem that the gate driving circuit occupies a large space. Summary of the invention

[0004] Embodiments of the present application provide a display panel and a display device, which are used to solve the technical problem that a gate driving circuit of an existing display panel occupies a large space.

[0005] In order to achieve the above object, according to a first aspect of the present application, a display panel is provided, the display panel comprising a plurality of cascaded gate drive circuits and a plurality of scan lines, each of the gate drive circuits comprising:

[0006] A pull-up control module electrically connected to the internal node;

[0007] A pull-up module, electrically connected to the internal node, the pull-up module comprising a first pull-up module and a second pull-up module;

[0008] Wherein, the gate driving circuit of the nth level includes a (2n-1)th signal output terminal and a 2nth signal output terminal, the (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, the 2nth signal output terminal is electrically connected to the 2nth scan line, the first pull-up module is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module is electrically connected between the 2nth clock signal line and the 2nth signal output terminal; n is greater than or equal to 1, and n is a positive integer.

[0009] According to a second aspect of the present application, a display device is provided, comprising a display panel as described in any one of the above embodiments.

[0010] An embodiment of the present application provides a display panel and a display device, wherein the display panel includes a plurality of cascaded gate driving circuits and a plurality of scan lines, wherein a pull-up module in each gate driving circuit includes a first pull-up module and a second pull-up module, and an n-th level gate driving circuit includes a (2n-1)th signal output terminal and a 2nth signal output terminal, wherein the (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, and the 2nth signal output terminal is electrically connected to the 2nth scan line, wherein the first pull-up module is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module is electrically connected between the 2nth clock signal line and the 2nth signal output terminal, so that a first-level gate driving circuit can output scan signals to two scan lines, so that the original two-level gate driving circuit can share at least part of the transistors in the pull-up module, the pull-down maintaining module and the pull-down module, thereby reducing the space occupied by the gate driving circuit, and thus reducing the frame of the display panel.

[0011] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0013] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same figure numbers represent the same parts in the following description.

[0014] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application.

[0015] Figure 2 A schematic diagram of the connection between each level of gate driving circuit and the scan line in the display panel provided in an embodiment of the present application.

[0016] Figure 3 A schematic diagram of the connections of the various modules of the gate drive circuit provided in an embodiment of the present application.

[0017] Figure 4 A first circuit diagram of a gate drive circuit provided in an embodiment of the present application.

[0018] Figure 5 A second circuit diagram of the gate drive circuit provided in an embodiment of the present application.

[0019] Figure 6This is a timing diagram of each signal line of the display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0020] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0021] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", and "electrically connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be directly connected, or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0022] In order to illustrate the principle of the technical problem of the present application, the embodiment of the present application illustrates the design of a comparative display device. It can be understood that the comparative display device cannot be used as the prior art in the embodiment of the present application. In order to reduce the frame, the comparative display device will use a gate drive circuit to replace the gate drive chip. Specifically, a multi-level gate drive circuit will be set up to connect each level of the gate drive circuit to each scan line. A pull-up unit, a pull-up control unit, a pull-down unit, a pull-down maintenance unit and a bootstrap capacitor will be set in each level of the gate drive circuit. At least one transistor will be provided in each unit, so that each level of the gate drive circuit needs to occupy a large space. When a multi-level gate drive circuit is set, the gate drive circuit will occupy a large space, resulting in a larger frame of the comparative display device. Therefore, the existing display panel has the technical problem that the gate drive circuit occupies a large space.

[0023] In view of the above technical problems, the embodiments of the present application provide a display panel and a display device to solve the above technical problems.

[0024] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application. Figure 2 A schematic diagram of the connection between each level of gate driving circuit and the scan line in the display panel provided in an embodiment of the present application. Figure 3 A schematic diagram of the connections of the various modules of the gate drive circuit provided in an embodiment of the present application. Figure 4 A first circuit diagram of a gate drive circuit provided in an embodiment of the present application. Figure 5A second circuit diagram of the gate drive circuit provided in an embodiment of the present application. Figure 6 This is a timing diagram of each signal line of the display panel provided in an embodiment of the present application.

[0025] like Figures 1 to 6 As shown, the embodiment of the present application provides a display panel, the display panel 1 includes a plurality of cascaded gate driving circuits 21 and a plurality of scanning lines 11, each of the gate driving circuits 21 includes a pull-up control module 211 and a pull-up module 212, the pull-up control module 211 is electrically connected to an internal node Q; the pull-up module 212 is electrically connected to the internal node Q, and the pull-up module 212 includes a first pull-up module 212a and a second pull-up module 212b;

[0026] Wherein, the nth level gate driving circuit 21 includes a (2n-1)th signal output terminal G(2n-1) and a 2nth signal output terminal G(2n), the (2n-1)th signal output terminal G(2n-1) is electrically connected to the (2n-1)th scan line, the 2nth signal output terminal is electrically connected to the 2nth scan line, the first pull-up module 212a is electrically connected between the (2n-1)th clock signal line CK(2n-1) and the (2n-1)th signal output terminal G(2n-1), and the second pull-up module 212b is electrically connected between the 2nth clock signal line CK(2n) and the 2nth signal output terminal G(2n); n is greater than or equal to 1, and n is a positive integer.

[0027] An embodiment of the present application provides a display panel, which enables the pull-up module 212 in each gate driving circuit 21 to include a first pull-up module 212a and a second pull-up module 212b, the n-th level gate driving circuit includes a (2n-1)th signal output terminal and a 2nth signal output terminal, the (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, the 2nth signal output terminal is electrically connected to the 2nth scan line, the first pull-up module 212a is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module 212b is electrically connected between the 2nth clock signal line and the 2nth signal output terminal, so that the first-level gate driving circuit can output a scan signal to two scan lines, so that the original two-level gate driving circuit can share the pull-up module, the pull-down holding module and at least part of the transistors in the pull-down module, thereby reducing the space occupied by the gate driving circuit, and thus reducing the border of the display panel.

[0028] Specifically, Figure 1As shown, the display panel 1 includes a display area 101 and a non-display area 102. The non-display area 102 can be arranged around the display area 101, but the embodiment of the present application is not limited thereto. The non-display area 102 can be arranged on one side, two sides or three sides of the display area 101, and the non-display area 102 can be bent to the back of the display area 101. The scan line 11 is arranged in the display area 101, and the non-display area 102 can include a gate drive circuit setting area 102a. The gate drive circuit 21 can be arranged in the gate drive circuit setting area 102a. The gate drive circuit setting area 102a can be arranged on one side of the display area 101 or on both sides of the display area 101. Accordingly, the gate drive circuit 21 can be arranged on one side of the display area 101 or on both sides of the display area 101.

[0029] Specifically, the non-display area 102 may further include a binding area (not shown).

[0030] Specifically, compared with the current display device, in which the first-level gate driving circuit has one signal output terminal, so that each level of the gate driving circuit outputs a scanning signal to a scanning line, the embodiment of the present application enables the first-level gate driving circuit to have two signal output terminals, so that the first-level gate driving circuit can output scanning signals to two scanning lines, and the two signal output terminals in the first-level gate driving circuit in the embodiment of the present application can share modules such as the pull-up control module, and can share some transistors in the pull-down module and the pull-down maintenance module, so that the space occupied by the first-level gate driving circuit in the embodiment of the present application is smaller than the space occupied by the two-level gate driving circuit in the current display device, thereby reducing the border.

[0031] Specifically, when two signal output terminals are set in a first-level gate driving circuit, in order to facilitate the connection between the gate driving circuit and the scan line, reduce the cross-line, and shorten the length of the wiring, the gate driving circuit of this level can be connected to the two nearest scan lines. For example, taking the number of scan lines of the display panel as 1000, only 500-level gate driving circuits need to be set accordingly (when the gate driving circuit is set on both sides of the display area, a 500-level gate driving circuit can be set on one side of the display area, and a 500-level gate driving circuit can be set on the other side of the display area, and each scan line is connected to the same level of gate driving circuit on both sides). The circuits are arranged from top to bottom, with the first-level gate driving circuit being arranged at the top of the display panel and the 500th-level gate driving circuit being arranged at the bottom of the display panel. Meanwhile, the scan lines are also arranged from top to bottom, with the first scan line being arranged at the top of the display panel and the 1000th scan line being arranged at the bottom of the display panel. The first-level gate driving circuit can be connected to the first scan line and the second scan line, the second-level gate driving circuit can be connected to the third scan line and the fourth scan line, ..., the 500th-level gate driving circuit can be connected to the 999th scan line and the 1000th scan line, thereby reducing the crossover line and the length of the wiring.

[0032] Specifically, Figure 2 As shown, taking the maximum value of n as N, k greater than 2 and less than N, and k being a positive integer as an example, the first-level gate drive circuit 21a is connected to the first scan line Scan1 and the second scan line Scan2, the second-level gate drive circuit 21b is connected to the third scan line Scan3 and the fourth scan line Scan4, ..., the k-th level gate drive circuit 21c is connected to the (2k-1)-th scan line Scan(2k-1) and the 2k-th scan line Scan2k, ..., the N-th level gate drive circuit 21c is connected to the (2N-1)-th scan line Scan(2N-1) and the 2N-th scan line Scan2N. It can be seen that the gate drive circuits of each level are connected to each scan line in sequence to avoid the need for crossing between the lines and to avoid the length of the lines being too long, thereby reducing impedance.

[0033] Specifically, when setting the clock signal line, the multi-stage gate drive circuit will reuse the clock signal line. For example, the display panel will be provided with 4 clock signal lines, the first-stage gate drive circuit will connect the first clock signal line and the second clock signal line, the second-stage gate drive circuit will connect the third clock signal line and the fourth clock signal line, the third-stage gate drive circuit will connect the first clock signal line and the second clock signal line, and the fourth-stage gate drive circuit will connect the third clock signal line and the fourth clock signal line. Similarly, the connection relationship between other gate drive circuits and clock signal lines can be determined. Based on the 4 clock signal lines, it can be determined that the 2n-1th clock signal line is the first clock signal line or the third clock signal line, and the 2nth clock signal line is the second clock signal line or the fourth clock signal line. According to the different levels of the gate drive circuit, the specific clock signal lines corresponding to the 2n-1th clock signal line and the 2nth clock signal line are determined.

[0034] Specifically, the above embodiment is described by taking the display panel including 4 clock signal lines as an example, but the embodiment of the present application is not limited thereto, and the display panel may include 8 clock signal lines or other numbers of clock signal lines.

[0035] In some embodiments, Figures 3 to 5As shown, the first pull-up module 212a includes a first pull-up transistor T21a, a first electrode of the first pull-up transistor T21a is electrically connected to the (2n-1)th clock signal line CK(2n-1), and a second electrode of the first pull-up transistor T21a is electrically connected to the (2n-1)th signal output terminal G(2n-1); the second pull-up module 212b includes a second pull-up transistor T21b, a first electrode of the second pull-up transistor T21b is electrically connected to the 2nth clock signal line CK(2n), and a second electrode of the second pull-up transistor T21b is electrically connected to the 2nth signal output terminal G(2n). By electrically connecting the first electrode of the first pull-up transistor to the (2n-1)th clock signal line CK(2n-1), the second electrode of the first pull-up transistor T21a to the (2n-1)th signal output terminal G(2n-1), the first electrode of the second pull-up transistor T21b to the 2nth clock signal line CK(2n), and the second electrode of the second pull-up transistor T21b to the 2nth signal output terminal G(2n), the first pull-up transistor and the second pull-up transistor can respectively control the (2n-1)th clock signal line CK(2n-1) and the 2nth clock signal line CK(2n) to output signals to the (2n-1)th signal output terminal G(2n-1) and the 2nth signal output terminal G(2n), so that each scan line is turned on in sequence, thereby driving the pixel.

[0036] In some embodiments, Figure 4 As shown, the gate of the first pull-up transistor T21a is electrically connected to the internal node Q, and the gate of the second pull-up transistor T21b is electrically connected to the internal node Q. By electrically connecting the gate of the first pull-up transistor T21a to the internal node Q, and the gate of the second pull-up transistor T21b to the internal node Q, the first pull-up transistor and the second pull-up transistor are controlled by the potential of the internal node, so that when the internal node Q outputs a valid potential, the clock signal line and the signal output end are connected.

[0037] In some embodiments, Figure 5 As shown, the gate of at least one of the first pull-up transistor T21a and the second pull-up transistor T21b includes a first gate and a second gate, and the display panel 1 further includes a gate control module 216, and the gate control module 216 is configured to turn off the first pull-up transistor T21a according to a signal of the 2nth signal output terminal G(2n), and / or turn off the second pull-up transistor T21b according to a signal of the (2n+1)th signal output terminal G(2n+1);

[0038] The first gate of at least one of the first pull-up transistor T21a and the second pull-up transistor T21b is electrically connected to the internal node Q, and the second gate of at least one of the first pull-up transistor T21a and the second pull-up transistor T21b is electrically connected to the gate control module 216. By making at least one of the first pull-up transistor and the second pull-up transistor include a first gate and a second gate, and the display panel further includes a gate control module, the first gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the internal node, and the second gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the gate control module, so that when the next signal output terminal outputs a signal, the previous signal output terminal can stop inputting a signal, thereby avoiding display abnormalities such as panel flickering.

[0039] Specifically, the first pull-up transistor can include a first gate and a second gate, the first gate of the first pull-up transistor is electrically connected to the internal node, the second gate of the first pull-up transistor is connected to the gate control module, and the gate of the second pull-up transistor is electrically connected to the internal node; or the gate of the first pull-up transistor is electrically connected to the internal node, the second pull-up transistor includes a first gate and a second gate, the first gate of the second pull-up transistor is electrically connected to the internal node, and the second gate of the second pull-up transistor is connected to the gate control module.

[0040] Specifically, compared to a gate drive circuit without a gate control module, since the internal node simultaneously controls the first pull-up transistor T21a and the second pull-up transistor T21 to be turned on or off, after the (2n-1)th signal output terminal completes signal output, since the 2nth signal output terminal needs to output a signal, the internal node Q still needs to maintain a high potential, resulting in the first pull-up transistor T21a still being in an on state, affecting the display effect. The embodiment of the present application sets a gate control module, so that after the (2n-1)th signal output terminal completes signal output, the first pull-up transistor T21a can be turned off to avoid display abnormalities.

[0041] In some embodiments, Figure 5 As shown, the gates of the first pull-up transistor T21a and the second pull-up transistor T21b both include a first gate and a second gate, and the gate control module 216 includes a first gate control module 216a and a second gate control module 216b;

[0042] The first gate of the first pull-up transistor T21a is electrically connected to the internal node Q, and the second gate of the first pull-up transistor T21a is electrically connected to the first gate control module 216a; the first gate of the second pull-up transistor T21b is electrically connected to the internal node Q, and the second gate of the second pull-up transistor T21b is electrically connected to the second gate control module 216b. By making the first pull-up transistor and the second pull-up transistor both include a first gate and a second gate, and the gate control module includes a first gate control module and a second gate control module, when the signal output terminal connected to the next scan line outputs a signal, the pull-up transistor connected to the signal output terminal of the previous scan line can be turned off to avoid display influence.

[0043] Specifically, the first gate and the second gate may be respectively regarded as the top gate and the bottom gate of the pull-up transistor. It can be understood that the first gate and the second gate may also be respectively regarded as the bottom gate and the top gate of the pull-up transistor.

[0044] In some embodiments, Figure 5 As shown, the first gate control module 216a includes a first gate control transistor T211a, the gate of the first gate control transistor T211a is electrically connected to the 2nth signal output terminal, the first electrode of the first gate control transistor T211a is electrically connected to the low potential power supply terminal VSS, and the second electrode of the first gate control transistor T211a is electrically connected to the second gate of the first pull-up transistor T21a. By setting the first gate control transistor T211a, the gate of the first gate control transistor T211a is electrically connected to the 2nth signal output terminal, the first electrode of the first gate control transistor T211a is electrically connected to the low potential power supply terminal VSS, and the second electrode of the first gate control transistor T211a is electrically connected to the second gate of the first pull-up transistor T21a, so that when the 2nth signal output terminal outputs a signal, the first gate control transistor can be turned on, so that the low potential power supply terminal VSS outputs a low potential signal to the second gate of the first pull-up transistor T21a, and the first pull-up transistor is turned off.

[0045] In some embodiments, Figure 5As shown, the second gate control module 216b includes a second gate control transistor T211b, the gate of the second gate control transistor T211b is electrically connected to the (2n+1)th signal output terminal G(2n+1), the first electrode of the second gate control transistor T211b is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second gate control transistor T211b is electrically connected to the second gate of the second pull-up transistor T21b. By setting the second gate control transistor T211b, the gate of the second gate control transistor T211b is electrically connected to the (2n+1)th signal output terminal, the first electrode of the second gate control transistor T211b is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second gate control transistor T211b is electrically connected to the second gate of the second pull-up transistor T21b, so that when the (2n+1)th signal output terminal outputs a signal, the second gate control transistor can be turned on, so that the low potential power supply terminal VSS outputs a low potential signal to the second gate of the second pull-up transistor T21b, and the second pull-up transistor is turned off.

[0046] In some embodiments, Figure 5 As shown, the gate drive circuit 21 also includes a storage module 215 and an anti-coupling transistor Tq, the storage module 215 is connected to the internal node Q, the gate of the anti-coupling transistor Tq and the first electrode of the anti-coupling transistor Tq are electrically connected to the storage module 215, the second electrode of the anti-coupling transistor Tq is electrically connected to the gate of the first pull-up transistor T21a, and the second electrode of the anti-coupling transistor Tq is electrically connected to the gate of the second pull-up transistor T21b. By setting the anti-coupling transistor, when the first pull-up transistor and the second pull-up transistor are turned off, the storage module can be blocked from discharging the gates of the first pull-up transistor and the second pull-up transistor, so that the first pull-up transistor and the second pull-up transistor can be turned off better.

[0047] Specifically, since the storage module is connected to the internal node, when the internal node outputs a low potential, the storage module may output a potential to the gate of the first pull-up transistor and the gate of the second pull-up transistor, resulting in the first pull-up transistor and the second pull-up transistor being unable to be completely turned off. The embodiment of the present application sets an anti-coupling transistor so that when the storage capacitor outputs a potential to the gate of the first pull-up transistor and the gate of the second pull-up transistor, the anti-coupling transistor can block the potential, thereby preventing the first pull-up transistor and the second pull-up transistor from being turned on, and making the first pull-up transistor and the second pull-up transistor better turned off.

[0048] In some embodiments, Figure 3As shown, the gate drive circuit 21 also includes a pull-down module 213, a pull-down maintaining module 214 and a storage module 215, the pull-down module 213 is electrically connected to the internal node Q, the (2n-1)th signal output terminal G(2n-1) and the 2nth signal output terminal G(2n), and the pull-down maintaining module is electrically connected to the internal node Q, the (2n-1)th signal output terminal G(2n-1) and the 2nth signal output terminal G(2n).

[0049] In some embodiments, Figure 4 , Figure 5 As shown, the pull-up control module 211 includes a pull-up control transistor T11, a gate of the pull-up control transistor T11 and a first electrode of the pull-up control transistor T11 are configured to receive a pull-up control signal, and a second electrode of the pull-up control transistor T11 is electrically connected to the internal node Q.

[0050] Specifically, Figure 4 , Figure 5 As shown, the gate of the pull-up control transistor T11 is connected to the start signal line STV or the (2n-5)th signal output terminal G(2n-5).

[0051] In some embodiments, Figure 4 , Figure 5 As shown, the pull-down module 213 includes a first pull-down transistor T31a, a second pull-down transistor T31b and a third pull-down transistor T41, the gate of the first pull-down transistor T31a is configured to receive a first pull-down control signal, the first electrode of the first pull-down transistor T31a is electrically connected to the low potential power supply terminal VSS, and the second electrode of the first pull-down transistor T31a is electrically connected to the (2n-1)th signal output terminal G(2n-1); the gate of the second pull-down transistor T31b is configured to receive a second pull-down control signal, the first electrode of the second pull-down transistor T31b is electrically connected to the low potential power supply terminal VSS, the second electrode of the second pull-down transistor T31b is electrically connected to the 2nth signal output terminal G(2n), the gate of the third pull-down transistor T41 is configured to receive a third pull-down control signal, the first electrode of the third pull-down transistor T41 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the third pull-down transistor T41 is electrically connected to the internal node Q. By electrically connecting the first pull-down transistor, the second pull-down transistor and the third pull-down transistor to the (2n-1)th signal output terminal G(2n-1), the 2nth signal output terminal G(2n) and the internal node Q respectively, a pull-down module can realize the functions of two pull-down modules in the two-stage gate driving circuit in the current display device, thereby reducing the occupied space of the gate driving circuit.

[0052] Specifically, Figure 4 , Figure 5 As shown, the gate of the first pull-down transistor T31a is connected to the (2n+3)th signal output terminal G(2n+3), the gate of the second pull-down transistor T31b is connected to the (2n+4)th signal output terminal G(2n+4), and the gate of the third pull-down transistor T41 is connected to the (2n+5)th signal output terminal G(2n+5).

[0053] In some embodiments, Figure 4 , Figure 5As shown, the pull-down maintenance module 214 includes a first inverting transistor T51, a second inverting transistor T52, a third inverting transistor T53, a first pull-down maintenance transistor T32a, a second pull-down maintenance transistor T32b and a third pull-down maintenance transistor T42, the gate of the first inverting transistor T51 is electrically connected to the high potential power supply terminal VGH, the first electrode of the first inverting transistor T51 is electrically connected to the high potential power supply terminal VGH; the gate of the second inverting transistor T52 is electrically connected to the internal node Q, the The first electrode of the second inverting transistor T52 is electrically connected to the low potential power supply terminal VSS, the second electrode of the second inverting transistor T52 is electrically connected to the second electrode of the first inverting transistor T51; the gate of the third inverting transistor T53 is electrically connected to the second electrode of the first inverting transistor T51, the first electrode of the third inverting transistor T53 is electrically connected to the high potential power supply terminal VGH, the second electrode of the third inverting transistor T53 is connected to the gate of the first pull-down holding transistor T32a; the gate of the fourth inverting transistor T54 is electrically connected to the internal node Q The first electrode of the fourth inverting transistor T54 is electrically connected to the low potential power supply terminal VSS; the gate of the first pull-down maintaining transistor T32a is electrically connected to the second electrode of the fourth inverting transistor T54; the first electrode of the first pull-down maintaining transistor T32a is electrically connected to the low potential power supply terminal VSS, the second electrode of the first pull-down maintaining transistor T32a is electrically connected to the (2n-1)th signal output terminal G(2n-1); the gate of the second pull-down maintaining transistor T32b is electrically connected to the gate of the fourth inverting transistor T54 The first electrode of the second pull-down sustaining transistor T32b is electrically connected to the low potential power supply terminal VSS, and the second electrode of the second pull-down sustaining transistor T32b is electrically connected to the 2nth signal output terminal G(2n); the gate of the third pull-down sustaining transistor T42 is electrically connected to the second electrode of the fourth inverting transistor T54; the first electrode of the third pull-down sustaining transistor T42 is electrically connected to the low potential power supply terminal VSS, and the second electrode of the third pull-down sustaining transistor T42 is electrically connected to the internal node Q. By making the first pull-down sustaining transistor, the second pull-down sustaining transistor and the third pull-down sustaining transistor electrically connected to the (2n-1)th signal output terminal G(2n-1), the 2nth signal output terminal G(2n) and the internal node Q respectively, a pull-down sustaining module can realize the functions of two pull-down sustaining modules in the two-stage gate driving circuit in the current display device, thereby reducing the occupied space of the gate driving circuit.

[0054] In some embodiments, Figure 4 , Figure 5As shown, the storage module 215 includes a first storage capacitor Cbt1 and a second storage capacitor Cbt2, one plate of the first storage capacitor Cbt1 is electrically connected to the internal node Q, the other plate of the first storage capacitor Cbt1 is electrically connected to the (2n-1)th signal output terminal G(2n-1), one plate of the second storage capacitor Cbt2 is electrically connected to the internal node Q, and the other plate of the second storage capacitor Cbt2 is electrically connected to the 2nth signal output terminal G(2n). By connecting the first storage capacitor to the internal node and the second storage capacitor to the internal node, the potential of the internal node can be increased, so that the (2n-1)th signal output terminal G(2n-1) and the 2nth signal output terminal G(2n) can be output normally.

[0055] Specifically, the above embodiment is described by taking the first electrode of the first gate-controlled transistor T211a being electrically connected to the low potential power supply terminal VSS as an example, but the embodiment of the present application is not limited thereto, and the first electrode of the first gate-controlled transistor T211a can be connected to other low potential signal lines, and the potential of the low potential signal line is lower than the potential of the low potential power supply terminal VSS. It can be understood that, since the internal node Q is still at a high potential when the gate drive circuit is in a state where the first pull-up transistor T21a needs to be turned off and the second pull-up transistor T21b is kept in an on state, then, to turn off the first pull-up transistor T21a, it is necessary to make the potential of the second gate of the first pull-up transistor T21a lower, and then the potential of the low potential signal line connected to the first electrode of the first gate-controlled transistor T211a can be made lower than the potential of the low potential power supply terminal VSS.

[0056] Specifically, the potential of the wiring connected to the first electrode of the first gate-controlled transistor T211a may be lower than the potential of the wiring connected to the first electrode of the second gate-controlled transistor T211b.

[0057] Specifically, the response speed of the first gate-controlled transistor T211a can be made faster than the response speed of the second gate-controlled transistor T211b, so that when the first pull-up transistor needs to be turned off, the speed of turning off the first pull-up transistor can be accelerated. Specifically, the width-to-length ratio of the channel of the first gate-controlled transistor T211a can be made greater than the width-to-length ratio of the channel of the second gate-controlled transistor T211b.

[0058] At the same time, if Figure 6As shown, taking the display panel including 8 clock signal lines as an example, a timing sequence of each signal line of a display panel is provided, and the display panel includes a first clock signal line CK1, a second clock signal line CK2, a third clock signal line CK3, a fourth clock signal line CK4, a fifth clock signal line CK5, a sixth clock signal line CK6, a seventh clock signal line CK7 and an eighth clock signal line CK8. The connection relationship between each clock signal line and the gate drive circuit can refer to the description in the above embodiment. Figure 6 As shown, it can be seen that the first clock signal line CK1 to the eighth clock signal line CK8 output high potential signals in sequence, the low potential power line VSS continuously outputs low potential signals, and the high potential power line VGH outputs high potential signals, so that each signal output end outputs a signal to the scan line in sequence, so that each scan line scans each row of pixel units in sequence, so that the display panel works normally.

[0059] Specifically, the above embodiment uses the effective level of each clock signal line ( Figure 6 In the figure, a high level is taken as an example for the effective level of the clock signal line, but the embodiments of the present application are not limited to this, and the effective level can be a low level) and an overlapping area is taken as an example for explanation. For example, the time when the first clock signal line CK1 outputs a valid level overlaps with the time when the second clock signal line CK2 outputs a valid level, but the embodiments of the present application are not limited to this, and the time when each clock signal line outputs a valid level may not overlap.

[0060] Specifically, the embodiment of the present application is described by taking the transistors in the gate drive circuit as N-type transistors as an example. Accordingly, each transistor is turned on when the gate is at a high input potential, but the embodiment of the present application is not limited to this. Each transistor can be a P-type transistor, or some transistors are N-type transistors and some transistors are P-type transistors.

[0061] Specifically, the transistor in the gate driving circuit may be an oxide semiconductor transistor or a silicon semiconductor transistor, and specifically may be a low-temperature polysilicon thin film transistor or a metal oxide thin film transistor.

[0062] Specifically, when the transistor has only one gate, the gate of the transistor refers to its only gate; when the transistor has two gates, unless otherwise specified, the gate of the transistor refers to its first gate.

[0063] Specifically, the above embodiments provide a detailed description of the display panel from aspects of the circuit, timing, transistor design, etc. of the display panel. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the gate of at least one of the first pull-up transistor and the second pull-up transistor includes a first gate and a second gate, and the display panel also includes a gate control module, and the gate control module is configured to turn off the first pull-up transistor according to a signal of the 2nth signal output terminal, and / or turn off the second pull-up transistor according to a signal of the (2n+1)th signal output terminal; wherein the first gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the internal node, and the second gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the gate control module, and the gate drive circuit also includes a storage module and an anti-coupling transistor, the storage module is connected to the internal node, the gate of the anti-coupling transistor and the first electrode of the anti-coupling transistor are electrically connected to the storage module, the second electrode of the anti-coupling transistor is electrically connected to the gate of the first pull-up transistor, and the second electrode of the anti-coupling transistor is electrically connected to the gate of the second pull-up transistor.

[0064] At the same time, an embodiment of the present application provides a display device, which includes a display panel as described in any of the above embodiments.

[0065] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0066] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0067] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0068] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: The invention comprises a plurality of cascaded gate drive circuits and a plurality of scan lines, each of the gate drive circuits comprising: A pull-up control module electrically connected to the internal node; A pull-up module, electrically connected to the internal node, the pull-up module comprising a first pull-up module and a second pull-up module; Wherein, the gate driving circuit of the nth level includes a (2n-1)th signal output terminal and a 2nth signal output terminal, the (2n-1)th signal output terminal is electrically connected to the (2n-1)th scan line, the 2nth signal output terminal is electrically connected to the 2nth scan line, the first pull-up module is electrically connected between the (2n-1)th clock signal line and the (2n-1)th signal output terminal, and the second pull-up module is electrically connected between the 2nth clock signal line and the 2nth signal output terminal; n is greater than or equal to 1, and n is a positive integer.

2. The display panel according to claim 1, characterized in that: The first pull-up module comprises a first pull-up transistor, a first electrode of the first pull-up transistor is electrically connected to the (2n-1)th clock signal line, and a second electrode of the first pull-up transistor is electrically connected to the (2n-1)th signal output terminal; The second pull-up module includes a second pull-up transistor, a first electrode of the second pull-up transistor is electrically connected to the 2nth clock signal line, and a second electrode of the second pull-up transistor is electrically connected to the 2nth signal output terminal.

3. The display panel according to claim 2, characterized in that: The gate of at least one of the first pull-up transistor and the second pull-up transistor includes a first gate and a second gate, and the display panel also includes a gate control module, and the gate control module is configured to turn off the first pull-up transistor according to a signal of a 2nth signal output terminal, and / or turn off the second pull-up transistor according to a signal of a (2n+1)th signal output terminal.

4. The display panel according to claim 3, characterized in that: A first gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the internal node, and a second gate of at least one of the first pull-up transistor and the second pull-up transistor is electrically connected to the gate control module.

5. The display panel according to claim 4, characterized in that: The gates of the first pull-up transistor and the second pull-up transistor each include a first gate and a second gate, and the gate control module includes a first gate control module and a second gate control module; Wherein, the first gate of the first pull-up transistor is electrically connected to the internal node, and the second gate of the first pull-up transistor is electrically connected to the first gate control module; The first gate of the second pull-up transistor is electrically connected to the internal node, and the second gate of the second pull-up transistor is electrically connected to the second gate control module.

6. The display panel according to claim 5, characterized in that: The first gate control module includes a first gate control transistor, a gate of the first gate control transistor is electrically connected to the 2nth signal output terminal, a first electrode of the first gate control transistor is electrically connected to the low potential power supply terminal, and a second electrode of the first gate control transistor is electrically connected to the second gate of the first pull-up transistor.

7. The display panel according to claim 5, characterized in that: The second gate-controlled module includes a second gate-controlled transistor, the gate of the second gate-controlled transistor is electrically connected to the (2n+1)th signal output terminal, the first electrode of the second gate-controlled transistor is electrically connected to the low potential power supply terminal, and the second electrode of the second gate-controlled transistor is electrically connected to the second gate of the second pull-up transistor.

8. The display panel according to any one of claims 1 to 7, characterized in that: The gate drive circuit also includes a storage module and an anti-coupling transistor, the storage module is connected to the internal node, the gate of the anti-coupling transistor and the first electrode of the anti-coupling transistor are electrically connected to the storage module, the second electrode of the anti-coupling transistor is electrically connected to the gate of the first pull-up transistor, and the second electrode of the anti-coupling transistor is electrically connected to the gate of the second pull-up transistor.

9. The display panel according to any one of claims 1 to 7, characterized in that: The gate drive circuit further includes: A pull-down module, electrically connected to the internal node, the (2n-1)th signal output terminal and the 2nth signal output terminal; A pull-down maintaining module, electrically connected to the internal node, the (2n-1)th signal output terminal and the 2nth signal output terminal; A storage module, comprising a first storage capacitor and a second storage capacitor, wherein one plate of the first storage capacitor is electrically connected to the internal node, the other plate of the first storage capacitor is electrically connected to the (2n-1)th signal output terminal, one plate of the second storage capacitor is electrically connected to the internal node, and the other plate of the second storage capacitor is electrically connected to the 2nth signal output terminal.

10. A display device, characterized in that: Comprising the display panel as claimed in any one of claims 1 to 9.

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