Gate driving circuit, driving method thereof and display device

Abstract

The invention provides a gate driving circuit, a driving method thereof and a display device, and relates to the technical field of display, and the gate driving circuit comprises a plurality of cascaded shift register units; the shift register unit comprises a scanning input module, a first node and a first node reset module. The output end of the delay circuit is connected to the first node; the time-delay circuit is configured in a way that when the reset input end has no signal, the output end of the time-delay circuit outputs a signal which is the same as the effective pulse of the first node reset control signal to the first node. According to the shift register unit, the delay circuit is arranged in the shift register unit, is connected to the first node and is used for outputting the signal which is the same as the effective pulse of the reset control signal of the first node to the first node when the reset input end has no signal, so that the potential of the first node jumps to the normal potential, and the corresponding shift register unit can work normally; therefore, the performance of the gate drive circuit is improved, and the display effect of the display device is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a gate driving circuit and a driving method thereof, and a display device. Background Art

[0002] With the development of the display field, all walks of life have higher and higher requirements for display effects and functions. In some display devices, different display areas have different driving frequencies. Due to the different frequencies of different display areas, some devices may not work properly in the boundary area, affecting product performance and display effects.

[0003] Therefore, how to improve the above problems has become one of the technical issues that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a gate driving circuit and a driving method thereof, and a display device, so as to improve the performance and display effect of a display panel.

[0005] In a first aspect, the present disclosure provides a gate driving circuit, comprising:

[0006] A plurality of cascaded shift register units;

[0007] The shift register unit includes a scan input module, a scan input terminal, a first node, a first node reset module and a reset input terminal;

[0008] The control end of the scan input module is connected to the scan input end, the first end is connected to the scan control signal, and the second end is connected to the first node; the scan input module is used to charge the first node according to the signal of the scan input end; the control end of the first node reset module is connected to the reset input end, the first end is connected to the first node reset control signal, and the second end is connected to the first node; the first node reset module is used to reset the first node according to the signal of the reset input end;

[0009] At least part of the shift register units include a delay circuit, and an output end of the delay circuit is connected to the first node;

[0010] The delay circuit is configured such that, when there is no signal at the reset input terminal, the output terminal of the delay circuit outputs a signal identical to a valid pulse of the first node reset control signal to the first node.

[0011] In a second aspect, the present disclosure provides a driving method of a gate driving circuit, for driving the gate driving circuit as described above, the driving method comprising: at least one frame of working time, including a delay circuit startup phase;

[0012] During the start-up phase of the delay circuit, the output end of the delay circuit outputs a signal identical to a valid pulse of a first node reset control signal to the first node.

[0013] In a third aspect, the present disclosure provides a display device, comprising the gate driving circuit as described above.

[0014] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0015] The present disclosure provides a gate driving circuit and a driving method thereof, and a display device, wherein the gate driving circuit includes a plurality of cascaded shift register units; the shift register unit includes a scan input module, a scan input terminal, a first node, a first node reset module and a reset input terminal; the control terminal of the first node reset module is connected to the reset input terminal, the first terminal is connected to the first node reset control signal, and the second terminal is connected to the first node; the first node reset module is used to reset the first node according to the signal of the reset input terminal; at least part of the shift register units include a delay circuit, and the output terminal of the delay circuit is connected to the first node; the delay circuit is configured such that when there is no signal at the reset input terminal, the output terminal of the delay circuit outputs a signal identical to the valid pulse of the first node reset control signal to the first node. The present invention provides a delay circuit in a shift register unit, wherein the delay circuit is connected to a first node and is used to output a signal identical to a valid pulse of a reset control signal of the first node to the first node when there is no signal at a reset input terminal, so that the potential of the first node jumps to a normal potential, the first node is reset, and the potential of the first node is stabilized. A device operating under the potential control of the first node can be normally shut down, and a corresponding shift register unit can operate normally, which is beneficial to improving the characteristic drift phenomenon of the shift register unit, thereby stabilizing the performance of each stage of the shift register unit in the gate drive circuit, which is beneficial to improving the performance of the gate drive circuit and improving the display effect of the display device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0017] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0018] Figure 1 Shown is a schematic diagram of a display device in the prior art;

[0019] Figure 2Shown is a schematic diagram of a display device provided by an embodiment of the present disclosure;

[0020] Figure 3 FIG. 1 is a schematic diagram of a module of a shift register unit provided by an embodiment of the present disclosure;

[0021] Figure 4 Shown is a module schematic diagram of a delay circuit provided by an embodiment of the present disclosure;

[0022] Figure 5 FIG. 1 is a schematic diagram of a delay circuit provided by an embodiment of the present disclosure;

[0023] Figure 6 Shown Figure 5 A timing diagram of the delay circuit provided;

[0024] Figure 7 FIG. 1 is a schematic diagram of a shift register unit provided by an embodiment of the present disclosure;

[0025] Figure 8 Shown Figure 7 A timing diagram of the shift register unit in . DETAILED DESCRIPTION

[0026] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0027] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0028] The inventors have found in their research that in some display devices, different display areas have different driving frequencies. For example, Figure 1 FIG. 1 is a schematic diagram of a display device in the prior art. Please refer to FIG. Figure 1The display device 000 includes a first display area AA1' and a second display area AA2'. The first display area AA1' plays a video. The first display area AA1' is driven at a high frequency. The second display area AA2' has no video and plays a static image. The second display area AA2' is driven at a low frequency to save power consumption. The gate driving circuit of the display device 000 scans the pixels in the display device 000 along a first direction D1'. The driving frequency of the first display area AA1' is greater than the driving frequency of the second display area AA2'. In the boundary area between the first display area AA1' and the second display area AA2', some devices in the gate driving circuit cannot receive the shutdown signal, which causes the voltage of some devices to be uncontrolled, resulting in temperature increase, and then causing characteristic drift, affecting the performance and display effect of the display device 000.

[0029] Therefore, how to improve the above problems has become one of the technical issues that need to be solved urgently at this stage.

[0030] In order to solve the above technical problems, the present disclosure provides a gate driving circuit and a driving method thereof, and a display device, so as to improve the performance and display effect of a display panel.

[0031] Figure 2 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 3 FIG. 1 is a schematic diagram of a module of a shift register unit provided by an embodiment of the present disclosure. Figure 2 and Figure 3 The present disclosure provides a gate driving circuit 200, comprising: a plurality of cascaded shift register units 210; the shift register unit 210 comprises a scan input module 211, a scan input terminal Gn-1, a first node P, a first node reset module 212 and a reset input terminal Gn+1; the control terminal of the scan input module 211 is connected to the scan input terminal Gn-1, the first terminal is connected to the scan control signal FW, and the second terminal is connected to the first node P; the scan input module 211 is used to charge the first node P according to the signal of the scan input terminal Gn-1; the control terminal of the first node reset module 212 .... The control terminal is connected to the reset input terminal Gn+1, the first terminal is connected to the first node reset control signal BW, and the second terminal is connected to the first node P; the first node reset module 212 is used to reset the first node P according to the signal of the reset input terminal Gn+1; at least part of the shift register unit 210 includes a delay circuit 213, and the output terminal of the delay circuit 213 is connected to the first node P; the delay circuit 213 is configured such that when there is no signal at the reset input terminal Gn+1, the output terminal of the delay circuit 213 outputs a signal identical to the valid pulse of the first node reset control signal BW to the first node P.

[0032] Specifically, the present disclosure provides a gate driving circuit 200, which includes a plurality of shift register units 210, which are cascaded. The shift register unit 210 includes a scan input module 211, a first node P, and a first node reset module 212. The scan input module 211 is connected to a scan input terminal Gn-1, a scan control signal FW, and a first node P. Under the control of the scan input terminal Gn-1, the scan input module 211 transmits the scan control signal FW to the first node P, wherein the scan input terminal Gn-1 of the first-stage shift register unit is provided by other driving signals (e.g., a start signal STV), and the scan input terminals Gn-1 of the shift register units of other stages except the first stage are connected to the output signal of the shift register unit 210 of the previous stage. The first node reset module 212 is connected to the reset input terminal Gn+1, the first node reset control signal BW and the first node P. Under the control of the reset input terminal Gn+1, the first node reset module 212 transmits the first node reset control signal BW to the first node P, wherein the reset input terminal Gn+1 is connected to the output signal of the next-stage shift register unit 210.

[0033] It should be noted that the scanning control signal FW and the first node reset control signal BW control the scanning direction of the gate drive circuit 200, and the scanning direction includes forward scanning and reverse scanning. Exemplarily, the gate drive circuit 200 includes n-level gate drive units (n≥2, and n is an integer), and the forward scanning is to turn on one by one from the first level to the nth level; the reverse scanning is to turn on one by one from the nth level to the first level. Optionally, during forward scanning, the scanning control signal FW is connected to a high-level signal, and the first node reset control signal BW is connected to a low-level signal; during reverse scanning, the scanning control signal FW is connected to a low-level signal, and the first node reset control signal BW is connected to a high-level signal. The present disclosure is only described by taking this as an example, and is not limited thereto.

[0034] The inventors found in the research that when the driving frequencies of the two adjacent cascaded shift register units 210 are the same, the devices in the shift register unit 210 can work normally. When the driving frequencies of the two adjacent cascaded shift register units 210 are different, the control end of the first node reset module 212 may not receive a valid signal, that is, there is no signal input to the reset input end Gn+1, then the first node reset module 212 cannot be turned off, resulting in the first node P voltage cannot be reset, the first node P voltage is unstable, and then the shift register unit 210 characteristic drift. It should be noted that the shift register unit 210 characteristic drift refers to the phenomenon that the performance parameters of the shift register unit 210 deviate from the initial design value.

[0035] The characteristic drift of the shift register unit 210 will affect the performance and display effect of the display device 100. Therefore, the present disclosure sets a delay circuit 213 in the shift register unit 210, and the delay circuit 213 is connected to the first node P, and the delay circuit 213 is connected to the reset input terminal Gn+1, and is used to output a signal identical to the valid pulse of the first node reset control signal BW to the first node P when there is no signal at the reset input terminal Gn+1, so that the potential of the first node P jumps to a normal potential, resets the first node P, stabilizes the potential of the first node P, and the device working under the potential control of the first node P can be normally turned off, and the corresponding shift register unit 210 can work normally, which is conducive to improving the characteristic drift phenomenon of the shift register unit 210, thereby stabilizing the performance of each stage of the shift register unit 210 in the gate drive circuit, which is conducive to improving the performance of the gate drive circuit 200 and improving the display effect of the display device 100.

[0036] Please refer to Figure 2 and Figure 3 In an optional embodiment of the present disclosure, the display device 100 includes a first display area AA1 and a second display area AA2. The display device 100 is scanned along a first direction D1. The frequency of the first display area AA1 is greater than the frequency of the second display area AA2. In the boundary area between the first display area AA1 and the second display area AA2, when there is no signal at the reset input terminal Gn+1, the first node reset module 212 cannot reset the potential of the first node P. The delay circuit 213 provided in the present disclosure outputs a signal identical to the valid pulse of the first node reset control signal BW to the first node P when there is no signal at the reset input terminal Gn+1, so that the potential of the first node P jumps to a normal potential, and the corresponding shift register unit 210 can work normally, which is beneficial to improving the performance of the gate drive circuit 200 and improving the display effect of the display device 100.

[0037] Please continue to refer to Figure 2 and Figure 3 In another optional embodiment of the present disclosure, the display device 100 scans along the second direction D2, the frequency of the first display area AA1 is greater than the frequency of the second display area AA2, and in the boundary area between the first display area AA1 and the second display area AA2, the reset input terminal Gn+1 signal of the shift register unit 210 is normal, and the delay circuit 213 has no output.

[0038] Figure 4 FIG. 1 is a schematic diagram of a module of a delay circuit provided by an embodiment of the present disclosure. Please refer to FIG. Figure 2 to Figure 4Optionally, the delay circuit 213 includes a working control module 2131, a charging control module 2132, a delay module 2133, a delay pull-down control module 2134, a delay pull-down module 2135, a delay reset module 2136, a first delay node Y1 and a second delay node Y2; the control end of the working control module 2131 is connected to the reset input end Gn+1, the first end is connected to the first level signal VGL, and the second end is connected to the first delay node Y1; the control end of the charging control module 2132 is connected to the scan input end Gn-1, the first end is connected to the second level signal VGH, the second end is connected to the first end of the delay module 2133, and the second end of the delay module 2133 is connected to the first delay node Y1; the delay pull-down control module 2134 includes The first submodule 21341 and the second submodule 21342, the control end of the first submodule 21341 is connected to the first delay node Y1, the first end is connected to the second level signal VGH, and the second end is connected to the second delay node Y2; the control end of the second submodule 21342 is connected to the second level signal VGH, the first end is connected to the first level signal VGL, and the second end is connected to the second delay node Y2; the control end of the delay pull-down module 2135 is connected to the second delay node Y2, the first end is connected to the first level signal VGL, and the second end is connected to the output end Pout of the delay circuit 213; the control end of the delay reset module 2136 is connected to the delay reset control signal RST, the first end is connected to the first level signal VGL, and the second end is connected to the first delay node Y1.

[0039] Specifically, the present disclosure provides a gate drive circuit 200, which includes a plurality of cascaded shift register units 210, and at least some of the shift register units 210 include a delay circuit 213. In the delay circuit 213, the working control module 2131 is used to transmit the first level signal VGL to the first delay node Y1 according to the signal of the reset input terminal Gn+1. The signal of the first delay node Y1 determines whether to output a valid signal to the output terminal Pout. Therefore, the working control module 2131 is a module that actually determines whether the delay circuit 213 works. The charging control module 2132 is used to transmit the second level signal VGH to the delay module 2133 under the control of the scan input terminal Gn-1. When the charging control module 2132 is turned on, the second level signal VGH is transmitted to the delay module 2133 to charge the delay module 2133. The delay pull-down control module 2134 includes a first submodule 21341 and a second submodule 21342. The first submodule 21341 transmits the second level signal VGH to the second delay node Y2 under the control of the first delay node Y1; the second submodule 21342 transmits the first level signal VGL to the second delay node Y1 under the control of the second level signal VGH. The first submodule 21341 and the second submodule 21342 mutually clamp the signal of the second delay node Y1, and the second delay node Y2 controls the conduction and closing of the delay pull-down module 2135. The delay pull-down module 2135 is in the closed state by default. Therefore, the second submodule 21342 is in the normally open state, and transmits the signal of controlling the delay pull-down module 2135 to close to the second delay node Y2. When the first submodule 21341 is turned on, the signal of controlling the delay pull-down module 2135 to turn on is transmitted to the second delay node Y2. The delay reset module 2136 is used for transmitting the first level signal VGL to the first delay node Y1 to reset the delay circuit 213 under the control of the delay reset control signal RST.

[0040] Optionally, the first level signal VGL may be a low level signal, and the second level signal VGH may be a high level signal. It should be noted that the present disclosure is only described by taking this as an example, and is not limited thereto.

[0041] Figure 5 FIG. 1 is a schematic diagram of a delay circuit provided by an embodiment of the present disclosure, referring to FIG. Figure 2 to Figure 5, further, the present disclosure provides an optional implementation mode, the working control module 2131 includes a working control transistor Ma, the gate of the working control transistor Ma is connected to the reset input terminal Gn+1, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the first delay node Y1; the charging control module 2132 includes a charging control transistor Mb, the gate of the charging control transistor Mb is connected to the scan input terminal Gn-1, the first electrode is connected to the second level signal VGH, and the second electrode is connected to the delay module 2133; the delay module 2133 includes a first capacitor C1 and a first resistor R1, the first electrode plate of the first capacitor C1 is connected to the second electrode of the charging control transistor Mb, and the second electrode plate is connected to the first delay node Y1; the first electrode of the first resistor R1 is connected to the first capacitor C1 The first electrode plate and the second electrode plate of the first capacitor C1; the delay pull-down control module 2134 includes a first delay pull-down control transistor Mc and a second delay pull-down control transistor Md, the gate of the first delay pull-down control transistor Mc is connected to the first delay node Y1, the first electrode is connected to the second level signal VGH, and the second electrode is connected to the second delay node Y2; the gate of the second delay pull-down control transistor Md is connected to the second level signal VGH, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the second delay node Y2; the delay pull-down module 2135 includes a delay pull-down transistor Me, the gate of the delay pull-down transistor Me is connected to the second delay node Y2, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the output end Pout of the delay circuit 213.

[0042] Specifically, this embodiment provides a more specific implementation of the delay circuit 213, the working control module 2131 includes a working control transistor Ma, the charging control module 2132 includes a charging control transistor Mb, the delay module 2133 includes a first capacitor C1 and a first resistor R1, the delay pull-down control module 2134 includes a first delay pull-down control transistor Mc and a second delay pull-down control transistor Md, the delay pull-down module 2135 includes a delay pull-down transistor Me, and the delay reset module 2136 includes a delay reset transistor Mf. The working control transistor Ma transmits the first level signal VGL to the first delay node Y1 under the control of the reset input terminal Gn+1, the charging control transistor Mb charges the delay module 2133 under the control of the scan input terminal Gn-1, the first delay pull-down control transistor Mc transmits the second level signal VGH to the second delay node Y2 under the control of the first delay node Y1, the second delay pull-down control transistor Md transmits the first level signal VGL to the second delay node Y2 under the control of the second level signal VGH, and the delay pull-down transistor Me transmits the first level signal VGL to the output terminal Pout of the delay circuit 213 under the control of the potential of the second delay node Y2.

[0043] It should be noted that the present disclosure uses the example that all transistors in the delay circuit 213 are N-type transistors for explanation, but is not limited to this. In some other embodiments of the present disclosure, at least one transistor in the delay circuit 213 may also be a P-type transistor. Figure 6 Shown Figure 5 For the timing diagram of the delay circuit provided, please refer to Figure 5 and Figure 6 , the present disclosure is directed to Figure 5 The delay circuit in Figure 6 The timing diagram in the figure illustrates the working principle and timing of the delay circuit 213. Specifically, the working period of the delay circuit 213 includes the first period S1, the second period S2 and the third period S3. In the first period S1, the reset input terminal Gn+1 signal is normally output, and the reset output terminal Gn+1 corresponding to each level of the shift register unit 211 can receive a valid signal. The gate of the working control transistor Ma can continuously receive a high-level signal, the working control transistor Ma is turned on, and the delay circuit 213 has no effect. Figure 6 In the timing range shown, after the first period S1, there is no valid signal at the reset input terminal Gn+1, and in the second period S2, the scan input terminal Gn-1 outputs a high level signal, the gate of the charge control transistor Mb receives the high level signal, the charge control transistor Mb is turned on, and the first capacitor C1 is charged. In the third period S3, the scan input terminal Gn-1 outputs a low level signal, the reset input terminal Gn+1 has no valid signal, the first capacitor C1 is discharged, the first delay pull-down control transistor Mc is turned on, the second level signal VGH is transmitted to the gate of the delay pull-down transistor Me, the delay pull-down transistor Me is turned on, and the first level signal VGL is transmitted to the output end of the delay circuit 213 through the delay pull-down transistor.

[0044] It should be noted that the delay circuit 213 provided in the above embodiment pulls down the potential of the first node P at a corresponding time when there is no input signal at the reset input terminal Gn+1, which is beneficial to the normal operation of the gate driving circuit 200 and improves the performance and display effect of the display device 100.

[0045] Please refer to Figure 6 Optionally, the width-to-length ratio of the working control transistor Ma is Ra, the width-to-length ratio of the first delay pull-down control transistor Mc is Rc, and Ra≥2Rc.

[0046] Specifically, the working control transistor Ma is the transistor that first determines whether the delay circuit 213 outputs a valid signal. The gate of the working control transistor Ma is connected to the reset input terminal Gn+1, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the first delay node Y1. The gate of the first delay pull-down control transistor Mc controls whether the delay pull-down transistor Me outputs a valid signal to the output terminal Pout under the control of the voltage of the first delay node Y1. Therefore, the working control transistor Ma is an important transistor that controls whether the entire delay circuit 213 works. When the reset input terminal Gn+1 signal is normal, the working control transistor Ma is turned on and outputs the first level signal VGL to the first delay node Y1. The first level signal VGL controls the first delay pull-down transistor Mc to be turned off. At this time, the delay circuit 213 does not work. Therefore, in order not to affect the normal operation of the shift register unit 210, the present disclosure sets the width-to-length ratio Ra of the working control transistor Ma to be greater than or equal to 2 times the width-to-length ratio Rc of the first delay pull-down control transistor Mc. In this way, the voltage required for the working control transistor Ma to turn on is relatively small. When the reset input terminal Gn+1 signal is normal, the working control transistor Ma can be turned on, and the delay circuit 213 does not need to work, which is conducive to avoiding the first delay pull-down control transistor Mc from being mis-turned on, thereby ensuring the normal operation of the shift register unit 210 and improving the reliability of the display device 100. The present disclosure provides an optional implementation method, Ra=2Rc; the present disclosure provides another optional implementation method, Ra=2.5Rc; the present disclosure provides another optional implementation method, Ra=3Rc.

[0047] It should be noted that the width-to-length ratio (W / L) of a transistor refers to the ratio of the channel width (W) to the channel length (L) of the transistor. The larger the width-to-length ratio of the transistor, the wider the channel width of the transistor, and the greater the current that can pass under the same gate voltage, that is, the stronger the current driving capability, thereby achieving faster switching speeds and higher signal transmission efficiency. At the same time, the width-to-length ratio will also affect the threshold voltage of the transistor. When the width-to-length ratio is large, the wide channel makes the electric field distribution between the source and the drain more uniform, and electrons are more easily injected from the source into the channel, so that the voltage required to turn on the transistor is smaller.

[0048] Please continue to refer to Figure 6 Optionally, the width-to-length ratio of the first delay pull-down control transistor Mc is Rc, the width-to-length ratio of the second delay pull-down control transistor Md is Rd, and Rc≥2Rd.

[0049] Specifically, the delay pull-down control module 2134 includes a first delay pull-down control transistor Mc and a second delay pull-down control transistor Md. The first delay pull-down control transistor Mc is used to transmit a signal for turning on the delay pull-down transistor Me to the second delay node Y2, and the second delay pull-down transistor Md is used to transmit a signal for turning off the delay pull-down transistor Me to the second delay node Y2. In order to ensure that the delayed pull-down transistor Me can be turned on normally, the width-to-length ratio Rc of the first delayed pull-down control transistor Mc is set to be less than or equal to 2 times the width-to-length ratio Rd of the second delayed pull-down control transistor Md. In this way, the turn-on voltage of the first delayed pull-down control transistor Mc is less than the turn-on voltage of the second delayed pull-down control transistor Md, and the signal transmission efficiency of the first delayed pull-down control transistor Mc is also stronger, which is conducive to adjusting the potential of the second delay node Y2 to a degree that can turn on the delayed pull-down transistor Me, better ensuring the function of the delay circuit 213, and further facilitating the improvement of the characteristic drift of the shift register unit 210, thereby facilitating the improvement of the performance and display effect of the display device 100. The present disclosure provides an optional implementation method, Rc=2Rd; the present disclosure provides another optional implementation method, Rc=3Rd; the present disclosure provides another optional implementation method, Rc=3.2Rd.

[0050] Please refer to Figure 2 and Figure 3 In an optional implementation of the present disclosure, each shift register unit 210 includes a delay circuit 213 .

[0051] Specifically, the present disclosure provides a use scenario of a delay circuit 213, in which, when the gate driving circuit 200 provides signals to the shift register unit 210 step by step, the driving signal switches from high frequency to low frequency, and in the boundary area, the reset input terminal Gn+1 of some shift register units 210 will have no signal, and the delay circuit 213 is used to output a signal identical to the valid pulse of the first node reset control signal BW to the first node P when there is no signal at the reset input terminal Gn+1. In this embodiment, a delay circuit 213 is provided in each shift register unit 210, so that the switching from high frequency to low frequency can be realized at any position of the display device 100, not limited to a partial area.

[0052] Figure 7 FIG. 1 is a schematic diagram of a shift register unit provided in an embodiment of the present disclosure. Please refer to FIG. Figure 2 , Figure 3 and Figure 7Optionally, the shift register unit 210 also includes a scan output module 30, a pull-down module 40, a pull-down control module 50, a pull-up module 60 and a second node Q; the control end of the scan output module 30 is connected to the first node P, the first end is connected to the first clock signal CK, and the second end is connected to the scan output end Gout; the scan output module 30 is used to transmit the first clock signal CK to the scan output end Gout according to the potential of the first node P; the pull-down module 40 is respectively connected to the first node P, the second node Q, the first level signal VGL and the scan output end Gout; the pull-down module 40 is used to transmit the first level signal VGL to the first node P and the scan output end Gout according to the potential of the second node Q; the pull-down control module 50 is respectively connected to the second node Q and the second level signal VGH; the pull-down control module 50 is used to transmit the second level signal VGH to the second node Q; the pull-up module 60 is respectively connected to the first node P, the second node Q, the first level signal VGL and the pull-down control module 50, and is used to transmit the first level signal VGL to the second node Q.

[0053] Specifically, the shift register unit 210 includes a scan input module 211, a scan output module 30, a first node P, a first node reset module 212, a pull-down module 40, a pull-down control module 50, a pull-up module 60 and a second node Q. The scan input module 211 is electrically connected to the scan input terminal Gn-1, the scan control signal FW and the first node P, respectively, and is used to charge the first node P according to the signal of the scan input terminal Gn-1. The scan output terminal Gout is electrically connected to the first node P, the first clock signal CK and the scan output terminal Gout, respectively, and is used to control the first clock signal CK to be output to the scan output terminal Gout according to the potential of the first node P. The pull-down module 40 is electrically connected to the first node P, the second node Q, the first level signal VGL and the scan output terminal Gout, respectively, and is used to control the first level signal VGL to be transmitted to the first node P and the scan output terminal Gout according to the potential of the second node Q. The pull-down control module 50 is electrically connected to the second node Q and the second level signal VGH, respectively, and is used to control the second level signal VGH to be transmitted to the second node Q. The pull-up module 60 is connected to the first node P, the second node Q, the first level signal VGL and the pull-down control module 50 respectively, and is used to transmit the first level signal VGL to the second node Q.

[0054] When the input signal received by the scan input terminal Gn-1 is an enable signal that can turn on the scan input module 211, the scan input module 211 charges the first node P according to the scan control signal FW, so that the potential of the first node P can control the scan output module 30 to turn on, so that the scan output module 30 can transmit the first clock signal CK to the scan output terminal Gout. When the first clock signal CK is an enable level, the scan signal output by the scan output terminal Gout is an enable level; when the first clock signal CK is a non-enable level, the scan signal output by the scan output terminal Gout is a non-enable level. When the first node P controls the scan output module 30 to turn on, it also controls the pull-up module 60 to turn on, so that the pull-up module 60 transmits the first level signal VGL to the second node Q, and the non-enable level of the second node Q controls the pull-down module 40 to turn off, so that the first level signal VGL will not be transmitted to the first node P through the pull-down module 40, so as not to affect the output of the scan signal by the scan output module 30. When the first node P needs to be discharged, the pull-down control module 50 transmits the second level signal VGH to the second node Q, so that the potential of the second node Q can control the pull-down module 40 to be turned on, and the pull-down module 40 transmits the first level signal VGL to the first node P, thereby realizing the discharge of the first node P. The shift register unit 210 also includes a first node reset module 212, the control end of the first node reset module 212 is connected to the reset input end Gn+1, and the reset input end Gn+1 is connected to the scan output end Gout of the next stage shift register unit 210. When the next stage shift register unit 210 outputs an enable signal, the first node P is reset, thereby stabilizing the potential of the first node P.

[0055] In some cases, when the reset input terminal Gn+1 cannot output a signal normally, the potential of the first node P will be unstable, causing the characteristic drift of the shift register unit 210, affecting the performance and display effect of the display device 100. Therefore, the present disclosure sets a delay circuit 213, which outputs a signal identical to the valid pulse of the first node reset control signal BW to the first node P when there is no signal at the reset input terminal Gn+1, so that the potential of the first node P jumps to a normal potential, and the corresponding shift register unit 210 can work normally, which is beneficial to improving the performance of the gate driving circuit 200 and improving the display effect of the display device 100.

[0056] Please continue to refer to Figure 2 , Figure 3 and Figure 7The present disclosure provides an optional implementation mode, wherein the scan input module 211 includes a first transistor M1, the gate of the first transistor M1 is connected to the scan input terminal Gn-1, the first electrode is connected to the scan control signal FW, and the second electrode is connected to the first node P; the first node reset module 212 includes a second transistor M2, the gate of the second transistor M2 is connected to the reset input terminal Gn+1, the first electrode is connected to the reset control signal BW, and the second electrode is connected to the first node P; the scan output terminal Gout includes a third transistor M3 and a storage capacitor Cst, the gate of the third transistor M3 is connected to the first node P, the first electrode is connected to the first clock signal CK, and the second electrode is connected to the scan output terminal Gout; the storage capacitor Cst is connected between the gate of the third transistor M3 and the second electrode; the pull-down module 40 includes a fourth transistor M4 and a fifth transistor M5, the gate of the fourth transistor M4 is connected to the second node Q, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the first node P; the gate of the fifth transistor M5 is connected to the second node Q, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the scan output terminal Gout; the pull-down control module 50 includes a sixth transistor M6 and a seventh transistor M7, the gate and the first electrode of the sixth transistor M6 are connected to the second level signal VGH, the second electrode is connected to the gate of the seventh transistor M7, the first electrode of the seventh transistor M7 is connected to the second level signal VGH, and the second electrode is connected to the second node Q; the pull-up module 60 includes an eighth transistor M8 and a ninth transistor M9, the gate of the eighth transistor M8 is connected to the first node P, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the second node Q; the gate of the ninth transistor M9 is connected to the first node P, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the pull-down control module 50.

[0057] Specifically, the structure of the shift register unit 210 is further refined in this embodiment, such as Figure 7 As shown, the scan input module 211 includes a first transistor M1, the first node reset module 212 includes a second transistor M2, the scan output terminal Gout includes a third transistor M3 and a storage capacitor Cst, the pull-down module 40 includes a fourth transistor M4 and a fifth transistor M5, the pull-down control module 50 includes a sixth transistor M6 and a seventh transistor M7, and the pull-up module 60 includes an eighth transistor M8 and a ninth transistor M9. It should be noted that the embodiment of the present disclosure is only described by taking the transistors in the shift register unit 210 as N-type transistors as an example, and is not limited thereto. Figure 8 Shown Figure 7 For a timing diagram of the shift register unit in Figure 7 Combined with Figure 8 , the working process of the shift register unit 210 is as follows:

[0058] In the t1 stage, the scan signal output by the scan output terminal Gout of the previous stage shift register unit 210 received by the scan input terminal Gn-1 is high level, so that the first transistor M1 is turned on, and the high level of the scan control signal FW is transmitted to the first node P, so that the first node P is high level, the eighth transistor M8 and the ninth transistor M9 are turned on, the first level signal VGL is transmitted to the second node Q via the eighth transistor M8, and is transmitted to the gate of the seventh transistor M7 via the ninth transistor M9, the seventh transistor M7, the fourth transistor M4 and the fifth transistor M5 are turned off, the third transistor M3 is turned on, the signal of the first clock signal CK is low level, and the first clock signal CK is transmitted to the scan output terminal Gout, so that the scan output terminal Gout outputs a low level scan signal.

[0059] In stage t2, the scan signal output by the scan output terminal Gout of the previous level scan shift register unit 210 received by the scan input terminal Gn-1 is low level, the first clock signal CK is high level, and the first node P still maintains the high level of stage t1 due to no low level signal input, the third transistor M3, the eighth transistor M8 and the ninth transistor M9 remain on, and under the control of the eighth transistor M8, the first level signal VGL is input to the second node Q, and the second node Q is low level; since the first clock signal CK is high level, the high level first clock signal CK is transmitted to the scan output terminal Gout through the third transistor M3, so that the scan output terminal Gout outputs a high level scan signal; due to the bootstrap effect of the storage capacitor Cst, the potential of the first node P is further increased.

[0060] In the t3 stage, the scan signal output by the scan output terminal Gout of the next-level scan shift register unit 210 received by the reset input terminal Gn+1 is high, the first clock signal CK is low, the second transistor M2 is turned on, and the low level of the first node reset control signal BW is written to the first node P, so that the first node P becomes a low level, the third transistor M3, the eighth transistor M8 and the ninth transistor M9 are turned off, and the seventh transistor M7 is turned on under the control of the second level signal VGH transmitted by the sixth transistor M6, so that the second level signal VGH is transmitted to the second node Q through the seventh transistor M7, thereby controlling the fourth transistor M4 and the fifth transistor M5 to be turned on, so that the first level signal VGL is transmitted to the first node P and the scan output terminal Gout, and the scan output terminal Gout stably outputs a low-level scan signal.

[0061] After stage t3, since the scan control signal FW is always at a high level, and the first node P and the scan output terminal Gout have been discharged through the second transistor M2 in stage t2, the eighth transistor M8 is in a closed state at this time, so the second node Q will not be discharged, and the scan output terminal Gout can stably output a low-level scan signal until entering the non-scanning stage of the scan cycle.

[0062] In the t3 stage, if the reset input terminal Gn+1 cannot receive the first node reset control signal BW, the potential of the first node P will not be able to be reduced, so that at the beginning of the scanning phase of the next scanning cycle, the potential of the first node P is no longer its original initial potential, but the potential after drifting. This makes the initial potential when charging the first node P become the potential after drifting. Under the premise of a certain charging time, charging starts with the potential of the first node P after drifting. After charging is completed, the potential of the first node P is different from that of the first node P. In serious cases, the potential of the first node P will control the scanning output module 30 to be turned on in advance, thereby making the scanning signal output by its scanning output terminal Gout inaccurate.

[0063] Therefore, the present disclosure sets up a delay circuit 213, and when there is no signal at the reset input terminal Gn+1, it outputs a signal identical to the valid pulse of the first node reset control signal BW to the first node P, so that the potential of the first node P jumps to a normal potential, and the corresponding shift register unit 210 can work normally, which is beneficial to improving the performance of the gate drive circuit 200 and improving the display effect of the display device 100.

[0064] Optionally, please continue to refer to Figure 7 The shift register unit 210 also includes a tenth transistor M10 and an eleventh transistor M11; the gate of the tenth transistor M10 is connected to the reset signal terminal RESET, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the first node P; the gate of the eleventh transistor M11 is connected to the off signal terminal Goff, the first electrode is connected to the first level signal VGL, and the second electrode is connected to the scan output terminal Gout.

[0065] Specifically, the shift register unit 210 further includes a tenth transistor M10 and an eleventh transistor M11. Under the control of the reset signal terminal RESET, the tenth transistor M10 transmits the first level signal VGL to the first node P; under the control of the shutdown signal terminal Goff, the eleventh transistor M11 transmits the first level signal VGL to the scan output terminal Gout. In this way, the reset signal terminal RESET and the shutdown signal terminal Goff can be high level before or after the enable level of the scan signal output by each level of the scan shift register unit 210, so that the tenth transistor M10 and the eleventh transistor M11 are turned on, and the first node P and the scan output terminal Gout are controlled to remain at a low level, thereby preventing other signals from interfering and affecting the output signal of the scan output terminal Gout, which is beneficial to improving the reliability and display effect of the display device.

[0066] Please refer to Figure 2 and Figure 3 Based on the same inventive concept, the present disclosure provides a driving method for a gate driving circuit, which is used to drive any gate driving circuit 200 provided in the embodiments of the present disclosure. The driving method includes: within at least one frame of working time, including a delay circuit startup phase. In the delay circuit startup phase, the output end of the delay circuit 213 outputs a signal identical to the valid pulse of the first node reset control signal BW to the first node P.

[0067] Specifically, the present disclosure provides a driving method for a gate driving circuit, which includes a delay circuit startup phase within at least one frame of working time. During the delay circuit startup phase, when there is no signal at the reset input terminal Gn+1, a signal identical to the valid pulse of the first node reset control signal BW is output to the first node P, so that the potential of the first node P jumps to a normal potential, and the corresponding shift register unit 210 can work normally, which is beneficial to improving the performance of the gate driving circuit 200 and improving the display effect of the display device 100.

[0068] Please refer to Figure 2 The present disclosure provides an optional implementation method that includes a scanning phase within a frame of working time; in the scanning phase, the scanning output end of each level of the shift register unit 210 sequentially outputs an enable signal of the scanning signal.

[0069] It should be noted that the scanning principle and timing of the shift register unit 210 may refer to the embodiment of the gate driving circuit provided in the present disclosure, and will not be described in detail again.

[0070] Please continue to refer to Figure 2 Based on the same inventive concept, the present disclosure further provides a display device 100, comprising any gate driving circuit 200 in the embodiments of the present disclosure.

[0071] It should be noted that the embodiment of the display device 100 provided in the present disclosure can refer to the embodiment of the gate driving circuit 200 provided in the present disclosure, and will not be repeated. The display device 100 provided in the present disclosure can be: a mobile phone, a tablet computer, a television, a touch controller, a laptop computer, a navigator, or any other product or component with a display function.

[0072] It can be seen from the above embodiments that the gate driving circuit and driving method thereof, and the display device provided by the present disclosure achieve at least the following beneficial effects:

[0073] The present disclosure provides a gate driving circuit and a driving method thereof, and a display device, wherein the gate driving circuit includes a plurality of cascaded shift register units; the shift register unit includes a scan input module, a scan input terminal, a first node, a first node reset module and a reset input terminal; the control terminal of the first node reset module is connected to the reset input terminal, the first terminal is connected to the first node reset control signal, and the second terminal is connected to the first node; the first node reset module is used to reset the first node according to the signal of the reset input terminal; at least part of the shift register units include a delay circuit, and the output terminal of the delay circuit is connected to the first node; the delay circuit is configured such that when there is no signal at the reset input terminal, the output terminal of the delay circuit outputs a signal identical to the valid pulse of the first node reset control signal to the first node. The present invention provides a delay circuit in a shift register unit, wherein the delay circuit is connected to a first node and is used to output a signal identical to a valid pulse of a reset control signal of the first node to the first node when there is no signal at a reset input terminal, so that the potential of the first node jumps to a normal potential, the first node is reset, and the potential of the first node is stabilized. A device operating under the potential control of the first node can be normally shut down, and a corresponding shift register unit can operate normally, which is beneficial to improving the characteristic drift phenomenon of the shift register unit, thereby stabilizing the performance of each stage of the shift register unit in the gate drive circuit, which is beneficial to improving the performance of the gate drive circuit and improving the display effect of the display device.

[0074] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0075] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of cascaded shift register units; The shift register unit includes a scan input module, a scan input terminal, a first node, a first node reset module and a reset input terminal; The control end of the scan input module is connected to the scan input end, the first end is connected to the scan control signal, and the second end is connected to the first node; the scan input module is used to charge the first node according to the signal of the scan input end; the control end of the first node reset module is connected to the reset input end, the first end is connected to the first node reset control signal, and the second end is connected to the first node; the first node reset module is used to reset the first node according to the signal of the reset input end; At least part of the shift register units include a delay circuit, and an output end of the delay circuit is connected to the first node; The delay circuit is configured such that, when there is no signal at the reset input terminal, the output terminal of the delay circuit outputs a signal identical to a valid pulse of the first node reset control signal to the first node.

2. The gate driving circuit according to claim 1, characterized in that: The delay circuit includes a working control module, a charging control module, a delay module, a delay pull-down control module, a delay pull-down module, a delay reset module, a first delay node and a second delay node; The control end of the working control module is connected to the reset input end, the first end is connected to the first level signal, and the second end is connected to the first delay node; The control end of the charging control module is connected to the scanning input end, the first end is connected to the second level signal, the second end is connected to the first end of the delay module, and the second end of the delay module is connected to the first delay node; The delay pull-down control module includes a first submodule and a second submodule, wherein the control end of the first submodule is connected to the first delay node, the first end is connected to the second level signal, and the second end is connected to the second delay node; the control end of the second submodule is connected to the second level signal, the first end is connected to the first level signal, and the second end is connected to the second delay node; The control end of the delay pull-down module is connected to the second delay node, the first end is connected to the first level signal, and the second end is connected to the output end of the delay circuit; The control end of the delay reset module is connected to the delay reset control signal, the first end is connected to the first level signal, and the second end is connected to the first delay node.

3. The gate driving circuit according to claim 2, characterized in that: The working control module comprises a working control transistor, a gate of the working control transistor is connected to the reset input terminal, a first electrode is connected to the first level signal, and a second electrode is connected to the first delay node; The charging control module comprises a charging control transistor, a gate of the charging control transistor is connected to the scanning input terminal, a first electrode is connected to the second level signal, and a second electrode is connected to the delay module; The delay module includes a first capacitor and a first resistor, wherein the first plate of the first capacitor is connected to the second electrode of the charge control transistor, and the second plate is connected to the first delay node; the first electrode of the first resistor is connected to the first plate of the first capacitor, and the second electrode is connected to the second plate of the first capacitor; The delay pull-down control module includes a first delay pull-down control transistor and a second delay pull-down control transistor, wherein the gate of the first delay pull-down control transistor is connected to the first delay node, the first electrode is connected to the second level signal, and the second electrode is connected to the second delay node; The gate of the second delay pull-down control transistor is connected to the second level signal, the first electrode is connected to the first level signal, and the second electrode is connected to the second delay node; The delay pull-down module includes a delay pull-down transistor, a gate of the delay pull-down transistor is connected to the second delay node, a first electrode is connected to the first level signal, and a second electrode is connected to the output end of the delay circuit.

4. The gate driving circuit according to claim 3, characterized in that: The width-to-length ratio of the working control transistor is Ra, the width-to-length ratio of the first delay pull-down control transistor is Rc, and Ra≥2Rc.

5. The gate driving circuit according to claim 3, characterized in that: The width-to-length ratio of the first time-delay pull-down control transistor is Rc, the width-to-length ratio of the second time-delay pull-down control transistor is Rd, and Rc≥2Rd.

6. The gate driving circuit according to claim 1, characterized in that: Each of the shift register units includes the delay circuit.

7. The gate driving circuit according to claim 1, characterized in that: The shift register unit further includes a scan output module, a pull-down module, a pull-down control module, a pull-up module and a second node; The control end of the scan output module is connected to the first node, the first end is connected to the first clock signal, and the second end is connected to the scan output end; the scan output module is used to transmit the first clock signal to the scan output end according to the potential of the first node; The pull-down module is connected to the first node, the second node, the first level signal and the scan output terminal respectively; the pull-down module is used to transmit the first level signal to the first node and the scan output terminal according to the potential of the second node; The pull-down control module is connected to the second node and the second level signal respectively; The pull-down control module is used to transmit the second level signal to the second node; The pull-up module is respectively connected to the first node, the second node, the first level signal and the pull-down control module, and is used to transmit the first level signal to the second node.

8. The gate driving circuit according to claim 7, characterized in that: The scan input module comprises a first transistor, a gate of the first transistor is connected to the scan input terminal, a first electrode is connected to the scan control signal, and a second electrode is connected to the first node; The first node reset module comprises a second transistor, the gate of the second transistor is connected to the reset input terminal, the first electrode is connected to the first node reset control signal, and the second electrode is connected to the first node; The scan output terminal comprises a third transistor and a storage capacitor, wherein the gate of the third transistor is connected to the first node, the first electrode is connected to the first clock signal, and the second electrode is connected to the scan output terminal; the storage capacitor is connected between the gate and the second electrode of the third transistor; The pull-down module includes a fourth transistor and a fifth transistor, wherein the gate of the fourth transistor is connected to the second node, the first electrode is connected to the first level signal, and the second electrode is connected to the first node; the gate of the fifth transistor is connected to the second node, the first electrode is connected to the first level signal, and the second electrode is connected to the scan output terminal; The pull-down control module includes a sixth transistor and a seventh transistor, the gate and the first electrode of the sixth transistor are connected to the second level signal, the second electrode is connected to the gate of the seventh transistor, the first electrode of the seventh transistor is connected to the second level signal, and the second electrode is connected to the second node; The pull-up module includes an eighth transistor and a ninth transistor, the gate of the eighth transistor is connected to the first node, the first electrode is connected to the first level signal, and the second electrode is connected to the second node; the gate of the ninth transistor is connected to the first node, the first electrode is connected to the first level signal, and the second electrode is connected to the pull-down control module.

9. The gate driving circuit according to claim 7, characterized in that: The shift register unit further includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is connected to the clear signal terminal, the first electrode is connected to the first level signal, and the second electrode is connected to the first node; the gate of the eleventh transistor is connected to the shutdown signal terminal, the first electrode is connected to the first level signal, and the second electrode is connected to the scan output terminal.

10. A driving method for a gate driving circuit, characterized in that: Used to drive the gate drive circuit according to any one of claims 1 to 9, the driving method comprising: at least one frame of working time, including a delay circuit startup phase; During the start-up phase of the delay circuit, the output end of the delay circuit outputs a signal identical to a valid pulse of a first node reset control signal to the first node.

11. The driving method of the gate driving circuit according to claim 10, characterized in that: One frame of working time also includes the scanning phase; In the scanning phase, the scanning output terminals of the shift register units at each level sequentially output the enable signal of the scanning signal.

12. A display device, characterized in that: The gate drive circuit comprises the gate drive circuit according to any one of claims 1 to 9.

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